Display devices

Abstract

A display device is provided, comprising: a substrate having a display area including primary pixels and a sensor area including secondary pixels and a transmissive portion; a plurality of first lines arranged in the sensor area, extending in a first direction, and bypassing the transmissive portion; and a first electrode layer located below the plurality of first lines, between the secondary pixels and the transmissive portion, and at least partially overlapping with spacing areas between the plurality of first lines.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0036199 filed on March 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments disclosed herein relate to a display device. Background Art

[0003] The use of display devices is becoming more diverse. In addition, the thickness and weight of display devices are decreasing, and the scope of their use is expanding.

[0004] Since display devices are utilized in various ways, there are various methods of designing the shape of the display devices. In addition, the functions added to or associated with the display devices are increasing. Summary of the Invention

[0005] One or more embodiments include a display device having a sensor area, wherein a sensor or the like may be located in the sensor area. However, embodiments are not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to one or more embodiments, a display device includes: a substrate having a display area including primary pixels and a sensor area including secondary pixels and a transmissive portion; a plurality of first lines arranged in the sensor area, extending in a first direction, and bypassing the transmissive portion; and a first electrode layer located below the plurality of first lines, between the secondary pixels and the transmissive portion, and at least partially overlapping with a spacing area between the plurality of first lines.

[0008] The plurality of first lines may include scan lines connected to the sub-pixels, and wherein the first electrode layer is connected to the scan lines through a contact hole.

[0009] The display device may further include a second electrode layer located between the substrate and the secondary thin film transistor of the secondary pixel and corresponding to the secondary pixel.

[0010] The display device may further include a driving voltage line extending in a second direction crossing the first direction and configured to supply a driving voltage to the sub-pixel, wherein the second electrode layer is connected to the driving voltage line through the contact hole.

[0011] The first electrode layer and the second electrode layer may be spaced apart from each other and have an island shape.

[0012] The sub-pixel may include a sub-thin film transistor including a semiconductor layer and a gate electrode, wherein some of the first lines are located on the same layer as the gate electrode, and wherein the first electrode layer is located below a layer where the semiconductor layer is located.

[0013] The display device may further include a third electrode layer overlapping at least one of the plurality of main thin film transistors in the main pixel, wherein the third electrode layer is located on the same layer as the first electrode layer.

[0014] The display device may further include a second line extending in a second direction crossing the first direction and overlapping the transmissive portion.

[0015] The display device may further include: a second line extending in a second direction crossing the first direction and arranged to bypass the transmission portion; and a second electrode layer located under the second line to overlap the second line and located at the same layer as the first electrode layer.

[0016] The resolution of the image provided by the sensor area may be less than the resolution of the image provided by the display area.

[0017] According to one or more embodiments, a display device includes: a substrate having a display area and a sensor area, the display area including primary pixels, the sensor area having a transmissive portion and including secondary pixels; a plurality of first lines arranged in the sensor area, extending in a first direction, and bypassing the transmissive portion; a plurality of second lines arranged in the sensor area, and extending in a second direction intersecting the first direction; and a first electrode layer located below the plurality of first lines and at least partially overlapping with a spacing area between the plurality of first lines, wherein the first electrode layer is located between the secondary pixels and the transmissive portion.

[0018] The display device may further include a component corresponding to the sensor area on a lower surface of the substrate.

[0019] Some of the plurality of second lines may cross the transmissive portion.

[0020] The display device may further include a second electrode layer located on one side of the transmissive portion, spaced apart from the first electrode layer, and located on the same layer as the first electrode layer, wherein the plurality of second lines are arranged to bypass along an edge of the transmissive portion, and wherein the second electrode layer overlaps the plurality of second lines.

[0021] The display device may further include: a pixel group surrounding the transmissive portion and including a plurality of sub-pixels; and a second electrode layer overlapping the entire pixel group.

[0022] The first electrode layer may be connected to a scan line for transmitting a scan signal to the sub-pixels, wherein the second electrode layer is connected to a driving voltage line for transmitting a driving voltage to the sub-pixels.

[0023] The first electrode layer and the second electrode layer may be spaced apart from each other.

[0024] The display device may further include a third electrode layer overlapping the main thin film transistor and located at the same layer as the first electrode layer, wherein the main pixel includes a main thin film transistor including a main semiconductor layer and a main gate electrode.

[0025] The third electrode layer may be connected to the main gate electrode.

[0026] The display device may further include: an opening area located in the sensor area; a first component corresponding to the opening area on the lower surface of the substrate; and a second component corresponding to the sensor area on the lower surface of the substrate, wherein the transmittance of the opening area is greater than the transmittance of the sensor area, and wherein the sensor area includes sub-pixels to realize an image. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and / or other aspects will become apparent and more readily understood through the following description of the embodiments with reference to the accompanying drawings, in which:

[0028] Figure 1 is a perspective view of a display device according to an embodiment;

[0029] Figure 2 is a cross-sectional view of a display device according to one or more embodiments;

[0030] Figure 3 is a plan view of a display device according to an embodiment;

[0031] Figure 4A is an equivalent circuit diagram of a pixel for performing active matrix driving according to an embodiment, wherein the pixel may be located in a display area of ​​a display device;

[0032] Figure 4B is an equivalent circuit diagram of a pixel for performing active matrix driving according to another embodiment, wherein the pixel may be located in a display area of ​​a display device;

[0033] Figure 5 is a plan view of a pixel circuit of a pixel of a display panel according to an embodiment;

[0034] Figure 6 It is arranged along Figure 5 a cross-sectional view of an organic light emitting diode in a cross-sectional view taken along line II' and line II-II';

[0035] Figure 7 is a plan view of some sub-pixels, lines, and transmissive portions arranged in a sensor area of ​​a display panel according to an embodiment;

[0036] Figure 8 yes Figure 7 An enlarged view of region III in FIG;

[0037] Figure 9 It is along Figure 8 A sectional view taken along line IV-IV';

[0038] Figure 10 is a cross-sectional view of a display panel according to another embodiment;

[0039] Figure 11 is a plan view of a display panel according to another embodiment;

[0040] Figure 12 It is along Figure 11 A sectional view taken along line V-V';

[0041] Figure 13 is a plan view of a display panel according to another embodiment;

[0042] Figure 14 is a plan view of a display panel according to another embodiment;

[0043] Figure 15 is a plan view of a display panel according to another embodiment; and

[0044] Figure 16 is a plan view of a display panel according to another embodiment. DETAILED DESCRIPTION

[0045] Reference will now be made to the embodiments in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following description of the embodiments with reference to the accompanying drawings is intended only to explain aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Expressions such as "at least one (of which)...", when following a column of elements (elements), modify the entire column of elements (elements) without modifying the individual elements (elements) in the column.

[0046] Because the inventive concept is susceptible to various modifications, preferred embodiments are shown in the drawings and described in the detailed description. The effects and features disclosed, as well as methods for achieving the same, will be apparent upon reference to the embodiments described with reference to the drawings. However, the disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0047] Hereinafter, the disclosed embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements, and repeated descriptions thereof will be omitted.

[0048] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms.

[0049] An expression used in the singular includes the expression in the plural form unless it has an obviously different meaning in the context.

[0050] It will also be understood that the term "comprise" and / or variations thereof used herein specify the presence of stated features or components, but does not preclude the presence or addition of one or more other features or components.

[0051] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, the layer, region, or component may be directly or indirectly formed on the other layer, region, or component. That is, intervening layers, regions, or components may be present, for example.

[0052] For the convenience of explanation, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0053] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order from the described order.

[0054] It will be understood that when a layer, region, or component is connected to another part, the layer, region, or component may be directly connected to the part, or there may be intervening layers, regions, or components. For example, when a layer, region, or component is electrically connected to another part, the layer, region, or component may be directly electrically connected to the part, or may be indirectly electrically connected to the part through another layer, region, or component.

[0055] Figure 1 is a perspective view of a display device according to an embodiment.

[0056] Reference Figure 1The display device 1 includes a display area DA for realizing an image and a non-display area NDA not for realizing an image. The display device 1 can provide a main image by using light emitted from a plurality of main pixels Pm in the display area DA.

[0057] The display device 1 includes a sensor area SA. Figure 2 As described above, the sensor area SA may be an area where components, such as sensors using infrared rays, visible light, or sound, are located below the sensor area SA. The sensor area SA may include a transmissive portion TA through which light and / or sound output from the components to the outside or traveling from the outside toward the components can pass. In embodiments, when infrared rays are transmitted through the sensor area SA, the transmittance may be approximately 10% or greater, approximately 20% or greater, approximately 25% or greater, approximately 50% or greater, approximately 85% or greater, or approximately 90% or greater.

[0058] In this embodiment, a plurality of sub-pixels Pa can be arranged in the sensor area SA, and a specific image can be provided using light emitted from the plurality of sub-pixels Pa. The image provided by the sensor area SA can have a lower resolution as a sub-image than the image provided by the display area DA. That is, because the sensor area SA has a transmissive portion TA through which light and / or sound can pass, the number of sub-pixels Pa that can be arranged per unit area can be smaller than the number of primary pixels Pm arranged per unit area in the display area DA.

[0059] The sensor area SA may be at least partially surrounded by the display area DA. Figure 1 It is shown that the sensor area SA is completely surrounded by the display area DA.

[0060] Hereinafter, an organic light emitting display is described as an example of the display device 1 according to an embodiment, however, the display device of the present disclosure is not limited thereto. In other embodiments, the display device 1 may be various types of display devices such as an inorganic light emitting (EL) display and a quantum dot EL display.

[0061] Figure 1 The sensor area SA is shown as being located on one side (upper right side) of the rectangular display area DA, but the present disclosure is not limited thereto. The shape of the display area DA may be, for example, circular, elliptical, or polygonal such as a triangle or pentagon, and the position of the sensor area SA and the number of sensor areas SA may vary.

[0062] Figure 2 is a cross-sectional view schematically illustrating a display device according to one or more embodiments, and can be compared with Figure 1 The cross section is taken along the line AA'.

[0063] Reference Figure 2 , the display device 1 may include a display panel 10 including a display element and a component 20 corresponding to the sensor area SA.

[0064] The display panel 10 may include a substrate 100, a display element layer 200 on the substrate 100, and a thin film encapsulation layer 300 as a sealing member for sealing the display element layer 200. In addition, the display panel 10 may further include a lower protective film 175 under the substrate 100.

[0065] The substrate 100 may include glass or a polymer resin. For example, the polymer resin may include polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC) and / or cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable or bendable. In some embodiments, the substrate 100 may have a multilayer structure including a layer comprising the polymer resin and an inorganic layer.

[0066] The display element layer 200 may include a circuit layer including thin film transistors TFT and TFT′, an organic light emitting diode OLED as a display element, and insulating layers IL and IL′ therebetween.

[0067] A main pixel Pm including a main thin film transistor TFT and an organic light emitting diode OLED connected to the main thin film transistor TFT may be located in the display area DA, and a sub-pixel Pa including a sub-thin film transistor TFT' and an organic light emitting diode OLED connected to the sub-thin film transistor TFT' and a line WL may be arranged in the sensor area SA.

[0068] In addition, the sensor area SA may be provided with a sub-thin film transistor TFT' and a transmissive portion TA that does not include any display element. The transmissive portion TA may be understood as an area through which light or signals emitted from the component 20 or light or signals incident on the component 20 are transmitted.

[0069] The component 20 may be located in the sensor area SA. The component 20 may be an electronic component that uses light or sound. For example, the component 20 may include a sensor that receives light (such as an infrared sensor), a sensor that outputs and detects light and / or sound to measure distance or identify fingerprints, a small lamp that outputs light, a speaker that outputs sound, and the like. In the case of an electronic component using light, light in various wavelength bands such as visible light, infrared light, and / or ultraviolet light may be used. The number of components 20 arranged in the sensor area SA may be multiple. For example, as a component 20, a light emitting element and a light receiving element may be arranged together in one sensor area SA. Alternatively, both the light emitting unit and the light receiving unit may be provided as a single component 20.

[0070] In this embodiment, if Figure 2 As shown in FIG, the electrode layer BSM may include a first electrode layer BSM1 and a second electrode layer BSM2. The first electrode layer BSM1 and / or the second electrode layer BSM2 may be located in the sensor area SA. The first electrode layer BSM1 may be positioned to correspond to (e.g., be located below) a plurality of lines WL in the sensor area SA, and the second electrode layer BSM2 may be positioned to correspond to (e.g., be located below) the sub-pixels Pa.

[0071] The first electrode layer BSM1 and the second electrode layer BSM2 may be arranged to correspond to the lower portion of the line WL and the lower portion of the sub-thin film transistor TFT'. The first electrode layer BSM1 and the second electrode layer BSM2 may reduce or prevent external light from reaching the line WL and the sub-pixel Pa including the sub-thin film transistor TFT'. For example, light emitted from the component 20 and reaching the sub-pixel Pa and the line WL may be reduced or prevented.

[0072] A constant voltage or signal may be applied to the first electrode layer BSM1 and the second electrode layer BSM2 to reduce or prevent damage to the pixel circuit due to electrostatic discharge. In some embodiments, the first electrode layer BSM1 and the second electrode layer BSM2 may receive different voltages, respectively.

[0073] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 2 A first inorganic encapsulating layer 310 and a second inorganic encapsulating layer 330 are shown with an organic encapsulating layer 320 therebetween.

[0074] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulators such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. Examples of polymer materials may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0075] A lower protective film 175 may be attached to the lower portion of the substrate 100 to support and protect the substrate 100. The lower protective film 175 may have an opening 175OP corresponding to the sensor area SA. Providing the opening 175OP in the lower protective film 175 may improve light transmittance of the sensor area SA. The lower protective film 175 may be formed of PET and / or PI.

[0076] The area of ​​the sensor region SA may be larger than the area where the component 20 is located. Therefore, the area of ​​the opening 175OP provided in the lower protective film 175 may not directly coincide with the area of ​​the sensor region SA. For example, the area of ​​the opening 175OP may be smaller than the area of ​​the sensor region SA.

[0077] In other embodiments, components such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may be further disposed on the display panel 10 .

[0078] Although the thin film encapsulation layer 300 is used as a sealing member for sealing the display element layer 200 in this embodiment, the disclosure is not limited thereto. For example, as a member for sealing the display element layer 200, a sealing substrate bonded to the substrate 100 by a sealant or glass frit may be used.

[0079] Figure 3 is a plan view of the display panel 10 according to the embodiment.

[0080] Reference Figure 3 , the display panel 10 includes a display area DA and includes a plurality of primary pixels Pm. Each primary pixel Pm may include a display element such as an organic light emitting diode. Each primary pixel Pm may emit light, such as red light, green light, blue light, or white light, through an organic light emitting diode. As described herein, the primary pixel Pm may be understood as a pixel that emits any one of the red light, green light, blue light, and white light as described above. The display area DA may be referred to above. Figure 2 The described sealing member is covered to be protected from outside air or moisture.

[0081] The sensor area SA may be located in the display area DA, and a plurality of sub-pixels Pa may be arranged in the sensor area SA. Each sub-pixel Pa may include a display element such as an organic light-emitting diode. Each sub-pixel Pa may emit light such as red light, green light, blue light, or white light through the organic light-emitting diode. As described herein, the sub-pixel Pa may be understood as a pixel that emits any one of the red light, green light, blue light, and white light described above. The sensor area SA may be provided with a transmissive portion TA located between the sub-pixels Pa.

[0082] In an embodiment, one primary pixel Pm may include the same pixel circuit as that of one secondary pixel Pa. However, the disclosure is not limited thereto. In other embodiments, the pixel circuit included in the primary pixel Pm may be different from the pixel circuit included in the secondary pixel Pa.

[0083] Because the sensor area SA includes the transmissive portion TA, the resolution in the sensor area SA may be lower than that in the display area DA. For example, the resolution of the sensor area SA may be approximately ½ that of the display area DA. In some embodiments, the resolution of the display area DA may be approximately 400 ppi or higher, and the resolution of the sensor area SA may be approximately 200 ppi.

[0084] Each of the primary pixel Pm and the secondary pixel Pa can be electrically connected to an external circuit arranged in the non-display area NDA. The non-display area NDA may include a first scan driving circuit 110, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power line 160, and a second power line 170.

[0085] The first scan drive circuit 110 can supply a scan signal to each of the primary pixels Pm and the secondary pixels Pa via scan lines SL. The first scan drive circuit 110 can also supply a light emission control signal to each pixel via emission control lines EL. The second scan drive circuit 120 can be positioned parallel to the first scan drive circuit 110, with the display area DA located therebetween. Some of the primary pixels Pm and secondary pixels Pa arranged in the display area DA and the sensor area SA can be electrically connected to the first scan drive circuit 110, while the remaining ones can be connected to the second scan drive circuit 120. In another embodiment, the second scan drive circuit 120 can be omitted.

[0086] The terminal 140 may be located on one side of the substrate 100. The terminal 140 may be exposed by not being covered by the insulating layer and may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. In some embodiments, the printed circuit board PCB transmits a signal or power of the controller to the display panel 10. The control signal generated by the controller may be transmitted to the first scan driving circuit 110 and the second scan driving circuit 120 respectively through the printed circuit board PCB. The controller may transmit the first power supply voltage ELVDD and the second power supply voltage ELVSS (see the following description) through the first connection line 161 and the second connection line 171. Figure 4A and Figure 4B) are respectively supplied to the first power line 160 and the second power line 170. The first power supply voltage ELVDD can be supplied to each of the primary pixel Pm and the sub-pixel Pa through the driving voltage line (e.g., the lower driving voltage line) PL connected to the first power line 160, and the second power supply voltage ELVSS can be supplied to the counter electrode of each of the primary pixel Pm and the sub-pixel Pa connected to the second power line 170.

[0087] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be supplied to each of the primary pixel Pm and the secondary pixel Pa through the corresponding connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Figure 3 The data driving circuit 150 is shown as being located on the printed circuit board PCB. However, in another embodiment, the data driving circuit 150 may be located on the substrate 100. For example, the data driving circuit 150 may be located between the terminal 140 and the first power line 160.

[0088] The first power line 160 may include a first sub-line 162 and a second sub-line 163, which are arranged in parallel (eg, at Figure 3 The second power line 170 extends in the x-direction shown in FIG. 1 and the display area DA is located therebetween. The second power line 170 may partially surround the display area DA in a ring shape with one side open.

[0089] Figure 4A and Figure 4B is an equivalent circuit diagram of a primary pixel and / or a secondary pixel that may be included in a display panel according to an embodiment.

[0090] Reference Figure 4A , each of the main pixel Pm and the sub-pixel Pa includes a pixel circuit PC connected to the scan line SL and to the data line DL, and includes an organic light emitting diode OLED connected to the pixel circuit PC.

[0091] The pixel circuit PC includes a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 is connected to the scan line SL and the data line DL and supplies a data signal Dm input through the data line DL to the driving TFT T1 according to the scan signal Sn.

[0092] The storage capacitor Cst is connected to the switching TFT T2 and the driving voltage line PL and stores a voltage corresponding to a difference between a voltage supplied from the switching TFT T2 and a first power voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0093] The driving TFT T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light (e.g., light with a predetermined brightness) according to the driving current.

[0094] although Figure 4A The case where the pixel circuit PC includes two TFTs and one storage capacitor Cst is described, but the disclosure is not limited thereto. Figure 4B As shown in , the pixel circuit PC may include seven thin film transistors and one storage capacitor.

[0095] Reference Figure 4B Each of the primary pixel Pm and the secondary pixel Pa includes a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor and a plurality of thin-film transistors. The thin-film transistors and the storage capacitor may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the drive voltage line PL.

[0096] although Figure 4B In the diagram, each of the primary pixel Pm and the secondary pixel Pa is connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the drive voltage line PL, but the present disclosure is not limited thereto. In another embodiment, at least one of the signal lines SLn, SLn-1, EL, and DL, the initialization voltage line VL, and the drive voltage line PL may be shared by adjacent pixels.

[0097] The plurality of thin film transistors may include a driving TFT T1 , a switching TFT T2 , a compensation TFT T3 , a first initialization TFT T4 , an operation control TFT T5 , an emission control TFT T6 , and a second initialization TFT T7 .

[0098] The signal lines include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting a previous scan signal Sn-1 to a first initialization TFT T4 and a second initialization TFT T7, an emission control line EL for transmitting an emission control signal En to an operation control TFT T5 and an emission control TFT T6, and a data line DL for transmitting a data signal Dm and intersecting the scan lines SL. A driving voltage line PL supplies a first power supply voltage ELVDD to the driving TFT T1, and an initialization voltage line VL transmits an initialization voltage Vint for initializing the driving TFT T1 and a pixel electrode (e.g., an anode electrode of an OLED).

[0099] The driving gate electrode G1 of the driving TFT T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line PL through the operation control TFT T5, and the driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 and converts the driving current I OLED Supply to the organic light emitting diode OLED.

[0100] A switching gate electrode G2 of the switching TFT T2 is connected to the scan line SL, a switching source electrode S2 of the switching TFT T2 is connected to the data line DL, a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1, and is also connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 is turned on in response to a scan signal Sn received through the scan line SL and performs a switching operation to transmit a data signal Dm transmitted to the data line DL to the driving source electrode S1 of the driving TFT T1.

[0101] A compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line SL. A compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1 and is also connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. A compensation drain electrode D3 of the compensation TFT T3 is connected to a first storage capacitor plate Cst1 of the storage capacitor Cst, to a first initialization drain electrode D4 of the first initialization TFT T4, and to the driving gate electrode G1 of the driving TFT T1. The compensation thin film transistor T3 is turned on in response to a scan signal Sn received via the scan line SL and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1, thereby diode-connecting the driving TFT T1.

[0102] A first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line SL-1, a first initialization source electrode S4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and to the initialization voltage line VL, a first initialization drain electrode D4 of the first initialization TFT T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, to the compensation drain electrode D3 of the compensation TFT T3, and to the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SL-1, and initializes the voltage of the driving gate electrode G1 of the driving TFT T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1.

[0103] An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL, an operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line PL, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and to the switching drain electrode D2 of the switching TFT T2.

[0104] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and to the compensation source electrode S3 of the compensation TFT T3, and the emission control drain electrode D6 of the emission control TFT T6 is electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and to the pixel electrode of the organic light emitting diode OLED.

[0105] The operation control TFT T5 and the emission control TFT T6 are substantially simultaneously turned on in response to the emission control signal En received through the emission control line EL, so that the driving voltage ELVDD is transmitted to the organic light emitting diode OLED and the driving current I OLED Flow through the organic light emitting diode OLED.

[0106] A second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SL-1, a second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and to the pixel electrode of the organic light emitting diode OLED, and a second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and to the initialization voltage line VL. The second initialization TFT T7 is turned on in response to the previous scan signal Sn-1 received through the previous scan line SLn-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0107] although Figure 4B The case where the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SL-1 is described, but the disclosure is not limited thereto. In another embodiment, the first initialization TFT T4 may be connected to the previous scan line SLn-1 and driven according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., the next scan line) and may be driven according to a signal transmitted to the signal line.

[0108] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving TFT T1. OLED and can emit light to display images.

[0109] Figure 4B The compensation TFT T3 and the first initialization TFT T4 are shown to have dual gate electrodes. However, in other embodiments, the compensation TFT T3 and the first initialization TFT T4 may have one gate electrode.

[0110] In this embodiment, the primary pixel Pm and the secondary pixel Pa may have the same pixel circuit PC. However, the disclosure is not limited thereto. The primary pixel Pm and the secondary pixel Pa may have corresponding pixel circuits PC having different structures. For example, the primary pixel Pm may adopt Figure 4B The pixel circuit of the sub-pixel Pa can be Figure 4A Pixel circuit, and various modifications are possible.

[0111] Figure 5 is a layout diagram of pixel circuits of pixels Pm and Pa of a display panel according to an embodiment, Figure 6 It is arranged along Figure 5 sectional views of an organic light emitting diode taken along lines II' and II-II'.

[0112] Reference Figure 5 , a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7 are arranged along a semiconductor layer 1130. The semiconductor layer 1130 is located on a substrate having a buffer layer formed thereon, the buffer layer including an inorganic insulating material.

[0113] Some areas of the semiconductor layer 1130 may correspond to the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and / or the second initialization TFT T7. In other words, it can be understood that the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and / or the second initialization TFT T7 are connected to each other and bent in various shapes.

[0114] The semiconductor layer 1130 includes a channel region and a source region and a drain region located on respective sides of the channel region, wherein the source region and the drain region can be understood as the source electrode and the drain electrode of the corresponding thin film transistor. Hereinafter, for convenience, the source region and the drain region are referred to as the source electrode and the drain electrode, respectively.

[0115] The driving TFT T1 includes a driving gate electrode G1 overlapping a driving channel region, and a driving source electrode S1 and a driving drain electrode D1 located on respective sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 has a curved shape, such as an omega shape, thereby enabling a long channel length to be formed in a narrow space. When the driving channel region is long, the driving range of the gate voltage becomes wider, making it possible to more accurately control the grayscale of light emitted from the organic light emitting diode (OLED), thereby improving display quality.

[0116] The switching TFT T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 on respective sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0117] The compensation TFT T3 may be a dual thin film transistor having a compensation gate electrode G3 overlapping two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 located on respective sides of the two compensation channel regions. The compensation TFT T3 may be connected to the driving gate electrode G1 of the driving TFT T1 via a node connection line 1174, which will be described below.

[0118] The first initialization TFT T4 may be a double thin film transistor having a first initialization gate electrode G4 overlapping two first initialization channel regions, and may include a first initialization source electrode S4 and a first initialization drain electrode D4 on respective sides of the two first initialization channel regions.

[0119] The operation control TFT T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and may include an operation control source electrode S5 and an operation control drain electrode D5 on respective sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0120] The emission control TFT T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and may include an emission control source electrode S6 and an emission control drain electrode D6 on respective sides of the emission control channel region. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0121] The second initialization TFT T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 on respective sides of the second initialization channel region.

[0122] The aforementioned thin film transistors may be connected to the signal lines SL, SL- 1 , EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0123] The scan line SL, the previous scan line SL- 1 , the emission control line EL, and the driving gate electrode G1 may be disposed over the aforementioned semiconductor layer 1130 with an insulating layer therebetween.

[0124] The scan line SL may extend in the first direction. Some regions of the scan line SL may correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, some regions of the scan line SL that overlap with the channel regions of the switching TFT T2 and the compensation TFT T3 may correspond to the switching gate electrode G2 and the compensation gate electrode G3.

[0125] The previous scan line SL-1 may extend in the first direction, and some regions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, some regions of the previous scan line SL-1 that overlap with the channel regions of the first initialization TFT T4 and the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0126] The emission control line EL extends in a first direction. Some regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, some regions of the emission control line EL that overlap with the channel regions of the operation control TFT T5 and the emission control TFT T6 may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0127] The driving gate electrode G1 is a floating electrode and may be connected to the compensation TFT T3 through the aforementioned node connection line 1174 .

[0128] The electrode voltage line HL may be located on the scan line SL, the previous scan line SL- 1 , the emission control line EL, and the driving gate electrode G1 with an insulating layer therebetween.

[0129] The electrode voltage line HL may extend in the first direction to cross the data line DL and the drive voltage line PL. A portion of the electrode voltage line HL covers at least a portion of the drive gate electrode G1 and may form a storage capacitor Cst together with the drive gate electrode G1. For example, the drive gate electrode G1 may be a first storage capacitor plate CE1 (e.g., Figure 4B Cst1 in FIG), a portion of the electrode voltage line HL may be a second storage capacitor plate CE2 (eg, Figure 4B Cst2 in).

[0130] The second storage capacitor plate CE2 of the storage capacitor Cst is electrically connected to the drive voltage line PL. In this regard, the electrode voltage line HL can be connected to the drive voltage line PL located above the electrode voltage line HL through the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the voltage level (constant voltage) of the drive voltage line PL. For example, the electrode voltage line HL can have a constant voltage of approximately +5V. The electrode voltage line HL can be understood as a horizontal drive voltage line.

[0131] Because the driving voltage line PL extends in the second direction and because the electrode voltage line HL electrically connected to the driving voltage line PL extends in the first direction crossing the second direction, the plurality of driving voltage lines PL and the electrode voltage lines HL may form a grid structure in the display area.

[0132] The data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 may be located on the electrode voltage line HL with an insulating layer therebetween.

[0133] The data line DL extends in the second direction and may be connected to the switching source electrode S2 of the switching TFT T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0134] As described above, the driving voltage line PL extends in the second direction and is connected to the electrode voltage line HL through the contact hole CNT. In addition, the driving voltage line PL can be connected to the operation control TFT T5 through the contact hole 1155. The driving voltage line PL can be connected to the operation control source electrode S5 through the contact hole 1155.

[0135] One end of the initialization connection line 1173 may be connected to the first and second initialization TFTs T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to an initialization voltage line VL to be described below through the contact hole 1151 .

[0136] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0137] The initialization voltage line VL may be located on the data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 with an insulating layer therebetween.

[0138] The initialization voltage line VL extends in the first direction and may be connected to the first initialization TFT T4 and the second initialization TFT T7 through the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, approximately -2V, etc.).

[0139] Initialization voltage line VL is connected to pixel electrode 210 of organic light emitting diode OLED (see Figure 6 ) is located on the same layer and may include the same material as that of the pixel electrode 210. The pixel electrode 210 may be connected to the emission control TFT T6. The pixel electrode 210 may be connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 may be connected to the emission control drain electrode D6 through the contact hole 1153.

[0140] although Figure 5 It is shown that the initialization voltage line VL and the pixel electrode 210 are located on the same layer, but in another embodiment, the initialization voltage line VL and the electrode voltage line HL may be located on the same layer.

[0141] In the following, reference is made to Figure 6 , a stack structure of components included in a display panel according to an embodiment will be described.

[0142] The substrate 100 may include glass or a polymer resin. For example, the polymer resin may include PES, PA, PEI, PEN, PET, PPS, PAR, PI, PC, or CAP. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. In other embodiments, the substrate 100 may have a multilayer structure including a layer comprising the polymer resin and an inorganic layer.

[0143] The buffer layer 111 is located on the substrate 100 to reduce or block the penetration of foreign matter, moisture or external air from the lower side of the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material, and may have a single-layer structure or a multi-layer structure including an inorganic material or an organic material. In other embodiments, a barrier layer may be further placed between the substrate 100 and the buffer layer 111 to block the penetration of external air. The buffer layer 111 may include a stacked first buffer layer 111a and a second buffer layer 111b.

[0144] The gate electrodes G1 and G6 are located on the semiconductor layers A1 and A6, and the first gate insulating layer 112 is located between them. Each of the gate electrodes G1 and G6 includes molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can be formed as a single layer or multiple layers. For example, each of the gate electrodes G1 and G6 can be a single layer of Mo. The scan line SL, the previous scan line SL-1, and the emission control line EL can be formed on the same layer as the gate electrodes G1 and G6. That is, the gate electrodes G1 and G6, the scan line SL, the previous scan line SL-1, and the emission control line EL can be located on the first gate insulating layer 112.

[0145] The first gate insulating layer 112 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO).

[0146] The second gate insulating layer 113 may be provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO.

[0147] The first storage capacitor plate CE1 of the storage capacitor Cst may be integrally formed with the driving gate electrode G1 of the driving TFT T1. For example, the driving gate electrode G1 of the driving TFT T1 may serve as the first storage capacitor plate CE1 of the storage capacitor Cst.

[0148] The second storage capacitor plate CE2 of the storage capacitor Cst overlaps the first storage capacitor plate CE1 with the second gate insulating layer 113 located therebetween. The second gate insulating layer 113 may serve as a dielectric layer for the storage capacitor Cst. The second storage capacitor plate CE2 may include a conductive material including Mo, Al, Cu, or Ti, and may be formed as a single layer or multiple layers including one or more of the aforementioned materials. For example, the second storage capacitor plate CE2 may be a single layer of Mo, or a multilayer of Mo / Al / Mo.

[0149] In the drawings, the storage capacitor Cst overlaps the driving TFT T1, but the disclosure is not limited thereto. The storage capacitor Cst may not overlap the driving TFT T1, and various modifications are possible.

[0150] The second storage capacitor plate CE2 may serve as the electrode voltage line HL. For example, a portion of the electrode voltage line HL may be the second storage capacitor plate CE2 of the storage capacitor Cst.

[0151] The interlayer insulating layer 115 may be provided to cover the second storage capacitor plate CE2. The interlayer insulating layer 115 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO.

[0152] The data line DL, the driving voltage line PL, and the connection metal 1175 may be located on the interlayer insulating layer 115. The data line DL, the driving voltage line PL, and the connection metal 1175 may include a conductive material including Mo, Al, Cu, Ti, etc., and may be formed as a single layer or multiple layers including one or more of the above materials. For example, the data line DL, the driving voltage line PL, and the connection metal 1175 may be formed of a multilayer structure of Ti / Al / Ti.

[0153] The second storage capacitor plate CE2 of the storage capacitor Cst may be connected to the driving voltage line PL through a contact hole CNT defined in the interlayer insulating layer 115. This may mean that the electrode voltage line HL is connected to the driving voltage line PL through the contact hole CNT. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the voltage level (constant voltage) of the driving voltage line PL.

[0154] The connection metal 1175 is connected to the semiconductor layer A6 of the emission control TFT T6 through the contact hole 1153 penetrating the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control TFT T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED through the connection metal 1175.

[0155] The planarization layer 117 is located on the data line DL, the driving voltage line PL, and the connection metal 1175 , and the organic light emitting diode OLED may be located on the planarization layer 117 .

[0156] The planarization layer 117 may have a flat top surface so that the pixel electrode 210 may be formed to be flat. The planarization layer 117 may include an organic material and may be formed as a single layer or as a multilayer. The planarization layer 117 may include a general polymer (such as benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) and / or polystyrene (PS)), a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, or a mixture thereof. The planarization layer 117 may include an inorganic material. The planarization layer 117 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. When the planarization layer 117 is formed of an inorganic material, chemical planarization polishing may be performed in some cases. In addition, the planarization layer 117 may include both organic and inorganic materials.

[0157] The pixel electrode 210 may be a (semi) transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective film formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a mixture thereof, and may include a transparent or semi-transparent electrode layer formed above the reflective film. The transparent or semi-transparent electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may be configured to use an ITO / Ag / ITO stacked structure.

[0158] The pixel defining layer 119 may be located on the planarization layer 117. The pixel defining layer 119 may have an opening 119OP for exposing the central portion of the pixel electrode 210 to define the light emitting area of ​​the pixel. In addition, the pixel defining layer 119 may reduce or prevent arcing at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 located on the pixel electrode 210. The pixel defining layer 119 may include an organic insulating material such as PI, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by spin coating.

[0159] The intermediate layer 220 of the organic light emitting diode OLED may include an organic emission layer. The organic emission layer may include an organic material containing a fluorescent or phosphorescent material that emits red, green, blue or white light. The organic emission layer may include a low molecular weight organic material or a high molecular weight organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) or an electron injection layer (EIL) may be further selectively arranged above and below the organic emission layer, respectively. The intermediate layer 220 may be arranged to correspond to each of the multiple pixel electrodes 210. However, the disclosure is not limited thereto. The intermediate layer 220 may include a layer that is integrated with the multiple pixel electrodes 210, and various modifications may be made.

[0160] The counter electrode 230 may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent electrode or a translucent electrode and may include a metal film having a small work function (including Li, Ca, lithium fluoride (LiF) / Ca, LiF / Al, Al, Ag, Mg or a mixture thereof). In addition, a transparent conductive oxide (TCO) layer including, for example, ITO, IZO, ZnO or In2O3 may be further arranged on the metal film. The counter electrode 230 may be arranged to extend over the display area DA and may be located on the intermediate layer 220 and the pixel defining layer 119. The counter electrode 230 may be integrally formed for a plurality of organic light emitting diodes OLED to correspond to a plurality of pixel electrodes 210.

[0161] When the pixel electrode 210 is configured as a reflective electrode and the counter electrode 230 is configured as a transparent electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and the display device can be a top-emission type. When the pixel electrode 210 is configured as a transparent or semi-transparent electrode and the counter electrode 230 is configured as a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and the display device can be a bottom-emission type. However, the present disclosure is not limited thereto. In addition, the type of the display device according to the embodiment can be a double-side emission type for emitting light toward the front and rear sides of the display device.

[0162] In this embodiment, for example, when referring to Figure 5 and Figure 6 When the pixel circuit described above is applied to the sub-pixel Pa in the sensor area SA, Figure 2 The first electrode layer BSM1 and the second electrode layer BSM2 described in may be located between the substrate 100 and the semiconductor layers A1 and A6.

[0163] Figure 7 is a plan view schematically showing some sub-pixels Pa, lines DL, PL, HL, VL, SL-1, SL, and EL, and a transmissive portion TA arranged in the sensor area SA, Figure 8 yes Figure 7 Magnified view of region III. Figure 9 It is along Figure 8 A cross-sectional view taken along line IV-IV'. Figure 9 In, with Figure 6 The same reference numerals as in the figures denote the same elements, and repeated descriptions will be omitted for the sake of brevity.

[0164] Reference Figure 7 and Figure 8 , the sensor area SA includes a sub-pixel Pa and a transmissive portion TA. The sub-pixels Pa may be continuously arranged to form a pixel group Pg. The pixel group Pg may include at least one sub-pixel Pa. Figure 7 In the embodiment, one pixel group Pg includes four sub-pixels Pa arranged in a row. However, the disclosure is not limited thereto. The number and arrangement of the sub-pixels Pa included in one pixel group Pg may vary. For example, one pixel group Pg may include eight sub-pixels Pa arranged in two rows.

[0165] The transmissive portion TA is a region with high light transmittance and is not located within the display element. A plurality of transmissive portions TA may be provided within the sensor area SA. The transmissive portions TA may be arranged alternately with the pixel groups Pg in the first and / or second directions. Alternatively, the transmissive portions TA may be arranged to surround the pixel groups Pg. Alternatively, the secondary pixels Pa may be arranged to surround the transmissive portions TA.

[0166] The sensor area SA is connected to the sub-pixel Pa and includes lines VL, SL- 1 , SL, and EL extending in a first direction and lines DL and PL extending in a second direction crossing the first direction.

[0167] The lines DL and PL extending in the second direction include data lines DL and driving voltage lines PL. When the lines DL and PL extending in the second direction are referred to as second lines, at least one of the second lines is arranged to pass through the transmissive portion TA. In some embodiments, the data lines DL and / or the driving voltage lines PL may be arranged to pass through the transmissive portion TA. However, the present disclosure is not limited thereto. At least one of the data lines DL and the driving voltage lines PL may be arranged to bypass the transmissive portion TA.

[0168] Some of the driving voltage lines PL may be positioned so as to pass through the transmissive portion TA, while other driving voltage lines PL may be disconnected with the transmissive portion TA located between them. In this case, because the driving voltage lines PL are connected to the electrode voltage lines HL extending in the first direction, the first power supply voltage (also referred to as the driving voltage) ELVDD can be transmitted through the electrode voltage lines HL to the disconnected driving voltage lines PL. Because some of the driving voltage lines PL are disconnected with the transmissive portion TA located between them, the light transmittance of the transmissive portion TA can be improved.

[0169] When the lines VL, SL-1, SL, and EL extending in the first direction among the lines connecting the sub-pixels Pa are referred to as first lines, the first lines are arranged to bypass the transmission part TA. This may be to ensure the transmittance of the transmission part TA. The first lines may be, for example, referring to Figure 4B and Figure 5 The initialization voltage line VL, the previous scan line SL-1, the scan line SL and the emission control line EL are described.

[0170] Since the first lines are arranged to bypass the transmission part TA, the first lines can be densely arranged at one side of the transmission part TA. That is, the interval d1 between adjacent first lines arranged adjacent to the transmission part TA can be smaller than the interval d2 between the first lines passing through the portion corresponding to the sub-pixel Pa (for example, d1 <d2)。

[0171] Therefore, a slit with a short spacing d1 may be formed between the first lines bypassing the transmissive portion TA. When light passes through the slit, light diffraction occurs, causing the component 20 located therebelow to not operate properly. In addition, light diffraction may distort the image realized by the sub-pixel Pa.

[0172] This embodiment introduces a first electrode layer BSM1 (e.g., in the thickness direction of the display panel) superimposed below the first line bypassing the transmissive portion TA to reduce or prevent this phenomenon. In a plan view, the first electrode layer BSM1 may be located between the transmissive portion TA and the sub-pixel Pa.

[0173] In the embodiment, the first electrode layer BSM1 is configured in an island shape so that the first electrode layer BSM1 can correspond to the plurality of first lines. That is, the first electrode layer BSM1 can overlap the plurality of first lines VL, SL-1, SL, and EL. As a result, it is possible to reduce or prevent external light from passing through the gaps between the first lines, thereby reducing light diffraction.

[0174] In an embodiment, the first electrode layer BSM1 can be connected to one of the first lines VL, SL-1, SL, and EL through a contact hole. The first electrode layer BSM1 is supplied with the voltage or signal of the first line, thereby significantly reducing the likelihood of electrostatic discharge. In some embodiments, the first electrode layer BSM1 can be connected to the scan line SL through the first contact hole C1. Thus, the first electrode layer BSM1 can function as part of the scan line SL, thereby reducing the resistance of the line used to transmit the scan signal. In other words, since the first electrode layer BSM1 is connected to the scan line SL, RC delay can be improved.

[0175] When the first electrode layer BSM1 contacts a line for supplying a constant voltage, damage caused by electrostatic discharge can be reduced, but parasitic capacitance can be increased. Therefore, the first electrode layer BSM1 may be more preferably connected to the scan line SL.

[0176] In an embodiment, the second electrode layer BSM2 may be located below the sub-pixel Pa. The second electrode layer BSM2 prevents external light from reaching the sub-thin film transistor TFT' included in the sub-pixel Pa, thereby stabilizing the characteristics of the sub-thin film transistor TFT'. In addition, the second electrode layer BSM2 may be introduced to reduce or prevent light diffraction caused by the slit formed in the sub-pixel Pa.

[0177] In an embodiment, the second electrode layer BSM2 is provided in an island shape, so that the second electrode layer BSM2 may correspond to a plurality of sub-pixels Pa. For example, the second electrode layer BSM2 may overlap the entire pixel group Pg.

[0178] In an embodiment, the first electrode layer BSM1 and the second electrode layer BSM2 are spaced apart from each other and may receive different voltages or signals, respectively.

[0179] For example, the second electrode layer BSM2 can be connected to the drive voltage line PL through the second contact hole C2. The second electrode layer BSM2 receives the drive voltage ELVDD as a constant voltage, so that the characteristics of the auxiliary thin-film transistor TFT' included in the auxiliary pixel Pa are not damaged. In other words, because the second electrode layer BSM2 is formed to overlap the auxiliary thin-film transistor TFT', when the second electrode layer BSM2 is connected to the line for providing a varying signal, the auxiliary thin-film transistor TFT' will be affected by the signal. Therefore, it may be more preferable that the second electrode layer BSM2 is connected to the drive voltage line PL that provides a constant voltage.

[0180] In addition, since the second electrode layer BSM2 is connected to the driving voltage line PL rather than being floated, the possibility of occurrence of electrostatic discharge may be reduced.

[0181] Reference Figure 9, the main pixel Pm is located in the display area DA, and the sub-pixel Pa, the transmission part TA, and the bypass line part DW bypassing the transmission part TA are arranged in the sensor area SA.

[0182] The main pixel Pm may include a main thin film transistor TFT and an organic light emitting diode OLED, and the subsidiary pixel Pa may include a subsidiary thin film transistor TFT′ and an organic light emitting diode OLED. Figure 9 The main thin film transistor TFT and the auxiliary thin film transistor TFT' shown in FIG. Figure 4A or Figure 4B Any one of the described TFTs T1 to T7.

[0183] The second electrode layer BSM2 may be located below the sub-pixel Pa in the sensor area SA. The second electrode layer BSM2 may be located between the first buffer layer 111a and the second buffer layer 111b. The second electrode layer BSM2 may include a conductive material including Mo, Al, Cu, or Ti and may be formed as a single layer or multiple layers.

[0184] The second electrode layer BSM2 may be connected to the driving voltage line PL through a second contact hole C2. The driving voltage line PL may be located on the interlayer insulating layer 115, and the second contact hole C2 may be provided to penetrate the interlayer insulating layer 115, the second gate insulating layer 113, the first gate insulating layer 112, and the second buffer layer 111b.

[0185] The first electrode layer BSM1 may be located below the bypass line portion DW in the sensor area SA. The first electrode layer BSM1 may be located between the first buffer layer 111a and the second buffer layer 111b. The first electrode layer BSM1 may include a conductive material including Mo, Al, Cu, or Ti, and may be formed as a single layer or as a multilayer. The bypass line portion DW may include an initialization voltage line VL, a previous scan line SL-1, a scan line SL, and an emission control line EL. In the accompanying drawings, the initialization voltage line VL is located on the planarization layer 117 (which is the same layer as the pixel electrode 210), but the present disclosure is not limited thereto. The initialization voltage line VL may be located on the first gate insulating layer 112 or the second gate insulating layer 113, and various modifications are possible.

[0186] The first electrode layer BSM1 may be positioned to cover the gaps between the lines included in the bypass line portion DW. The first electrode layer BSM1 may be positioned to correspond to the plurality of bypass line portions DW and to the gaps therebetween. That is, the plurality of bypass line portions DW may correspond to the first electrode layer BSM1.

[0187] The first electrode layer BSM1 may be connected to the scan line SL through a first contact hole C1. The scan line SL may be located on the first gate insulating layer 112. The first contact hole C1 may be provided to penetrate the first gate insulating layer 112 and the second buffer layer 111b.

[0188] The sensor area SA has a transmission portion TA. The planarization layer 117 may have a first transmission opening 117OP, and the pixel defining layer 119 may have a second transmission opening 119OP2 to correspond to the transmission portion TA.

[0189] Therefore, the first buffer layer 111a, the second buffer layer 111b, the first gate insulating layer 112, the second gate insulating layer 113, the interlayer insulating layer 115, and the counter electrode 230 may be stacked on the transmission portion TA. In addition, the organic layer (e.g., hole transport layer, hole injection layer, electron transport layer, electron injection layer, etc.) formed on the entire surface of the substrate 100 in the intermediate layer 220 may be further located between the interlayer insulating layer 115 and the counter electrode 230 in the transmission portion TA. In addition, referring to Figure 2 The depicted thin film encapsulation layer 300 or sealing substrate may be located on the counter electrode 230 .

[0190] In some embodiments, the counter electrode 230 may be removed to correspond to the transmissive portion TA. In another embodiment, the inorganic insulating layer (i.e., the first buffer layer 111a, the second buffer layer 111b, the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115) may all be removed to correspond to the transmissive portion TA. In this case, when the contact holes C1 and C2 are formed, the inorganic insulating layer may be removed by the same etching process.

[0191] exist Figure 9 In the embodiment, the electrode layer is not located below the main thin film transistor TFT in the display area DA, but the disclosure is not limited thereto. Figure 10 As shown in FIG, the third electrode layer BSM3 may be located below the main thin film transistor TFT. The third electrode layer BSM3 may be formed of the same material as the first electrode layer BSM1 and the second electrode layer BSM2 and may be located on the same layer as the first electrode layer BSM1 and the second electrode layer BSM2.

[0192] The third electrode layer BSM3 may not be positioned to correspond to the entire main pixel Pm, but may be positioned to correspond to the lower portion of a given TFT. For example, the third electrode layer BSM3 may be positioned to correspond to the reference pixel Pm. Figure 4BIn the TFTs described above, the third electrode layer BSM3 corresponds to the driving TFT T1, the compensation TFT T3, or the first initialization TFT T4. In some embodiments, the third electrode layer BSM3 positioned corresponding to one TFT can be connected to the gate electrode of the TFT and can be used as one of the dual gate electrodes. However, the disclosure is not limited thereto. In another embodiment, the third electrode layer BSM3 can be connected to a line to which a constant voltage is applied, such as the driving voltage line PL. In another embodiment, the third electrode layer BSM3 can correspond to one primary pixel Pm or to multiple primary pixels Pm.

[0193] The third electrode layer BSM3 may be introduced to stabilize characteristics of a TFT included in the main pixel Pm.

[0194] Figure 11 is a schematic plan view illustrating an arrangement of a wire bypassing a transmissive portion in a sensor region and a first electrode layer according to another embodiment. Figure 12 It is along Figure 11 Schematic cross-sectional view taken along line V-V'.

[0195] Reference Figure 11 and Figure 12 The first electrode layer BSM1 is positioned to overlap the spacing between the plurality of first lines. The first electrode layer BSM1 may include a 1-1 electrode layer BSM1a and a 1-2 electrode layer BSM1b spaced apart from each other. The 1-1 electrode layer BSM1a may be positioned to cover the spacing between the previous scan line SL-1 and the scan line SL. In some embodiments, the spacing distances d1a and d1b between corresponding lines in the first lines in the second direction may be smaller than the widths Wa and Wb of the 1-1 electrode layer BSM1a and the 1-2 electrode layer BSM1b in the second direction.

[0196] The 1-2 electrode layer BSM1b may be positioned to cover the spacing region between the scan line SL and the emission control line EL, thereby blocking light incident on the spacing region so that light diffraction does not occur.

[0197] In addition, the 1-1st electrode layer BSM1a can be connected to the scan line SL through the 1-1st contact hole C1a. The 1-2nd electrode layer BSM1b can be connected to the scan line SL through the 1-2nd contact hole C1b. Therefore, the 1-1st electrode layer BSM1a and the 1-2nd electrode layer BSM1b function as part of the scan line SL, which can reduce the resistance of the line and can be advantageous in terms of RC delay.

[0198] Figure 13 and Figure 14 1 is a schematic plan view showing a portion of a sensor area according to another embodiment. Figure 13 and Figure 14 In, with Figure 7 The same reference numerals in the drawings denote the same elements, and repeated descriptions will be omitted.

[0199] Reference Figure 13 , a plurality of sub-pixels Pa surrounding the transmissive portion TA are arranged in the sensor area SA, and a line connecting the sub-pixels Pa separated by the transmissive portion TA may be arranged to bypass the transmissive portion TA.

[0200] exist Figure 7 In the embodiment, the line extending in the first direction only bypasses the upper side of the transmissive portion TA, but the disclosure is not limited thereto. Figure 13 As shown in FIG, the first lines VL, SL-1, SL, and EL extending in the first direction may extend to bypass the upper and lower sides of the transmissive portion TA, respectively. Therefore, the first electrode layer BSM1 may be positioned so that the transmissive portion TA is located therebetween. The first electrode layer BSM1 may be connected to the scan line SL through a contact hole.

[0201] exist Figure 7 In the embodiment, the data lines DL and / or the driving voltage lines PL extending in the second direction are arranged to pass through the transmissive portion TA, but the disclosure is not limited thereto. Figure 13 As shown in FIG, the data line DL and the driving voltage line PL can be arranged to bypass the left and / or right side of the transmissive portion TA. In this case, the bypassed data line DL and / or driving voltage line PL can be arranged to overlap the second electrode layer BSM2. The second electrode layer BSM2 can be connected to the driving voltage line PL through a contact hole. The second electrode layer BSM2 can overlap the entire pixel group Pg including a plurality of sub-pixels Pa. In this embodiment, the pixel group Pg can be composed of three sub-pixels Pa arranged in parallel in the first direction.

[0202] Reference Figure 14 The pixel groups Pg may be arranged in two rows. The first line connecting the sub-pixels Pa arranged in the first row 1R may bypass the upper side of the transmissive portion TA, and the first line connecting the sub-pixels Pa arranged in the second row 2R may bypass the lower side of the transmissive portion TA.

[0203] The first electrode layer BSM1 may be positioned with the transmissive portion TA therebetween. The first electrode layer BSM1 may be positioned corresponding to a first line bypassing the transmissive portion TA and may block light that would be incident on the first line. The first electrode layer BSM1 may be connected to the scan line SL.

[0204] The second electrode layer BSM2 may be positioned to overlap the plurality of data lines DL that bypass the transmissive portion TA. Since the second electrode layer BSM2 overlaps the bypassed data lines DL, the second electrode layer BSM2 may include a region protruding in the direction of the transmissive portion TA. The second electrode layer BSM2 may be connected to the driving voltage line PL.

[0205] Figure 15 and Figure 16 is a plan view showing a portion of a display panel according to another embodiment.

[0206] Reference Figure 15 , the display panel 10 ′ may further include an opening area OA.

[0207] The component 30 may be located below the opening area OA. The opening area OA may be understood as a transmissive area through which light and / or sound output from the component 30 to the outside or traveling from the outside toward the component 30 may be transmitted. In an embodiment, when light is transmitted through the opening area OA, the transmittance may be approximately 50% or greater, approximately 70% or greater, approximately 75% or greater, approximately 80% or greater, approximately 85% or greater, or approximately 90% or greater. The opening area OA may be an area in which the display element is not located and is not capable of providing an image. In the present embodiment, the opening area OA is located inside the display area DA, and the main pixels may be arranged to surround the opening area OA.

[0208] The component 20 may also be located below the sensor area SA. In addition, the sensor area SA may be provided with sub-pixels to provide a specific image.

[0209] In some embodiments, the light transmittance of the opening area OA may be greater than that of the sensor area SA. Therefore, a component 30 with high light transmittance (eg, a camera) may be located in the opening area OA, and a sensor for detecting infrared rays may be located in the sensor area SA.

[0210] Reference Figure 16 The sensor area SA of the display panel 10 ″ includes an area where the component 20 is located, and the display area DA may be located on one side of the sensor area SA. The sensor area SA may be positioned to correspond to one side of the display area DA, and a plurality of components 20 may be arranged corresponding to the sensor area SA.

[0211] In addition, the sensor area SA has the sub-pixels Pa and the transmissive portion TA, and may provide an image having a lower resolution than that of the display area DA.

[0212] The sensor area SA may include an opening area OA. The opening area OA is a region having a higher light transmittance than the sensor area SA, and the photosensitive component 30 may be located in the opening area OA. The opening area OA may be surrounded by the sub-pixels Pa and the transmissive portion TA.

[0213] According to an embodiment, the pixel portion and the transmission portion are arranged in a sensor area corresponding to a component such as a sensor, and an electrode layer arranged to correspond to the pixel portion, etc. is provided, so that an environment can be realized in which the sensor can operate and an image can be realized in an area overlapping with the component.

[0214] Therefore, a display device having various functions and improved quality can be provided. However, the above-described effects are illustrative.

[0215] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the claims and their functional equivalents to be included therein.

Claims

1. A display device, comprising: a substrate having a display area and a sensor area including a transmissive portion; a bottom metal layer disposed on the substrate in the sensor region; a thin film transistor, disposed on the bottom metal layer and comprising a semiconductor layer and a gate electrode on the semiconductor layer; as well as an organic light emitting diode electrically connected to the thin film transistor and comprising a pixel electrode, an organic emission layer and a counter electrode, wherein the bottom metal layer completely overlaps the emission region of the organic light emitting diode, and A pixel group including a plurality of sub-pixels is disposed in the sensor region, and the bottom metal layer overlaps the entire light-emitting regions of the plurality of sub-pixels in the pixel group.

2. The display device according to claim 1, wherein The transmission portion and the pixel group are provided in plural numbers, and the transmission portion and the pixel group are alternately arranged.

3. The display device according to claim 1, wherein The bottom metal layer includes an opening corresponding to the transmission portion.

4. The display device according to claim 1 , further comprising a plurality of first lines arranged in the sensor area and extending in a first direction, in, The plurality of first lines are arranged to go around along an edge of the transmissive portion.

5. The display device according to claim 4, wherein At least some of the plurality of first lines overlap the bottom metal layer. The display device according to claim 4 , wherein: The plurality of first lines include scan lines, emission control lines, and initialization voltage lines.

7. The display device according to claim 4, further comprising a driving voltage line extending in a second direction crossing the first direction, in, The bottom metal layer is connected to the driving voltage line through a contact hole.

8. The display device according to claim 4, further comprising a plurality of second lines extending in a second direction intersecting the first direction, in, The plurality of second lines are arranged to go around along an edge of the transmissive portion.

9. The display device according to claim 8, wherein At least some of the plurality of second lines overlap the bottom metal layer.

10. The display device according to claim 8, wherein The plurality of second lines include data lines and driving voltage lines.

11. The display device according to claim 8, wherein The transmission portion is surrounded by at least a portion of the plurality of first lines, the plurality of second lines, and the bottom metal layer.

12. The display device according to claim 1, wherein The resolution of the image provided by the sensor area is smaller than the resolution of the image provided by the display area. 13 . The display device according to claim 1 , further comprising a component corresponding to the sensor area on a lower surface of the substrate.

14. The display device according to claim 1, further comprising an electrode layer provided on the display area, wherein: The electrode layer overlaps the main thin film transistor on the display area, and the electrode layer is disposed between the substrate and the main thin film transistor.

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