Display device

Abstract

Disclosed is a display device having a display area and a frame area defined therein. The display device includes: a display panel including an active area, a peripheral area, and pixels, wherein an image is displayed in the active area, the peripheral area being adjacent to the active area, the pixels including a pixel circuit and a light-emitting layer, the pixel circuit defining a stacked structure; a window; and a pattern film located between the display panel and the window, the pattern film including a first film and a pattern layer, the first film including a first area and a second area corresponding to the display area and the frame area of ​​the display device, respectively, the pattern layer being located on the second film in the second area of ​​the second film. The pattern layer of the pattern film includes a stacked structure identical to the stacked structure defined by the pixel circuit of the display panel.

Description

[0001] This application claims priority to and all benefits of Korean Patent Application No. 10-2019-0036194, filed on March 28, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0002] The present disclosure relates to a display device having a frame area. Background Art

[0003] A display device displays various images on a display screen to provide information to a user. The display device includes a display area where the images are displayed and a frame area adjacent to the display area. The frame area of ​​the display device may have a predetermined color, and the display device includes a printed layer disposed in the frame area to provide the predetermined color. Summary of the Invention

[0004] The present disclosure provides a display device in which a distinction between a display area and a bezel area is minimized when an image is not displayed.

[0005] An embodiment of the invention provides a display device in which a display area and a frame area are defined. The display device includes: a display panel including an active area and a peripheral area, an image is displayed in the active area, and the peripheral area is adjacent to the active area; a first film corresponding to the active area and the peripheral area; and pixels located on the first film, the pixels including a pixel circuit and a light-emitting layer, the pixel circuit defining a stacked structure; a window; and a pattern film located between the display panel and the window, the pattern film including: a second film including a first area and a second area corresponding to the display area and the frame area of ​​the display device, respectively; and a pattern layer located on the second film in the second area of ​​the second film. The pattern layer of the pattern film includes a stacked structure identical to the stacked structure defined by the pixel circuit of the display panel.

[0006] The display device may further include a polarizing film disposed between the window and the pattern film, the polarizing film corresponding to the first and second regions of the pattern film.

[0007] The display panel may further include dummy pixels, and the dummy pixels include dummy pixel circuits and dummy light emitting layers.

[0008] The pixels of the display panel may correspond to an active area of ​​the display panel, and the dummy pixels may correspond to a peripheral area of ​​the display panel.

[0009] The dummy pixel may be provided in plurality, and the dummy pixel includes a plurality of dummy pixels corresponding to the first region and the second region of the pattern film, respectively.

[0010] The pattern layer may be disposed between the window and the second film.

[0011] The pattern layer may be disposed between the second film and the display panel.

[0012] The pattern layer may include a first sub-pattern layer disposed on the first film and a second sub-pattern layer disposed on the first sub-pattern layer, the first sub-pattern layer may have the same stacking structure as the pixel circuit, and the second sub-pattern layer may include the same material as the light emitting layer.

[0013] The display panel may further include a thin film encapsulation layer covering the light emitting layer.

[0014] The pattern layer may include a first sub-pattern layer disposed on the first film and a second sub-pattern layer disposed on the first sub-pattern layer, the first sub-pattern layer may have the same stacking structure as the pixel circuit, and the second sub-pattern layer may have the same stacking structure as the thin film encapsulation layer.

[0015] The pattern layer may include a first sub-pattern layer arranged on the first film, a second sub-pattern layer arranged on the first sub-pattern layer, and a third sub-pattern layer arranged on the second sub-pattern layer, the first sub-pattern layer may have the same stacking structure as the pixel circuit, the second sub-pattern layer may include the same material as the light-emitting layer, and the third sub-pattern layer may have the same stacking structure as the thin film encapsulation layer.

[0016] The display device may further include a colored adhesive layer disposed under the display panel.

[0017] The display device may further include an input sensing layer disposed between the display panel and the first film.

[0018] Reflectivity and transmittance of external light incident to the display device at the display region may be equal to reflectivity and transmittance of external light incident to the display device at the bezel region, respectively.

[0019] An embodiment of the invention provides a display device in which a display area and a frame area are defined. The display device includes: a display panel including an active area where an image is displayed and a peripheral area adjacent to the active area; a window; and a pattern film located between the display panel and the window, the pattern film including: a first film including a transmissive area corresponding to the display area of ​​the display device; and a pattern layer located on the first film and corresponding to the frame area of ​​the display device. The reflectivity of external light incident on the display device at the area corresponding to the display area is equal to the reflectivity of external light incident on the display device at the area corresponding to the frame area.

[0020] The display panel may also include a second film corresponding to the active area and the peripheral area and pixels located on the second film, the pixels including a pixel circuit and a light-emitting layer, the pixel circuit defines a stacked structure, and the pattern layer may include a first sub-pattern layer having the same stacked structure as the pixel circuit.

[0021] The pattern layer further includes a second sub-pattern layer, which is disposed on the first sub-pattern layer and has the same stacking structure as the light-emitting layer.

[0022] The display device may further include an encapsulation layer covering the pixels, and the pattern layer may further include a second sub-pattern layer disposed on the first sub-pattern layer and having the same stacking structure as the encapsulation layer.

[0023] The display device may further include a polarizing film disposed between the window and the pattern film, and a plane area of ​​the polarizing film may be equal to a plane area of ​​the window.

[0024] The display panel may further include a plurality of dummy pixels, each of which includes a dummy pixel circuit and a dummy light-emitting layer. The pixels of the display panel may correspond to an effective area of ​​the display panel, and the dummy pixels may correspond to both the transmission area and the pattern layer.

[0025] According to the above, the pattern layer defines the border area of ​​the display device and can have the same stacking structure and layout as the stacking structure and layout of the components within the display panel. The pattern layer can be provided or formed by the same process as the components used to manufacture the display panel and by using the same material or the same material layer applied to the display panel for forming such components. Therefore, the reflectivity difference and transmittance difference of the external light incident on the display device at the area corresponding to the display panel and the pattern film in which the pattern layer is provided can be reduced. Therefore, a display device can be provided in which the difference between the display area and the border area is minimized when no image is displayed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other advantages of the present disclosure will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a top view showing an exemplary embodiment of a display device;

[0028] Figure 2 is a cross-sectional view illustrating an exemplary embodiment of a display device;

[0029] Figure 3 is a cross-sectional view illustrating another exemplary embodiment of a display device;

[0030] Figure 4 is a cross-sectional view illustrating yet another exemplary embodiment of a display device;

[0031] Figure 5A is a cross-sectional view illustrating an exemplary embodiment of a display module;

[0032] Figure 5Bis a cross-sectional view illustrating another exemplary embodiment of a display module;

[0033] Figure 6 is a top view illustrating an exemplary embodiment of a display panel;

[0034] Figure 7 is an enlarged cross-sectional view illustrating an exemplary embodiment of a portion of a display device;

[0035] Figure 8 is an equivalent circuit diagram illustrating an exemplary embodiment of a pixel;

[0036] Figure 9 is an enlarged cross-sectional view showing an embodiment of a display panel;

[0037] Figure 10 is an enlarged cross-sectional view illustrating an exemplary embodiment of a pattern film;

[0038] Figure 11 is an enlarged cross-sectional view showing another exemplary embodiment of a pattern film;

[0039] Figure 12 is an enlarged cross-sectional view illustrating yet another exemplary embodiment of a pattern film; and

[0040] Figure 13 is an enlarged cross-sectional view illustrating still another exemplary embodiment of a pattern film. DETAILED DESCRIPTION

[0041] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals represent like elements throughout. In the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively depicting the technical content.

[0042] In the following description, it will be understood that when an element or layer is referred to as being associated with another element (such as being “on,” “connected to,” or “coupled to” another element or layer), the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being directly associated with another element (such as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer), there are no intervening elements or layers present.

[0043] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0044] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. "At least one" is not to be construed as limited to "one" or "an." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] For ease of description, spatially relative terms such as "under," "beneath," "down," "over," "up," etc. may be used herein to describe the relationship of one element or feature to another element or features as shown in the figures.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0047] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with measuring the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] It will also be understood that when the terms “comprises,” “includes,” and / or variations thereof are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, nor are they intended to limit the scope of the claims presented.

[0050] Hereinafter, the present disclosure will be explained in detail with reference to the accompanying drawings.

[0051] Figure 1 is a top view illustrating an exemplary embodiment of a display device DD.

[0052] Reference Figure 1 , the display device DD can be a device that is activated in response to an electrical signal. The activation of the display device DD can generate light and / or emit light, generate an image and / or display an image to the outside of the display device DD via the display screen of the display device DD. The display device DD may include various embodiments. In an exemplary embodiment, for example, the display device DD can be applied to relatively large-sized electronic items such as televisions, display monitors, or outdoor billboards, as well as relatively small and medium-sized electronic items such as personal computers, notebook computers, personal digital assistants, car navigation units, game units, mobile electronic devices, and cameras. These are merely exemplary, and thus the display device DD can be applied to other electronic devices without departing from the concept of the present disclosure. In this exemplary embodiment, a tablet computer will be described as a representative example of the display device DD.

[0053] The display device DD may include a display area DA-D and a frame area NDA-D. An image may be displayed in the display area DA-D. The image may not be displayed in the frame area NDA-D, but is not limited thereto or thereby. The display device DD may include or define a surface substantially parallel to a plane defined by a first direction DR1 and a second direction DR2 that intersect each other. The display device DD may display an image IM toward a third direction DR3 such that the image IM is visible from outside the display device DD. The image IM may include a moving (e.g., dynamic) image and a still image. Figure 1A clock window and an icon are shown as representative examples of the image IM. The bezel area NDA-D is adjacent to the display area DA-D. In an exemplary embodiment, the bezel area NDA-D may surround the display area DA-D in a top view. The image IM is not displayed in the bezel area NDA-D. The display area DA-D may be defined by the bezel area NDA-D. The display area DA-D and the bezel area NDA-D may define the total planar area of ​​the display device DD in a top view, without limitation.

[0054] In this exemplary embodiment, the front (or upper) surface and the rear (or lower) surface of each component of the display device DD are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface face each other along a third direction DR3, and the normal direction of each of the front surface and the rear surface is substantially parallel to the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative to each other, and thus the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be changed to other directions. In the following description, the expression "when viewed in a plan view" may represent a state of viewing along the third direction DR3.

[0055] The display device DD may include electronic modules. When viewed in plan, the electronic modules may overlap the bezel areas NDA-D. However, this is merely exemplary, and the present disclosure should not be limited thereto or thereby. In an exemplary embodiment, for example, when viewed in plan, some electronic modules may overlap the display areas DA-D.

[0056] The electronic modules may include: a camera module for capturing external images; a proximity illuminance sensor module for measuring the illuminance of the environment outside the display device DD and the proximity of objects in that environment; an infrared light emitting module for outputting infrared light from the display device DD; and a light receiving module for sensing infrared light. In exemplary embodiments of the present disclosure, in addition to the electronic modules mentioned above, the display device DD may further include a sound output module for outputting sound from the display device DD or a heat sensing module for sensing heat. In exemplary embodiments, at least one of the electronic modules may be omitted.

[0057] Figure 2 is a cross-sectional view illustrating an exemplary embodiment of a display device DD-1. Figure 2 A cross section defined by the second direction DR2 and the third direction DR3 is shown. Figure 2 It is shown in a simplified manner to illustrate the stacking relationship of the functional components of the display device DD-1.

[0058] Reference Figure 2, the display device DD-1 may include a window WD, a polarizing film POL, a pattern film FF, a display module DM, an adhesive layer PSA, and a board SUS.

[0059] The window WD and the polarizing film POL, the polarizing film POL and the pattern film FF, and the pattern film FF and the display module DM can be bonded to each other by adhesive members OCA (e.g., multiple adhesive members OCA). The adhesive member OCA can include a conventional adhesive or a pressure-sensitive adhesive. In an exemplary embodiment, for example, the adhesive member OCA can be an optically clear adhesive.

[0060] The window WD may be a layer that provides the outermost surface of the display device DD-1. The window WD may include a glass substrate, a synthetic resin film, or a composite film. The window WD may also include a functional coating. The functional coating may include an anti-fingerprint layer, an anti-reflection layer, and a relatively hard coating.

[0061] The polarizing film POL may be disposed below the window WD. The polarizing film POL may reduce the amount of light from outside the display device DD-1 (eg, Figure 2 The reflectivity of external light incident on the polarizing film POL (above the window WD in the image).

[0062] The polarizing film POL according to an exemplary embodiment of the present disclosure may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be a film type and may include a stretched synthetic resin film. The retarder and polarizer may further include a protective film. The retarder and polarizer together, or the protective film alone, may be defined as the base layer of the polarizing film POL.

[0063] When viewed in a plan view, the polarizing film POL may have a plane area substantially the same as that of the window WD. The aforementioned plane area may be the total plane area of ​​the various components, without being limited thereto. In an exemplary embodiment, for example, the polarizing film POL may be Figure 1 The display area DA-D and the frame area NDA-D shown in FIG are overlapped. Since the polarizing film POL is attached to the entire surface of the window WD, when the image IM is not displayed at the display area DA-D (refer to FIG. Figure 1 ), the difference in the boundary between the display area DA-D and the frame area NDA-D can be reduced.

[0064] The pattern film FF may be disposed under the polarizing film POL. The pattern film FF may include a first film FL1 (eg, a first substrate FL1) and a pattern layer PL (eg, a light shielding pattern PL).

[0065] The first film FL1 may include or define a first area AR1 and a second area AR2 adjacent to the first area AR1 (such as surrounding the first area AR1 in a plan view), without being limited thereto. The first area AR1 may correspond to Figure 1 The display area DA-D, the second area AR2 may correspond to Figure 1 The first area AR1 may be a transmissive area of ​​the display device DD, through which light and / or images from the display module DM are transmissive, and the second area AR2 may be a light-shielding area of ​​the display device DD, through which light from the display module DM is non-transmissive (e.g., shielded). The first film FL1 may be, but is not limited to, a plastic film. In an exemplary embodiment, the first film FL1 may include, for example, a polyimide resin.

[0066] The pattern layer PL may be provided on a surface of the first film FL1. In an exemplary embodiment, for example, the surface may be the upper surface of the first film FL1 facing the window WD. Therefore, the pattern layer PL may be provided between the window WD and the first film FL1 along the thickness direction of the display device DD-1 (e.g., the third direction DR3).

[0067] The pattern layer PL may partially overlap the first film FL1. The pattern layer PL may be disconnected along the first film FL1 (e.g., along the first direction DR1 and / or the second direction DR2). When viewed in a plan view, the pattern layer PL may overlap the second area AR2 and may not overlap the first area AR1. That is, the border area NDA-D (refer to Figure 1 ) may correspond to the pattern layer PL and / or be defined by the pattern layer PL.

[0068] According to exemplary embodiments of the present disclosure, the reflectivity difference between the regions of the display device DD-1 corresponding to the pattern layer PL and the display panel DP of the display module DM, as well as the transmittance difference between the regions of the display device DD-1 corresponding to the pattern layer PL and the display panel DP of the display module DM, can be reduced. Therefore, when the display module DM is not providing an image, the distinction between the boundary between the first area AR1 and the second area AR2 can be minimized. A detailed description of this will be provided later.

[0069] The display module DM may be disposed below the pattern film FF. The display module DM may generate and / or display an image. Furthermore, the display module DM may sense external input incident upon the display module DM or upon the display device DD-1. The external input may be user input incident upon the display device DD-1 using an input tool such as a part of the user's body, light, heat, a pen, or pressure.

[0070] An adhesive layer PSA may be provided below the display module DM. The adhesive layer PSA may be colored, such as by including a colored dye (e.g., a colored adhesive layer PSA). The colored adhesive layer PSA is provided facing the pattern film FF, and the display panel DP is provided between the colored adhesive layer PSA and the pattern film FF. In an embodiment, for example, the adhesive layer PSA may be a pressure-sensitive adhesive including a black dye. Light incident on the adhesive layer PSA may be absorbed by the adhesive layer PSA. Thus, reflection of incident light from outside the display device DD may be reduced or effectively prevented. The colored dye may be combined with the base material or matrix of the adhesive layer PSA to provide it with color.

[0071] The SUS plate may be disposed below the adhesive layer PSA. The SUS plate may include a material having relatively higher rigidity than the display module DM. In an exemplary embodiment, for example, the SUS plate may include multiple frames and / or multiple plates, and the multiple frames and / or multiple plates may include glass, plastic, metal alloy, or a combination thereof.

[0072] Figure 3 is a cross-sectional view illustrating another exemplary embodiment of a display device DD-2.

[0073] Reference Figure 3 , the display device DD-2 may include a window WD, a polarizing film POL, a pattern film FFa, a display module DM, an adhesive layer PSA, and a board SUS.

[0074] The pattern film FFa may include a first film FL1 and a pattern layer PL. The pattern layer PL may be disposed on a surface of the first film FL1. In an exemplary embodiment, for example, the surface may be the bottom surface of the first film FL1 facing the display module DM. Thus, the pattern layer PL may be disposed between the first film FL1 and the display module DM.

[0075] Figure 4 is a cross-sectional view showing still another exemplary embodiment of the display device DD-3.

[0076] Reference Figure 4 The display device DD-3 may include a window WD, a pattern film FF, a polarizing film POL, a display module DM, an adhesive layer PSA, and a plate SUS. The pattern film FF may be disposed under the window WD, and the polarizing film POL may be disposed under the pattern film FF.

[0077] Reference Figure 1 The display device DD described may be a reference Figures 2 to 4 Any of the described display device DD-1, display device DD-2, and display device DD-3.

[0078] Figure 5Ais a cross-sectional view illustrating an exemplary embodiment of a display module DM- 1 . Figure 5B is a cross-sectional view illustrating another exemplary embodiment of a display module DM- 2 . Figures 2 to 4 The display module DM described in the embodiment may include Figure 5A Display module DM-1 or Figure 5B Display module DM-2.

[0079] Reference Figure 5A The display module DM-1 may include a display panel DP, an adhesive member OCA, and an input sensing panel ISP. The display panel DP and the input sensing panel ISP may be coupled to each other via the adhesive member OCA.

[0080] The display panel DP may be a light-emitting display panel, but is not particularly limited thereto. In exemplary embodiments, for example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, an organic light-emitting display panel will be described as a representative example of a display panel DP.

[0081] The input sensing panel ISP may be disposed on the display panel DP, and an adhesive member OCA may be disposed between the input sensing panel ISP and the display panel DP to attach the two components to each other. The input sensing panel ISP may include a plurality of insulating layers and a plurality of conductive layers. The conductive layers may form sensing electrodes, sensing lines connected to the sensing electrodes, and sensing pads (or "pads") connected to the sensing lines, and the display module DM-1 may sense external inputs through the sensing electrodes. The input sensing panel ISP may sense external inputs in a mutual capacitance manner and / or a self-capacitance manner, however, the sensing manner for external inputs should not be limited thereto or subject to such limitations.

[0082] Reference Figure 5B , the display module DM-2 may include a display panel DP and an input sensing layer ISL. The input sensing layer ISL may be directly disposed on the display panel DP. In the following description, the statement that component "B" is directly disposed on component "A" indicates that there is no intermediate element such as an adhesive layer / adhesive member between component "B" and component "A". This direct relationship may be used to distinguish between a "layer" and a "panel". In an exemplary embodiment, the "layer" may include component "B", which is formed on a substrate surface provided by component "A" through a continuous process after component "A" is formed.

[0083] Figure 6 is a top plan view illustrating an exemplary embodiment of the display panel DP. Figure 7 2 is an enlarged cross-sectional view showing part of the display device DD including the display panel DP.

[0084] Reference Figure 6 and Figure 7 The display panel DP may include a second film FL2 (eg, a second substrate FL2) and a plurality of pixels PX (eg, a plurality of pixels PX) disposed on the second film FL2. At the pixels PX, light may be emitted, an image may be generated, and / or an image may be displayed.

[0085] The second film FL2 can be a relatively rigid film or a relatively flexible film. The second film FL2 can be a glass substrate or a plastic substrate. The plastic substrate can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin. As an example, the second film FL2 can include a single layer structure of polyimide resin, however, the present invention is not limited to this. In other words, the second film FL2 can have a stacked structure including multiple insulating layers.

[0086] The display panel DP may include or define an active area AA and a peripheral area NAA adjacent to the active area AA (such as surrounding the active area AA in a top view). The active area AA may provide an image through the pixels PX. That is, the image may be displayed in the active area AA. The image may not be displayed in the peripheral area NAA, but is not limited thereto or thereby.

[0087] Figure 6 The boundary BD-W (hereinafter, referred to as “pattern boundary”) and the boundary BD-P (hereinafter, referred to as “effective boundary”) are shown. The boundary BD-W is located in the first area AR1 of the first film FL1 (refer to FIG. Figure 2 ) and the second area AR2 (refer to Figure 2 ), the boundary BD-P is located between the active area AA and the peripheral area NAA of the display panel DP. The pattern boundary BD-W may correspond to the display area DA-D (refer to Figure 1 ) and the border area NDA-D (refer to Figure 1 That is, the first area AR1 of the first film FL1 includes a portion of the peripheral area NAA of the display panel DP.

[0088] When viewed in plan, the pattern boundary BD-W may not overlap the active boundary BD-P. In an exemplary embodiment, for example, the active boundary BD-P may be surrounded by the pattern boundary BD-W. Since the first area AR1 is a transmissive area, a portion of the peripheral area NAA and the entire active area AA may be identified through the first area AR1.

[0089] According to an exemplary embodiment of the present disclosure, the display panel DP may further include a plurality of dummy pixels D-PX (e.g., a plurality of dummy pixels D-PX). The dummy pixels D-PX may be arranged in the peripheral area NAA. When viewed in a plan view, some of the dummy pixels D-PX may be located in the second area AR2 (e.g., overlapping with the second area AR2), and other dummy pixels D-PX may be located in the first area AR1 (e.g., overlapping with the first area AR1). That is, some of the dummy pixels D-PX may be covered by the pattern layer PL. In addition, a portion of the peripheral area NAA in which the dummy pixels D-PX are not arranged or excluded may be covered by the pattern layer PL. Such a portion includes a plane area between the dummy pixels D-PX adjacent to each other along the first direction DR1 and / or the second direction DR2.

[0090] The dummy pixel D-PX may not emit light, may not generate an image, and may not display an image, but may include a stacking structure and layout that is the same as the stacking structure and layout of the pixel PX. Therefore, the reflectivity and transmittance of light incident on the display device DD at the active area AA of the display panel DP through the stacking structure and layout may be substantially the same as the reflectivity and transmittance of light incident on the display device DD at the peripheral area NAA of the display panel DP. According to an exemplary embodiment of the present disclosure, since the reflectivity and transmittance in the active area AA are substantially the same as the reflectivity and transmittance in the peripheral area NAA, the effective boundary BD-P is not recognized when the display panel DP does not display an image. In the present disclosure, the layout may refer to the arrangement relationship of the conductive wiring and the pattern when the display panel DP is viewed in a plan view.

[0091] In this disclosure, the phrase "the transmittance is the same" may be interpreted as meaning substantially the same. The phrase "the reflectance is the same" may be interpreted as meaning substantially the same. In exemplary embodiments, for example, the transmittance may be the same within a predetermined deviation. Furthermore, the reflectance may be the same within a predetermined deviation. The predetermined deviation may be within approximately 5%. The numerical values ​​given as the predetermined deviation are merely exemplary, and the predetermined deviation should not be limited to or constrained thereby.

[0092] Figure 8 is an equivalent circuit diagram illustrating an exemplary embodiment of a pixel PX.

[0093] Reference Figure 8 The pixel PX is arranged in the active area AA of the display panel DP (refer to Figure 6 ) and is an element through which light can be emitted, images can be generated and / or images can be displayed.

[0094] The pixel PX can be electrically connected to a plurality of signal lines. Figure 8The signal lines include scan lines SLi and SLi-1, a data line DL, a first power line PL1, a second power line PL2, an initialization power line VIL, and a light emission control line ECLi. Figure 8 Various signal lines not shown in the example. Can be omitted Figure 8 Some of the signal lines shown in .

[0095] The pixel PX may include a light emitting element LD and a pixel circuit CC connected to the light emitting element LD. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The pixel circuit CC may control the amount of current flowing through the light emitting element LD in response to an electrical signal such as a data signal.

[0096] The light emitting element LD may generate light and / or emit light with a predetermined brightness in response to the amount of current supplied from the pixel circuit CC. To this end, the first power source ELVDD may have a level set higher than that of the second power source ELVSS.

[0097] Each of the transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In the following description, for ease of explanation, one of the input electrode and the output electrode may be referred to as a "first electrode," and the other of the input electrode and the output electrode may be referred to as a "second electrode."

[0098] A first electrode of the first transistor T1 is connected to a first power line PL1 via a fifth transistor T5. The first power line PL1 may be a line to which a first power source ELVDD is applied. A second electrode of the first transistor T1 is connected to an anode electrode of the light-emitting element LD via a sixth transistor T6. In the present disclosure, the first transistor T1 may be referred to as a "driving transistor."

[0099] The first transistor T1 controls the amount of current flowing through the light emitting element LD in response to a voltage applied to a control electrode of the first transistor T1 .

[0100] The second transistor T2 is connected between the data line DL and the first electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the i-th scan line SLi. When the i-th scan signal is applied to the i-th scan line SLi, the second transistor T2 is turned on and electrically connects the data line DL to the first electrode of the first transistor T1.

[0101] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line SLi. When the i-th scan signal is applied to the i-th scan line SLi, the third transistor T3 is turned on and electrically connects the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode configuration.

[0102] The fourth transistor T4 is connected between the node ND and the initialization power line VIL. The control electrode of the fourth transistor T4 is connected to the (i-1)th scan line SLi-1. The node ND may be the node at which the fourth transistor T4 is connected to the control electrode of the first transistor T1. When the (i-1)th scan signal is applied to the (i-1)th scan line SLi-1, the fourth transistor T4 is turned on and provides the initialization voltage Vint to the node ND.

[0103] The fifth transistor T5 is connected between the first power line PL1 and the first electrode of the first transistor T1.

[0104] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element LD. The control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 are connected to the i-th light emission control line ECLi.

[0105] The seventh transistor T7 is connected between the initialization power line VIL and the anode electrode of the light-emitting element LD. The control electrode of the seventh transistor T7 is connected to the i-th scan line SLi. When the i-th scan signal is applied to the i-th scan line SLi, the seventh transistor T7 is turned on and provides the initialization voltage Vint to the anode electrode of the light-emitting element LD.

[0106] The seventh transistor T7 can improve the black rendering capability of the pixel PX. Specifically, when the seventh transistor T7 is turned on, the parasitic capacitance (not shown) of the light-emitting element LD is discharged. Therefore, when black brightness is implemented, the light-emitting element LD does not emit light due to the leakage of current from the first transistor T1, thereby improving the black rendering capability.

[0107] In addition, Figure 8 In the embodiment, the control electrode of the seventh transistor T7 is connected to the i-th scan line SLi, however, it should not be limited thereto or thereby. According to another embodiment, the control electrode of the seventh transistor T7 may be connected to the i-1-th scan line SLi-1 or the i+1-th scan line (not shown).

[0108] Figure 8A PMOS is shown as a reference for the pixel circuit CC, however, it should not be limited thereto or thereby. According to another embodiment, the pixel circuit CC may be implemented by an NMOS. According to another embodiment, the pixel circuit CC may be implemented by a combination of an NMOS and a PMOS.

[0109] The capacitor CP is provided between the first power line PL1 and the node ND. The capacitor CP is charged with a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on by the voltage charged in the capacitor CP, the amount of current flowing through the first transistor T1 can be determined.

[0110] The light emitting element LD may be electrically connected to the sixth transistor T6 and the second power line PL2 , and may receive the second power source ELVSS via the second power line PL2 .

[0111] The light emitting element LD may generate light and / or emit light using a voltage corresponding to a difference between an electric signal provided through the sixth transistor T6 and a second power source ELVSS provided through the second power line PL2 .

[0112] In the present disclosure, the structure of the pixel PX should not be limited to Figure 8 According to another embodiment of the present disclosure, the pixel PX may be implemented in various ways to allow the light emitting element LD to generate light and / or emit light.

[0113] In addition, the dummy pixel D-PX (refer to Figure 7 ) may include Figure 8 That is, the dummy pixel D-PX may include the same equivalent circuit as the pixel PX described above. Figure 8 The layout of the conductive wiring and pattern arrangement of the pixel PX described in the preceding embodiment is similar to that of the embodiment of the present invention. In an exemplary embodiment, for example, the dummy pixel D-PX may include a dummy pixel circuit and a dummy light-emitting element. The dummy pixel circuit may correspond to the pixel circuit CC, and the dummy light-emitting element may correspond to the light-emitting element LD. The dummy pixel circuit may define a dummy stacked structure of the display panel DP, and the pixel circuit CC may define a stacked structure of the display panel DP.

[0114] Figure 9 is an enlarged cross-sectional view showing an embodiment of the display panel DP. Figure 9 The arrangement relationship of the conductive wirings and patterns in FIG. 1 may be included in the pixel PX, but is not limited thereto.

[0115] Reference Figure 9 The first insulating layer 10 may be disposed on the second film FL2. The first insulating layer 10 may include a barrier layer 11 and a buffer layer 12.

[0116] The barrier layer 11 may include an inorganic material. The barrier layer 11 may reduce or effectively prevent oxygen or moisture flowing through the second film FL2 from entering the pixel PX defined on the second film FL2 (refer to FIG. Figure 6 ) and dummy pixel D-PX (refer to Figure 6 ).

[0117] The buffer layer 12 may include an inorganic material and may provide the pixel PX with surface energy lower than that of the second film FL2 so that the pixel PX is stably disposed or formed on the second film FL2.

[0118] exist Figure 9 In the embodiment, each of the barrier layer 11 and the buffer layer 12 is shown as being provided as a single layer, however, this is merely exemplary. Each of the barrier layer 11 and the buffer layer 12 may be provided as a plurality, and the barrier layer 11 and the buffer layer 12 may be alternately stacked. As another exemplary embodiment, at least one of the barrier layer 11 and the buffer layer 12 may be provided as a plurality or may be omitted.

[0119] Pixel PX (refer to Figure 6 ) each pixel PX may include a pixel circuit CC (refer to Figure 8 ) and light-emitting layer EML. Figure 9 Only one transistor TR is shown. The transistor TR may correspond to Figure 8 The sixth transistor T6 described in .

[0120] The transistor TR may be disposed on the first insulating layer 10. The transistor TR may include a semiconductor pattern SP, a control electrode CNE, a first electrode ET1, and a second electrode ET2. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material. The control electrode CNE may be spaced apart from the semiconductor pattern SP, with a second insulating layer 20 interposed therebetween.

[0121] The first electrode ET1 and the second electrode ET2 may be connected to opposite sides of the semiconductor pattern SP by respectively passing through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 at contact holes in the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. The transistor TR according to the exemplary embodiment of the present disclosure may be implemented in various stacked structures and should not be limited to Figure 9 The structure shown in .

[0122] The upper electrode UE may be provided between the third insulating layer 30 and the fourth insulating layer 40. The upper electrode UE may be connected to Figure 8 The electrodes of the capacitor CP described in .

[0123] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the first and second electrodes ET1 and ET2. The fifth insulating layer 50 may include an organic material and / or an inorganic material and may have a single layer structure or a multi-layer structure.

[0124] The pixel electrode PE may be disposed on the fifth insulating layer 50. The pixel electrode PE may be electrically connected to the transistor TR by passing through the fifth insulating layer 50 at a contact hole in the fifth insulating layer 50.

[0125] In the present disclosure, the structure from the first insulating layer 10 to the pixel electrode PE may be referred to as a "pixel circuit layer PX-CL". Figure 8 ) may correspond to the cross-sectional structure of the pixel circuit layer PX-CL.

[0126] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. An opening may be defined by the sixth insulating layer 60, and at least a portion of the pixel electrode PE may be exposed through the opening. The sixth insulating layer 60 may be referred to as a "pixel defining layer." The opening in the sixth insulating layer 60 may correspond to the light emitting region of the pixel PX, but is not limited thereto.

[0127] The light-emitting layer EML may be disposed on the pixel electrode PE exposed through the opening defined by the sixth insulating layer 60. The light-emitting layer EML may include a light-emitting material. In an exemplary embodiment, for example, the light-emitting layer EML may include at least one material selected from materials that emit red light, green light, and blue light, respectively. The light-emitting layer EML may include a fluorescent material or a phosphorescent material. The light-emitting layer EML may include an organic light-emitting material or an inorganic light-emitting material. The light-emitting layer EML may define a stacked structure using one or more of the aforementioned materials. The light-emitting layer EML may emit light in response to a potential difference between the pixel electrode PE and the common electrode CE.

[0128] The common electrode CE may be disposed on the light emitting layer EML. The common electrode CE may be disposed on the active area AA of the display panel DP (refer to FIG. Figure 6 ) extends to the peripheral area NAA of the display panel DP (refer to Figure 6 ) to have a single form. The common electrode CE may be opposite to a plurality of pixels PX (refer to Figure 6 ) are set together.

[0129] The common electrode CE may include a transmissive conductive material or a semi-transmissive conductive material. Therefore, the light generated by the light emitting layer EML can easily travel to the outside of the display panel DP along the third direction DR3 after passing through the common electrode CE (for example, a top surface emission mode). However, this is only exemplary, and the light emitting element LD according to the exemplary embodiment of the present disclosure (refer to FIG. Figure 8) can be operated in a rear surface emission mode or a multi-surface emission mode. In the rear surface emission mode, the pixel electrode PE includes a transmissive material or a semi-transmissive material so that light generated by the light-emitting layer EML can easily travel to the outside of the display panel DP along the third direction DR3 after passing through the pixel electrode PE. In the multi-surface emission mode, light is emitted at both the front surface and the rear surface of the display panel DP, and should not be limited to specific embodiments. In the present disclosure, the light-emitting element LD may collectively include the pixel electrode PE, the light-emitting layer EML, and the common electrode CE.

[0130] The thin film encapsulation layer TFE may be provided on the common electrode CE to encapsulate the light emitting layer EML on the second film FL2. The thin film encapsulation layer TFE may be provided from the active area AA of the display panel DP (refer to FIG. Figure 6 ) extends to the peripheral area NAA of the display panel DP (refer to Figure 6 Although not shown in the drawings, a cover layer may be provided between the common electrode CE and the thin film encapsulation layer TFE to cover the common electrode CE.

[0131] The thin film encapsulation layer TFE may include a first inorganic layer EF1, an organic layer EF2, and a second inorganic layer EF3 stacked in sequence along a third direction DR3. That is, the thin film encapsulation layer TFE may define a stacked structure including one or more of the first inorganic layer EF1, the organic layer EF2, and the second inorganic layer EF3. In this exemplary embodiment, each of the first inorganic layer EF1, the organic layer EF2, and the second inorganic layer EF3 may be provided as a single layer, however, this is merely exemplary. At least one of the first inorganic layer EF1, the organic layer EF2, and the second inorganic layer EF3 may be provided as a plurality or may be omitted, however, this should not be limited to a specific embodiment.

[0132] The first inorganic layer EF1 may cover the common electrode CE. The first inorganic layer EF1 may reduce or effectively prevent external moisture or oxygen from entering the light-emitting layer EML. In an exemplary embodiment, the first inorganic layer EF1 may include silicon nitride, silicon oxide, or a combination thereof. In an embodiment of a method for manufacturing a display device DD, the first inorganic layer EF1 may be formed by a deposition process.

[0133] The organic layer EF2 may be disposed on the first inorganic layer EF1 to be in contact with the first inorganic layer EF1. The organic layer EF2 may provide a flat surface on the first inorganic layer EF1.

[0134] The uneven shape formed by the upper surface of the first inorganic layer EF1 and the particles present on the first inorganic layer EF1 can be covered by the organic layer EF2, thereby preventing the surface state of the upper surface of the first inorganic layer EF1 having the uneven shape or particles from affecting components subsequently disposed or formed on the organic layer EF2. In addition, the organic layer EF2 can relieve stress between contacting layers in the thin film encapsulation layer TFE. The organic layer EF2 may include an organic material and, in an embodiment of the method for manufacturing the display device DD, may be formed by a solution process such as spin coating, slit coating, or inkjet process.

[0135] The second inorganic layer EF3 may be disposed on the organic layer EF2 to cover the organic layer EF2. The second inorganic layer EF3 may be stably disposed or formed on a relatively flat surface compared to the surface on which the first inorganic layer EF1 is disposed or formed. The second inorganic layer EF3 may encapsulate or absorb moisture leaking from the organic layer EF2 to reduce or effectively prevent moisture from being transferred to the exterior of the second inorganic layer EF3. The second inorganic layer EF3 may include silicon nitride, silicon oxide, or a combination thereof. In an embodiment of a method for manufacturing a display device DD, the second inorganic layer EF3 may be disposed or formed by a deposition process.

[0136] Reference Figure 9 and described below Figures 10 to 13 , layers 11-P, 12-P, 20-P, 30-P, 40-P, UE-P, 50-P, PE-P, 60-P, EML-P, CE-P, EF1-P, EF2-P, EF3-P, ET2-P, SP-P, CNE-P and ET1-P can respectively correspond to the layers 11, 12, 20, 30, 40, UE, 50, PE, 60, EML, CE, EF1, EF2, EF3, ET2, SP, CNE and ET1 described above.

[0137] Figure 10 is an enlarged cross-sectional view illustrating an exemplary embodiment of the pattern film FF-1. Figure 10 The arrangement relationship of the conductive wiring and patterns in may be included in the dummy pixel D-PX, but is not limited thereto. Figures 2 to 4 The pattern film FF and the pattern film FFa described in the Figure 10 Pattern film FF-1.

[0138] Reference Figure 9 and Figure 10 The pattern film FF-1 may include a first film FL1 and a pattern layer PL-1. The pattern layer PL-1 may include a first sub-pattern layer SPL1, a second sub-pattern layer SPL2, and a third sub-pattern layer SPL3 in sequence from the first film FL1.

[0139] The first sub-pattern layer SPL1 may be disposed on the surface of the first film FL1 , the second sub-pattern layer SPL2 may be disposed on the first sub-pattern layer SPL1 , and the third sub-pattern layer SPL3 may be disposed on the second sub-pattern layer SPL2 .

[0140] The first sub-pattern layer SPL1 may have a stack structure substantially the same as the stack structure of the pixel circuit layer PX-CL, or may be defined by a stack structure substantially the same as the stack structure of the pixel circuit layer PX-CL. In an exemplary embodiment of the display device DD, the stack structure in which the first sub-pattern layer SPL1 is provided on the first film FL1 and the stack structure in which the pixel circuit layer PX-CL is provided on the second film FL2 may be provided or formed by the same process, without limitation thereto. The stack structure in which the first sub-pattern layer SPL1 is provided on the first film FL1 may include one or more portions of the same material layers as those included in the stack structure in which the pixel circuit layer PX-CL is provided on the second film FL2.

[0141] Similar to the first sub-pattern layer SPL1, the second sub-pattern layer SPL2 may include the same layer or the same material layer as the light-emitting layer EML, or be defined by the same layer or the same material layer as the light-emitting layer EML. In addition, like the light-emitting layer EML, the second sub-pattern layer SPL2 may also include a layer having the same material and the same structure as the sixth insulating layer 60 and the common electrode CE.

[0142] Similar to the first sub-pattern layer SPL1 , the third sub-pattern layer SPL3 may have the same stacking structure as the thin film encapsulation layer TFE.

[0143] According to an exemplary embodiment of the present disclosure, the pattern layer PL-1 on the first film FL1 may have the same stacking structure and layout as the stacking structure and layout of the components provided on the second film FL2 of the display panel DP. In an exemplary embodiment of the method of manufacturing the display device DD, the pattern layer PL-1 may be provided or formed by the same process used to manufacture the display panel DP using the same material or layer of the display panel DP as that used to manufacture the display panel DP.

[0144] When the pixel circuit layer PX-CL is formed using multiple first masks, the first sub-pattern layer SPL1 can be formed using a mask having the same mask pattern as the first mask. In an exemplary embodiment, for example, when the pixel circuit layer PX-CL includes wiring or signal lines containing titanium or molybdenum, the first sub-pattern layer SPL1 can have an element containing the same material and the same pattern as the wiring or signal lines. The second sub-pattern layer SPL2 can be provided or formed using the same material or layer as the sixth insulating layer 60, the light-emitting layer EML, and the common electrode CE, and the same process as used to form the sixth insulating layer 60, the light-emitting layer EML, and the common electrode CE. In addition, the third sub-pattern layer SPL3 can be provided or formed using the same material or layer as the thin film encapsulation layer TFE and the same process as used to form the thin film encapsulation layer TFE.

[0145] The degree of reflection and refraction of light incident on the pattern layer PL-1 from the outside of the display device DD may be similar to the degree of reflection and refraction of light incident on the display panel DP from the outside of the display device DD. That is, the reflectivity and transmittance of the display panel DP may be substantially the same as the reflectivity and transmittance of the pattern film FF-1 in which the pattern layer PL-1 is disposed.

[0146] According to an exemplary embodiment of the present disclosure, the pattern film FF-1 (refer to Figure 10 ) of the frame area NDA-D of the display device DD (refer to Figure 1 ) of the pattern layer PL-1 can be connected to the display panel DP (refer to Figure 9 ) is substantially the same as above the second film FL2. Therefore, not only in various environments such as under sunlight or under fluorescent light, but also at various angles at which the display device DD is viewed, the frame area NDA-D (refer to FIG. Figure 1 ) may have a display area DA-D (refer to Figure 1 ) has a transmittance, reflectance, and color similar to that of the display area DA-D. As a result, when no image is displayed, the difference in the boundary between the bezel area NDA-D and the display area DA-D can be minimized.

[0147] Figure 11 is an enlarged cross-sectional view illustrating another exemplary embodiment of the pattern film FF-2.

[0148] Reference Figure 9 and Figure 11 The pattern film FF-2 may include a first film FL1 and a pattern layer PL-2. The pattern layer PL-2 may include a first sub-pattern layer SPL1a and a second sub-pattern layer SPL2a.

[0149] Reference Figure 10 The pattern layer described in PL-1, Figure 11 The pattern layer PL-2 may not include a layer corresponding to a component disposed between the pixel circuit layer PX-CL and the thin film encapsulation layer TFE. In an exemplary embodiment, for example, the first sub-pattern layer SPL1a may have the same stacking structure as the pixel circuit layer PX-CL, and the second sub-pattern layer SPL2a may have the same stacking structure as the thin film encapsulation layer TFE.

[0150] Since the pattern layer PL-2 has a stacked structure rather than a conventional pattern layer provided or formed by a printing method, the reflectivity difference between the pattern layer PL-2 and the display panel DP and the transmittance difference between the pattern layer PL-2 and the display panel DP can be reduced. Therefore, when no image is displayed, a display device DD can be provided in which the difference between the display area DA-D and the bezel area NDA-D is minimized.

[0151] Figure 12 is an enlarged cross-sectional view illustrating still another exemplary embodiment of the pattern film FF-3.

[0152] Reference Figure 9 and Figure 12 , the pattern film FF-3 may include a first film FL1 and a pattern layer PL-3. The pattern layer PL-3 may include a first sub-pattern layer SPL1b and a second sub-pattern layer SPL2b. Figure 10 The pattern layer described in PL-1, Figure 12 The pattern layer PL-3 may not include a layer corresponding to the thin film encapsulation layer TFE.

[0153] The first sub-pattern layer SPL1b may have the same stack structure as the pixel circuit layer PX-CL. The second sub-pattern layer SPL2b may include layers having the same material and the same structure as the light emitting layer EML, the sixth insulating layer 60, and the common electrode CE.

[0154] Figure 13 is an enlarged cross-sectional view illustrating still another exemplary embodiment of the pattern film FF-4.

[0155] Reference Figure 9 and Figure 13 , the pattern film FF-4 may include a first film FL1 and a pattern layer PL-4. Figure 10 The pattern layer described in PL-1, Figure 13 The pattern layer PL-4 may not include a layer corresponding to a layer disposed on the pixel circuit layer PX-CL of the display panel DP. Therefore, the pattern layer PL-4 may have the same stack structure as the pixel circuit layer PX-CL.

[0156] Reference Figures 2 to 4 The pattern film FF and pattern film FFa described can be changed to refer to Figures 10 to 13Described pattern films FF-1, FF-2, FF-3 and FF-4.

[0157] Although exemplary embodiments of the present disclosure have been described, it is understood that the invention should not be limited to these exemplary embodiments, but rather that various changes and modifications may be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the invention should be determined according to the claims.

Claims

1. A display device, wherein a display area and a frame area are defined in the display device, the display device comprising: The display panel includes: an active area and a peripheral area, an image is displayed in the active area, the peripheral area is adjacent to the active area; a first film corresponding to the active area and the peripheral area; and a pixel located on the first film, the pixel including a pixel circuit and a light emitting layer, the pixel circuit defining a stacked structure; windows; and A pattern film is located between the display panel and the window, the pattern film comprising: a second film including a first area and a second area corresponding to the display area and the frame area of ​​the display device, respectively; and a pattern layer located on the second film, in the second area of ​​the second film, Wherein, the pattern layer of the pattern film includes a stacking structure that is the same as a stacking structure defined by the pixel circuit of the display panel.

2. The display device according to claim 1, further comprising: A polarizing film is located between the window and the pattern film, wherein the polarizing film corresponds to both the first area and the second area of ​​the pattern film.

3. The display device according to claim 1, wherein The display panel further includes a dummy pixel, and the dummy pixel includes a dummy pixel circuit and a dummy light emitting layer.

4. The display device according to claim 3, wherein The pixels of the display panel correspond to the active area of ​​the display panel, and the dummy pixels correspond to the peripheral area of ​​the display panel.

5. The display device according to claim 3, wherein The dummy pixels are provided in plurality, and the dummy pixels include a plurality of dummy pixels corresponding to the first region and the second region of the pattern film, respectively. The display device according to claim 1 , wherein: The pattern layer of the pattern film is located between the window and the second film of the pattern film.

7. The display device according to claim 1, wherein The pattern layer is located between the display panel and the second film of the pattern film.

8. The display device according to claim 1, wherein The pattern layer includes a first sub-pattern layer and a second sub-pattern layer sequentially arranged from the second film, The first sub-pattern layer has the same stacking structure as the stacking structure defined by the pixel circuit, and The second sub-pattern layer includes the same material as that of the light emitting layer.

9. The display device according to claim 1, wherein The display panel further includes a thin film encapsulation layer covering the light emitting layer.

10. The display device according to claim 9, wherein The thin film encapsulation layer defines a stacked structure, The pattern layer includes a first sub-pattern layer and a second sub-pattern layer sequentially arranged from the second film, The first sub-pattern layer has the same stacking structure as the stacking structure defined by the pixel circuit, and The second sub-pattern layer has the same stacking structure as the stacking structure defined by the thin film encapsulation layer.

11. The display device according to claim 9, wherein The thin film encapsulation layer defines a stacked structure, The pattern layer includes a first sub-pattern layer, a second sub-pattern layer and a third sub-pattern layer sequentially arranged from the second film, The first sub-pattern layer has a stacking structure that is the same as the stacking structure defined by the pixel circuit, The second sub-pattern layer includes the same material as the light emitting layer, and The third sub-pattern layer has the same stacking structure as the stacking structure defined by the thin film encapsulation layer.

12. The display device according to claim 1, further comprising: The colored adhesive layer faces the pattern film, and the display panel is disposed between the colored adhesive layer and the pattern film. 13 . The display device according to claim 1 , further comprising an input sensing layer located between the display panel and the second film of the pattern film.

14. The display device according to claim 1, wherein A reflectivity and a transmittance of external light incident on the display device at a region corresponding to the display area are respectively equal to a reflectivity and a transmittance of external light incident on the display device at a region corresponding to the bezel area.

15. A display device, wherein a display area and a frame area are defined in the display device, the display device comprising: a display panel including an active area at which an image is displayed and a peripheral area adjacent to the active area, and including a pixel circuit having a stacked structure; window; as well as a pattern film located between the display panel and the window, the pattern film comprising: a first film including a transmissive area corresponding to the display area of ​​the display device; and a pattern layer located on the first film and corresponding to the frame area of ​​the display device; The pattern layer includes a stacked structure having the same material as that of the stacked structure used for the pixel circuit.

16. The display device according to claim 15, wherein The display panel further includes: a second film corresponding to the active area and the peripheral area, and a pixel located on the second film, the pixel including the pixel circuit and the light-emitting layer, and The pattern layer includes a first sub-pattern layer having the same stacking structure as the stacking structure defined by the pixel circuit.

17. The display device according to claim 16, wherein: The light emitting layer defines a stacked structure, and The pattern layer further includes a second sub-pattern layer facing the first film, with the first sub-pattern layer disposed between the second sub-pattern layer and the first film, and the second sub-pattern layer having the same stacking structure as the stacking structure defined by the light-emitting layer.

18. The display device according to claim 16, further comprising an encapsulation layer covering the pixel, the encapsulation layer defining a stacked structure, in, The pattern layer further includes a second sub-pattern layer facing the first film, with the first sub-pattern layer disposed between the second sub-pattern layer and the first film, and the second sub-pattern layer has the same stacking structure as the stacking structure defined by the encapsulation layer.

19. The display device according to claim 15, further comprising a polarizing film located between the window and the pattern film, wherein: The planar area of ​​the polarizing film is equal to the planar area of ​​the window.

20. The display device according to claim 15, wherein The display panel further includes a plurality of dummy pixels, each of which includes a dummy pixel circuit and a dummy light-emitting layer. The pixels of the display panel correspond to the active area of ​​the display panel, and The plurality of dummy pixels correspond to the transmission area of ​​the pattern film and the pattern layer.

Images