An analog equalizer with adjustable high and low frequency gain

Abstract

The present invention discloses an analog equalizer with adjustable high and low frequency gains, which is composed of two active load networks, three equalization circuits and one active feedback circuit; the two active load networks include a first active load network and a second active load network; the three equalization circuits include a first low-frequency fine-tuning equalization circuit, a second low-frequency fine-tuning equalization circuit and a low-frequency coarse-tuning equalization circuit. The input ends of the first low-frequency fine-tuning equalization circuit and the second low-frequency fine-tuning equalization circuit form the input end of the analog equalizer. The output ends of the first active load network, the first low-frequency fine-tuning equalization circuit, the second low-frequency fine-tuning equalization circuit and the active feedback circuit are connected to the input end of the low-frequency coarse-tuning equalization circuit; the output end of the second active load network, the output end of the low-frequency coarse-tuning equalization circuit and the input end of the active feedback circuit form the output end of the analog equalizer. The present invention can improve the overall equalization capability, increase the adjustable range of low-frequency fine-tuning, and reduce the layout area.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to an analog equalizer with adjustable high and low frequency gains. Background Art

[0002] As a large amount of data is generated, people have higher and higher requirements for data transmission rate. However, in serial communication systems, due to the presence of non-ideal factors such as dielectric loss and skin effect in wired channels such as transmission lines and coaxial cables, these non-ideal factors will cause signal attenuation, and the higher the data rate, the greater the attenuation. The more severe the attenuation, the more it affects the integrity of the signal, affecting the normal judgment of the receiving circuit, and causing the system's bit error rate to increase.

[0003] In order to reduce the bit error rate in high-speed serial communication systems, an equalizer that compensates for high-frequency signals is usually added to the receiving end to weaken the attenuation of the limited channel to the signal and obtain a relatively flat overall frequency response. In the transmission of a serial communication system, different wired channels have different attenuations; the same wired channel but different channel lengths have different attenuations; the same wired channel, the same channel length, but different data rates have different attenuations. Because the attenuation of the channel is unpredictable and time-varying, the gain of the equalizer is required to be adjustable to cope with different channel attenuations. However, when facing strong attenuation channel equalization, the existing equalizer has problems such as low low-frequency adjustable range, unadjustable high-frequency peak gain, and excessive layout area. Summary of the invention

[0004] The present invention aims to solve the problems that the existing equalizer has a low adjustable low-frequency range, an unadjustable high-frequency peak gain and an excessively large layout area when equalizing a strongly attenuated channel, and provides an analog equalizer with adjustable high and low frequency gains.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] An analog equalizer with adjustable high and low frequency gains is composed of two active load networks, three equalization circuits and one active feedback circuit. The two active load networks include a first active load network and a second active load network. The three equalization circuits include a first low-frequency fine-tuning equalization circuit, a second low-frequency fine-tuning equalization circuit and a low-frequency coarse-tuning equalization circuit. After the input terminal vin of the first low-frequency fine-tuning equalization circuit is connected to the input terminal vin of the second low-frequency fine-tuning equalization circuit, an input terminal VIN of the analog equalizer is formed. After the input terminal vip of the first low-frequency fine-tuning equalization circuit is connected to the input terminal vip of the second low-frequency fine-tuning equalization circuit, an input terminal VIP of the analog equalizer is formed. The output terminal vonr of the first active load network is connected to the output terminal von of the first low-frequency fine-tuning equalization circuit, the output terminal von of the second low-frequency fine-tuning equalization circuit, the output terminal vonfb of the active feedback circuit and the input terminal vin of the low-frequency coarse-tuning equalization circuit. The output terminal vopr of the first active load network is connected to the output terminal vop of the first low-frequency fine adjustment equalization circuit, the output terminal vop of the second low-frequency fine adjustment equalization circuit, the output terminal vopfb of the active feedback circuit, and the input terminal vip of the low-frequency coarse adjustment equalization circuit. The output terminal vonr of the second active load network, the output terminal von of the low-frequency coarse adjustment equalization circuit, and the input terminal vipfb of the active feedback circuit are connected to form the output terminal VON of the analog equalizer. The output terminal vopr of the second active load network, the output terminal vop of the low-frequency coarse adjustment equalization circuit, and the input terminal vinfb of the active feedback circuit are connected to form the output terminal VOP of the analog equalizer.

[0007] In the above solution, the first low-frequency fine-tuning equalization circuit, the second low-frequency fine-tuning equalization circuit and the low-frequency coarse-tuning equalization circuit have the same structure.

[0008] In the above scheme, each equalizing circuit includes MOS tubes NM1-5, feedback resistor R1 and feedback capacitor C1. Among them, MOS tubes NM1-5 are NMOS tubes. The drain of MOS tube NM1 forms the output terminal von of the equalizing circuit. The gate of MOS tube NM1 forms the input terminal vin of the equalizing circuit. The source of MOS tube NM1, one end of feedback resistor R1, one end of feedback capacitor C1, the drain of MOS tube NM3 and the drain of MOS tube NM4 are connected. The drain of MOS tube NM2 forms the output terminal vop of the equalizing circuit. The gate of MOS tube NM2 forms the input terminal vip of the equalizing circuit. The source of MOS tube NM2, the other end of feedback resistor R1, the other end of feedback capacitor C1, the source of MOS tube NM3 and the drain of MOS tube NM5 are connected. The gate of MOS tube NM3 is connected to the control voltage VCL. The source of MOS tube NM4 and the source of MOS tube NM5 are grounded. The gate of the MOS transistor NM4 and the gate of the MOS transistor NM5 are connected to the control voltage vb.

[0009] In the above solution, the first active load network and the second active load network have the same structure.

[0010] In the above scheme, each active load network includes MOS transistors PM1-4, MOS transistors NM20-23 and load resistors R4-5. Among them, MOS transistors PM1-4 are PMOS transistors, and MOS transistors NM20-23 are NMOS transistors. The source of MOS transistor PM1 is connected to the power supply VDD. The gate of MOS transistor PM1 is connected to the drain of MOS transistor PM3 and the drain of MOS transistor NM21, and the drain of MOS transistor PM1 is connected to the source of MOS transistor PM3 and one end of resistor R4. The other end of resistor R4 forms the output end vonr of the active load network. The gate of MOS transistor PM3 is connected to the high-frequency control voltage VC. The gate of MOS transistor NM21, the gate of MOS transistor NM20 and the drain of MOS transistor NM20 are connected to the control current IC. The sources of MOS transistors NM20 and MOS transistor NM21 are grounded. The source of MOS transistor PM2 is connected to the power supply VDD. The gate of MOS transistor PM2 is connected to the drain of MOS transistor PM4 and the drain of MOS transistor NM23, and the drain of MOS transistor PM2 is connected to the source of MOS transistor PM4 and one end of resistor R5. The other end of resistor R5 forms the output end vopr of the active load network. The gate of MOS transistor PM4 is connected to the high-frequency control voltage VC. The gate of MOS transistor NM23, the gate of MOS transistor NM22 and the drain of MOS transistor NM22 are connected to the control current IC. The sources of MOS transistor NM22 and MOS transistor NM23 are grounded.

[0011] In the above scheme, the active feedback circuit includes MOS tubes NM11-14. Among them, MOS tubes NM11-14 are NMOS tubes. The gate of MOS tube NM11 forms the input terminal vinfb of the active feedback circuit. The drain of MOS tube NM11 forms the output terminal vonfb of the active feedback circuit. The source of MOS tube NM11 is connected to the drain of MOS tube NM13. The gate of MOS tube NM13 is connected to the control voltage vb, and the source of MOS tube NM13 is grounded. The gate of MOS tube NM12 forms the input terminal vipfb of the active feedback circuit. The drain of MOS tube NM12 forms the output terminal vopfb of the active feedback circuit. The source of MOS tube NM12 is connected to the drain of MOS tube NM14. The gate of MOS tube NM14 is connected to the control voltage vb, and the source of MOS tube NM14 is grounded.

[0012] Compared with the prior art, the present invention has the following characteristics:

[0013] 1. The input of the equalization circuit adopts a parallel structure, which improves the overall equalization ability and increases the adjustable range of low-frequency fine-tuning.

[0014] 2. The structure of low-frequency coarse-tuning equalization circuit and low-frequency fine-tuning equalization circuit in series improves the ability to equalize high-attenuation channels.

[0015] 3. It can balance data at high transmission rates and provide a peak gain of 16dB for data at a transmission rate of 15Gbps.

[0016] 4. Active inductors are used to provide the equalizer with inductive peaking capabilities, which improves the equalization capability while reducing the layout area. In addition, because the inductance value of the active inductor is adjustable, the high-frequency peak gain of the equalizer is adjustable. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the circuit schematic of an analog equalizer with adjustable high and low frequency gain.

[0018] Figure 2 This is the simulation result of the amplitude-frequency characteristic curve of the present invention.

[0019] Figure 3 The simulation results of different VCL control voltage amplitude-frequency characteristic curves.

[0020] Figure 4 The simulation results of different VCH control voltage amplitude-frequency characteristic curves.

[0021] Figure 5 The simulation results of different VCH and VCL control voltage amplitude-frequency characteristic curves.

[0022] Figure 6 FIG. 1 is a graph showing the change in inductance of the active inductor in the first active load network under different VC control voltages.

[0023] Figure 7 FIG. 1 is a graph showing the change in inductance of the active inductor in the second active load network under different VC control voltages.

[0024] Figure 8 Simulation results of the amplitude-frequency characteristic curves of the control voltages for different VC, VCH and VCL. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific examples and with reference to the accompanying drawings.

[0026] An analog equalizer with adjustable high and low frequency gain, such as Figure 1As shown, it is composed of two active load networks, three balancing circuits and one active feedback circuit. The two active load networks include a first active load network and a second active load network. The three balancing circuits include a first low-frequency fine-tuning balancing circuit, a second low-frequency fine-tuning balancing circuit and a low-frequency coarse-tuning balancing circuit. After the input terminal vin of the first low-frequency fine-tuning balancing circuit is connected to the input terminal vin of the second low-frequency fine-tuning balancing circuit, the input terminal VIN of the present analog equalizer is formed. After the input terminal vip of the first low-frequency fine-tuning balancing circuit is connected to the input terminal vip of the second low-frequency fine-tuning balancing circuit, the input terminal VIP of the present analog equalizer is formed. The output terminal vonr of the first active load network is connected to the output terminal von of the first low-frequency fine-tuning balancing circuit, the output terminal von of the second low-frequency fine-tuning balancing circuit, the output terminal vonfb of the active feedback circuit and the input terminal vin of the low-frequency coarse-tuning balancing circuit. The output terminal vopr of the first active load network is connected to the output terminal vop of the first low-frequency fine adjustment equalization circuit, the output terminal vop of the second low-frequency fine adjustment equalization circuit, the output terminal vopfb of the active feedback circuit, and the input terminal vip of the low-frequency coarse adjustment equalization circuit. The output terminal vonr of the second active load network, the output terminal von of the low-frequency coarse adjustment equalization circuit, and the input terminal vipfb of the active feedback circuit are connected to form the output terminal VON of the analog equalizer. The output terminal vopr of the second active load network, the output terminal vop of the low-frequency coarse adjustment equalization circuit, and the input terminal vinfb of the active feedback circuit are connected to form the output terminal VOP of the analog equalizer.

[0027] The first low-frequency fine-tuning equalization circuit includes NMOS tubes NM1-5, feedback resistor R1 and feedback capacitor C1. MOS tubes NM1 and NM2 are differential pair amplifier tubes, and the parallel network formed by feedback resistor R1, feedback capacitor C1 and MOS tube NM3 is the source negative feedback network of the differential pair. MOS tubes NM4 and NM5 are tail current tubes of the differential pair. The drain of MOS tube NM1 forms the output terminal von1 of the first low-frequency fine-tuning equalization circuit, the gate of MOS tube NM1 forms the input terminal vin1 of the first low-frequency fine-tuning equalization circuit, and the source of MOS tube NM1, one end of feedback resistor R1, one end of feedback capacitor C1, the drain of MOS tube NM3 and the drain of MOS tube NM4 are connected. The drain of the MOS tube NM2 forms the output terminal vop1 of the first low-frequency fine-tuning equalizing circuit, the gate of the MOS tube NM2 forms the input terminal vip1 of the first low-frequency fine-tuning equalizing circuit, the source of the MOS tube NM2, the other end of the feedback resistor R1, the other end of the feedback capacitor C1, the source of the MOS tube NM3 and the drain of the MOS tube NM5 are connected. The gate of the MOS tube NM3 is connected to the control voltage VCL. The source of the MOS tube NM4 and the source of the MOS tube NM5 are grounded, and the gate of the MOS tube NM4 and the gate of the MOS tube NM5 are connected to the control voltage vb.

[0028] The second low-frequency fine-tuning equalization circuit includes NMOS tubes NM6-10, feedback resistor R2 and feedback capacitor 2. MOS tube NM6 and MOS tube NM7 are differential pair amplifier tubes, and the parallel network formed by feedback resistor R2, feedback capacitor C2 and MOS tube NM8 is the source negative feedback network of the differential pair. MOS tube NM9 and MOS tube NM10 are the tail current tubes of the differential pair. The drain of MOS tube NM6 forms the output terminal von2 of the second low-frequency fine-tuning equalization circuit, and the gate of MOS tube NM6 forms the input terminal vin2 of the second low-frequency fine-tuning equalization circuit. The source of MOS tube NM6, one end of feedback resistor R2, one end of feedback capacitor C2, the drain of MOS tube NM8 and the drain of MOS tube NM9 are connected. The drain of the MOS tube NM7 forms the output terminal vop2 of the second low-frequency fine-tuning equalization circuit, the gate of the MOS tube NM7 forms the input terminal vip2 of the second low-frequency fine-tuning equalization circuit, the source of the MOS tube NM7, the other end of the feedback resistor R2, the other end of the feedback capacitor C2, the source of the MOS tube NM8 and the drain of the MOS tube NM10 are connected. The gate of the MOS tube NM8 is connected to the control voltage VCL. The source of the MOS tube NM9 and the source of the MOS tube NM10 are grounded, and the gate of the MOS tube NM9 and the gate of the MOS tube NM10 are connected to the control voltage vb.

[0029] The low-frequency coarse adjustment equalization circuit includes NMOS tubes NM15-19, feedback capacitor C3 and feedback resistor R3. MOS tubes NM15 and NM16 are differential pair amplifiers, and the parallel network formed by feedback resistor R3, feedback capacitor C3 and MOS tube NM17 is the source negative feedback network of the differential pair. MOS tubes NM18 and MOS tubes NM19 are tail current tubes of the differential pair. The gate of MOS tube NM15 forms the input terminal vin3 of the low-frequency coarse adjustment equalization circuit, and the drain of MOS tube NM15 forms the output terminal von3 of the low-frequency coarse adjustment equalization circuit. The source of MOS tube NM15, one end of feedback capacitor C3, one end of feedback resistor R3, MOS tube NM17 and drain of MOS tube NM18 are connected. The gate of MOS tube NM18 is connected to the control voltage vb, and the source of MOS tube NM18 is grounded. The gate of the MOS tube NM16 forms the input terminal vip3 of the low-frequency coarse adjustment equalization circuit, the drain of the MOS tube NM16 forms the output terminal vop3 of the low-frequency coarse adjustment equalization circuit, the source of the MOS tube NM16, the other end of the feedback capacitor C3, the other end of the feedback resistor R3, the source of the MOS tube NM17, and the drain of the MOS tube NM19 are connected. The gate of the MOS tube NM19 is connected to the control voltage vb, the source of the MOS tube NM19 is grounded, and the gate of the MOS tube NM17 is connected to the external control voltage VCH.

[0030] The first active load network includes PMOS transistors PM1-4, NMOS transistors NM20-23, and load resistors R4-5. The source of MOS transistor PM1 is connected to the power supply VDD, the gate of MOS transistor PM1 is connected to the drain of MOS transistor PM3 and the drain of MOS transistor NM21, and the drain of MOS transistor PM1 is connected to the source of MOS transistor PM3 and one end of resistor R4. The other end of resistor R4 forms the output end vonr1 of the first active load network, and is connected to the output end von1 of the first low-frequency fine-tuning equalization circuit and the output end von2 of the second low-frequency fine-tuning equalization circuit. The gate of MOS transistor PM3 is connected to the high-frequency control voltage VC. The source of MOS transistor NM21 is grounded, the gate of MOS transistor NM21, the gate of MOS transistor NM20, the drain of MOS transistor NM20 are connected to the control current IC, and the source of MOS transistor NM20 is grounded. The source of MOS transistor PM2 is connected to the power supply VDD, the gate of MOS transistor PM2 is connected to the drain of MOS transistor PM4 and the drain of MOS transistor NM23, and the drain of MOS transistor PM2 is connected to the source of MOS transistor PM4 and one end of resistor R5. The other end of resistor R5 forms the output end vop1 of the first active load network, and is connected to the output end vopr1 of the first low-frequency fine-tuning equalization circuit and the output end vop2 of the second low-frequency fine-tuning equalization circuit. The gate of MOS transistor PM4 is connected to the high-frequency control voltage VC. The source of MOS transistor NM23 is grounded, the gate of MOS transistor NM23, the gate of MOS transistor NM22, the drain of MOS transistor NM22 are connected to the control current IC, and the source of MOS transistor NM22 is grounded.

[0031] The second active load network includes PMOS transistors PM5-8, NMOS transistors NM24-27, and load resistors R6-7. The source of MOS transistor PM5 is connected to the power supply VDD, the gate of MOS transistor PM5 is connected to the drain of MOS transistor PM7 and the drain of MOS transistor NM25, and the drain of MOS transistor PM5 is connected to the source of MOS transistor PM7 and one end of resistor R6. The other end of resistor R6 forms the output end vonr2 of the second active load network and is connected to the output end von3 of the low-frequency coarse adjustment equalization circuit. The gate of MOS transistor PM7 is connected to the high-frequency control voltage VC. The source of MOS transistor NM25 is grounded, the gate of MOS transistor NM25, the gate of MOS transistor NM24, the drain of MOS transistor NM24 are connected to the control current IC, and the source of MOS transistor NM24 is grounded. The source of MOS transistor PM6 is connected to the power supply VDD, the gate of MOS transistor PM6 is connected to the drain of MOS transistor PM8 and the drain of MOS transistor NM27, and the drain of MOS transistor PM6 is connected to the source of MOS transistor PM8 and one end of resistor R7. The other end of resistor R7 forms the output end vopr2 of the second active load network and is connected to the output vop3 of the low-frequency coarse adjustment equalization circuit. The gate of MOS transistor PM8 is connected to the high-frequency control voltage VC. The source of MOS transistor NM27 is grounded, the gate of MOS transistor NM27, the gate of MOS transistor NM26, the drain of MOS transistor NM26 are connected to the control current IC, and the source of MOS transistor NM26 is grounded.

[0032] The active feedback circuit includes NMOS tubes NM11-14. MOS tubes NM11 and NM12 are differential pair amplifier tubes. MOS tubes NM13 and NM14 are tail current tubes of the differential pair. The gate of MOS tube NM11 forms the input terminal vinfb of the active feedback circuit, the drain of MOS tube NM11 forms the output terminal vonfb of the active feedback circuit, and the source of MOS tube NM11 is connected to the drain of MOS tube NM13. The gate of MOS tube NM13 is connected to the control voltage vb, and the source of MOS tube NM13 is grounded. The gate of MOS tube NM12 forms the input terminal vipfb of the active feedback circuit, the drain of MOS tube NM12 forms the output terminal vopfb of the active feedback circuit, and the source of MOS tube NM12 is connected to the drain of MOS tube NM14. The gate of MOS tube NM14 is connected to the control voltage vb, and the source of MOS tube NM14 is grounded.

[0033] MOS tubes NM1-27 are NMOS tubes with a standard voltage of 1.8V, and MOS tubes PM1-8 are PMOS tubes with a standard voltage of 1.8V.

[0034] The first low-frequency fine-tuning equalization circuit, the second low-frequency fine-tuning equalization circuit and the low-frequency coarse-tuning equalization circuit have the same structure, that is, they are all composed of a differential pair with capacitor-resistor source negative feedback. Due to the source negative feedback of the capacitor-resistor, the differential pair generates a zero point and a pole on the left side of the complex frequency domain. The position of the zero point is related to the size of the feedback resistor and the feedback capacitor. When the gain curve passes through this zero point, the gain increases, which can compensate for the channel attenuation after the zero point. In addition, the structure of the first low-frequency fine-tuning equalization circuit, the second low-frequency fine-tuning equalization circuit in parallel and the low-frequency coarse-tuning equalization circuit in series allows the entire equalization circuit to generate three zero points and five poles. When the gain curve passes through each zero point, it will increase at a slope of 20dB / dec. Reasonable adjustment of the feedback resistor and the feedback capacitor values, changing the positional relationship between the zero point and the pole can increase the gain difference between the high frequency and the low frequency, and increase the equalization capability for high-loss channels.

[0035] The first active load network and the second active load network have the same structure, and the balancing circuit and the corresponding load are connected in series, that is, the low-frequency fine-tuning balancing circuit is connected in series with the first active load network, and the low-frequency coarse-tuning balancing circuit is connected in series with the second active load network. The active load network can be equivalent to an active inductor connected in series with a load resistor. The active inductor can provide a zero point and a pole for the equalizer. The existence of the active inductor will reduce the load capacitance of the balancing circuit, thereby increasing the frequency point where the pole is located, and increasing the bandwidth of the equalizer, so that signals with higher transmission rates can be balanced. The feedback circuit takes the output of the low-frequency coarse-tuning balancing circuit as input, and the output compensates for the output of the low-frequency fine-tuning balancing circuit to reduce the zero-point jitter of the differential signal.

[0036] for Figure 1 The high and low frequency adjustable analog equalizer shown in the figure is designed using 0.18μm process and obtained through simulation Figure 2-8 The simulation results are shown in Figure 2.

[0037] Figure 2 When the control voltages VC=0V, VCH=0.9V and VCL=0.9V are fixed, the amplitude-frequency response of the circuit shows a peak value of 16dB, and the frequency corresponding to the peak value is 7.7GHz.

[0038] Figure 3 When the control voltage VC=0V and VCH=0.9V is fixed, the adjustable range of the amplitude-frequency response when the control voltage VCL is changed from 0V to 1.8V is also the adjustable range of the low-frequency fine-tuning equalizer circuit. It can be seen that the low-frequency gain is 2dB when VCL=0V, and the low-frequency gain is 4dB when VCL=1.8V.

[0039] Figure 4When the control voltage VC=0V and VCL=0.9V is fixed, the adjustable range of the amplitude-frequency response when the control voltage VCH is changed from 0V to 1.8V is also the adjustable range of the low-frequency coarse adjustment equalization circuit. It can be seen that when VCH=0V, the low-frequency gain is -1.6dB, and when VCH=1.8V, the low-frequency gain is 4.9dB.

[0040] Figure 5 When the control voltage VC is fixed at 0V, the adjustable range of the amplitude-frequency response when the control voltages VCH and VCL are changed from 0V to 1.8V is also the overall adjustable range of the low-frequency coarse-tuning equalizer circuit and the low-frequency fine-tuning equalizer. It can be seen that when VCH=0V and VCL=0V, the low-frequency gain is -2.7dB, and when VCH=1.8V and VCL=1.8V, the low-frequency gain is 5.8dB.

[0041] Figure 6-7 In order to change the inductance of the active inductor in the active load when the control voltage VC changes from 0V to 0.6V, the reason why the equalizer is adjustable at high frequency is because the inductance of the active inductor is adjustable.

[0042] Figure 8 To change the control voltage VC from 0V to 0.6V, and change the control voltage VCH and VCL from 0V to 1.8V, the adjustable range of the amplitude-frequency response is also the adjustable range of the overall equalizer circuit. It can be seen that the low-frequency adjustable range is from -6dB to 6.5dB, and the high-frequency peak adjustable range is from 11.1dB to 16.1dB.

[0043] It should be noted that, although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. An analog equalizer with adjustable high and low frequency gain, characterized in that: It consists of 2 active load networks, 3 balancing circuits and 1 active feedback circuit; the 2 active load networks include a first active load network and a second active load network; the 3 balancing circuits include a first low-frequency fine-tuning balancing circuit, a second low-frequency fine-tuning balancing circuit and a low-frequency coarse-tuning balancing circuit; The input terminal vin of the first low-frequency fine-tuning equalizing circuit and the input terminal vin of the second low-frequency fine-tuning equalizing circuit are connected to form the input terminal VIN of the analog equalizer; The input terminal vip of the first low-frequency fine-tuning equalization circuit and the input terminal vip of the second low-frequency fine-tuning equalization circuit are connected to form the input terminal VIP of the analog equalizer; The output terminal vonr of the first active load network is connected to the output terminal von of the first low-frequency fine adjustment equalization circuit, the output terminal von of the second low-frequency fine adjustment equalization circuit, the output terminal vonfb of the active feedback circuit and the input terminal vin of the low-frequency coarse adjustment equalization circuit; The output terminal vopr of the first active load network is connected to the output terminal vop of the first low-frequency fine adjustment equalization circuit, the output terminal vop of the second low-frequency fine adjustment equalization circuit, the output terminal vopfb of the active feedback circuit and the input terminal vip of the low-frequency coarse adjustment equalization circuit; The output terminal vonr of the second active load network, the output terminal von of the low-frequency coarse adjustment equalization circuit and the input terminal vipfb of the active feedback circuit are connected to form the output terminal VON of the analog equalizer; The output terminal vopr of the second active load network, the output terminal vop of the low-frequency coarse adjustment equalization circuit and the input terminal vinfb of the active feedback circuit are connected to form the output terminal VOP of the analog equalizer.

2. The analog equalizer with adjustable high and low frequency gains according to claim 1, characterized in that: The first low-frequency fine-tuning equalizing circuit, the second low-frequency fine-tuning equalizing circuit and the low-frequency coarse-tuning equalizing circuit have the same structure.

3. The analog equalizer with adjustable high and low frequency gains according to claim 1 or 2, characterized in that: Each equalization circuit includes a MOS tube NM1-5, a feedback resistor R1 and a feedback capacitor C1; wherein the MOS tube NM1-5 is an NMOS tube; The drain of the MOS tube NM1 forms the output terminal von of the equalizing circuit; the gate of the MOS tube NM1 forms the input terminal vin of the equalizing circuit; the source of the MOS tube NM1, one end of the feedback resistor R1, one end of the feedback capacitor C1, the drain of the MOS tube NM3 and the drain of the MOS tube NM4 are connected; the drain of the MOS tube NM2 forms the output terminal vop of the equalizing circuit; the gate of the MOS tube NM2 forms the input terminal vip of the equalizing circuit; the source of the MOS tube NM2, the other end of the feedback resistor R1, the other end of the feedback capacitor C1, the source of the MOS tube NM3 and the drain of the MOS tube NM5 are connected; the gate of the MOS tube NM3 is connected to the control voltage VCL; the source of the MOS tube NM4 and the source of the MOS tube NM5 are grounded; the gate of the MOS tube NM4 and the gate of the MOS tube NM5 are connected to the control voltage vb.

4. The analog equalizer with adjustable high and low frequency gains according to claim 1, characterized in that: The first active load network and the second active load network have the same structure.

5. The analog equalizer with adjustable high and low frequency gains according to claim 1 or 4, characterized in that: Each active load network includes MOS transistors PM1-4, MOS transistors NM20-23 and load resistors R4-5; wherein MOS transistors PM1-4 are PMOS transistors, and MOS transistors NM20-23 are NMOS transistors; The source of MOS transistor PM1 is connected to power supply VDD; the gate of MOS transistor PM1 is connected to the drain of MOS transistor PM3 and the drain of MOS transistor NM21, the drain of MOS transistor PM1 is connected to the source of MOS transistor PM3 and one end of resistor R4; the other end of resistor R4 forms the output end vonr of active load network; the gate of MOS transistor PM3 is connected to high-frequency control voltage VC; the gate of MOS transistor NM21, the gate of MOS transistor NM20 and the drain of MOS transistor NM20 are connected to control current IC; the sources of MOS transistor NM20 and MOS transistor NM21 are grounded; The source of the MOS transistor PM2 is connected to the power supply VDD; the gate of the MOS transistor PM2 is connected to the drain of the MOS transistor PM4 and the drain of the MOS transistor NM23, and the drain of the MOS transistor PM2 is connected to the source of the MOS transistor PM4 and one end of the resistor R5; the other end of the resistor R5 forms the output end vopr of the active load network; the gate of the MOS transistor PM4 is connected to the high-frequency control voltage VC; the gate of the MOS transistor NM23, the gate of the MOS transistor NM22 and the drain of the MOS transistor NM22 are connected to the control current IC; the sources of the MOS transistors NM22 and NM23 are grounded.

6. The analog equalizer with adjustable high and low frequency gains according to claim 1, characterized in that: The active feedback circuit includes MOS tubes NM11-14; wherein the MOS tubes NM11-14 are NMOS tubes; The gate of the MOS tube NM11 forms the input terminal vinfb of the active feedback circuit; the drain of the MOS tube NM11 forms the output terminal vonfb of the active feedback circuit; the source of the MOS tube NM11 is connected to the drain of the MOS tube NM13; the gate of the MOS tube NM13 is connected to the control voltage vb, and the source of the MOS tube NM13 is grounded; The gate of the MOS tube NM12 forms the input terminal vipfb of the active feedback circuit; the drain of the MOS tube NM12 forms the output terminal vopfb of the active feedback circuit; the source of the MOS tube NM12 is connected to the drain of the MOS tube NM14; the gate of the MOS tube NM14 is connected to the control voltage vb, and the source of the MOS tube NM14 is grounded.

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