A low-noise, high-gain mixer

Abstract

This invention relates to a low-noise, high-gain mixer. It employs a set of current-multiplexed transconductance amplifier circuits and a set of cross-coupled load circuits. Signal amplification is achieved through symmetrical P-type and N-type transconductors, resulting in a larger equivalent transconductance without increasing the path current. Simultaneously, a negative feedback resistor is connected between the input and output of the transconductor, eliminating the need for additional bias circuitry. An inductor is added between the source and ground of the transconductor to form a source negative feedback structure, increasing circuit stability without increasing power consumption or noise. Furthermore, the cross-coupled load circuit generates a larger equivalent load, achieving greater gain and improving circuit noise without increasing power consumption. This mixer exhibits high gain, low noise, and low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a low-noise, high-gain mixer. Background Technology

[0002] In radio frequency (RF) signal receiving and transmitting channels, the role of a mixer is to change the signal frequency from one frequency to another. For example, in the receiving channel, it can convert the signal frequency from the input RF frequency to the output intermediate frequency. However, traditional mixers suffer from problems such as high noise and low gain. Summary of the Invention

[0003] The purpose of this invention is to provide a low-noise, high-gain mixer that has high gain, low noise, and low power consumption.

[0004] To achieve the above objectives, the technical solution adopted by this invention is as follows: a low-noise, high-gain mixer employs a set of current-multiplexed transconductance amplifier circuits and a set of cross-coupled load circuits. The signal is amplified through symmetrical P-type and N-type transconductances, achieving a larger equivalent transconductance without increasing the path current. Simultaneously, a negative feedback resistor is connected between the input and output of the transconductance, eliminating the need for additional bias circuitry. An inductor is added between the source of the transconductance and ground to form a source negative feedback structure, increasing circuit stability without increasing power consumption or noise. Furthermore, the cross-coupled load circuit generates a larger equivalent load, achieving greater gain and improving circuit noise without increasing power consumption.

[0005] Furthermore, it includes a current-reused transconductance amplifier circuit, a switching stage circuit, and a cross-coupled load circuit; wherein, the current-reused transconductance amplifier circuit includes a first NMOS transistor M1, a second NMOS transistor M3, a first PMOS transistor M2, a second PMOS transistor M4, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4; the switching stage circuit includes a third NMOS transistor M5, a fourth NMOS transistor M6, a fifth NMOS transistor M7, and a sixth NMOS transistor M8; the cross-coupled load circuit includes a third PMOS transistor M9, a fourth PMOS transistor M10, a fifth PMOS transistor M11, a sixth PMOS transistor M12, and a third resistor R3.

[0006] Furthermore, one end of the first capacitor C1 serves as the differential input signal port VINP, and the other end of the first capacitor C1 is connected to the gate of the first NMOS transistor M1, the gate of the first PMOS transistor M2, and one end of the first resistor R1. The source of the first NMOS transistor M1 is connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to GND. The source of the first PMOS transistor M2 is connected to one end of the second inductor L2, and the other end of the second inductor L2 is connected to VDD. The other end of the first resistor R1 is connected to the drain of the first NMOS transistor M1 and the gate of the first PMOS transistor M2. The drain of the OS transistor M2, the source of the third NMOS transistor M5, and the source of the fourth NMOS transistor M6 are connected. One end of the second capacitor C2 serves as the differential input signal port VINN. The other end of the second capacitor C2 is connected to the gate of the second NMOS transistor M3, the gate of the second PMOS transistor M4, and one end of the second resistor R2. The source of the second NMOS transistor M3 is connected to one end of the third inductor L3, and the other end of the third inductor L3 is connected to GND. The source of the second PMOS transistor M4 is connected to one end of the fourth inductor L4, and the other end of the fourth inductor L4 is connected to VDD. The other end of the second resistor R2 is connected to the drain of the second NMOS transistor M3, the drain of the second PMOS transistor M4, the source of the fifth NMOS transistor M7, and the source of the sixth NMOS transistor M8; the gates of the third NMOS transistor M5 and the fifth NMOS transistor M7 serve as the input terminals of the local oscillator signal LO+, and the gates of the fourth NMOS transistor M6 and the sixth NMOS transistor M8 serve as the input terminals of the local oscillator signal LO-; the drains of the third NMOS transistor M5, the sixth NMOS transistor M8, the third PMOS transistor M9, and the fourth PMOS transistor M8 are connected to the source of ... The drain of transistor M10, the gate of the fifth PMOS transistor M11, and one end of the third resistor R3 are connected to the output port VOUTN; the drain of the fourth NMOS transistor M6, the drain of the fifth NMOS transistor M7, the drain of the fifth PMOS transistor M11, the drain and gate of the sixth PMOS transistor M12, the gate of the fourth PMOS transistor M10, and the other end of the third resistor are connected to the output port VOUTP; the source of the third PMOS transistor M9, the source of the fourth PMOS transistor M10, the source of the fifth PMOS transistor M11, and the source of the sixth PMOS transistor M12 are connected to VDD.

[0007] Compared with existing technologies, the present invention has the following advantages: The present invention employs a set of current-reused transconductance circuits as the transconductance stage, achieving a larger equivalent transconductance without increasing the operating current. Furthermore, it generates self-bias voltage through negative feedback without the need for a bias circuit. An inductor is added between the transconductance source and ground to form a negative feedback structure, increasing circuit stability without increasing power consumption or noise. In addition, a set of cross-coupled load circuits is used, introducing the concept of negative impedance to generate a larger output impedance. This simultaneously improves the thermal noise and output swing problems caused by traditional resistive loads, resulting in higher gain and lower power consumption. Attached Figure Description

[0008] Figure 1 This is a circuit structure diagram of a low-power, high-gain mixer according to an embodiment of the present invention;

[0009] Figure 2 This is the gain curve of the low-power, high-gain mixer according to an embodiment of the present invention;

[0010] Figure 3 This is the noise curve of the low-power, high-gain mixer according to an embodiment of the present invention;

[0011] Figure 4 This is a circuit diagram of a typical Gilbert double-balanced mixer;

[0012] Figure 5 This is the gain curve of a typical Gilbert double-balanced mixer;

[0013] Figure 6 This is the noise profile of a typical Gilbert double-balanced mixer. Detailed Implementation

[0014] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0015] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0016] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0017] This embodiment provides a low-noise, high-gain mixer circuit, such as... Figure 1As shown, the low-noise, high-gain mixer includes a current-multiplexed transconductance amplifier circuit 1, a switching stage circuit 2, and a cross-coupled load circuit 3. The current-multiplexed transconductance amplifier circuit 1 includes a first NMOS transistor M1, a second NMOS transistor M3, a first PMOS transistor M2, a second PMOS transistor M4, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2, a third inductor L3, and a fourth inductor L4. The switching stage circuit 2 includes a third NMOS transistor M5, a fourth NMOS transistor M6, a fifth NMOS transistor M7, and a sixth NMOS transistor M8. The cross-coupled load circuit 3 includes a third PMOS transistor M9, a fourth PMOS transistor M10, a fifth PMOS transistor M11, a sixth PMOS transistor M12, and a third resistor R3.One end of the first capacitor C1 serves as the differential input signal port VINP. The other end of the first capacitor C1 is connected to the gate of the first NMOS transistor M1, the gate of the first PMOS transistor M2, and one end of the first resistor R1. The source of the first NMOS transistor M1 is connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to GND. The source of the first PMOS transistor M2 is connected to one end of the second inductor L2, and the other end of the second inductor L2 is connected to VDD. The other end of the first resistor R1 is connected to the drain of the first NMOS transistor M1, the gate of the first PMOS transistor M2, and one end of the first resistor R1. The drain of transistor M2, the source of transistor M5, and the source of transistor M6 are connected together. One end of capacitor C2 serves as the differential input signal port VINN. The other end of capacitor C2 is connected to the gate of transistor M3, the gate of transistor M4, and one end of resistor R2. The source of transistor M3 is connected to one end of inductor L3, and the other end of inductor L3 is connected to GND. The source of transistor M4 is connected to one end of inductor L4, and the other end of inductor L4 is connected to VDD. The other end of the second resistor R2 is connected to the drain of the second NMOS transistor M3, the drain of the second PMOS transistor M4, the source of the fifth NMOS transistor M7, and the source of the sixth NMOS transistor M8; the gates of the third NMOS transistor M5 and the fifth NMOS transistor M7 serve as the input terminals of the local oscillator signal LO+, and the gates of the fourth NMOS transistor M6 and the sixth NMOS transistor M8 serve as the input terminals of the local oscillator signal LO-; the drains of the third NMOS transistor M5, the sixth NMOS transistor M8, the third PMOS transistor M9, and the fourth PMOS transistor M10... The drain of the first NMOS transistor M11, the gate of the fifth PMOS transistor M11, and one end of the third resistor R3 are connected to the output port VOUTN; the drain of the fourth NMOS transistor M6, the drain of the fifth NMOS transistor M7, the drain of the fifth PMOS transistor M11, the drain and gate of the sixth PMOS transistor M12, the gate of the fourth PMOS transistor M10, and the other end of the third resistor are connected to the output port VOUTP; the source of the third PMOS transistor M9, the source of the fourth PMOS transistor M10, the source of the fifth PMOS transistor M11, and the source of the sixth PMOS transistor M12 are connected to VDD. The current-multiplexed transconductance amplifier circuit determines the transconductance of the mixer circuit, and the cross-coupled load circuit determines the output impedance of the mixer. Assume the input signal is V. RF COS(W RF t), the local oscillator switching signal is V LO COS(W LO t), the transconductance of both transcatheters M1 and M3 is g. mn The transconductance of both transcatheters M2 and M4 is g. mp The transconductance of cross-coupled transistors M9 and M12 is (g m1The transconductance of cross-coupled transistors M10 and M11 is ( g m2 The resistance of resistor R3 is 2R. load At this time, the equivalent conversion gain of the mixer circuit If g mp = g mn = g m The equivalent transconductance of the transconductance stage is 2g. m It will be twice that of the traditional structure. By selecting appropriate MOSFET parameters and resistor values, the equivalent output impedance of the load stage can be reduced. It is much larger than the traditional structure, and the circuit gain is greatly improved.

[0018] Figure 2 , 3 These are the gain and noise curves of the low-power, high-gain mixer provided in this embodiment.

[0019] Figure 4 This is a circuit diagram of a typical Gilbert double-balanced mixer. Figure 5 , 6 These are the gain and noise curves of a typical Gilbert double-balanced mixer.

[0020] Compared with a typical Gilbert double-balanced mixer, the low-noise, high-gain mixer provided in this embodiment uses a current-reused transconductance circuit as the transconductance stage, achieving a larger equivalent transconductance without increasing the operating current. Furthermore, it generates self-bias through negative feedback without the need for a bias circuit. An inductor is added between the transconductance source and ground to form a negative feedback structure, increasing circuit stability without increasing power consumption or noise. Simultaneously, a set of cross-coupled load circuits is employed, introducing the concept of negative impedance to generate a larger output impedance. This overcomes the problem of small output voltage swing under excessive current in traditional resistive loads, while also improving the thermal noise issues caused by resistive loads, resulting in higher gain and lower power consumption.

[0021] In summary, the low-noise, high-gain mixer provided by this invention can effectively solve the problems of thermal noise limitation of resistive load and insufficient gain in improving the noise performance of the mixer, while achieving the goal of improving the gain and noise performance of the mixer circuit.

[0022] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A low noise high gain mixer characterized by, A set of current multiplexing transconductance amplification circuits and a set of cross-coupled load circuits are adopted, a signal is amplified through symmetric P-type transconductance tubes and N-type transconductance tubes, greater equivalent transconductance is obtained under the premise of not increasing the passage current, a negative feedback resistor is connected between the input and output of the transconductance tube, a bias circuit is not needed to be additionally introduced for biasing, an inductor is added between the source of the transconductance tube and the ground to form a source negative feedback structure, the circuit stability is increased under the premise of not increasing the power consumption and noise; Greater equivalent load is generated by the cross-coupled load circuit, greater gain is obtained under the premise of not increasing the power consumption, and the circuit noise is improved; The current multiplexing transconductance amplification circuit (1) comprises a first NMOS tube (M1), a second NMOS tube (M3), a first PMOS tube (M2), a second PMOS tube (M4), a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2), a first inductor (L1), a second inductor (L2), a third inductor (L3) and a fourth inductor (L4); the switch stage circuit (2) comprises a third NMOS tube (M5), a fourth NMOS tube (M6), a fifth NMOS tube (M7) and a sixth NMOS tube (M8); and the cross-coupled load circuit (3) comprises a third PMOS tube (M9), a fourth PMOS tube (M10), a fifth PMOS tube (M11) and a sixth PMOS tube (M12) and a third resistor (R3). One end of the first capacitor (C1) is a differential input signal port VINP, the other end of the first capacitor (C1) is connected with the gate of the first NMOS transistor (M1), the gate of the first PMOS transistor (M2) and one end of the first resistor (R1), the source of the first NMOS transistor (M1) is connected with one end of the first inductor (L1), the other end of the first inductor (L1) is connected with GND, the source of the first PMOS transistor (M2) is connected with one end of the second inductor (L2), the other end of the second inductor (L2) is connected with VDD, the other end of the first resistor (R1) is connected with the drain of the first NMOS transistor (M1), the drain of the first PMOS transistor (M2), the source of the third NMOS transistor (M5) and the source of the fourth NMOS transistor (M6); one end of the second capacitor (C2) is a differential input signal port VINN, the other end of the second capacitor (C2) is connected with the gate of the second NMOS transistor (M3), the gate of the second PMOS transistor (M4) and one end of the second resistor (R2), the source of the second NMOS transistor (M3) is connected with one end of the third inductor (L3), the other end of the third inductor (L3) is connected with GND, the source of the second PMOS transistor (M4) is connected with one end of the fourth inductor (L4), the other end of the fourth inductor (L4) is connected with VDD, the other end of the second resistor (R2) is connected with the drain of the second NMOS transistor (M3), the drain of the second PMOS transistor (M4), the source of the fifth NMOS transistor (M7) and the source of the sixth NMOS transistor (M8); the gate of the third NMOS transistor (M5) and the gate of the fifth NMOS transistor (M7) are input terminals of the local oscillator signal LO+, the gate of the fourth NMOS transistor (M6) and the gate of the sixth NMOS transistor (M8) are input terminals of the local oscillator signal LO-; the drain of the third NMOS transistor (M5), the drain of the sixth NMOS transistor (M8), the drain and the gate of the third PMOS transistor (M9), the drain of the fourth PMOS transistor (M10), the gate of the fifth PMOS transistor (M11) and one end of the third resistor (R3) are connected with the output port VOUTN; the drain of the fourth NMOS transistor (M6), the drain of the fifth NMOS transistor (M7), the drain of the fifth PMOS transistor (M11), the drain and the gate of the sixth PMOS transistor (M12), the gate of the fourth PMOS transistor (M10) and the other end of the third resistor (R3) are connected with the output port VOUTP; the source of the third PMOS transistor (M9), the source of the fourth PMOS transistor (M10), the source of the fifth PMOS transistor (M11), the source of the sixth PMOS transistor (M12) are connected with VDD.

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