FPGA reinforcement system and method for resisting single event upset

Abstract

The present invention belongs to the field of data processing technology and relates to an FPGA hardening system for single-event upset resistance. The system comprises an SRAM-type FPGA, a FLASH-type FPGA, and a FLASH memory. The FLASH-type FPGA includes a common pin and an SPI pin. The common pin is connected to the SRAM-type FPGA. The FLASH-type FPGA is used to refresh erroneous configuration information generated by single-event upsets within the SRAM-type FPGA in real time. The SPI pin is connected to the FLASH memory. This radiation-hardening system, which uses the Flash-type FPGA to refresh the SRAM-type FPGA, is inexpensive and allows for repeated programming of logic.

Description

Technical Field

[0001] The present invention relates to an FPGA reinforcement system and method for resisting single-particle upset, and belongs to the technical field of data processing. Background Art

[0002] The radiation environment created by high-energy particle discharges in modern particle experiments poses significant challenges to the radiation resistance and autonomous, stable operation of instrumentation. Large-scale integrated circuits (VLSIs), particularly field-programmable gate arrays (FPGAs), with their superior interfaces and powerful data processing capabilities, have become the information exchange hub for data acquisition, transmission, and processing in digital systems, and are widely used. However, due to their high level of integration, FPGA logic circuits are susceptible to radiation from high-energy charged particles, causing upsets in circuit structures such as registers and memory cells. Single-event upsets (SEUs) occur at random locations, and if they occur at critical bits, they can cause single-event functional interruptions. Therefore, designing front-end acquisition systems with strong radiation resistance is crucial.

[0003] Faults that occur in SRAM-based FPGAs can be divided into two types: permanent faults and transient faults. When an SEU occurs in a configuration bit in the configuration memory, the SEU may cause the user circuit to malfunction. If the FPGA is not reconfigured, the SEU will remain permanently in the configuration memory, and the circuit will permanently malfunction. This type of fault is called a permanent fault, and errors caused by permanent faults are called permanent errors. When an SEU occurs in a trigger in the FPGA or in an SRAM cell used as distributed RAM in the configuration memory, the SEU only affects the current circuit state. When the storage cell receives the next value, a correct new value will overwrite the previously flipped value, and after a period of time, the circuit returns to a fault-free state. This type of fault is called a transient fault, and errors caused by transient faults are called transient errors. Whether it is a permanent fault or a transient fault in an SRAM-based FPGA, it is caused by a single-particle upset. Summary of the Invention

[0004] In response to the above problems, the purpose of the present invention is to provide an FPGA reinforcement system and method for single-event upset resistance, which selects Flash-type FPGA to refresh SRAM-type FPGA for radiation-resistant reinforcement. It is cheap and can repeatedly burn logic multiple times.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: an FPGA reinforcement system for resisting single-particle upsets, comprising: an SRAM-type FPGA, a FLASH-type FPGA, and a FLASH memory; the FLASH-type FPGA includes a common pin and an SPI pin, the common pin is connected to the SRAM-type FPGA, the FLASH-type FPGA is used to refresh the erroneous configuration information generated by single-particle upsets in the SRAM-type FPGA in real time, and the SPI pin is connected to the FLASH memory.

[0006] Furthermore, the data processing path in the SRAM-type FPGA is divided into several areas, each area includes a redundant logic block and a configuration control block; when an area generates erroneous configuration information, only the area corresponding to the erroneous configuration information is refreshed.

[0007] Furthermore, the refresh of the area adopts a triple-module redundancy method.

[0008] Furthermore, the region includes three redundant logic blocks, all of which are connected to the voting and feedback module. The voting and feedback module gives a final result based on the majority priority principle. One output end of the voting and feedback module outputs the final result, and the other output end of the voting and feedback module is connected to the configuration control block, which generates a control signal.

[0009] Furthermore, if there is erroneous configuration information in the area, the voting and feedback module determines the redundant logic block where the error occurs, and generates a corresponding control signal through the configuration control block.

[0010] Furthermore, the control signal is connected to the error handling module, which is connected to the FLASH FPGA and is used to summarize the control signals generated by each area, generate total error configuration information, and feed back the total error configuration information to the FLASH FPGA. The error handling module includes a buffer queue, which is sent to the refresh control logic in the Flash FPGA according to the timing.

[0011] Furthermore, the FLASH type FPGA includes a FLASH file download control unit and a FLASH programming control unit. The FLASH file download control unit is responsible for downloading the bit stream file generated by the PC to the Flash memory on the board; the FLASH programming control unit is connected to the SRAM type FPGA to control the judgment and start of the SRAM type FPGA refresh.

[0012] Furthermore, the FLASH programming control unit includes a status arbitration FSM, an error buffer queue and a Flash data reading and programming processing module. When the status arbitration FSM receives the error configuration information from the error processing module, it gives a refresh start signal, the target address and data length of the error configuration information, and repairs this part of the error circuit through the programming pin; when the error buffer queue has too many error areas and is greater than the correction speed, it buffers the remaining unprocessed error configuration information.

[0013] Furthermore, the Flash data reading and programming processing module includes ordinary pins and SPI pins, and is connected to the Flash memory and the SRAM type FPGA through the ordinary pins and the SPI pins respectively.

[0014] The present invention also discloses an FPGA reinforcement method for resisting single-particle upsets, which adopts any of the above-mentioned FPGA reinforcement systems for resisting single-particle upsets, including the following steps: S1 starts and powers on the reinforcement system; S2 configures the refresh process of the FLASH type FPGA, and stores data in the Flash memory through the FLASH type FPGA; S3 configures the SRAM type FPGA, and at the same time determines whether there is erroneous configuration information through a voting and feedback module. If so, the erroneous information is transmitted to the FLASH type FPGA, and refreshes according to the instructions of the FLASH type FPGA to repair the erroneous configuration information.

[0015] Due to the above technical solutions, the present invention has the following advantages: 1. The SRAM-type FPGA structure is relatively flexible and conducive to function development. It is easy to refresh and repair after errors. Therefore, the target system functions are developed based on the SRAM-type FPGA. 2. The Flash-type FPGA has a floating gate structure, which is not easily affected by radiation and has higher reliability. It can refresh and repair the circuit configuration and operating process of the target system that are susceptible to single-event upsets. 3. A solution combining triple-module redundancy reinforcement technology and partial reconfiguration refresh technology is used to implement radiation-resistant hardening design. The circuits in the SRAM-type FPGA structure are partitioned and planned, enabling independent refresh in each area to improve the speed of error repair. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of an FPGA reinforcement system for resisting single event upset in one embodiment of the present invention;

[0017] Figure 2 Schematic diagram of a triple-module redundancy method in an SRAM-type FPGA according to one embodiment of the present invention;

[0018] Figure 3 1 is a schematic diagram of the structure of a Flash-type FPGA in one embodiment of the present invention;

[0019] Figure 4 This is a flow chart of a method for reinforcing an FPGA against single event upsets in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical direction of the present invention, the present invention will be described in detail through specific embodiments. However, it should be understood that the provision of specific embodiments is only for a better understanding of the present invention and they should not be construed as limitations of the present invention. In the description of the present invention, it should be understood that the terms used are for descriptive purposes only and are not to be construed as indicating or implying relative importance.

[0021] Example 1

[0022] An FPGA hardening system for single event upset resistance, such as Figure 1 As shown, it includes: an SRAM-type FPGA, a FLASH-type FPGA, and a FLASH memory. The FLASH-type FPGA includes a common pin and an SPI pin. The common pin is connected to the SRAM-type FPGA. The FLASH-type FPGA is used to refresh the incorrect configuration information generated by single-particle upsets in the SRAM-type FPGA in real time. The SPI pin is connected to the FLASH memory. The pins connecting the SRAM-type FPGA and the FLASH-type FPGA are mainly the SRAM-type FPGA's configuration pins (reconfiguration pin, initialization pin, download completion pin, configuration clock pin, and bitstream input pin) connected to the FLASH-type FPGA's common IO pins. Several common IO pins of the SRAM-type FPGA are connected to the common IO pins of the FLASH-type FPGA. The FLASH-type FPGA's SPI mode configuration pin is connected to the corresponding pins of the FLASH memory, such as the chip select pin, configuration clock pin, data write pin, and data output pin.

[0023] In order to ensure that the system functions can operate normally during the error and refresh phases without intermittent impact, this patent proposes a refresh mechanism for triple-module redundancy that can effectively enhance the system's operational stability. The basic idea is to use triple-module redundancy design to improve the circuit. When a circuit flip problem occurs in one of the three redundant blocks, it can output correct data based on the result of the voter algorithm and immediately start the configuration refresh function to repair and refresh the erroneous circuit to ensure that no circuit errors accumulate. In order to match the form of partial reconfiguration blocks, such as Figure 2As shown, in this embodiment, the data processing path in the SRAM-based FPGA is divided into several regions, each of which includes a redundant logic block and a configuration control block. When a region generates incorrect configuration information, only the region corresponding to the incorrect configuration information is refreshed. This region refresh utilizes a triple-module redundancy method. Each region includes three redundant logic blocks, each connected to a voting and feedback module. The voting and feedback module generates a final result based on the majority rule. One output of the voting and feedback module outputs the final result, and another output of the voting and feedback module is connected to the configuration control block, which generates a control signal. If a region contains incorrect configuration information, the voting and feedback module determines the redundant logic block with the error and generates a corresponding control signal through the configuration control block. The control signal is connected to an error processing module, which is connected to the FLASH-based FPGA and aggregates the control signals generated by each region to generate total error configuration information. This total error configuration information is then fed back to the FLASH-based FPGA. The error processing module includes a buffer queue, which is sent to the refresh control logic in the Flash-based FPGA in a timed manner.

[0024] Each redundant logic block is a partially reconfigurable block and has a corresponding partial bitstream file for backup. When an error occurs in the circuit, the triple-module redundant voter determines which redundant logic block is faulty based on the outputs of the three circuits and activates the corresponding refresh logic. As long as the refresh logic's refresh rate is slower than the rate at which two redundant logic blocks in the triple-module redundant module experience failures simultaneously, the first faulty redundant logic block can be repaired before the second fault occurs, thus protecting the circuit without affecting normal system operation.

[0025] like Figure 3 As shown, a FLASH-based FPGA includes a FLASH file download control unit and a FLASH programming control unit. The FLASH file download control unit is responsible for downloading the bitstream file generated by the PC to the onboard Flash memory. The FPGA and PC use the UART protocol (or other buses or custom buses) to transmit the partial bitstream file for each region, and use the SPI protocol to write the data to the Flash memory as a backup. The Flash memory stores the correct bitstream file, including the complete bitstream and some partial bitstream files. The Flash memory contains different versions of the bitstream file, which can be replaced at any time according to system needs.

[0026] The FLASH programming control unit is connected to the SRAM type FPGA to control the judgment and startup of the SRAM type FPGA refresh logic and monitor the working status of each module. It can read the appropriate bit stream file from the Flash memory according to the voting results of the SRAM type FPGA and configure the FLASH type FPGA with the appropriate timing relationship.

[0027] The FLASH programming control unit consists of a state arbitration FSM, an error buffer queue, and a flash data read and programming processing module. The state arbitration FSM is a state machine that controls the overall operating state and all programming and refresh startup logic of the system. When the state arbitration FSM receives error configuration information from the error handling module, it issues a refresh start signal, the target address and data length of the error configuration information, and repairs the erroneous circuitry via the programming pins. When the error buffer queue has too many error areas and exceeds the correction speed, it buffers the remaining unprocessed error configuration information. The flash data read and programming processing module includes standard pins and SPI pins, which connect to the flash memory and SRAM-type FPGA via these pins, respectively. The flash memory is accessed page by page in 256KB increments, and the read data is then sent to the programming pins for configuration according to a specific timing relationship.

[0028] Example 2

[0029] Based on the same inventive concept, this embodiment discloses a method for reinforcing an FPGA against a single event upset, using any of the above-mentioned FPGA reinforcement systems for reinforcing an FPGA against a single event upset, such as Figure 4 As shown, the following steps are included:

[0030] S1 will power on the reinforcement system;

[0031] S2 configures the refresh process for the FLASH type FPGA and stores the data in the Flash memory through the FLASH type FPGA;

[0032] S3 configures the SRAM FPGA and determines whether there is any erroneous configuration information through the voting and feedback module. If so, the erroneous information is transmitted to the FLASH FPGA and refreshed according to the instructions of the FLASH FPGA to repair the erroneous configuration information.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the specific embodiments of the present invention can still be modified or replaced by equivalents, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be included within the scope of protection of the claims of the present invention. The above content is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An FPGA reinforcement system for single event upset resistance, characterized in that: include: SRAM type FPGA, FLASH type FPGA and FLASH memory; The FLASH-type FPGA peripheral connection pins include a common pin and an SPI pin. The common pin is connected to the SRAM-type FPGA. The FLASH-type FPGA is used to refresh error information generated by single-particle upsets inside the SRAM-type FPGA in real time. The SPI pin is connected to the FLASH memory. The SRAM-type FPGA is configured and, at the same time, determines whether error information exists through a voting and feedback module. If so, the error information is transmitted to the FLASH-type FPGA, and the error area is refreshed according to the instructions of the FLASH-type FPGA to repair the error information. The data processing path in the SRAM-type FPGA is processed in regions, and redundant logic blocks and configuration control blocks are divided alternately. Each group of redundant logic blocks and configuration control blocks is a triple-module redundant design. When a redundant logic block generates error information, only the region corresponding to the error information is refreshed. The region includes three redundant logic blocks, and the three redundant logic blocks are all connected to a voting and feedback module. The voting and feedback module gives a final result based on the majority priority principle. One output end of the voting and feedback module outputs the final result, and the other output end of the voting and feedback module is connected to the configuration control block. The configuration control block generates a control signal. The refresh technology of the region and triple-module redundancy are used in combination to improve the fault tolerance of the FPGA to radiation effects.

2. The FPGA reinforcement system for resisting single event upset according to claim 1, characterized in that: If error information exists in the region, the voting and feedback module determines the redundant logic block where the error occurs, and generates a corresponding control signal through the configuration control block for the error information.

3. The FPGA reinforcement system for resisting single event upset according to claim 2, characterized in that: The control signal is connected to the error processing module, and the error processing module is connected to the FLASH type FPGA, and is used to summarize the control signals generated by each area, generate total error information, and feed back the total error information to the FLASH type FPGA. The error processing module includes a buffer queue, and the error processing module sends it to the refresh control logic in the Flash type FPGA according to the timing.

4. The FPGA reinforcement system for resisting single event upset according to claim 3, characterized in that: The FLASH type FPGA logic unit includes a FLASH file download control unit and a FLASH programming control unit. The FLASH file download control unit is responsible for downloading the bit stream file generated by the PC end to the Flash memory on the board; The FLASH programming control unit is connected to the SRAM type FPGA and is used to control the judgment and start of the SRAM type FPGA refresh.

5. The FPGA reinforcement system for resisting single event upset according to claim 4, characterized in that: The FLASH programming control unit includes a state arbitration FSM, an error buffer queue and a Flash data reading and programming processing module. When the state arbitration FSM receives error information from the error processing module, it gives a refresh start signal, the target address and data length of the error information, and repairs this part of the error circuit through the programming pin; when there are too many error areas in the error buffer queue and the speed is greater than the correction speed, the remaining unprocessed error information is buffered.

6. The FPGA reinforcement system for resisting single event upset according to claim 5, characterized in that: The Flash data reading and programming processing logic are circuits for accessing the Flash chip and actually configuring the SRAM type FPGA respectively; the peripheral connection pins include ordinary pins and SPI pins, and are connected to the SRAM type FPGA and Flash memory respectively through ordinary pins and SPI pins.

7. A method for reinforcing FPGA against single event upset, characterized in that: The FPGA reinforcement system for resisting single event upset according to any one of claims 1 to 6 comprises the following steps: S1 starts and powers on the reinforcement system; S2 performs a refresh process configuration on the FLASH type FPGA and downloads the bit stream file into the Flash memory through the FLASH type FPGA; S3 configures the SRAM-type FPGA and determines whether there is error information through the voting and feedback module, that is, whether a single-event upset occurs in the regional circuit. If so, the error information is transmitted to the FLASH-type FPGA and the error area is refreshed according to the instruction of the FLASH-type FPGA to repair the error information.

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