Semiconductor Package

Abstract

The present invention provides a semiconductor package, which may include: a frame including an insulating layer, a first column and a second column, a wiring layer and a metal plate, the insulating layer having a cavity formed in the lower surface of the insulating layer, the first column and the second column being spaced apart from the cavity, the wiring layer being disposed on the upper surface of the insulating layer, and the metal plate being disposed on the upper side of the cavity; a semiconductor chip having a first surface provided with a connection pad and a second surface opposite to the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip and including one or more redistribution layers. The first column is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second column is spaced apart from the first column.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0039027 filed on April 3, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package, for example, a fan-out type semiconductor package. Background Art

[0003] In recent years, one of the main trends in the development of technology related to semiconductor chips is to reduce the size of components. Therefore, in the field of packaging, it is necessary to realize a large number of pins with small size according to the surge in demand for small semiconductor chips and the like.

[0004] To meet this demand, one proposed semiconductor packaging technology is a fan-out semiconductor package, which can redistribute electrical connection structures outside the area where the semiconductor chip is disposed, thereby enabling a large number of pins while maintaining a small size. Summary of the invention

[0005] An aspect of the present disclosure is to provide a semiconductor package having improved heat dissipation performance and relatively high design freedom.

[0006] One solution proposed in the present disclosure is to form a cavity in which a semiconductor chip is disposed by using a metal plate as an etching barrier and to introduce an insulating metal pillar.

[0007] According to one aspect of the present disclosure, a semiconductor package includes: a frame including an insulating layer, a first column and a second column, a wiring layer, and a metal plate, the insulating layer having a cavity located in a lower surface of the insulating layer, the first column and the second column being embedded in the insulating layer and spaced apart from the cavity, the wiring layer being disposed on an upper surface of the insulating layer, and the metal plate being disposed on an upper side of the cavity; a semiconductor chip having a first surface provided with a connection pad and a second surface opposite to the first surface, and including a bump disposed on the connection pad, the semiconductor chip being disposed in the cavity and the second surface facing the metal plate; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers electrically connected to the bump of the semiconductor chip. The first column is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second column is spaced apart from the first column.

[0008] According to one aspect of the present disclosure, a semiconductor package includes: a connection structure including a redistribution layer; an insulating layer disposed on the connection structure and having a cavity; a first column and a second column embedded in the insulating layer and extending from the connection structure; a semiconductor chip having a first surface provided with a connection pad and a second surface opposite to the first surface, and including a bump connecting the connection pad and the connection structure to each other; an encapsulant filling the cavity and separating a side surface of the semiconductor chip and the insulating layer from each other; a metal plate disposed between the insulating layer and the second surface of the semiconductor chip; and a wiring layer disposed on the insulating layer. The first column is electrically connected to the wiring layer, the redistribution layer, and the connection pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0011] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0012] Figure 3A and Figure 3B is a schematic cross-sectional view showing states of a fan-in type semiconductor package before and after being packaged;

[0013] Figure 4 is a schematic cross-sectional view showing a packaging process of a fan-in type semiconductor package;

[0014] Figure 5 is a schematic cross-sectional view showing a state where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device;

[0015] Figure 6 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device;

[0016] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package;

[0017] Figure 8 is a schematic cross-sectional view showing a state where a fan-out type semiconductor package is mounted on a main board of an electronic device;

[0018] Fig. 9 is a schematic cross-sectional view showing a semiconductor package according to an example;

[0019] FIG. 10A to FIG. 10C It is shown along Fig. 9 A schematic plan view of a section taken along line II′;

[0020] Fig.11 and Fig.12 is a schematic cross-sectional view showing a semiconductor package according to other examples; and

[0021] Figures 13 to 18 It shows that according to Fig.12 A schematic diagram of a manufacturing process of a semiconductor package is shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings. For clarity, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0023] Electronic Devices

[0024] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0025] Referring to the drawings, the electronic device 1000 may include a mainboard 1010. The mainboard 1010 may be physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040. They may also be combined with other components to be described later through various signal lines 1090.

[0026] The chip-related components 1020 may include the following chips: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc., but are not limited thereto, and may include other types of chip-related components. These chip-related components 1020 may be combined with each other.

[0027] The network-related components 1030 may include components operating according to protocols such as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless protocols and wired protocols designated as the following protocols, but the network-related components 1030 are not limited thereto, but may also include components operating according to other various wireless standards or protocols or wired standards or protocols. The network-related components 1030 may also be combined with the chip-related components 1020.

[0028] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc., but other components 1040 are not limited thereto, but may include other passive components for various other purposes. Other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0029] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. The other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage device (e.g., a hard disk drive) (not shown), a compact disk (CD) (not shown), and a digital versatile disk (DVD) (not shown), etc., but are not limited thereto and may include other components for various purposes according to the type of the electronic device 1000.

[0030] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, an automotive component, etc., but the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0031] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0032] Referring to the accompanying drawings, the semiconductor package may be applied to various electronic devices for various purposes as described above. For example, a printed circuit board 1110 (such as a main board) may be included in a body 1101 of a smart phone 1100. In addition, various components 1120 may be physically and / or electrically connected to the printed circuit board 1110. In addition, other components (such as a camera 1130) that may or may not be physically and / or electrically connected to the printed circuit board 1110 may be accommodated in the body 1101. A portion of the component 1120 may be a chip-related component, such as, but not limited to, a semiconductor package 1121. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0033] Semiconductor Package

[0034] Generally, a semiconductor chip may have many integrated microelectronic circuits therein, but the semiconductor chip itself is not necessarily used as a finished semiconductor product, and the semiconductor chip may be damaged by external physical impact or chemical impact. Therefore, the semiconductor chip itself may not be used as it is, but may be packaged and used in an electronic device or the like in such a packaged state.

[0035] In terms of electrical connection, semiconductor packaging may be necessary due to the difference in circuit width between the semiconductor chip and the main board of the electronic device. Specifically, for the semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small and narrow, while the size of the component mounting pad and the spacing between the component mounting pads are much larger and wider than the specifications of the semiconductor chip, respectively. Therefore, since it is difficult to directly mount the semiconductor chip on such a main board, a packaging technology that can alleviate the difference in circuit width between the semiconductor chip and the main board of the electronic device is required.

[0036] Semiconductor packages manufactured by such packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and uses.

[0037] Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.

[0038] Fan-in semiconductor package

[0039] Figure 3A and Figure 3B is a cross-sectional view schematically showing a fan-in type semiconductor package before and after packaging.

[0040] Figure 4 is a cross-sectional view schematically illustrating a packaging process of a fan-in type semiconductor package.

[0041] Referring to the accompanying drawings, the semiconductor chip 2220 may be an integrated circuit (IC) in a bare state. The body 2221 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The connection pad 2222 may include a conductive material (such as aluminum (Al), etc.) and is formed on one surface of the body 2221. A passivation film 2223 (such as an oxide film, a nitride film, etc.) may be formed on one surface of the body 2221 and may cover at least a portion of the connection pad 2222. In this case, since the connection pad 2222 is very small, it may be difficult to even mount the integrated circuit (IC) on a printed circuit board (PCB) of a medium-sized class and a main board of an electronic device.

[0042] According to the size of the semiconductor chip 2220, a connection structure 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222. The connection structure 2240 may be prepared by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin; forming a via hole 2243h for opening the connection pads 2222; and forming a wiring pattern 2242 and a via 2243. Then, a passivation layer 2250 for protecting the connection structure 2240 may be formed, an opening 2251 may be formed, and an under bump metallization layer 2260 may be formed. For example, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an under bump metallization layer 2260 may be formed by a series of processes.

[0043] As described above, a fan-in semiconductor package may be a package type in which all the connection pads (e.g., input / output (I / O) terminals) of a semiconductor chip are arranged inside the component. The fan-in semiconductor package may have good electrical characteristics and may be produced at a relatively low cost. Therefore, many components in a smart phone may be manufactured in the form of a fan-in semiconductor package. Specifically, the fan-in semiconductor package is developing in the direction of achieving a small size and simultaneously achieving fast signal transmission.

[0044] Since in a fan-in semiconductor package, all I / O terminals should be arranged inside the semiconductor chip, there may be many limitations in space. Therefore, such a structure may be difficult to apply to a semiconductor chip with a large number of I / O terminals or a semiconductor chip with a small size. In addition, due to this problem, it may not be possible to directly mount the fan-in semiconductor package on the mainboard of an electronic device and use the fan-in semiconductor package in the mainboard of the electronic device. Even when the size and spacing of the I / O terminals of the semiconductor chip are enlarged in the redistribution process, they do not have a size and spacing sufficient to be directly mounted on the mainboard of the electronic device.

[0045] Figure 5 is a cross-sectional view schematically showing that a fan-in type semiconductor package is mounted on an interposer substrate that is finally mounted on a main board of an electronic device.

[0046] Figure 6 is a cross-sectional view schematically showing a fan-in type semiconductor package embedded in an interposer substrate that is finally mounted on a main board of an electronic device.

[0047] Referring to the drawings, the fan-in type semiconductor package 2200 may be configured such that the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 are redistributed again through the interposer substrate 2301, and the fan-in type semiconductor package 2200 mounted on the interposer substrate 2301 is mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like may be fixed using the bottom filling resin 2280, and the outside of the solder balls 2270 may be covered using the molding material 2290 and the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 may be redistributed again through the interposer substrate 2302 in an embedded form, and finally mounted on the main board 2500 of the electronic device.

[0048] As described above, it may be difficult to directly mount the fan-in type semiconductor package on the main board of the electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate interposer substrate and then mounted on the main board of the electronic device through a packaging process, or may be mounted on the main board of the electronic device in a form embedded in the interposer substrate.

[0049] Fan-out semiconductor packages

[0050] Figure 7 is a cross-sectional view schematically showing a fan-out type semiconductor package.

[0051] Referring to the drawings, in a fan-out type semiconductor package 2100, for example, the outside of a semiconductor chip 2120 may be protected by an encapsulant 2130, and a connection pad 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 by a connection structure 2140. A passivation layer 2150 may be further formed on the connection structure 2140. An under bump metallization layer 2160 may be further formed in an opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metallization layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, and the like. The connection structure 2140 may include: an insulating layer 2141; a wiring layer 2142 formed on the insulating layer 2141; and a via 2143 for electrically connecting the connection pad 2122 and the wiring layer 2142.

[0052] A fan-out semiconductor package can be formed in the following manner: the I / O terminals are redistributed to the outside of the semiconductor chip through a connection structure formed on the semiconductor chip. As described above, in a fan-in semiconductor package, all the I / O terminals of the semiconductor chip should be arranged inside the semiconductor chip. When the size of the element is reduced, the size and pitch of the ball should be reduced. Therefore, a standardized ball layout may not be used. On the other hand, in a fan-out semiconductor package, the I / O terminals can be redistributed from the semiconductor chip to the outside through a connection structure formed on the semiconductor chip. Although the size of the semiconductor chip is reduced, the standardized ball layout can still be used as it is. Therefore, the fan-out semiconductor package can be mounted on the mainboard of an electronic device without a separate printed circuit board, as described later.

[0053] Figure 8 is a cross-sectional view schematically showing that a fan-out type semiconductor package is mounted on a main board of an electronic device.

[0054] Referring to the drawings, the fan-out type semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through solder balls 2170, etc. For example, as described above, the fan-out type semiconductor package 2100 may include a connection structure 2140 on the semiconductor chip 2120 that may redistribute the connection pads 2122 to a fan-out region outside the size of the semiconductor chip 2120. The standardized ball layout may be used as is, and as a result, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device without a separate printed circuit board, etc.

[0055] Since the fan-out semiconductor package can be mounted on the main board of the electronic device without a separate interposer substrate (as above), the fan-out semiconductor package can be made thinner than the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package can be made smaller and thinner. Because of the excellent thermal and electrical properties of the fan-out semiconductor package, it can also be suitable for mobile products. In addition, the fan-out semiconductor package can be implemented to be more compact than the ordinary package-on-package (POP) type using a printed circuit board (PCB), and problems caused by the bending phenomenon can be prevented.

[0056] A fan-out semiconductor package may refer to a packaging technology used to mount a semiconductor chip on a mainboard of an electronic device, etc. and to protect the semiconductor chip from external impacts, and may have a different concept from a printed circuit board (PCB) such as an intermediate substrate in which a fan-in semiconductor package is embedded (the two differ from each other in specifications, uses, etc.).

[0057] Hereinafter, various embodiments of the present disclosure may be described with reference to the accompanying drawings.

[0058] Fig. 9 is a schematic cross-sectional view illustrating a semiconductor package according to an example.

[0059] Reference Fig. 9 A semiconductor package 100A according to an example embodiment may include: a frame 110 including an insulating layer 111, a first pillar 114 and a second pillar 115, a wiring layer 112, and a metal plate 116, the insulating layer 111 having a cavity 110H formed on a lower surface of the insulating layer 111, the first pillar 114 and the second pillar 115 embedded in the insulating layer 111 and spaced apart from the cavity 110H, the wiring layer 112 disposed on an upper surface of the insulating layer 111, and the metal plate 116 disposed on an upper side of the cavity 110H; a semiconductor chip 120 having There is a first surface provided with connection pads 120P and a second surface opposite to the first surface, and includes bumps 120B provided on the connection pads 120P, the second surface of the semiconductor chip is provided in the cavity 110H and faces the metal plate 116; an encapsulant 130 covering at least a portion of the semiconductor chip 120; and a connection structure 140 provided on the frame 110 and the first surface of the semiconductor chip 120, and including one or more redistribution layers 142 electrically connected to the bumps 120B of the semiconductor chip 120. The first pillar 114 may be electrically connected to the wiring layer 112 of the frame 110 and the redistribution layer 142 of the connection structure 140, and the second pillar 115 may be spaced apart from the first pillar 114 by a predetermined distance.

[0060] The cavity 110H may be a groove structure recessed from one surface of the insulating layer 111 into the insulating layer 111 without penetrating the frame 110, and may serve as a barrier for preventing the metal plate 116 disposed on one side of the cavity 110H from penetrating the insulating layer 111. As described later, since the cavity 110H may be formed by etching a cavity metal, the shape of the cavity 110H may be freely designed by designing the cavity metal in a specific form.

[0061] The first column 114 may be electrically connected to the wiring layer 112 and the redistribution layer 142 to form an electrical path inside the frame 110. The second column 115 may be spaced apart from the first column 114 by a predetermined distance without physically contacting the first column 114 in the frame 110. For example, the second column 115 may be physically separated from the first column 114 and may be formed in a space where the first column 114 is not provided to increase the volume of the metal surrounding the semiconductor chip 120. Therefore, the heat dissipation performance of the package may be improved. In addition, the second column 115 may be electrically connected to the ground pattern of the wiring layer 112 and the redistribution layer 142 to serve as a ground. Optionally, the second column 115 may be electrically insulated from the first column 114, the wiring layer 112, the redistribution layer 142, and the connection pad 120P.

[0062] Furthermore, since the encapsulant 130 on the frame 110 excluding the encapsulant 130 filling the cavity 110H is removed through the grinding process, the thickness of the package may be reduced while warpage due to the encapsulant 130 may be minimized.

[0063] FIG. 10A to FIG. 10C It is shown along Fig. 9 Schematic plan view of a section taken along line II′.

[0064] Reference FIG. 10A to FIG. 10C , a semiconductor package 100A according to an example may include a first column 114 and a second column 115 of a metal material surrounding a cavity in which a semiconductor chip 120 is disposed. A plurality of first columns 114 may be arranged around the semiconductor chip 120 at any interval, and a plurality of second columns 115 may be arranged so as not to overlap with the first columns 114, specifically, a plurality of second columns 115 may be centrally disposed in an area in which the first columns 114 are distributed in a relatively small number. FIG. 10A to FIG. 10C The shape of the second pillar 115 shown in FIG. 1 may be for illustration purposes only and is not limited thereto.

[0065] Hereinafter, each configuration included in the semiconductor package 100A according to an example will be described in more detail.

[0066] The frame 110 may improve the rigidity of the semiconductor package 100A according to a specific material, and may play a role in ensuring the uniformity of the thickness of the encapsulant 130. The frame 110 may have at least one cavity 110H. The cavity 110H may be recessed from one side of the frame 110, and the semiconductor chip 120 may be disposed in the cavity 110H. The semiconductor chip 120 may be spaced apart from the wall surface of the cavity 110H by a predetermined distance, and may be surrounded by the wall surface of the cavity 110H. It is understood that the present disclosure is not limited to the above-described embodiments, and various changes and modifications may be made without departing from the scope and spirit of the present disclosure.

[0067] Since the frame 110 may include the wiring layer 112, the connection structure 140 may be further simplified. Therefore, it is possible to improve the reduction in yield due to defects generated in the process of forming the connection structure 140. Specifically, since the wiring layer 112 may be provided on the ineffective surface of the semiconductor chip 120, a backside wiring layer for the semiconductor chip 120 may be provided without forming a separate backside wiring layer, and the process cost for forming a separate backside wiring layer may be reduced.

[0068] The metal plate 116 may be disposed on the upper surface of the cavity 110H. The semiconductor chip 120 may be disposed on the metal plate 116. In addition, the metal plate 116 may be used as an etch stop layer for forming the cavity 110H.

[0069] The process of forming the cavity 110H is not particularly limited, and the cavity 110H may be formed by an etching operation. As described later, the cavity metal may be removed to use the space previously occupied by the cavity metal as a cavity, and the shape of the cavity may depend on the shape of the cavity metal. For example, the shape of the wall surface of the cavity may correspond to the shape of the side wall of the cavity metal, and the width of the cavity 110H may correspond to the width of the metal plate 116. In this case, the interval between the semiconductor chip 120 and the side wall of the cavity 110H may be kept constant to increase the heat radiation efficiency through the frame 110.

[0070] The material of the insulating layer 111 is not particularly limited. For example, a resin containing a reinforcing material such as an inorganic filler (such as silica, alumina, etc.) and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide (specifically, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), photosensitive dielectric (PID) resin, etc.) can be used. Alternatively, a material of a thermosetting resin or a thermoplastic resin impregnated with a core material such as glass fiber, glass cloth, glass fabric, etc. and an inorganic filler (for example, a prepreg, etc.) can be used. In this case, excellent rigidity can be maintained, and the frame 110 can be used as a supporting member.

[0071] The wiring layer 112 may perform the function of redistributing the connection pads 120P of the semiconductor chip 120. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof may be used as materials for forming the wiring layer. The wiring layer 112 may perform various functions according to the desired design of the layer. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. It may also include a via pad, a connection terminal pad, etc. As a non-limiting example, all wiring layers 112 may include a ground pattern. In this case, since the ground pattern can be minimized and can be formed in the redistribution layer 142 of the connection structure 140, the wiring design freedom can be improved.

[0072] As needed, a surface treatment layer (not shown) may be further formed on the wiring layer 112 exposed through the opening 151 in the second passivation layer 150-2 formed on the wiring layer 112. The surface treatment layer (not shown) is not particularly limited as long as it is known in the art, for example, the surface treatment layer may be formed by an electroplating gold process, an electroless gold plating process, an OSP or electroless tin plating process, an electroless silver plating process, an electroless nickel plating / displacement gold plating process, a DIG plating process, a HASL process, etc. The thickness of the wiring layer 112 of the frame 110 may be thicker than the thickness of the redistribution layer 142 of the connection structure 140. This is because the thickness of the frame 110 may be equal to that of the semiconductor chip 120, while the connection structure 140 needs to be thin, and their processes may also be different from each other.

[0073] The connecting via 113 can electrically connect the wiring layer 112 to the first column 114. Thus, an electrical path in the frame 110 can be formed. The connecting via 113 can also be formed using a conductive material. The connecting via 113 can be completely filled with a conductive material, or the conductive material can be formed along the wall surface of the passage hole. In addition, all known shapes can be applied, such as not only a conical shape but also a cylindrical shape. When forming a hole for the connecting via 113, the upper surface of the first column 114 can be used as a stopper. In terms of process, a connecting via 113 having a conical shape (for example, the width of the upper surface is wider than the width of the lower surface) may be advantageous. In this case, the connecting via 113 can be integrated with a portion of the wiring layer 112.

[0074] The first pillar 114 may electrically connect the wiring layer 112 formed on the second surface of the frame 110 to the redistribution layer 142 formed on the first surface of the frame 110 through the connection via 113. Thus, an electrical path in the frame 110 may be formed. A conductive material may also be used as a material of the first pillar 114. The first pillar 114 may be completely filled with a conductive material, and may have various shapes such as a cylindrical shape, a polygonal pillar shape, and the like.

[0075] The second column 115 may be physically spaced apart from the first column 114 in an area that does not overlap with the first column 114. Therefore, the distribution of the conductive material within the frame 110 may be increased. The second column 115 may also use a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof as a material for forming the second column 115. The first column 114 may be arranged around the semiconductor chip 120 at a specific interval, and the second column 115 may be arranged not to overlap with the first column 114, specifically, the second column 115 may be centrally arranged in an area where the first column 114 is distributed in a relatively small number. Therefore, the second column 115 may be in the form of a column having various types of flat cross-sections.

[0076] The first pillars 114 and the second pillars 115 may include conductive materials to provide a path for dissipating heat generated in the semiconductor chip 120. Specifically, the second pillars 115 may be centrally disposed in a region where the first pillars 114 are relatively few in number, which helps improve the heat dissipation performance of the package.

[0077] The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. The semiconductor chip 120 may be: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM)), a flash memory, etc.; an application processor chip, such as a central processing unit (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, etc.; a logic chip, such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., but is not necessarily limited thereto.

[0078] The semiconductor chip 120 can be formed based on an effective wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. can be used as the matrix material constituting the main body. Various circuits can be formed in the main body. The connection pad 120P can be used to electrically connect the semiconductor chip 120 to other components. Conductive materials such as aluminum (Al) can be used as the formation material of the connection pad 120P without any special restrictions. The surface on which the connection pad 120P is arranged can become an effective surface, and the surface opposite to it can become an invalid surface. As required, a passivation film covering at least a portion of the connection pad 120P can be formed on the main body. The passivation film can be an oxide film or a nitride film, or can be a double layer of an oxide film and a nitride film. An insulating film (not shown) etc. can be further arranged at other required positions.

[0079] The semiconductor chip 120 may include a bump 120B disposed on and connected to the connection pad 120P. The bump 120B may be made of a metal such as copper (Cu), or may be a solder material. As can be seen from the process to be described later, the semiconductor package 100A according to the example may be processed using a grinding process. In this case, the surface of the first column 114 of the frame 110 connected to the redistribution layer 142 may be located at the same height as the surface of the bump 120B of the semiconductor chip 120 connected to the redistribution layer 142. The same height may be a concept including a slight deviation due to process errors. The height of the via 143 for connecting the bump 120B to the redistribution layer 142 and the height of the via 143 for connecting the first column 114 to the redistribution layer 142 may be the same as each other. The same height may also be a concept including a slight deviation due to process errors. When the surface formed with the connection structure 140 is flat as described above, the insulating layer 141 may be formed to be flat. Therefore, the redistribution layer 142 and the via 143 may be formed more finely. In addition, although the semiconductor package 100A according to the example shows a structure including one semiconductor chip 120 , a plurality of semiconductor chips 120 may be used as necessary.

[0080] The encapsulant 130 may be filled in the cavity 110H to protect the semiconductor chip 120, etc. The shape of the encapsulant 130 is not particularly limited, and may be a shape that covers at least a portion of the semiconductor chip 120. For example, the encapsulant 130 may cover the effective surface of the semiconductor chip 120, and may fill the space between the wall surface of the cavity 110H and the side surface of the semiconductor chip 120. The cavity 110H may be filled with the encapsulant 130 to act as an adhesive according to a specific material, and may simultaneously reduce a buckling phenomenon.

[0081] The material of the encapsulant 130 is not particularly limited. For example, an insulating material can be used. In this case, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a mixture of a thermosetting resin or a thermoplastic resin and an inorganic filler, or a resin impregnated with a core material such as glass fiber, glass cloth or glass fabric (such as a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used as an insulating material. If necessary, a photosensitive material (for example, a photosensitive encapsulant (PIE)) can be used.

[0082] In the semiconductor package 100A according to the example, the encapsulant 130 may not be formed on the first surface of the frame 110 except the inner space of the cavity 110H. In the grinding process to be described later, the encapsulant 130 covering the first surface of the frame 110 (e.g., the lower surface of the first column 114 and the second column 115) may be removed to leave only the encapsulant 130 filling the cavity 110H. Therefore, the step difference between the encapsulant 130 formed on the semiconductor chip 120 and the encapsulant 130 formed on the frame 110 may be removed to achieve a flat surface. For example, the boundary surface between the connection structure 140 and the bump 120B of the semiconductor chip may be located at the same height as the boundary surface between the connection structure 140 and the encapsulant 130, and the boundary surface between the connection structure 140 and the first column 114 may be located at the same height as the boundary surface between the connection structure 140 and the bump 120B of the semiconductor chip. In this case, the same height may be a concept including a slight deviation due to a process error.

[0083] The connection structure 140 may include a redistribution layer 142 disposed on one side of the frame 110 and electrically connected to the semiconductor chip 120. For example, the connection structure 140 may redistribute the connection pads 120P of the semiconductor chip 120, and may electrically connect the wiring layer 112 of the frame 110 to the connection pads 120P of the semiconductor chip 120. Tens to millions of connection pads of the semiconductor chip having various functions may be redistributed through the connection structure 140, and may be physically connected and / or electrically connected to the outside through the electrical connection metal 170 according to their functions. The connection structure 140 may include an insulating layer 141 disposed on the effective surface of the semiconductor chip 120 and the frame 110, a redistribution layer 142 disposed on the insulating layer 141, and a via 143 penetrating the insulating layer 141 and connecting any one of the connection pads 120P and the first pillar 114 to the redistribution layer 142 of each layer. The insulating layer, the redistribution layer, and the via of the connection structure 140 may be designed to have fewer or more layers than the number of layers shown in the drawings.

[0084] An insulating material can be used as the material of the insulating layer 141. In this case, in addition to the above-mentioned insulating materials, a photosensitive insulating material such as PID resin can be used as the insulating material. For example, the plurality of insulating layers 141 can be photosensitive insulating layers, respectively. When the insulating layer 141 has photosensitivity, the insulating layer 141 can be made thinner and the fine pitch of the via 143 can be more easily achieved. The insulating layer 141 can be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 has multiple layers, these materials can be the same as each other and can be different from each other as needed. When the insulating layer 141 is in the form of multiple layers, since they are unified according to the process, the boundaries among them may not be clear. In addition, more insulating layers than the number of insulating layers shown in the drawings can be formed.

[0085] The redistribution layer 142 can substantially redistribute the connection pads 120P, and a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof can be used as a forming material of the redistribution layer 142. The redistribution layer 142 can perform various functions according to the design of the desired layer. For example, a ground (GND) pattern (not shown) may be included, and a power (PWR) pattern, a signal (S) pattern, etc. may also be included. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. In addition, the redistribution layer 142 may include a via pad pattern. Although not shown in the drawings, the redistribution layer 142 may be formed to have a redistribution layer 142 with fewer or more than the number of redistribution layers 142 shown in the drawings.

[0086] The via 143 can electrically connect the redistribution layer 142, the connection pad 120P, the wiring layer 112, etc. formed on different layers. Therefore, an electrical path in the semiconductor package 100A can be formed. The via 143 can use a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof as its forming material. The via 143 can be completely filled with a conductive material, or the conductive material can be formed along the wall surface of the via hole. In addition, all shapes known in the art can be applied, such as not only a conical shape but also a cylindrical shape.

[0087] The first passivation layer 150-1 can protect the connection structure 140 from external physical damage or chemical damage, etc. The first passivation layer 150-1 may have an opening that exposes at least a portion of the redistribution layer 142 of the connection structure 140. These openings can be formed in the first passivation layer 150-1 in the range of tens to millions. The material of the first passivation layer 150-1 is not particularly limited. For example, an insulating material can be used. In this case, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a mixture of a thermosetting resin or a thermoplastic resin and an inorganic filler, or a resin impregnated with a core material such as glass fiber, glass cloth or glass fabric (such as a semi-cured sheet, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used as an insulating material. Optionally, a solder resist can be used.

[0088] The second passivation layer 150-2 can protect the frame 110 (specifically, the wiring layer 112) from external physical damage or chemical damage, etc. The second passivation layer 150-2 may have an opening 151 that exposes at least a portion of the wiring layer 112 of the frame 110. The opening 151 can be formed in the second passivation layer 150-2 in the range of tens to millions. The material of the second passivation layer 150-2 is not particularly limited. For example, an insulating material can be used. In this case, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a mixture of a thermosetting resin or a thermoplastic resin and an inorganic filler, or a resin impregnated with a core material such as glass fiber, glass cloth or glass fabric (such as a semi-cured sheet, ABF (AjinomotoBuild-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used as an insulating material. Optionally, a solder resist can be used.

[0089] The under bump metal 160 can improve the connection reliability of the electrical connection metal 170, thereby improving the board-level reliability of the package. The under bump metal 160 can be connected to the redistribution layer 142 of the connection structure 140 exposed through the opening of the first passivation layer 150-1. The under bump metal 160 can be formed in the opening of the first passivation layer 150-1 using a known conductive material (e.g., metal) by a known metallization method, but is not limited thereto.

[0090] The electrical connection metal 170 can physically connect and / or electrically connect the semiconductor package 100A to the outside. For example, the semiconductor package 100A can be mounted on the mainboard of the electronic device through the electrical connection metal 170. The electrical connection metal 170 can be formed using a solder such as a low melting point metal (for example, an alloy containing tin (Sn), more specifically, a tin (Sn)-aluminum (Al)-copper (Cu) alloy, etc.), but this may only be an example and is not particularly limited to this. The electrical connection metal 170 can be a pad, a solder ball, a pin, etc. The electrical connection metal 170 can be formed using multiple layers or a single layer. In the case of multiple layers, copper pillars and solder may be included. In the case of a single layer, tin-silver solder or copper may be included, but this may only be an example and is not limited to this.

[0091] The number, spacing, arrangement type, etc. of the electrical connection metal 170 are not particularly limited, and those skilled in the art can make sufficient modifications according to the design specifications. For example, the number of the electrical connection metal 170 can be from tens to thousands, and can have a greater or lesser number. When the electrical connection metal 170 is a solder ball, the electrical connection metal 170 can cover the side of the under-bump metal 160 formed by extending along one side of the first passivation layer 150-1. In this case, the reliability can be further improved.

[0092] At least one of the electrical connection metals 170 may be disposed in a fan-out region of the semiconductor chip 120. The fan-out region refers to a region other than the region where the semiconductor chip 120 is disposed. The fan-out type package may be more reliable than the fan-in type package, may have many I / O terminals, and may facilitate 3D interconnection. In addition, a package thinner than a ball grid array (BGA) package, a land grid array (LGA) package, etc. may be manufactured, and may have excellent price competitiveness.

[0093] Fig.11 and Fig.12 is a schematic cross-sectional view showing a semiconductor package according to other examples.

[0094] Reference Fig.11 According to another example, the semiconductor package 100B may further include an attachment member 125 disposed between the second surface of the semiconductor chip 120 and the metal plate 116. The attachment member 125 may be an attachment member known in the art such as a die attach film (DAF).

[0095] Reference Fig.12According to another example, the semiconductor package 100C may further include a buildup structure 180 including a buildup wiring layer 182 formed on the wiring layer 112 of the frame 110 and a buildup connection via 183 electrically connecting the buildup wiring layer 182 to the wiring layer 112 of the frame 110. A second passivation layer 150-2 may be provided on the buildup structure 180 and having a plurality of openings 151 exposing at least a portion of the buildup wiring layer 182. By further forming the buildup wiring layer 182 on the ineffective surface of the semiconductor chip 120, the degree of freedom in designing the wiring layer 112 of the frame 110 may be increased. The electrical path of the external device through the back side of the semiconductor chip 120 may be variously designed.

[0096] Other configurations may be substantially the same as those described in the above-mentioned semiconductor package 100A and the like, and a detailed description thereof will be omitted.

[0097] Figures 13 to 18 It shows that according to Fig.12 The schematic diagram of the manufacturing process of the semiconductor package is shown. Through the description of the manufacturing process, the structural features of the semiconductor package with the above structure will be more clearly understood.

[0098] Reference Fig.13 , a patterned cavity metal 110HM, a first column 114, and a second column 115 may be formed on one or both surfaces of a first carrier film C1 such as a copper clad laminate (CCL) using a dry film or the like. In this case, the first column 114 and the second column 115 may be formed together in the height direction of the cavity metal 110HM, so that the cavity metal 110HM, the first column 114, and the second column 115 may be formed at the same height. In addition, the cavity metal 110HM may be in the form of a semiconductor chip, and the first column 114 may be cylindrical. The second column 115 may not have a fixed shape, may be separated from the cavity metal 110HM and the first column 114, and may be mainly distributed in an area where the first column 114 is not formed, but is not limited thereto. The lower surface of the first column 114 and the lower surface of the second column 115 may be located at the same height as the lower surface of the frame to be formed later. In this case, the same height may be a concept including a slight deviation due to a process error.

[0099] Next, a metal plate 116 may be formed on the upper surface of the cavity metal 110HM. The metal plate 116 may be formed to have the same width as that of the cavity metal 110HM, and the lower surface of the metal plate 116 may be located at the same height as the upper surfaces of the first pillar 114 and the second pillar 115. Since the insulating layer 111 forming the frame 110 is formed to cover the cavity metal 110HM, the first pillar 114, and the second pillar 115, the upper surface of the metal plate 116 may be spaced apart from the second surface of the frame 110 by a predetermined distance. In this case, the same height may be a concept including a slight deviation due to a process error.

[0100] A metal film (not shown) may be formed on one surface or both surfaces of the first carrier film C1. The bonding surface between the metal films may be surface treated to facilitate separation in a subsequent separation operation. Optionally, a release layer may be provided between the metal films to facilitate separation in a subsequent operation. The first carrier film C1 may be a known insulating substrate, and any material may be used. The metal film may be a copper foil, but is not limited thereto, and may be a thin film made of other conductive materials.

[0101] Reference Fig.14 , an insulating layer 111 filling the space between the cavity metal 110HM, the first pillar 114 and the second pillar 115 and covering the upper surfaces of the cavity metal 110HM, the first pillar 114 and the second pillar 115, a wiring layer 112 formed on the insulating layer 111, and a connecting via 113 penetrating the insulating layer 111 to electrically connect the wiring layer 112 to any one of the metal plate 116 and the first pillar 114. The insulating layer 111 can be formed by the following methods: a method of laminating and curing a precursor by a known lamination method, or a method of coating and curing a precursor material by a known coating method. The wiring layer 112 can be formed using a known plating process, and the connecting via 113 can be formed using mechanical drilling and / or laser drilling. Therefore, the connecting via 113 can have a shape in which the inner wall is tapered so that the diameter of the surface in contact with the first pillar 114 or the metal plate 116 is narrow. A boundary surface between the first pillar 114 and the connection via 113 may be located at a lower height than a boundary surface between the metal plate 116 and the connection via 113 .

[0102] Next, a buildup insulating layer 181, a buildup wiring layer 182, and a buildup connecting via 183 may be formed on the frame 110. The buildup insulating layer 181 may be formed by laminating and curing ABF, etc. Next, a second passivation layer 150-2 covering the buildup structure 180 may be formed.

[0103] Reference Fig.15, the first carrier film C1 may be removed, and the surface provided with the second passivation layer 150-2 may be attached to the second carrier film C2. Next, the dry film M may be masked on the surface of the cavity metal 110HM, the surface of the first pillar 114, and the surface of the second pillar 115, and only the cavity metal 110HM may be exposed through an etching operation. The inner wall of the cavity 110H formed by removing the cavity metal 110HM may be formed to be parallel to the side surface of the first pillar 114 and the side surface of the second pillar 115. This means that the side surfaces of each of the first pillar 114, the second pillar 115, and the cavity metal 110HM formed in the same direction are parallel to each other. In this case, the expression of "parallel" refers to a concept including a slight process error.

[0104] Reference Fig.16 , after removing the dry film M, the semiconductor chip 120 may be placed in the cavity 110H so that the ineffective surface of the semiconductor chip 120 may be attached to the metal plate 116. In this attachment operation, an attachment member 125 such as a die attach film (DAF) known in the art may be used. The semiconductor chip 120 may be attached with a connection pad 120P and a bump 120B such as a copper pillar formed on the connection pad 120P. Then, an encapsulant 130 may be used to encapsulate at least a portion of the semiconductor chip 120 and the frame 110. The encapsulant 130 may be formed by laminating and curing ABF or the like.

[0105] Reference Fig.17 , and then the encapsulant 130 may be ground so that the surface of the bump 120B may be exposed. The surface of the encapsulant 130 may be flattened by the grinding operation, so that the surface of the bump 120B and the surface of the first column 114 and the surface of the second column 115 may be exposed. The encapsulant 130 covering the upper surface of the frame 110 may be formed so that the ground surface of the frame 110, the ground surface of the encapsulant 130 covering the semiconductor chip 120, and the ground surface of the bump 120B of the semiconductor chip may be coplanar with each other. Therefore, the thickness of the package may be reduced, and warpage may be minimized. Similarly, the expression of "coplanar" refers to the concept of involving slight deviations caused by process errors.

[0106] Next, a connection structure 140 may be formed on the first surface of the frame 110 planarized by the grinding operation. The connection structure 140 may include an insulating layer 141, and a redistribution layer 142 and a via 143 may be formed on the insulating layer 141 using a plating operation and a photolithography operation. As needed, a first passivation layer 150-1 may be formed on the connection structure 140. The first passivation layer 150-1 may be formed by a method of laminating and curing a precursor of the first passivation layer 150-1, by a method of coating and curing a forming material of the first passivation layer 150-1, and the like. An opening (not shown) may be formed in the first passivation layer 150-1 to expose at least a portion of the redistribution layer 142 of the connection structure 140, and an under bump metal 160 may be formed in the opening of the first passivation layer 150-1 using a known metallization method.

[0107] Reference Fig.18 , then the electrical connection metal 170 may be formed on the under bump metal 160. The method of forming the electrical connection metal 170 is not particularly limited, and the electrical connection metal 170 may be formed by a method known in the art according to its structure and form. The electrical connection metal 170 may be fixed by a reflow operation, and a portion of the electrical connection metal 170 may have a configuration that covers the side surface of the under bump metal 160 protruding toward the upper portion of the first passivation layer 150-1 to strengthen the fixing force. As needed, an opening 151 may be formed in the second passivation layer 150-2 from which the second carrier film C2 is removed to expose a portion of the buildup wiring layer 182.

[0108] In the present disclosure, for convenience, words such as "lower", "lower part", "lower surface", etc. are used to indicate a direction toward a mounting surface of a fan-out type semiconductor package relative to a cross section of a drawing, and words such as "upper", "upper part", "upper surface", etc. are used to indicate a direction opposite thereto. It should be understood that the definition refers to a direction for convenience of interpretation, and the scope of the claims is not limited to the description of such a direction.

[0109] The term "connecting" or "connection" in the present disclosure may be not only a direct connection but also a concept including an indirect connection through an adhesive layer or the like. In addition, the term "electrically connected" or "electrically connected" means a concept including both physical connection and physical disconnection. In addition, expressions such as "first", "second", etc. are used to distinguish one component from other components and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the spirit of the invention.

[0110] The expressions "exemplary embodiments" used in this disclosure do not all refer to the same embodiment, but may be provided to emphasize and explain different unique features. However, the above exemplary embodiments do not exclude being implemented in combination with features of other exemplary embodiments. For example, although the description in a specific exemplary embodiment is not described in other exemplary embodiments, it may be understood as an explanation related to other exemplary embodiments unless otherwise described by other exemplary embodiments or contradictory to other exemplary embodiments.

[0111] The terms used in the present disclosure are only used to illustrate example embodiments and are not intended to limit the present disclosure.At this time, unless the context clearly indicates otherwise, a singular expression also includes a plural expression.

[0112] As one of various effects of the present disclosure, a semiconductor package having improved heat dissipation performance and having a relatively high degree of freedom in design can be provided.

[0113] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a frame comprising an insulating layer, a first column and a second column, a wiring layer, and a metal plate, wherein the insulating layer has a cavity in a lower surface of the insulating layer, the first column and the second column are embedded in the insulating layer and spaced apart from the cavity, the wiring layer is disposed on an upper surface of the insulating layer, and the metal plate is disposed on an upper side of the cavity; a semiconductor chip having a first surface provided with connection pads and a second surface opposite to the first surface and including bumps provided on the connection pads, the semiconductor chip being provided in the cavity and the second surface facing the metal plate; an encapsulant covering at least a portion of the semiconductor chip; as well as a connection structure disposed on the frame and the first surface of the semiconductor chip and comprising one or more redistribution layers electrically connected to the bumps of the semiconductor chip, wherein the first pillar is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and The second pillar is spaced apart from the first pillar and is electrically insulated from the first pillar.

2. The semiconductor package according to claim 1, wherein: The first pillar and the second pillar extend in a height direction of the cavity.

3. The semiconductor package according to claim 1, wherein: An upper surface of the metal plate is spaced apart from an upper surface of the insulating layer.

4. The semiconductor package according to claim 1, wherein: An upper surface of the first column and an upper surface of the second column are located at the same height as a lower surface of the metal plate of the frame.

5. The semiconductor package according to claim 1, wherein: A lower surface of the first column and a lower surface of the second column are located at the same height as a lower surface of the insulating layer of the frame.

6. The semiconductor package according to claim 1, wherein: An inner wall of the cavity is parallel to a side surface of the first column and a side surface of the second column.

7. The semiconductor package according to claim 1, wherein: The frame further includes a connection via penetrating at least a portion of the insulating layer to connect the wiring layer to the first pillar and the metal plate.

8. The semiconductor package according to claim 7, wherein: The connecting via has a tapered inner wall.

9. The semiconductor package according to claim 7, wherein: A boundary surface between the first pillar and the connection via is located at a lower height than a boundary surface between the metal plate and the connection via.

10. The semiconductor package according to claim 1, wherein A boundary surface between the connection structure and the bump of the semiconductor chip is located at the same height as a boundary surface between the connection structure and the encapsulant.

11. The semiconductor package according to claim 1, wherein: A boundary surface between the connection structure and the first pillar is located at the same height as a boundary surface between the connection structure and the bump of the semiconductor chip.

12. The semiconductor package according to claim 1, further comprising: a first passivation layer disposed on the connection structure and having a plurality of first openings exposing at least a portion of the redistribution layer; as well as The second passivation layer is disposed on the upper surface of the frame and has a plurality of second openings exposing at least a portion of the wiring layer.

13. The semiconductor package according to claim 12, further comprising: a plurality of under bump metallurgies, respectively disposed in the plurality of first openings of the first passivation layer and electrically connected to the exposed redistribution layer; and A plurality of electrical connection metals are respectively disposed on the plurality of under bump metals and electrically connected to the exposed redistribution layer through the under bump metals. 14 . The semiconductor package according to claim 1 , further comprising an adhesive member disposed between the second surface of the semiconductor chip and the metal plate. 15 . The semiconductor package according to claim 1 , further comprising a build-up structure including a build-up wiring layer formed on the wiring layer of the frame and a build-up connection via electrically connecting the build-up wiring layer and the wiring layer of the frame. 16 . The semiconductor package of claim 15 , further comprising a second passivation layer disposed on the build-up structure and having a plurality of third openings exposing at least a portion of the build-up wiring layer.

17. The semiconductor package according to claim 1, wherein: The second pillar surrounds the first pillar and is spaced apart from the first pillar by the insulating layer.

18. The semiconductor package according to claim 1, wherein In a plan view, the second pillar has a different shape from the first pillar.

19. A semiconductor package, comprising: connection structures, including redistribution layers; an insulating layer, disposed on the connection structure and having a cavity; a plurality of first posts and one or more second posts embedded in the insulating layer and extending from the connection structure; a semiconductor chip having a first surface provided with connection pads and a second surface opposite to the first surface, and including bumps connecting the connection pads and the connection structure to each other; an encapsulant filling the cavity and separating the side surface of the semiconductor chip and the insulating layer from each other; a metal plate disposed between the insulating layer and the second surface of the semiconductor chip; as well as a wiring layer disposed on the insulating layer, wherein the plurality of first pillars are electrically connected to the wiring layer, the redistribution layer and the connection pads, wherein, in a plan view, the one or more second pillars are arranged to be spaced apart from the plurality of first pillars and substantially surround the periphery of the plurality of first pillars, and Wherein, in the plan view, an area occupied by each of the one or more second pillars is greater than an area occupied by each of the plurality of first pillars.

20. The semiconductor package according to claim 19, wherein The one or more second pillars are electrically insulated from the plurality of first pillars, the wiring layer, the redistribution layer, and the connection pads.

21. The semiconductor package according to claim 19, wherein The one or more second pillars are spaced apart from the plurality of first pillars by the insulating layer.

22. The semiconductor package according to claim 19, wherein: The connection structure includes a layer of vias connecting the redistribution layer to the first pillar and the bump, respectively.

23. The semiconductor package according to claim 19, wherein In the plan view, the one or more second pillars have a different shape from the plurality of first pillars.

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