Display panel and display device

Abstract

The present application provides a display panel and a display device, wherein the display panel includes a base substrate and a thin film transistor array layer arranged on the base substrate, wherein a plurality of first thin film transistors, second thin film transistors and storage capacitors are arranged at intervals in the thin film transistor array layer, wherein the first thin film transistor includes a stacked polysilicon semiconductor layer and a first gate electrode, and the second thin film transistor includes a stacked oxide semiconductor layer and a second gate electrode, wherein the first gate electrode and a first electrode plate constitute a storage capacitor, and the first electrode plate and the second gate electrode of the second thin film transistor are arranged in the same layer, and a gate insulating layer used for separating the first electrode plate from the first gate electrode and the second gate electrode in layers can be omitted, thereby reducing the number of film layers in the display panel and the thickness of the film layer stacking structure, thereby reducing the complexity of the display panel process and improving the bending ability of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of wearable device technology and the lack of significant breakthroughs in battery technology, people have higher and higher requirements for the power consumption of display devices. Currently, low temperature polysilicon (LTPS) technology used to drive thin film transistors and switch thin film transistors is still the mainstream technology trend due to its low power consumption. However, due to the large carrier mobility of LTPS, there is a problem of high leakage current, so low temperature polycrystalline oxide (LTPO) technology came into being. It combines the advantages of LTPS and oxide, which can improve the response speed of display devices while reducing the power consumption of display devices.

[0003] like Figure 1 As shown, Figure 1 This is a schematic diagram of the film layer structure of a display panel using low-temperature polycrystalline oxide technology in the prior art. The semiconductor layers of the driving thin film transistor 11 and the switching thin film transistor 12 are respectively a polycrystalline silicon semiconductor layer and an oxide semiconductor layer. The storage capacitor 13 of the display panel is composed of a first gate electrode 111 and a second gate electrode 112 respectively arranged on a first gate insulating layer 14 and a second gate electrode 112 arranged on a second gate insulating layer 15. The third gate electrode 121 of the switching thin film transistor 12 is separated from the metal layer where the first gate electrode 111 and the second gate electrode 112 are located by the third gate insulating layer 16. As a result, the number of film layers in the display panel is large and the thickness of the film layer stack is large, which makes the manufacturing process of the display panel more complicated and reduces the bending ability of the display panel.

[0004] In summary, the existing display panels using low temperature polycrystalline oxide technology have the problem of a large number of film layers and a large film layer stacking structure, which leads to a complex display panel manufacturing process and reduced display panel bending ability. Therefore, it is necessary to provide a display panel and a display device to improve this defect. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a manufacturing method thereof, and a display device, which are used to solve the problem that the existing display panels using low-temperature polycrystalline oxide technology have a large number of film layers and a large thickness of the film layer stacking structure, which leads to a complicated display panel manufacturing process and reduced bending ability of the display panel.

[0006] An embodiment of the present application provides a display panel, including:

[0007] substrate substrate;

[0008] A thin film transistor array layer, disposed on the base substrate, wherein a plurality of first thin film transistors, second thin film transistors and storage capacitors arranged at intervals are disposed in the thin film transistor array layer;

[0009] Among them, the first thin film transistor includes a stacked polysilicon semiconductor layer and a first gate, the second thin film transistor includes a stacked oxide semiconductor layer and a second gate, the storage capacitor includes a first electrode plate arranged on a side of the first gate away from the substrate, the first gate and the first electrode plate constitute the storage capacitor, and the first electrode plate and the second gate are arranged in the same layer.

[0010] According to an embodiment of the present application, the distance between the surface of the oxide semiconductor layer close to the substrate and the substrate is greater than the distance between the surface of the polysilicon semiconductor layer close to the substrate and the substrate.

[0011] According to one embodiment of the present application, the thin film transistor array layer includes a first gate insulating layer and a first interlayer insulating layer which are sequentially stacked on the polycrystalline silicon semiconductor layer, the first gate is arranged between the first gate insulating layer and the first interlayer insulating layer, and the oxide semiconductor layer is arranged on a side of the first interlayer insulating layer away from the first gate insulating layer.

[0012] According to an embodiment of the present application, the first interlayer insulating layer is a stacked structure formed of silicon nitride and silicon oxide materials, and the atomic percentage of silicon-hydrogen bonds in the first interlayer insulating layer is between 20% and 30%.

[0013] According to one embodiment of the present application, the thin film transistor array layer also includes a second gate insulating layer and a second interlayer insulating layer stacked on a side of the first interlayer insulating layer away from the first gate insulating layer, and the first electrode and the second gate are both arranged between the second gate insulating layer and the second interlayer insulating layer.

[0014] According to an embodiment of the present application, the first electrode plate and the second gate are made of the same layer of metal.

[0015] According to an embodiment of the present application, the storage capacitor includes a first capacitor and a second capacitor connected in parallel, a second plate is provided between the first gate and the first plate, and the second plate constitutes the first capacitor and the second capacitor with the first gate and the first plate respectively.

[0016] According to an embodiment of the present application, an orthographic projection area of ​​the second electrode plate on the base substrate overlaps with an orthographic projection area of ​​the first gate or the first electrode plate on the base substrate.

[0017] According to an embodiment of the present application, the second electrode plate is disposed on the same layer as the oxide semiconductor layer.

[0018] According to an embodiment of the present application, the second electrode plate and the oxide semiconductor layer are made of the same oxide material.

[0019] According to an embodiment of the present application, the first thin film transistor includes a first source and a first drain, and the second thin film transistor includes a second source and a second drain, the first source and the first drain are respectively connected to the polycrystalline silicon semiconductor layer through a first via hole penetrating the second interlayer insulating layer, the second gate insulating layer, the first interlayer insulating layer and the first gate insulating layer, and the second source and the second drain are respectively connected to the oxide semiconductor layer through a second via hole penetrating the second interlayer insulating layer and the second gate insulating layer.

[0020] An embodiment of the present application provides a display device, including a device body and a display panel as described above and arranged on the device body.

[0021] The present application also provides a method for manufacturing a display panel, including:

[0022] Providing a substrate substrate, and forming a polycrystalline silicon semiconductor layer on the substrate substrate;

[0023] forming a first gate insulating layer covering the polycrystalline silicon semiconductor layer on the substrate;

[0024] forming a first gate on a side of the first gate insulating layer away from the base substrate;

[0025] forming a first interlayer insulating layer covering the first gate on a side of the first gate insulating layer away from the base substrate;

[0026] forming an oxide semiconductor layer on a side of the first interlayer insulating layer away from the first gate insulating layer;

[0027] forming a second gate insulating layer covering the oxide semiconductor layer on a side of the first interlayer insulating layer away from the gate insulating layer;

[0028] Depositing a metal material on a side of the second gate insulating layer away from the base substrate, and forming a plurality of first plates and second gates arranged at intervals by a patterning process, wherein the first plates and the first gates constitute a storage capacitor; and

[0029] A first source, a first drain, a second source and a second drain are formed on a side of the second gate away from the second gate insulating layer, the first source and the first drain, the first gate and the polysilicon semiconductor layer constitute a first thin film transistor, and the second source and the second drain, the second gate and the oxide semiconductor layer constitute a second thin film transistor.

[0030] According to an embodiment of the present application, the step of forming the oxide semiconductor layer includes:

[0031] Depositing a layer of oxide semiconductor material on a side of the first interlayer insulating layer away from the first gate insulating layer; and

[0032] A plurality of the oxide semiconductor layers and the second electrode plates arranged at intervals are formed by a patterning process, and the second electrode plates respectively form the first capacitor and the second capacitor of the storage capacitor together with the first gate and the first electrode plate.

[0033] Beneficial effects of the embodiments of the present application: The present application utilizes the first gate electrode and the first electrode plate of the first thin film transistor to form a storage capacitor, and the first electrode plate and the second gate electrode of the second thin film transistor are arranged on the same layer. The gate insulating layer used to separate the first electrode plate from the first gate electrode and the second gate electrode can be omitted, thereby reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby reducing the complexity of the display panel process flow and improving the bending ability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a film layer structure of a display panel in the prior art;

[0036] Figure 2 A schematic diagram of the film layer structure of the first display panel provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the film layer structure of a second display panel provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0039] FIG. 5A to FIG. 5IA schematic diagram of a film layer structure of a display panel corresponding to the first method for manufacturing a display panel provided in an embodiment of the present application; and

[0040] FIG. 6A to FIG. 6B A schematic diagram of the film layer structure of a display panel corresponding to the second method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following descriptions of the embodiments are made with reference to the attached drawings to illustrate specific embodiments that the present application may be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the drawings, units with similar structures are represented by the same reference numerals.

[0042] The present application is further described below in conjunction with the accompanying drawings and specific embodiments.

[0043] The present application embodiment provides a display panel, Figure 2 For detailed explanation, Figure 2 The display panel provided in the embodiment of the present application comprises a base substrate 20, a thin film transistor array layer 21 disposed on the base substrate 20, and a display device layer disposed on a side of the thin film transistor array layer 21 away from the base substrate 20.

[0044] In the embodiment of the present application, the base substrate 20 includes a first substrate, a barrier layer, a second substrate, a buffer layer and a third substrate (not shown in the figure) stacked in sequence, the first substrate and the second substrate are both made of polyimide materials, and the third substrate is a stacked structure formed of silicon nitride, silicon oxide and amorphous silicon materials. Of course, the material and structure of the base substrate 20 are not limited to the materials and structures provided in the embodiment of the present application. In some other embodiments, the base substrate 20 can also be other structures and materials, which are not limited here.

[0045] The display panel provided in the embodiment of the present application can be an organic light emitting diode display panel, and the display device layer includes a flat layer 22 arranged on the side of the thin film transistor array layer 21 away from the base substrate 20, a pixel definition layer 23, a plurality of spacers 24 arranged on the surface of one side of the pixel definition layer 23, and an anode 25, a light emitting layer 26 and a cathode 27 stacked on the side of the flat layer 22 away from the base substrate 20. Its structure and materials are the same as those of the organic light emitting diode display device in the prior art, and are not described in detail here. Of course, the display devices in the display device layer are not limited to the organic light emitting diode devices in the embodiment of the present application. In some other embodiments, the display devices in the display device layer may also include but are not limited to micro light emitting diodes, mini light emitting diodes and other light emitting display devices. The type of display device can be selected according to actual needs and is not limited here.

[0046] like Figure 2 As shown, in the embodiment of the present application, a plurality of first thin film transistors T1, second thin film transistors T2 and storage capacitors C are arranged at intervals in the thin film transistor array layer 21. The first thin film transistors T1 and the second thin film transistors T2, the storage capacitors C and the circuit wiring arranged in the thin film transistor array layer 21 constitute the pixel driving circuit of each sub-pixel unit in the display panel.

[0047] The pixel driving circuit provided in the embodiment of the present application is a 7T1C pixel driving circuit, including 1 driving thin film transistor, 6 switching thin film transistors and 1 storage capacitor C, wherein the first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. Of course, in other embodiments, the pixel driving circuit of the display panel may also be other circuit structures, and the number of its internal driving thin film transistors, switching thin film transistors and capacitors is not limited to the number provided in the embodiment of the present application, and the specific structure can be set according to actual needs, and is not limited here.

[0048] In the embodiment of the present application, the first thin film transistor T1 includes a stacked polycrystalline silicon semiconductor layer 210, a first gate GE1, a first source S1 and a first drain D1 arranged on a side of the first gate GE1 away from the polycrystalline silicon semiconductor layer 210, the second thin film transistor T2 includes a stacked oxide semiconductor layer 217, a second gate GE2, and a second source S2 and a second drain D2 arranged on a side of the second gate GE2 away from the oxide semiconductor layer 217, the storage capacitor C includes a first electrode plate 216 arranged on a side of the first gate GE1 away from the base substrate 20, the orthographic projection areas of the first electrode plate 216 and the first gate GE1 on the base substrate 20 overlap with the orthographic projection area of ​​the channel region of the polycrystalline silicon semiconductor layer 210 on the base substrate 20, the orthographic projection area of ​​the second gate GE2 on the base substrate 20 overlaps with the orthographic projection area of ​​the oxide semiconductor layer 217 on the base substrate 20, the first electrode plate 216 and the first gate GE1 of the first thin film transistor T1 constitute a storage capacitor C, and the first electrode plate 216 and the second gate GE2 are arranged on the same film layer.

[0049] In the embodiment of the present application, the polysilicon semiconductor layer 210 is a low-temperature polysilicon semiconductor layer, and the material of the oxide semiconductor layer 217 is preferably indium gallium zinc oxide (IGZO). Of course, in some other embodiments, the material of the oxide semiconductor layer 217 may also include but is not limited to oxide semiconductor materials such as indium gallium oxide or indium zinc oxide, and the specific material can be selected according to actual needs and is not limited here.

[0050] like Figure 2 As shown, the distance between the surface of the oxide semiconductor layer 217 of the second thin film transistor T2 close to the substrate 20 and the substrate is greater than the distance between the surface of the polysilicon semiconductor layer 210 of the first thin film transistor T1 close to the substrate 20 and the substrate.

[0051] Specifically, refer to Figure 2 The thin film transistor array layer 21 includes a first gate insulating layer 211 and a first interlayer insulating layer 212 which are sequentially stacked on the polycrystalline silicon semiconductor layer 210, the first gate insulating layer 211 covers the polycrystalline silicon semiconductor layer 210, the first gate GE1 is disposed between the first gate insulating layer 211 and the first interlayer insulating layer 212, and the oxide semiconductor layer 217 is disposed on a side of the first interlayer insulating layer 212 away from the first gate insulating layer 211. By disposing the oxide semiconductor layer 217 on a side of the polycrystalline silicon semiconductor layer 210 away from the base substrate 20, it is possible to prevent the high temperature during the preparation of the polycrystalline silicon semiconductor layer 210 from damaging the structure and properties of the oxide semiconductor layer 217.

[0052] In the embodiment of the present application, the material of the first gate insulating layer 211 is silicon oxide, the first interlayer insulating layer 212 is a stacked structure formed by silicon nitride and silicon oxide materials, the silicon nitride film layer is arranged between the silicon oxide film layer and the first gate insulating layer 211, and the atomic percentage of the silicon-hydrogen bond content in the first interlayer insulating layer 212 is 25%. By increasing the hydrogen content in the first interlayer insulating layer 212, the stability of the polysilicon semiconductor layer 210 can be improved, and the silicon oxide film layer in the first interlayer insulating layer 212 can also be used to prevent hydrogen ions in the silicon nitride film layer from diffusing into the oxide semiconductor layer 217, thereby ensuring that the stability of the oxide semiconductor layer 217 is not affected. Of course, the atomic percentage of the silicon-hydrogen bond content in the first interlayer insulating layer 212 is not limited to the setting provided in the embodiment of the present application. In some other embodiments, the atomic percentage of the silicon-hydrogen bond content in the first interlayer insulating layer 212 can also include but not be limited to 20% or 30%, and the value is preferably between 20% and 30%. The specific value can be set according to actual needs and is not limited here.

[0053] Furthermore, the thin film transistor array layer 21 further includes a second gate insulating layer 213 and a second interlayer insulating layer 214 stacked on the first interlayer insulating layer 212 away from the first gate insulating layer 211, and the first electrode 216 and the second gate GE2 are both disposed between the second gate insulating layer 213 and the second interlayer insulating layer 214. Figure 1 The display panel shown in the embodiment of the present application sets the first electrode 216 of the storage capacitor and the second gate GE2 of the second thin film transistor T2 on the same layer, and utilizes the second gate insulating layer 213 under the second gate GE2 to separate the film layer where the second gate GE2 and the first electrode 216 are located from the metal film layer where the first gate GE1 is located, thereby eliminating the gate insulating layer formed by inorganic insulating material that is originally used to separate the metal film layer where the first gate GE1 is located from the metal film layer where the first electrode 216 is located, thereby reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby reducing the complexity of the display panel process flow and improving the bending ability of the display panel.

[0054] Preferably, in the embodiment of the present application, the first electrode plate 216 and the second gate GE2 are made of the same layer of metal, so the first electrode plate 216 and the second gate GE2 can be simultaneously prepared using one mask plate, thereby omitting the mask plate and related process required for preparing the first electrode plate 216 alone, thereby reducing the complexity of the display panel process and the production cost. Of course, in some embodiments, although the first electrode plate 216 and the second gate GE2 are arranged on the same layer, they can be made of different materials and prepared by different processes, which is not limited here.

[0055] Specifically, Figure 2 As shown, the first source S1, the first drain D1, the second source S2 and the second drain D2 are all arranged between the second interlayer insulating layer 214 and the passivation protection layer 215. The first source S1 and the first drain D1 are respectively connected to the first source region and the first drain region of the polysilicon semiconductor 210 through a plurality of first via holes penetrating the second interlayer insulating layer 214, the second gate insulating layer 213, the first interlayer insulating layer 212 and the first gate insulating layer 211, and the anode 25 arranged between the planar layer 22 and the pixel definition layer 23 is connected to the first drain D1 through the via hole. The second source S2 and the second drain D2 are connected to the second source region and the second drain region of the oxide semiconductor layer 217 through a plurality of second via holes penetrating the second interlayer insulating layer 214 and the second gate insulating layer 213.

[0056] Beneficial effects of the embodiments of the present application: The present application utilizes the first gate and the first electrode plate of the first thin film transistor to form a storage capacitor, and the first electrode plate and the second gate of the second thin film transistor are arranged on the same layer. The gate insulating layer used to separate the first gate and the first electrode plate in layers, and the mask plate required for preparing the first electrode plate can be omitted, thereby reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby reducing the complexity of the display panel process and the production cost, and improving the bending ability of the display panel.

[0057] The present application also provides a display panel. Figure 3 For detailed explanation, Figure 3 Schematic diagram of the film layer structure of the display panel provided in the embodiment of the present application. The display panel provided in the embodiment of the present application has substantially the same structure as the display panel provided in the above embodiment, and will not be described in detail here. The difference between the display panel provided in the embodiment of the present application and the display panel provided in the above embodiment is that, in the embodiment of the present application, the storage capacitor C includes a first capacitor and a second capacitor connected in parallel, and a second electrode plate 218 is provided between the first gate GE1 and the first electrode plate 216, and the orthographic projection area of ​​the second electrode plate 218 on the base substrate 20 overlaps with the orthographic projection area of ​​the first electrode plate 216 and the first gate GE1 on the base substrate 20, respectively.

[0058] The first gate GE1 and the second electrode plate 218 form a first capacitor, the first electrode plate 216 and the second electrode plate 218 form a second capacitor, and the first capacitor and the second capacitor are connected in parallel through a signal line arranged in the thin film transistor array layer 21, so as to increase the unit capacitance value of the storage capacitor C, thereby compressing the size of the storage capacitor C while ensuring that the capacitance value of the storage capacitor C remains unchanged, thereby reducing the area occupied by the pixel circuit and improving the resolution of the display panel. Of course, in some other embodiments, the capacitance value of the storage capacitor C can also be increased by the method of this embodiment while the size of the storage capacitor C remains unchanged, thereby reducing the influence of the leakage current on the storage capacitor C when storing the potential signal, thereby improving the stability of the display effect of the display panel under the state of low refresh rate or low power consumption.

[0059] Furthermore, in the embodiment of the present application, the second electrode 218 is arranged in the same layer as the oxide semiconductor layer 217 of the second thin film transistor T2, so that the original number of film layers and the film layer structure of the display panel can be kept unchanged when the second electrode 218 is added, and the bending performance of the display panel is not affected. Of course, the position of the second electrode 218 is not limited to the same layer as the oxide semiconductor stack 217 provided in the embodiment of the present application. In some other embodiments, the second electrode 218 can be arranged in other film layers except the film layer where the oxide semiconductor layer 217 is located between the first gate GE1 and the first electrode 216, which can also achieve the same technical effect as the above embodiment. The specific film layer position can be selected according to the actual situation and is not limited here.

[0060] Preferably, in the embodiment of the present application, the second electrode 218 and the oxide semiconductor layer 217 are made of the same layer of oxide material, so the oxide semiconductor layer 217 and the second electrode 218 can be simultaneously prepared using a mask, thereby omitting the mask and related process required for preparing the second electrode 218 alone, thereby reducing the complexity of the display panel process and the production cost. Of course, in some embodiments, although the second electrode 218 and the second gate GE2 are arranged in the same layer, they can be made of different materials and prepared by different processes, which is not limited here.

[0061] Beneficial effects of the embodiments of the present application: The embodiments of the present application utilize the first gate and the first electrode plate of the first thin film transistor to form a storage capacitor, and at the same time, a second electrode plate is arranged between the first gate and the first electrode plate, and the second electrode plate forms a first capacitor and a second capacitor in parallel with the first gate and the first electrode plate respectively of the storage capacitor, and at the same time, the first electrode plate and the second gate of the second thin film transistor are arranged in the same layer, and the second electrode plate and the oxide semiconductor layer are arranged in the same layer, and the gate insulating layer used to separate the first gate and the first electrode plate in layers and the mask plates used to prepare the first electrode plate and the second electrode plate respectively can be omitted, thereby reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby reducing the complexity of the display panel process and the production cost, and improving the bending ability of the display panel and the display effect of the display panel.

[0062] The present application also provides a display device. Figure 4 For detailed explanation, Figure 4 This is a schematic diagram of the structure of the display device provided in the embodiment of the present application. Figure 4 As shown, the display device 3 includes a device body 31 and a display panel 32. The device body 31 includes a frame assembly and components such as a power supply, a processor, and a camera (not shown in the figure) disposed in the frame assembly. The display panel 32 is disposed on the device body 31. The display panel 31 provided in the embodiment of the present application is any one of the display panels provided in the above embodiments, and the display device 3 provided in the embodiment of the present application can also achieve the same technical effects as the display panels provided in the above embodiments, which will not be repeated here.

[0063] The present application also provides a method for manufacturing a display panel. FIG. 5A to FIG. 5I For detailed explanation, FIG. 5A to FIG. 5I The following is a schematic diagram of a film structure of a display panel corresponding to a method for manufacturing a display panel provided in an embodiment of the present application. The method for manufacturing a display panel provided in an embodiment of the present application includes:

[0064] Step S1: Figure 5A As shown, a substrate 40 is provided, and a polycrystalline silicon semiconductor layer 410 is formed on the substrate 40;

[0065] Step S2: Figure 5B As shown, a first gate insulating layer 411 covering the polysilicon semiconductor layer 410 is formed on the base substrate 40;

[0066] Step S3: Figure 5CAs shown, a metal material is deposited on a side of the first gate insulating layer 411 away from the substrate 40, and a patterned first gate GE1 is formed through a patterning process, and the orthographic projection area of ​​the first gate GE1 on the substrate 40 overlaps with the orthographic projection area of ​​the channel region of the polycrystalline silicon semiconductor layer 410 on the substrate 40;

[0067] Step S4: Figure 5D As shown, a first interlayer insulating layer 412 covering the first gate GE1 is formed on a side of the first gate insulating layer 411 away from the substrate 40;

[0068] Step S5: Figure 5E As shown, an oxide semiconductor layer 417 is formed on a side of the first interlayer insulating layer 412 away from the first gate insulating layer 411;

[0069] Step S6: Fig. 5F As shown, a second gate insulating layer 413 covering the oxide semiconductor layer 417 is formed on a side of the first interlayer insulating layer 412 away from the gate insulating layer;

[0070] Step S7: Figure 5G As shown, a metal material is deposited on a side of the second gate insulating layer 413 away from the base substrate 40, and a plurality of first electrodes 416 and second gates GE2 arranged at intervals are formed by a patterning process, the orthographic projection area of ​​the first electrode plate 416 on the base substrate 20 overlaps the orthographic projection area of ​​the first gate GE1 on the base substrate, and the first electrode plate 416 and the first gate GE1 constitute a storage capacitor C;

[0071] Step S8: Figure 5H As shown, a second interlayer insulating layer 414 covering the second gate GE2 and the first electrode plate 416 is formed on a side of the second gate GE2 away from the second gate insulating layer 413, a plurality of first via holes penetrating the second interlayer insulating layer 414, the second gate insulating layer 413, the first interlayer insulating layer 412 and the first gate insulating layer 411 and a second via hole penetrating the second interlayer insulating layer 414 and the second gate insulating layer 413 are formed by etching, a first source S1, a first drain D1, a second source S2 and a second drain D2 are formed on the second interlayer insulating layer 414, the first source S1 and the first drain D1, the first gate GE1 and the polycrystalline silicon semiconductor layer 410 constitute a first thin film transistor T1, and the second source S2 and the second drain D2, the second gate GE2 and the oxide semiconductor layer 417 constitute a second thin film transistor T2;

[0072] Step S9: Fig.5IAs shown, a passivation protection layer 415 covering the first source S1, the first drain D1, the second source S2 and the second drain D2 is formed on the second interlayer insulating layer 414, and a flat layer 42, an anode 45, a pixel definition layer 43, a light emitting layer 46, a cathode 47, and a plurality of spacers 44 arranged at intervals on the surface of the pixel definition layer 43 are sequentially formed on the side of the passivation protection layer 415 away from the second interlayer insulating layer 414. The manufacturing method in step S9 is the same as the manufacturing method in the prior art, and will not be repeated here.

[0073] In step S4 of the embodiment of the present application, the first interlayer insulating layer 412 formed is a stacked structure of silicon nitride and silicon oxide materials, and the silicon nitride film layer is located between the silicon oxide film layer and the first gate insulating layer 411. The silicon nitride film layer needs to be made in a gas atmosphere of SiH4+NH3+N2. The atomic percentage of silicon-hydrogen bonds in the first interlayer insulating layer 412 is controlled between 20% and 30% by the proportion of SiH4 in the gas atmosphere, thereby improving the stability of the polycrystalline silicon semiconductor layer 410. At the same time, the silicon oxide film layer in the first interlayer insulating layer 412 can also be used to prevent hydrogen ions in the silicon nitride film layer from diffusing into the oxide semiconductor layer 417, thereby ensuring that the stability of the oxide semiconductor layer 417 is not affected.

[0074] In step S7 of the embodiment of the present application, the deposited metal material may be a stacked structure formed by a variety of materials such as Cu, Al, Mo, etc. In other embodiments, the second gate GE2 and the first electrode 416 may also be other conductive materials and structures, which are not limited here. In step S7, the first electrode 416 of the storage capacitor C is formed simultaneously by the patterning process of the second gate GE2, and the mask plate and related process used to form the first electrode 416 can be omitted. At the same time, the gate insulating layer used to separate the metal film layer where the first electrode 416 is located from the metal film layer where the first gate GE1 is located can also be omitted in the structure, thereby not only reducing the complexity of the display panel manufacturing process, but also reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby improving the bending ability of the display panel.

[0075] Beneficial effects of the embodiments of the present application: The manufacturing method of the display panel provided in the embodiments of the present application utilizes the process for preparing the second gate to simultaneously manufacture the first electrode plate of the storage capacitor, thereby omitting the mask plate and related process for forming the first electrode plate, reducing the complexity of the display panel manufacturing process, and at the same time reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby improving the bending ability of the display panel.

[0076] The present application also provides a method for manufacturing a display panel, and the steps are substantially the same as those of the manufacturing method in the above embodiment, and will not be described in detail here. The difference between the method for manufacturing a display panel provided in the present application and the method for manufacturing a display panel provided in the above embodiment is that, Fig. 6A and Figure 6B As shown, Fig. 6A and Figure 6B is a schematic diagram of a film layer structure of a display panel corresponding to a method for manufacturing a display panel provided in an embodiment of the present application, wherein step S5 of forming an oxide semiconductor layer includes:

[0077] Step S501: Fig. 6A As shown, a layer of oxide semiconductor material 401 is deposited on a side of the first interlayer insulating layer 412 away from the first gate insulating layer 411; and

[0078] Step S502: Figure 6B As shown, a plurality of oxide semiconductor layers 417 and second electrodes 418 arranged at intervals are formed by a patterning process, and the orthographic projection area of ​​the second electrode 418 on the base substrate 40 overlaps with the orthographic projection area of ​​the first gate GE1 on the base substrate 40 .

[0079] The subsequent steps of the embodiment of the present application are substantially the same as the manufacturing method provided in the above embodiment. The structure of the display panel formed is similar to that in the above embodiment. Figure 3 The structure of the display panel is the same as that of the display panel, which will not be repeated here. The second electrode 418 formed in step S502 can respectively form the first capacitor and the second capacitor in parallel in the storage capacitor with the first gate GE1 and the first electrode 416, so that the unit capacitance value of the storage capacitor C can be increased, so that the size of the storage capacitor C can be compressed while ensuring that the capacitance value of the storage capacitor C remains unchanged, thereby reducing the area occupied by the pixel circuit and improving the resolution of the display panel. Similarly, the capacitance value of the storage capacitor C can be increased while the size of the storage capacitor C remains unchanged, so that when the storage capacitor C stores a potential signal, the influence of the leakage current on it is reduced, thereby improving the stability of the display effect of the display panel under the state of low refresh rate or low power consumption.

[0080] In step S5, the material of the oxide semiconductor layer 417 is preferably IGZO. Of course, in some other embodiments, the material of the oxide semiconductor layer 417 may also include but is not limited to oxide semiconductor materials such as indium gallium oxide or indium zinc oxide. The specific material can be selected according to actual needs and is not limited here. From step S501 to step S502, the second electrode 418 is formed simultaneously by the process of preparing the oxide semiconductor layer 417, so that when the second electrode 418 is added, the original number of film layers and the thickness of the film layers of the display panel are kept unchanged, thereby ensuring the bending performance of the display panel. At the same time, the mask plate and related process flow required for preparing the second electrode 418 alone can be omitted, thereby reducing the complexity of the process flow and production cost of the display panel.

[0081] Beneficial effects of the embodiments of the present application: The manufacturing method of the display panel provided in the embodiments of the present application utilizes the process of preparing the second gate and the oxide semiconductor layer to simultaneously form the first electrode and the second electrode, thereby reducing the number of masks and related process steps, and also reducing the number of film layers in the display panel and the thickness of the film layer stack, thereby reducing the complexity of the display panel process flow and the production cost, while improving the bending ability of the display panel and the display effect of the display panel.

[0082] In summary, although the present application is disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; A thin film transistor array layer is disposed on the base substrate, wherein a plurality of first thin film transistors, second thin film transistors and storage capacitors are arranged at intervals in the thin film transistor array layer; Among them, the first thin film transistor includes a stacked polysilicon semiconductor layer and a first gate, the second thin film transistor includes a stacked oxide semiconductor layer and a second gate, the storage capacitor includes a first electrode plate arranged on the side of the first gate away from the substrate, the first gate and the first electrode plate constitute the storage capacitor, the first electrode plate and the second gate are arranged in the same layer, and the orthographic projection area of ​​the first electrode plate on the substrate overlaps with the orthographic projection area of ​​the first gate on the substrate; the storage capacitor includes a first capacitor and a second capacitor, a second electrode plate is arranged between the first gate and the first electrode plate, the first gate and the second electrode plate constitute the first capacitor, the first electrode plate and the second electrode plate constitute the second capacitor, and the first capacitor and the second capacitor are connected in parallel.

2. The display panel according to claim 1, wherein: The distance between the surface of the oxide semiconductor layer close to the substrate and the substrate is greater than the distance between the surface of the polysilicon semiconductor layer close to the substrate and the substrate.

3. The display panel according to claim 1, wherein: The thin film transistor array layer includes a first gate insulating layer and a first interlayer insulating layer which are sequentially stacked on the polycrystalline silicon semiconductor layer, the first gate is arranged between the first gate insulating layer and the first interlayer insulating layer, and the oxide semiconductor layer is arranged on a side of the first interlayer insulating layer away from the first gate insulating layer.

4. The display panel according to claim 3, wherein: The first interlayer insulating layer is a stacked structure formed by silicon nitride and silicon oxide materials, and the atomic percentage of silicon-hydrogen bonds in the first interlayer insulating layer is between 20% and 30%.

5. The display panel according to claim 3, wherein: The thin film transistor array layer also includes a second gate insulating layer and a second interlayer insulating layer stacked on a side of the first interlayer insulating layer away from the first gate insulating layer, and the first electrode plate and the second gate are both arranged between the second gate insulating layer and the second interlayer insulating layer.

6. The display panel according to claim 5, wherein: The first electrode plate and the second grid are made of the same layer of metal.

7. The display panel according to claim 5, wherein: An orthographic projection area of ​​the second electrode plate on the base substrate overlaps with an orthographic projection area of ​​the first gate or the first electrode plate on the base substrate.

8. The display panel according to claim 5, wherein: The second electrode plate is disposed on the same layer as the oxide semiconductor layer.

9. The display panel according to claim 8, wherein: The second electrode plate and the oxide semiconductor layer are made of the same oxide material.

10. The display panel according to claim 5, wherein: The first thin film transistor includes a first source and a first drain, and the second thin film transistor includes a second source and a second drain. The first source and the first drain are respectively connected to the polycrystalline silicon semiconductor layer through first vias penetrating the second interlayer insulating layer, the second gate insulating layer, the first interlayer insulating layer and the first gate insulating layer, and the second source and the second drain are respectively connected to the oxide semiconductor layer through second vias penetrating the second interlayer insulating layer and the second gate insulating layer.

11. A display device, characterized in that: The device comprises a device body and a display panel as claimed in any one of claims 1 to 10 arranged on the device body.

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