Method for initializing a differential two-wire data bus and method for transmitting data

Abstract

A method for initializing a differential two-wire data bus and a method for transmitting data are provided. The method for initializing a differential two-wire data bus, wherein the two-wire data bus comprises a first single-wire data bus and a second single-wire data bus, wherein the second single-wire data bus is divided into at least two two-wire data bus sections by at least two bus nodes, comprises the following steps: determining a new bus node address by the bus master; storing the bus node address in a bus node address register of a bus node, i.e., a bus node under consideration by the bus master; connecting one or more two-wire data bus sections with one or more other two-wire data bus sections by closing a transmission gate of the bus node under consideration, wherein during the closing of the transmission gate, the bus node is prevented from storing the bus node address in the bus node address register of the bus node under consideration by the bus master.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201780079357.5, which entered the Chinese national phase on June 20, 2019, and the invention name is "Chained two-wire data bus composed of two single-wire data buses respectively having multiple differential levels for transmitting lighting data based on the JTAG protocol."

[0002] This application claims the priority of German patent application 10 2016 125 290.5 filed on December 21, 2016 and German patent application 10 2017 100 718.0 filed on January 16, 2017, the contents of which are hereby incorporated by reference into the subject matter of the present patent application.

[0003] The present invention relates to a modified JTAG interface of a bus node in a differential two-wire data bus and a two-wire data bus system for a lighting device, the two-wire data bus system having a differential two-wire data bus and a bus node provided with a modified JTAG interface, for controlling at least one control device of at least one light-emitting device respectively via the bus node. In addition, the present invention relates to a method for controlling a light-emitting device by means of an electrical device of one of a plurality of bus nodes of a differential two-wire data bus system having a differential two-wire data bus. The present invention relates to a method for initializing a differential two-wire data bus. In addition, the present invention relates to a device for transmitting data after the differential two-wire data bus has been initialized. Finally, the present invention also relates to a two-wire data bus system having a differential two-wire data bus and a method for data transmission in such a two-wire data bus system having a differential two-wire data bus, as well as a device for connecting a bus node to a differential two-wire data bus.

[0004] introduction

[0005] In the automotive industry, it should be possible in the future to use light strips consisting of light-emitting diodes (LEDs) with preferably a plurality of colors. These LEDs should be controlled and powered by means of known pulse modulation methods such as pulse width modulation (PWM), pulse code modulation (PCM), pulse count modulation (PCM), phase shift modulation (POM), pulse density modulation (PDM), pulse frequency modulation (PFM), etc. The corresponding modulation types are available to the skilled person from the relevant literature. When PWM is mentioned below, all pulse modulation types currently known in the prior art are therefore meant within the scope of the present invention. Depending on the average voltage level or current level applied to the respective LED, the brightness of the LED can be adjusted and, if necessary, also the color temperature of the LED can be adjusted to some extent. Thus, for example in the case of PWM modulation, the duty cycle and the level determine the brightness appearance and the perceived color temperature.

[0006] The LEDs of a light strip are typically evenly distributed over the length of the light strip.

[0007] In the prior art, a plurality of integrated circuits are usually used to drive LEDs, which are distributed more or less evenly on the light strip as bus nodes. Typically, in this case, a plurality of luminous means, preferably LEDs, are assigned to each bus node, which are then respectively controlled by the bus node.

[0008] This control is carried out for individual integrated circuits for individual LEDs or for a plurality of LEDs which are typically arranged in succession on a light strip, ie for the light strip section which is assigned to the integrated circuit.

[0009] In the prior art, shift registers with inputs and outputs are now usually provided for each of these integrated circuits. In this case, the input of the subsequent shift register of the subsequent integrated circuit on the light strip is connected to the output of the shift register of the previous integrated circuit in the light strip. The first integrated circuit of the light strip is connected to a bus master (BM) instead of the previous integrated circuit, which generates the data and the shift clock. Typically, the bus master is a microcontroller.

[0010] The bus master (BM) provides the necessary shift clock and acceptance signals to all shift register segments of all integrated circuits along this composite shift register chain via the clock conductor (TCK), and the acceptance signal is transmitted via the test data conductor (TDI) in time division multiplexing or the test mode signal conductor (TMS) in space division multiplexing. Using this space division multiplexing, the current values ​​in each segment of the shift register chain are loaded into the shadow register of the integrated circuit.

[0011] Therefore, in order to transmit the required information, the bus master (BM) generates a serial data stream containing information about the brightness and / or color temperature, which it shifts into the shift register chain in the correct bit order and signals the acceptance to the integrated circuits with the correct clock. The integrated circuits then load their shadow registers accordingly and adjust the PWM modulation of the LED driver in terms of amplitude and duty cycle or fill factor according to the brightness and color temperature values ​​thus loaded.

[0012] Here are a few issues to address when using it in a car.

[0013] First, the methods and devices known from the prior art for controlling such light strips require a supply voltage conductor, a ground conductor, a clock conductor, a signaling conductor and a data conductor, i.e. a total of five conductors. If necessary, the vehicle body can be used as a ground conductor if it is not made of non-conductive plastic or another insulator. Then four conductors are still required. This leads to increased costs and weight.

[0014] Secondly, no feedback channel is provided in order to be able to identify, for example, error situations and / or to be able to measure the temperature at the location of the LEDs and / or to be able to perform self-tests and the like.

[0015] Third, the achievable speed is not sufficient for many applications. Further increases in data rates could result in radiation.

[0016] There is therefore a need for a solution which allows programming and reading of an integrated circuit via a single data conductor.

[0017] The JTAG protocol is known in the prior art. The JTAG protocol has developed into one of the leading auxiliary tools in the programming, testing, debugging and simulation of integrated circuits. In a method called a boundary scan method, a main processor can control the state of an integrated circuit. In particular, the main processor as a bus master can appropriately program the integrated circuit as a bus node via a dedicated interface, i.e., a JTAG interface according to the IEEE 1149 standard and initialize it when necessary. In addition, the main processor as a bus master can read the state of the integrated circuit after a predetermined number of system clock cycles of the JTAG interface according to the IEEE 1149 standard or when a predetermined event is recognized, or change the state of the integrated circuit during the operation of the integrated circuit, i.e., during the operation of the bus node. This also includes stopping the time flow of the finite automaton that executes the program and stops the integrated circuit through the integrated circuit, or forcing it to change to other states or changing the memory content. However, the JTAG protocol is a point-to-point connection, so it is not suitable for controlling the automotive light strip. Although the link of the JTAG test interface has long been known from EP-B-0 503 117. However, EP-B-0 503 117 discloses the link of a four-wire JTAG interface. Therefore, the technology of EP-B-0 503 117 does not meet the requirements for a two-wire data bus for controlling automotive LED-based light strips.

[0018] The proposal according to the invention described below therefore relates to a method and a device for linked control and / or programming of a plurality of integrated circuits, for example microsystems such as microelectromechanical systems (MEMS) and integrated microelectronic optical systems (MEOS), by means of a two-wire data bus, wherein the integrated circuits to be controlled, i.e. the microsystems comprising the microelectromechanical systems (MEMS) and the integrated microelectronic optical systems (MEOS), each assume the role of a bus node. For such systems, these systems are now usually controlled in a purely point-to-point configuration via a JTAG test bus in accordance with the IEEE 1149 standard for manufacturing tests. This standard JTAG interface has a test data port, typically with four test connections, i.e. with

[0019] 1. At least one serial data input (test data input) TDI,

[0020] 2. At least one serial data output (test output) TDo,

[0021] 3. At least one mode input (test mode input) TMS,

[0022] 4. At least one clock input (test clock input) TCK,

[0023] 5. Optional reset input (test reset input) TRST.

[0024] Since this method has been known for decades, reference is made here to the corresponding specialist literature and other publications (eg IEEE 1149 standard).

[0025] Here is just a brief description: the JTAG protocol according to the IEEE 1149 standard includes five signal groups in the basic standard, which are exchanged between the simulation unit and the integrated circuit as a slave, the simulation unit contains a main processor and thus acts as a bus master, and the integrated circuit is referred to as a bus node in the following. The TCK signal represents the system clock and synchronizes the internal state machine of the test controller (TAPC) of the JTAG test interface of the integrated circuit according to the IEEE 1149 standard in time. The TMS signal controls the state of the test controller (TAPC) of the JTAG interface of the bus node. Depending on the state of the test controller (TAPC), the JTAG test interface of the bus node performs different operations. The TDI input represents the serial data input. The TDo output represents the serial data output. Typically (but not necessarily) the rising TCK edge is used to sample the two inputs TMS and TDI. The data output (TDo) typically changes its data with the falling edge of the TCK signal. In the prior art, the TCK single signal, the TMS single signal and the TDI single signal form the test data input signal. In the context of the present invention, they form the data input signal. The TDo signal represents the output signal. With the rising system clock edge (TCK edge) and with the instruction register (IR) inside the test controller (TAPC) of the test controller (TAPC) being appropriately adjusted, the data is serially shifted into the integrated circuit as a bus node via the serial data input TDI in the so-called scan path to different shift register chains. At the same time, the original content of the scan chain involved is output at the serial data output (TDo). In this case, the state vector of the finite automaton within the bus node can be part of the scan chain. Therefore, in the prior art, the content and state of the memory cells of the scan chain can be easily changed or controlled via this interface. Reference is again made to the professional literature here.

[0026] Figure 1(Prior Art)

[0027] Figure 1 A standardized state diagram of a JTAG test controller (TAPC) according to the prior art and relevant standards is shown. After the system is reset, the test controller (TAPC) is in the "test logic (TLR) reset" state. As long as the test mode signal (TMS) is 1, the test controller will remain in this state. If the test mode signal (TMS) is 0, the test controller (TAPC) changes to the "wait state" (RUN) synchronously with the system clock (TCK). The test controller (TAPC) remains in this state until 1 is applied to the test mode signal (TMS). Then, the test controller (TAPC) changes to the "data register shift start" (SDRS) state. If the test mode signal (TMS) shows 1 again next time, the test controller (TAPC) changes to the "instruction register shift start" (SIRS) state. Then if 1 is applied to the test mode signal (TMS) again at the next clock, the test controller (TAPC) changes to the "test logic reset" (TLR) state and resets the data interface logic.

[0028] However, if there is a 0 on the test mode signal (TMS) in the "start of instruction register shift" (SIRS) state, the test controller (TAPC) changes to the "load instruction register data" (CIR) state, in which the data available in the instruction shadow register are loaded into the instruction register (IR). In this regard, the instruction register (IR) is a two-stage register, wherein the foreground is formed by the shift register, while the actual data is located in the shadow register, which is only read in this state. The shift register of the instruction register (IR) is used to input and output data, while the shadow register of the instruction register (IR) contains the actual, valid data. This two-stage nature applies to all registers, in particular also to the data register (DR) of the JTAG interface and to the register according to the invention of the interface according to the invention described below. If necessary, the shadow register of the instruction register (IR) can still be divided in whole or in part into one for the read process and one for the write operation. Other visibility changes and access possibility changes depending on the internal state are possible. If a 1 is applied in the "Load Instruction Register Data" (CIR) state at the next clock of the test mode signal (TMS), the test controller (TAPC) changes directly to the "Instruction Register Exit 1" (EIR1) state described later. However, if a 0 is applied, the test controller (TAPC) changes to the "Instruction Register Shift" (SIR) state, in which the test controller remains as long as a 0 is applied at the test mode signal (TMS). Only in this state does the shift register of the instruction register (IR) operate in the function of a shift register, and its data content is shifted by one bit with each clock of the system clock (TCK) in the direction of the serial data output (TDo), to which the last memory cell of the shift register of the instruction register (IR) is connected. The shadow register of the instruction register (IR) is not affected by this shift process. The data information applied to the data input (TDI) is loaded into the first cell of the shift register of the instruction register (IR) with each clock of the system clock (TCK) and is carried backwards from there with each additional clock during the shift. However, if 1 is applied to the test mode signal at one clock, the test controller (TAPC) leaves the "instruction register shift" (SIR) state and changes to the "instruction register exit 1" (EIR1) state mentioned above. If 1 is applied again at the next clock of the system clock (TCK), the test controller (TAPC) changes to the "write instruction register" (UIR2) state, in which the value (IR) of the shift register portion of the instruction register (IR) is written into the shadow register of the instruction register.However, if 0 is applied to the test mode signal (TMS) in the "Instruction Register Exit 1" (EIR1) state, the test controller (TAPC) changes to the "Pause Instruction Register" (PIR) state, and remains in this state as long as 0 is applied as the test mode signal (TMS). If 1 is applied to the test mode signal (TMS) in the "Pause Instruction Register" (PIR) state, the test controller (TAPC) changes to the "Instruction Register Exit 2" (EIR2) state. If 0 is applied to the test mode signal (TMS) with the next system clock (TCK), the test controller (TAPC) changes back to the "Instruction Register Shift" (SIR) state already described. However, if 1 is applied to the test mode signal (TMS) with the next system clock (TCK) in the "Instruction Register Exit 2" (EIR2) state, the test controller (TAPC) changes to the "Write Instruction Register" (UIR2) state. In the next clock, if 1 is applied as the test mode signal (TMS) at this clock, the test controller (TAPC) changes to the "data register shift start" (SDRS) state, and if 0 is applied, it changes to the "wait" (RUN) state.

[0029] If 0 is present as the test mode signal (TMS) in the "data register start shift" (SDRS) state, the test controller (TAPC) changes to the "load data register data" (CDR) state, in which the data available in the data shadow register is loaded into the corresponding data register (DR). In this case, which data register (DR) is selected from a plurality of data registers as the standard determines at least a part of the valid bits of the shadow register of the data register (DR). The data register (DR) is also typically a two-stage register here, wherein the foreground is formed by the shift register, while the actual data is located in the shadow register that is only read in this state. The shift register of the data register (DR) is also used for inputting and outputting data here, while the shadow register of the data register (DR) contains the actual data. This two-stage property is valid for all registers of the JTAG interface as described above, that is, the register according to the invention of the interface according to the invention described below, which is implemented as a data register (DR) as a standard. If necessary, the shadow register of the data register (DR) can be divided again completely or partially into one for the reading process and one for the writing process. Other visibility changes and access possibility changes according to the internal state are also possible here. If 1 is applied in the "Load Data Register Data" (CDR) state at the next clock of the test mode signal (TMS), the test controller (TAPC) changes directly to the "Data Register Exit 1" (EDR1) state described later. However, if 0 is applied, the test controller (TAPC) changes to the "Data Register Shift" (SDR) state, in which the test controller remains as long as 0 is applied at the test mode signal (TMS). Only in this state and not otherwise, the shift register of the data register (DR) operates in the function of a shift register and its data content is shifted by one bit with each clock of the system clock (TCK) in the direction of the serial data output (TDo), to which the last memory cell of the shift register of the data register (DR) is connected. The shadow register of the data register (DR) is not affected by this shift process. The data information applied to the data input (TDI) is loaded into the first cell of the shift register of the data register (DR) with each clock of the system clock (TCK) and is carried backward from there with each additional clock during the shift. However, if a 1 is applied to the test mode signal (TMS) at the clock, the test controller (TAPC) leaves the "data register shift" (SDR) state and changes to the "data register exit 1" (EDR1) state already mentioned above.If 1 is applied again at the next clock of the system clock (TCK), the test controller (TAPC) changes to the "write data register" (UDR2) state, in which the value of the shift register part of the data register (DR) is written to the shadow register of the data register (DR). However, if 0 is applied as the test mode signal (TMS) in the "data register exit 1" (EDR1) state, the test controller (TAPC) changes to the "pause data register" (PDR) state, and the test controller remains in this state as long as 0 is applied as the test mode signal (TMS). If 1 is applied as the test mode signal (TMS) in the "pause data register" (PDR) state, the test controller (TAPC) changes to the "data register exit 2" (EDR2) state. If 0 is applied as the test mode signal (TMS) with the next system clock (TCK), the test controller (TAPC) changes back to the "data register shift" (SDR) state already described. However, if 1 is applied to the test mode signal (TMS) in the "Data Register Exit 2" (EDR2) state with the next system clock (TCK), the test controller (TAPC) changes to the "Write Data Register" (UDR2) state. In the next clock, if 1 is applied as the test mode signal (TMS) at this clock, the test controller (TAPC) changes to the "Data Register Shift Start" (SDRS) state, and if 0 is applied, it changes to the "Wait" (RUN) state.

[0030] It is particularly useful to use the state scheme of the IEEE 1149 JTAG standard in order to maintain compatibility with the already widely used standard on the software level. Of course, deviations from the JTAG standard are conceivable. The description of the invention is based on the following example, i.e., the state diagram for the test controller (TAPC) complies with the JTAG standard.

[0031] In recent years, the semiconductor industry has repeatedly attempted to reduce the number of connectors to be used for this JTAG interface in order to limit the size of the required housing and therefore limit manufacturing costs. In US-A-2007 / 0033465, a technology is described that does not allow the data of the IEEE 1149.14-wire-JTAG protocol to be consistently converted into the data of the method described there, and vice versa. The device arrangement described there and the method described there require a time slot that is synchronized between the bus master, i.e., the main processor and the bus node, i.e., the integrated circuit as a slave, which should be tested, programmed or debugged. If the bus master and the bus node lack time synchronization to access the test data bus, the TDo output driver of the bus node and the bus master output driver (typically a push-pull stage) may generate a short circuit when sending access to the test data line at the same time. In addition, US-A-2007 / 0033465 only discloses point-to-point connection.

[0032] From US-A-2007 / 0033465 and US-A-2011 / 0150065, multi-level single-line point-to-point arrangements are known, which already suffice with only one data line, but are not suitable for operating a plurality of bus nodes. An extension of the linking method disclosed in EP-B-0 503 117 is not possible, since it does not disclose a method for bidirectional relaying suitable for intermediate levels. Various embodiments of data transmission bus systems are described in DE-A-102 56 631, DE-B-102 61 14, DE-A-10 2010 042 311, DE-B-10 2015 004 434, US-A-6 105 077, US-A-2004 / 0208200, US-A-2011 / 0150065, US-A-2012 / 0144078, US-A-2013 / 0073761 and US-A-2014 / 0281076.

[0033] US-B-8 492 983 discloses linking by means of a single-wire point-to-point data conductor (reference numeral 11 in US-B-8 492 983). However, this link requires a feedback conductor (reference numeral 11 in US-B-8 492 983). Figure 4 ). The advantage of a single data line is therefore again lost due to the necessity of a feedback line.

[0034] Various publications are also known which relate to data transmission. DE-C-196 43 013, DE-A-10 215 720, DE-A-2006 022 985, DE-B-10 2007 060 441, US-A-2009 / 0252210 and US-A-2008 / 0255791 should be mentioned here. In principle, for the control of LEDs, for example, DE-U-20 2008 012 029, DE-U-20 2013103146, US-A-5 859 657, US-B-6 297 724, US-A-2003 / 0009715, US-A-2010 / 0109530 and US-A-2014 / 0333207 disclose single-wire data bus systems and, if necessary, two-wire data bus systems that operate in a differential manner. However, in all these systems, the JTAG interface is not used in the bus node, and the JTAG interface is conventionally used for boundary scan tests, for example. None of the documents mentioned here discloses how a bus master (BM) controls the bus node by means of the JTAG interface when the bus nodes are linked.

[0035] This also applies to US-A-2014 / 0281076, which discloses a star topology. This star topology of the network does not allow a correlation between physical locations and logical addresses and is therefore not suitable for the application of a method for assigning bus addresses (automatic addressing). However, the applicability of this method is a prerequisite for use in the automotive industry.

[0036] US-A-2014 / 0333207 discloses a device and a method for operating a lighting system in which messages from "intelligent" nodes are received and forwarded. The operation of the known lighting system results in time delays in the forwarding of data between data bus segments within the nodes, which is not suitable for fast adjustment of light scenes.

[0037] US-A-2012 / 0144078 discloses a method for unidirectionally transmitting clock and data from a slave to a master. In this case, the clock is transmitted from the master to the slave with the first edge of the combined clock / data stream, and the data is transmitted from the slave to the master with the second edge of the combined clock / data stream. This method is not bidirectional.

[0038] US-A-2009 / 0021955 discloses controlling LED interior lighting via a hierarchical two-wire data bus, which can be implemented as a series arrangement (paragraph

[0033] of US-A-2009 / 0021955). However, the technical teaching of US-A-2009 / 0021955 also relates to a star topology. Bus masters and slaves alternate in a time slot method. The transmission of system clocks and data and the control and address allocation of bus nodes are not explained. In particular, the bus master cannot specifically call the test resources installed in the corresponding bus slave at the physical level. Summary of the invention

[0039] The object of the invention is to allow bidirectional, freely configurable lighting data transmission using two data lines for more than one bus node (BS1, BS2, BS3) as slave of a bus master (BM).

[0040] This task is solved by each embodiment. Specifically, a method for initializing a differential two-wire data bus between a first sub-device, namely a bus master (BM), and at least two other sub-devices, namely bus nodes, is provided, wherein the two-wire data bus includes a first single-wire data bus and a second single-wire data bus, the second single-wire data bus is divided by at least two bus nodes into at least two two-wire data bus segments having a first single-wire data bus segment and a second single-wire data bus segment, and is terminated by at least one bus node in the bus nodes, namely an end bus node, comprising the following steps: determining a new bus node address by the bus master; initializing a new bus node address by the bus master (BM) at the bus node, namely The bus node address is stored in a bus node address register (BKADR) of the bus node under consideration, wherein the bus master (BM) and the bus node under consideration are connected to each other via one or more two-wire data bus segments, and the bus node address register (BKADR) is a data register (DR) of a modified JTAG interface or a part of a data register (DR) of a modified JTAG interface of the bus node under consideration or a part of an instruction register (IR) of a modified JTAG interface of the bus node under consideration, wherein the modified JTAG interface is characterized in that it has a test controller with a state diagram according to the IEEE 1149 standard or a sub-standard thereof; one or more two-wire data bus segments are connected to one or more other two-wire data bus segments by closing a transmission gate (TG) of the bus node under consideration, wherein during the closing of the transmission gate (TG), the bus node is always prevented from storing the bus node address in the bus node address register (BKADR) of the bus node under consideration by the bus master (BM).

[0041] The invention proposes a modified JTAG interface of a bus node (BS1, BS2, BS3) in a differential two-wire data bus system for controlling at least one operating device of at least one lighting device via the bus node (BS1, BS2, BS3) of a lighting chain, wherein the modified JTAG interface provides:

[0042] - the modified JTAG interface comprises at least one lighting register (ILR) as a data register (DR) of the modified JTAG interface, the actuation of the lighting means via the bus nodes (BS1, BS2, BS3) at least temporarily depending on the at least temporary content of the at least one lighting register,

[0043] - wherein the modified JTAG interface is characterized in that the JTAG test controller (TAPC) comprises a state diagram according to the IEEE 1149 standard and in particular according to one or more of the substandards IEEE 1149.1 to IEEE 1149.8 and their further developments.

[0044] According to the invention, the JTAG interface is modified in that it now operates with differential signals instead of absolute voltage signals, ie voltage signals which vary relative to a reference level (eg ground), as transmitted according to the invention in a differential two-wire data bus.

[0045] The present invention also proposes a two-wire data bus system for lighting devices, which has

[0046] - differential two-wire data bus, and

[0047] a plurality of bus nodes (BS1, BS2, BS3), each bus node controlling at least one operating device for at least one luminous means,

[0048] - wherein each bus node (BS1, BS2, BS3) has a modified JTAG interface coupled to the two-wire data bus, the modified JTAG interface comprising at least one illumination register (ILR) as a data register (DR) of the modified JTAG interface, the actuation of the light-emitting device by the bus node (BS1, BS2, BS3) being at least temporarily dependent on the at least temporary content of the data register, and

[0049] - wherein the modified JTAG interface is characterized in that a JTAG test controller (TAPC) comprises a state diagram according to the IEEE 1149 standard and in particular according to one or more of the substandards IEEE 1149.1 to IEEE 1149.8 and further developments thereof.

[0050] The present invention also proposes a method for controlling a light-emitting device by means of an electrical device of one of a plurality of bus nodes (BS1, BS2, BS3) of a two-wire data bus system having a differential two-wire data bus, comprising the following steps:

[0051] - transmitting control data for adjusting a light value for at least one light emitting device via a JTAG test controller (TAPC) operating the modified JTAG interface in a bus node (BS1, BS2, BS3), wherein the bus node supplies controllable electrical energy to the at least one light emitting device according to these control data,

[0052] - wherein the modified JTAG interface is characterized in that the JTAG test controller (TAPC) comprises a state diagram according to the IEEE 1149 standard and in particular according to one or more of the substandards IEEE 1149.1 to IEEE 1149.8 and further developments thereof.

[0053] According to the invention, a variant of the JTAG interface according to the invention is provided by a modified JTAG interface for controlling an operating device of a lighting device via a bus node (BS1, BS2, BS3) of a two-wire data bus system having a differential two-wire data bus, wherein according to the invention, provision is made in the modified JTAG interface that

[0054] - the modified JTAG interface comprises at least one illumination control register (ILCR) as a data register of the modified JTAG interface and comprises an illumination register (ILR) as a data register of the modified JTAG interface,

[0055] - the content of the lighting control register (ILCR) depends at least in part on whether the lighting register (ILR) receives lighting data from a driver for controlling the luminous means via the bus node via the test data interface (TMS_TDI) or the separate data input (SILDI) of the modified JTAG interface, and

[0056] - the actuation of the luminous means by the bus node (BS1, BS2, BS3) is at least temporarily dependent on the at least temporary content of the lighting register (ILR),

[0057] - wherein the modified JTAG interface is characterized in that it comprises a JTAG test controller (TAPC) having a state diagram according to the IEEE 1149 standard and in particular according to one or more of the substandards IEEE 1149.1 to IEEE 1149.8 and further developments thereof.

[0058] The present invention also relates to a method for initializing a differential two-wire data bus between a first sub-device, i.e. a bus master (BM), and at least two other sub-devices, i.e. bus nodes (BS1, BS2, BS3), wherein the two-wire data bus (b1b2b3b4) comprises a first single-wire data bus (b1a, b2a, b3a) and a second single-wire data bus (b1b, b2b, b3b), the second single-wire data bus being divided by at least two bus nodes into at least two two-wire data bus sections (b1, b2, b3) with the corresponding first single-wire data bus sections (b1a, b2a, b3a) and second single-wire data bus sections (b1b, b2b, b3b), and being terminated by at least one bus node (BS3) of the bus nodes (BS1, BS2, BS3), i.e. an end bus node (BS3). The method comprises the following steps:

[0059] - Determine the new bus node address through the bus master;

[0060] - storing the bus node address in a bus node address register (BKADR) of a bus node (BS1, BS2, BS3), i.e. the bus node under consideration, by a bus master (BM), wherein the bus master (BM) and the bus node under consideration are connected to one another via one or more two-wire data bus segments (b1, b2, b3), and the bus node address register (BKADR) is a data register (DR) of a modified JTAG interface or a part of a data register (DR) of a modified JTAG interface of the bus node under consideration or a part of an instruction register (IR) of a modified JTAG interface of the bus node under consideration, wherein the modified JTAG interface is characterized in that it has a test controller with a state diagram according to the IEEE 1149 standard or a substandard thereof;

[0061] - connecting one or more two-wire data bus segments (b1, b2, b3) to one or more other two-wire data bus segments (b1, b2, b3) by closing a transmission gate (TG) of the bus node under consideration, wherein, while the transmission gate (TG) is closed, the bus node is always prevented from storing the bus node address in the bus node address register (BKADR) of the bus node under consideration (BS1, BS2, BS3) by the bus master (BM).

[0062] An advantageous development of the method comprises the step of storing the instruction for opening the transmission gate (TG) in a transmission gate control register (TGCR) or in an instruction register (IR) of the modified JTAG interface of the bus node under consideration.

[0063] A further variant of the method expediently comprises the step of checking correct addressing of the at least one bus node by cyclic writing and reading, in particular of a bypass register.

[0064] Finally, the method according to the invention may also comprise the steps of determining by a bus master (BM) the number of correctly addressable bus nodes, comparing the number of correctly addressable bus nodes with a rated number, and triggering at least one signal or measure as a function of this number by the bus master or a connected system.

[0065] According to the present invention, a method for transmitting data after initialization of a differential two-wire data bus is also proposed, comprising the following steps:

[0066] - simultaneously transmitting the transmit address to all reachable bus nodes by writing the transmit registers (SR) of all bus nodes with the transmit address by the bus master (BM), wherein the respective transmit register (SR) of the respective bus node is a data register or a part of a data register or an instruction register (IR) of a modified JTAG interface of the bus node and wherein the bus node address register (BKADR) is not part of the register in question;

[0067] - by each bus node comparing the send address in the send register (SR) with the bus node address in the bus node address register (BKADR) by means of a predetermined comparison algorithm;

[0068] - activating the sending capability for the respective bus node at a time specified for this purpose, if the comparison algorithm of the comparison previously carried out by the respective bus node results in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR);

[0069] - The sending capability for the respective bus node is deactivated if the comparison algorithm of the comparison previously carried out by the respective bus node does not result in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR).

[0070] Furthermore, according to the present invention, a method for transmitting data after initialization of a differential two-wire data bus is proposed, comprising the following steps:

[0071] - simultaneously transmitting the transmit address to all reachable bus nodes by writing the transmit registers (SR) of all bus nodes with the transmit address by the bus master (BM), wherein the respective transmit register (SR) of the respective bus node is a data register or a part of a data register or an instruction register (IR) of a modified JTAG interface of the bus node and wherein the bus node address register (BKADR) is not part of the register in question;

[0072] - by each bus node comparing the send address in the send register (SR) with the bus node address in the bus node address register (BKADR) by means of a predetermined comparison algorithm;

[0073] - activating the receiving capability of the respective bus node for the content of a predetermined data register of the respective bus node, if the comparison algorithm of the comparison previously carried out by the respective bus node results in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR);

[0074] - If the comparison algorithm of the comparison previously performed by the corresponding bus node does not result in sufficient agreement with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR), the receiving capability of the corresponding bus node is deactivated for the content of the predetermined data register of the corresponding bus node.

[0075] According to the present invention, a method for transmitting data after initialization of a differential two-wire data bus is also proposed, comprising the following steps:

[0076] - simultaneously transmitting the transmit address to all reachable bus nodes by writing the transmit registers (SR) of all bus nodes with the transmit address by the bus master (BM), wherein the respective transmit register (SR) of the respective bus node is a data register or a part of a data register or an instruction register (IR) of a modified JTAG interface of the bus node and wherein the bus node address register (BKADR) is not part of the register in question;

[0077] - by each bus node comparing the send address in the send register (SR) with the bus node address in the bus node address register (BKADR) by means of a predetermined comparison algorithm;

[0078] - activating the receiving capability of the respective bus node for the content of the predetermined content of the instruction register (IR) of the respective bus node to allow a predetermined instruction to the instruction decoder (IRDC) of the modified JTAG interface of the respective bus node, if the comparison algorithm of the comparison previously carried out by the respective bus node results in a sufficient agreement with the combination of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR) expected for a send permission;

[0079] - If the comparison algorithm of the comparison previously performed by the corresponding bus node does not result in sufficient agreement with the combination expected for the send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR), the receiving capability of the corresponding bus node is deactivated for the content of the predetermined content of the instruction register (IR) of the corresponding bus node in order to inhibit the predetermined instructions of the instruction decoder (IRDC) of the modified JTAG interface of the corresponding bus node.

[0080] The invention also relates to a two-wire data bus system having a differential two-wire data bus (b1b2b3) for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3),

[0081] - wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by bus nodes (BS1, BS2, BS3) and ends by a bus node, namely an end bus node (BS3), and - wherein each bus node (BS1, BS2, BS3) except the first bus node (BS1) is connected to the preceding bus node (BS1, BS2, BS3) of the two-wire data bus section (b1, b2, b3) via the preceding two-wire data bus section (b2, b3) of the bus node (BS1, BS2, BS3) (BS1, BS2), and the first bus node (BS1) is connected to the bus master (BM) via the preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3), and - wherein each bus node (BS1, BS2, BS3) is connected to the subsequent bus node (BS3, BS4) of the bus nodes (BS1, BS2, BS3) via the subsequent two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3), except for the end bus node (BS3), and

[0082] - wherein the two-wire data bus system has a bus master (BM) with a master two-wire data bus interface (OWM), and

[0083] - wherein the master two-wire data bus interface (OWM) of the bus master (BM) is configured to bidirectionally send and receive data via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of the two-wire data bus segments (b1, b2, b3) (hereinafter referred to as the two-wire data bus segment (b1, b2, b3) under consideration) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels, and - wherein the two-wire data bus segment (b1, b2, b3) under consideration comprises two signal conductors, and

[0084] wherein a two-wire data bus interface (OWS1, OWS2, OWS3) of one of the bus nodes (BS1, BS2, BS3) (hereinafter referred to as the bus node (BS1, BS2, BS3) under consideration) is electrically connected to the two-wire data bus section under consideration, and

[0085] wherein the two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration is configured to receive data from the two-wire data bus segment under consideration (b1, b2, b3) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels, and

[0086] wherein the two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration is configured to transmit data via the two-wire data bus segment under consideration (b1, b2, b3) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels, and

[0087] - the bus nodes (BS1, BS2, BS3) under consideration are in turn equipped with a master two-wire data bus interface (OWM1, OWM2, OWM3), and

[0088] - wherein the master two-wire data bus interface (OWM1, OWM2, OWM3) of the bus node (BS1, BS2, BS3) under consideration is configured to bidirectionally transmit and receive data to and from a subsequent bus node (BS2, BS3) via at least one subsequent two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3) (hereinafter referred to as subsequent two-wire data bus segment (b2, b3)) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels, and

[0089] - wherein the bus node (BS1, BS2, BS3) under consideration has a first bus master control register (OWMCR) which is designed to control a master two-wire data bus interface (OWM1, OWM2, OWM3) of the bus node (BS1, BS2, BS3) under consideration, and

[0090] -Wherein the bus master (BM) can write to the bus master control register (OWMCR) of the bus node under consideration (BS1, BS2, BS3) via the master two-wire data bus interface (OWM) of the bus master (BM) and the two-wire data bus (b1b2b3) or the two-wire data bus segment under consideration (b1, b2, b3) and the two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration, and can thus control the state of the master two-wire data bus interface (OWM1, OWM2, OWM3) of the bus node under consideration (BS1, BS2, BS3).

[0091] The invention also relates to a method for data transmission in a two-wire data bus system having a differential two-wire data bus, comprising:

[0092] a differential two-wire data bus (b1b2b3) with two signal conductors for differential transmission of data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3),

[0093] - wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by a bus node (BS1, BS2, BS3) and ends by a bus node, namely an end bus node (BS3), and - wherein each bus node (BS1, BS2, BS3) except the first bus node (BS1) is connected to the preceding two-wire data bus section (b2, b3) of the bus node (BS1, BS2, BS3) by a preceding two-wire data bus section (b1, b2, b3) of the bus node (BS1, BS2, BS3) points (BS1, BS2), and the first bus node (BS1) is connected to the bus master (BM) via the preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3), and - wherein each bus node (BS1, BS2, BS3) is connected to the subsequent bus node (BS2, BS3) of the bus node (BS1, BS2, BS3) via the subsequent two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3) except the end bus node (BS3).

[0094] In this method, the following operations are further performed:

[0095] - bidirectionally sending and receiving data via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of a two-wire data bus segment (b1, b2, b3) (hereinafter referred to as the two-wire data bus segment (b1, b2, b3) under consideration) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels through a master two-wire data bus interface (OWM) of a bus master (BM);

[0096] - receiving data from the two-wire data bus section under consideration (b1, b2, b3) via a two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration of the bus node (BS1, BS2, BS3) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels;

[0097] - sending data via the two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node under consideration of the bus node (BS1, BS2, BS3) via the two-wire data bus segment (b1, b2, b3) concerned by means of a data bus protocol using more than two differential physical voltage levels and / or current levels;

[0098] - bidirectionally sending and receiving data to a subsequent bus node (BS2, BS3) via at least one subsequent two-wire data bus segment (b2, b3) of the two-wire data bus segment (b2, b3) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels through a master two-wire data bus interface (OWM1, OWM2, OWM3) of the bus node under consideration; and

[0099] - controlling a master two-wire data bus interface (OWM1, OWM2, OWM3) of the bus node under consideration via a bus master control register (OWMCR) of the bus node under consideration, which is designed to be writable by the bus master via the two-wire data bus (b1b2b3).

[0100] The invention also has a device for connecting to a differential two-wire data bus (b1b2b3) of a data bus system as a bus node for transmitting lighting data for light-emitting devices (LED1, LED2, LED3, LED4), wherein the two-wire data bus (b1b2b3) has a plurality of two-wire data bus sections (b1, b2, b3) divided by the bus nodes, and wherein the device is equipped with

[0101] - housing (GH),

[0102] - wherein the housing (GH) has at least two rows of connection terminals, namely a first row of connection terminals (GND, b1a, b1b, V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ),

[0103] - wherein at least two of the connection end rows are arranged opposite each other on the housing (GH),

[0104] wherein each terminal row comprises a supply potential terminal for a first, in particular negative, supply potential (GND) and a second, in particular positive, supply potential (V bat ) connection end,

[0105] - In which not only the first connection terminal row (GND, b1a, b1b, V bat ) for the first power supply potential connection terminal (GND) and the second connection terminal row (GNd, b2a, b2b, V bat ) for the first power supply potential connection terminal (GND), and the first connection terminal row (GND, b1a, b1b, V bat ) for the second power supply potential connection terminal (V bat ) and the second connection terminal row (GNd, b2a, b2b, V bat ) for the second power supply potential connection terminal (V bat ) are connected without crossing each other,

[0106] - Among them, the first connection terminal row (GND, b1a, b1b, V bat ) has two bus connections (b1a, b1b) for a two-wire data bus section (b1) upstream of the bus node, which are arranged between a connection for a first supply potential (GND) and a supply potential connection for a second supply potential (V bat )between,

[0107] - Among them, the second connection terminal row (GND, b2a, b2b, V bat ) has two bus connections (b2a, b2b) for a two-wire data bus section (b2) downstream of the bus node, which are arranged between a connection for a first supply potential (GND) and a connection for a second supply potential (V bat ), and

[0108] -Wherein, each connection terminal row has at least one connection terminal for connecting to a light-emitting device (LED1, LED2, LED3, LED4), which is adjacent to the connection terminal (GND) for a first power supply potential of the connection terminal row in question, and is adjacent to the side of the connection terminal (GND) for the first power supply potential of the connection terminal row in question that is opposite to the bus connection terminal (b1a, b1b, b2a, b3b).

[0109] Finally, the present invention also includes a device for connecting to a differential two-wire data bus (b1b2b3) of a data bus system as a bus node for transmitting lighting data for light-emitting devices (LED1, LED2, LED3, LED4), wherein the two-wire data bus (b1b2b3) has a plurality of two-wire data bus sections (b1, b2, b3) divided by bus nodes, and wherein the device is equipped with

[0110] - housing (GH),

[0111] - wherein the housing (GH) has at least two rows of connection terminals, namely a first row of connection terminals (GND, b1a, b1b, V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ),

[0112] - wherein at least two of the connection end rows are arranged opposite each other on the housing (GH),

[0113] wherein each terminal row comprises a terminal for a first, in particular negative, supply potential (GND) and a terminal for a second, in particular positive, supply potential (V bat ),

[0114] - In which not only the first connection terminal row (GND, b1a, b1b, V bat ) for the first power supply potential connection terminal (GND) and the second connection terminal row (GNd, b2a, b2b, V bat ) for the first power supply potential connection terminal (GND), and the first connection terminal row (GND, b1a, b1b, V bat ) for the second power supply potential connection terminal (V bat ) and the second connection terminal row (GNd, b2a, b2b, V bat ) for the second power supply potential connection terminal (V bat ) are connected without crossing each other,

[0115] - Among them, the first connection terminal row (GND, b1a, b1b, V bat) has two bus connections (b1a, b1b) for a two-wire data bus section (b1) upstream of the bus node, which are arranged between a connection for a first supply potential (GND) and a connection for a second supply potential (V bat )between,

[0116] - Among them, the second connection terminal row (GND, b2a, b2b, V bat ) has two bus connections (b2a, b2b) for a two-wire data bus section (b2) downstream of the bus node, which are arranged between a connection for a first supply potential (GND) and a connection for a second supply potential (V bat ), and

[0117] - at least one light emitting device (LED1, LED2, LED3, LED4),

[0118] The lighting means (LED1, LED2, LED3, LED4) is arranged in a recess (ASP) of the housing (GH) or on the housing (GH).

[0119] In the case of the above-mentioned two devices, at least three groups of light-emitting devices (LED1, LED2, LED3) can be set, each group of light-emitting devices having at least one light-emitting device (LED1, LED2, LED3), which are arranged outside the housing (GH) or in a recess (ASP) of the housing (GH) and / or on the housing (GH), wherein at least one light-emitting device (LED1, LED2, LED3) in each group of light-emitting devices (LED1, LED2, LED3) has a different luminous color relative to at least one light-emitting device (LED1, LED2, LED3) in another group of light-emitting devices (LED1, LED2, LED3).

[0120] In addition, at least two light-emitting device (LED1, LED2, LED3, LED4) groups each having a light-emitting device (LED1, LED2, LED3, LED4) or at least three light-emitting device (LED1, LED2, LED3, LED4) groups each having a light-emitting device (LED1, LED2, LED3, LED4) can be provided, wherein the brightness of at least one light-emitting device (LED1, LED2, LED3, LED4) of each light-emitting device (LED1, LED2, LED3, LED4) group can be adjusted differently relative to at least one light-emitting device (LED1, LED2, LED3, LED4) of each other light-emitting device (LED1, LED2, LED3, LED4) group by adjusting the luminous intensity according to the data content of the lighting register (ILR).

[0121] Furthermore, the present invention includes a device for connecting to a differential two-wire data bus (b1b2b3) of a data bus system as a bus node for transmitting lighting data for light-emitting devices (LED1, LED2, LED3, LED4), wherein the two-wire data bus (b1b2b3) has a plurality of two-wire data bus sections (b1, b2, b3) divided by the bus nodes, and wherein the device is provided with

[0122] - housing (GH),

[0123] - wherein the housing (GH) has at least three rows of connection terminals, namely a first row of connection terminals (GND, b1a, b1b, V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ) and the third connection terminal row (V bat , b3a, b3b) and an optional fourth connection terminal row (GND, b4a, 4b4),

[0124] wherein each of the three or four connection rows has at least one adjacent connection row on the housing (GH) which is arranged at an angle to the connection row, in particular at an acute angle or an obtuse angle or an angle of 90°,

[0125] wherein each terminal row has a terminal for a first, in particular negative, supply potential (GND) and a terminal for a second, in particular positive, supply potential (V bat ),

[0126] wherein of two adjacent rows of terminals of the housing (GH), one row of terminals has terminals for a first supply potential (GND) and the other row of terminals has terminals for a second supply potential (V bat ),

[0127] wherein, with respect to the clockwise or counterclockwise counting direction, the corresponding supply potential connection of all connection terminal rows of the housing (GH) is in each case the first connection terminal of the connection terminal row,

[0128] - each terminal row comprises two bus terminals (b1a, b1b, b2a, b2b, b3a, b3b, b4a, b4b) for one two-wire data bus section (b1, b2, b3),

[0129] - two bus terminals (b1a, b1b, b2a, b2b, b3a, b3b, b4a, b4b) for a two-wire data bus section (b1, b2, b3) are adjacent to the supply potential terminal of the terminal row in question, and - at least one luminous means (LED1, LED2, LED3),

[0130] At least one luminous means (LED1, LED2, LED3) is arranged in a recess (ASP) of the housing (GH) or on the housing (GH).

[0131] In the case of such a device or another of the above-mentioned devices according to the present invention, a conductive mounting element (lead frame) can be provided for leading out of the housing (GH) the contact banks of the bare die with the IC circuit embedded in the housing (GH), wherein the housing (GH) has two opposite rows of connection terminals, each row of connection terminals having a first power supply potential (GND) or a second power supply potential (V bat ) and wherein the power supply potential terminals of the two terminal rows are electrically conductively connected to one another via a mounting element (lead frame).

[0132] Furthermore, it is possible that the mounting element (lead frame) has a support member (die paddle) that carries the die, and the support member connects the two opposite connection terminals to the first power supply potential (GND) or the second power supply potential (V bat ) are electrically conductively connected to each other.

[0133] In this further development of the invention, it is provided that the V of each housing bat The GND connection terminal of each housing is connected to each other via the die holder of the lead frame. The corresponding other power supply potential connection terminal (GND or V bat ) via printed conductors constructed in the bare die, or via printed conductors constructed on a printed circuit board (on which the bare die is located).

[0134] The present invention also includes a device for connecting to a differential two-wire data bus (b1b2b3) of a data bus system as a bus node for transmitting lighting data for light emitting devices (LED1, LED2, LED3, LED4), wherein the two-wire data bus (b1b2b3) has a plurality of two-wire data bus sections (b1, b2, b3) divided by the bus nodes, and wherein the device is provided with

[0135] - housing (GH),

[0136] - bus connections (b1a, b1b, b2a, b2b) for receiving lighting data via a differential two-wire data bus (b1b2b3),

[0137] - wherein the bus connections (b1a, b1b, b2a, b2b) are arranged at a supply potential connection for a first, in particular negative, supply potential (GND) and at a second, in particular positive, supply potential (V bat) between the power supply potential connection terminals,

[0138] - at least one light emitting device (LED1, LED2, LED3),

[0139] - an illumination register (ILR) operable via signals to be applied to the bus connections (b1a, b1b, b2a, b2b), and

[0140] - means for operating light emitting devices (LED1, LED2, LED3), wherein the brightness and / or the color of the light emitted by at least one of the light emitting devices depends on the content of an illumination register (ILR).

[0141] In this case, at least three groups of light-emitting devices (LED1, LED2, LED3) are provided, each group of light-emitting devices having at least one light-emitting device (LED1, LED2, LED3), and the light-emitting device groups are arranged outside the housing (GH) or in a recess (ASP) of the housing (GH) and / or on the housing (GH), wherein at least one light-emitting device (LED1, LED2, LED3) of each group of light-emitting devices (LED1, LED2, LED3) has a different luminous color relative to at least one light-emitting device (LED1, LED2, LED3) of each other group of light-emitting devices (LED1, LED2, LED3).

[0142] In addition, at least two light-emitting device (LED1, LED2, LED3, LED4) groups each having a light-emitting device (LED1, LED2, LED3, LED4) or at least three light-emitting device (LED1, LED2, LED3, LED4) groups each having a light-emitting device (LED1, LED2, LED3, LED4) can be provided, wherein the brightness of at least one light-emitting device (LED1, LED2, LED3, LED4) of each light-emitting device (LED1, LED2, LED3, LED4) group can be adjusted differently relative to at least one light-emitting device (LED1, LED2, LED3, LED4) of each other light-emitting device (LED1, LED2, LED3, LED4) group by adjusting the luminous intensity according to the data content of the lighting register (ILR). Summary of the invention

[0144] According to the present invention, it has been recognized that when each bus node has a sub-device suitable for bidirectional relaying, a two-wire data bus consisting of two single-wire test buses is particularly suitable for the transmission of such data, and is particularly suitable for controlling the light-emitting devices of the light-emitting strip. The two-wire data bus (including the associated operating method) is described, for example, in the documents DE-B-10 2015 004433, DE-B-10 2015 004 434, DE-B-10 2015 004 435 and DE-B-10 2015 004 436, the contents of which are hereby incorporated by reference into the subject matter of the present application. The use of a differential multilevel JTAG bus for controlling the power supply is described in DE-B-10 2016 100 837, DE-B-10 2016 100 838, DE-B-10 2016 100 839, DE-B-10 2016 100 840, DE-B-10 2016 100 841, DE-B-10 2016 100 842, DE-B-10 2016 100 843, DE-B-10 2016 100 845, DE-B-10 2016 100 847 and DE-B-10 2016 101 181, the contents of which are hereby incorporated by reference into the subject matter of the present patent application.

[0145] In contrast to the subject matter of DE-B-10 2015 004 433, DE-B-10 2015 004 434, DE-B-10 2015 004 435 and DE-B-10 2015 004 436, however, instead of transmitting test data differentially, useful data are now transmitted differentially, in particular for lighting control. The differential transmission of useful data allows significantly higher data transmission rates and at the same time lower EMC emissions. In contrast to the known CAN protocol, the data clock is also transmitted, which makes the complex reconstruction of the data clock in the bus nodes superfluous and thus significantly reduces the number of bus nodes (BS1 to BS2). n). In addition, the test buses disclosed in DE-B-10 2015 004 433, DE-B-10 2015 004 434, DE-B-10 2015 004 435 and DE-B-10 2015 004436 are also only designed for point-to-point connection. Therefore, on the one hand, it is necessary to modify the test bus so that multiple bus slaves can be controlled as bus nodes, and on the other hand, it is necessary to modify the test bus so that it can operate with an increased data rate. The latter is achieved by using a two-wire data bus composed of two single-wire data buses. In this case, according to the present invention, control data is written into a dedicated data register (DR) of the JTAG interface via the two-wire data bus or read from the dedicated data register of the JTAG interface.

[0146] Therefore, unlike the documents DE-B-10 2016 100 837, DE-B-10 2016 100 838, DE-B-10 2016 100839, DE-B-10 2016 100 840, DE-B-10 2016 100 841, DE-B-10 2016 100 842, DE-B-10 2016 100 843, DE-B-10 2016 100 845, DE-B-10 2016 100 847 and DE-B-10 2016 101 181, higher speeds can be achieved when transmitting lighting data to the bus node according to the technical teaching of the claimed invention.

[0147] The core idea of ​​the present invention is the complementary modulation of two single-wire data buses, thereby reducing EMC radiation and achieving higher data transmission speeds.

[0148] The above-mentioned and other tasks are solved according to the invention by providing an interface unit with a JTAG interface, which can exchange time-multiplexed signals with an integrated circuit in a chronological order by means of an interface device and can manipulate the signals via a two-wire data bus. These signals are formatted so that all the information required to control the data flow and adjust the lighting parameters of the connected light-emitting device via the JTAG interface is transmitted serially and with differential signals via this interface. In this case, all data values ​​of the JTAG boundary protocol are transmitted as differential signals in the time slots provided for this purpose. In addition to the time multiplexing of the JTAG control signals, the interface device according to the invention also uses three different differential voltage value ranges (V B1 , V B2 , V B3 ) for differential voltage signals and differential signal levels (TOW) in order to achieve differential two-wire data bus (see Figure 2 )

[0149] 1. At least the serial test data input TDI data, and

[0150] 2. At least serial test output TDo data, and

[0151] 3. control data of at least the test mode input TMS for controlling the test controller of the integrated circuit, and

[0152] 4. A test clock for providing at least the test controller with its test system clock TCK, and

[0153] 5. Optional test reset signal TRST.

[0154] In this case, unlike the patent documents already mentioned above, Figure 2 Now differential rather than absolute levels are shown.

[0155] Therefore, the present invention mainly relates to a bidirectional differential data bus (see FIG. 1 ) having a two-wire data bus (b1b2b3b4) between a first sub-device, namely a bus master (BM), and at least two other sub-devices, namely bus nodes (BS1, BS2, BS3). Figure 6), which is composed of two single-wire data buses (b1a, b1b, b3a, b4a; b1b, b2b, b3b, b4b). In this case, the bus node also has the above-mentioned integrated circuit for controlling the light-emitting device by means of PWM in the broadest sense, the state of which is to be controlled or changed. Of course, the bidirectional differential data bus described in the present invention is also suitable for controlling other consumers of electrical energy. Such a bidirectional differential data bus preferably has only one ground conductor (GND), a first single data conductor in the form of a first single-wire data bus (b1a, b1b, b3a, b4a) of a two-wire data bus (b1a, b1b, b3a, b4a; b1b, b2b, b3b, b4b) and a second single data conductor in the form of a second single-wire data bus (b1b, b2b, b3b, b4b) of a two-wire data bus (b1a, b2a, b3a, b4a; b1b, b2b, b3b, b4b). A two-wire data bus (b1a, b1b, b3a, b4a; b1b, b2b, b3b, b4b) and therefore a first single-wire data bus (b1a, b1b, b3a, b4a) and a second single-wire data bus (b1b, b2b, b3b, b4b) are divided into individual two-wire data bus sections (b1, b2, b3) via bus nodes (BS1, BS2, BS3), wherein a first single-wire data bus of the two-wire data bus is divided into corresponding single-wire data bus sections (b1a, b1b, b3a, b4a), and wherein a second single-wire data bus of the two-wire data bus is also divided into corresponding single-wire data bus sections (b1b, b2b, b3b, b4b). In this case, the first and the second single-wire data bus section of the two-wire data bus section are advantageously implemented in each case as a single-wire data bus section according to DE-B-10 2016 100 837, DE-B-10 2016 100 838, DE-B-10 2016 100 839, DE-B-10 2016 100 840, DE-B-10 2016 100 841, DE-B-10 2016 100 842, DE-B-10 2016 100 843, DE-B-10 2016 100 845, DE-B-10 2016 100847 and DE-B-10 2016 101 181. As a result, each bus node (BS1, BS2, BS3) requires only two additional pairs of electrical terminals. In order to be able to send data from the bus master (BM) to one of the bus nodes (BS1, BS2, BS3) (hereinafter referred to as the bus node in question) and to be able to read data from the bus node in question to the bus master (BM), data can now be transmitted bidirectionally via the two-wire data bus (b1b2b3).In this case, the data are transmitted complementary on the first and second single-wire data bus of the two-wire data bus (b1b2b3). This means that, in contrast to the aforementioned document group, the potential of a single, i.e., first or second single-wire data bus conductor is not evaluated relative to a reference potential, but rather the potential difference between the first single-wire data bus conductor (b1a, b1b, b3a, b4a) and the second single-wire bus data conductor (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) is evaluated. This potential difference is also referred to below as the differential level (TOW). In other respects, the method and device for the first and second single-wire data bus preferably correspond to the method and device of the aforementioned document.

[0156] The problem now arises that, in addition to data transmission, synchronization signals must also be transmitted differentially. For this purpose, a system clock is additionally transmitted via the two-wire data bus (b1b2b3) by means of a clock signal, namely the TCK signal, in particular from the bus master (BM) to the bus node (BS1, BS2, BS3). In order to allow this communication, the bus node (BS1, BS2, BS3) has a first device which compares the differential signal level (TOW) on the two-wire data bus segments (b1, b2, b3) on the first single-wire data bus (b1a, b2a, b3a) and the second single-wire data bus (b1b, b2b, b3b) of the two-wire data bus (b1b2b3) or on the connection of the two-wire data bus (b1b2b3) with a third threshold value (V 2H ) for comparison (see also Fig. 9 ). For this purpose, the differential signal level (TOW) is preferably detected by the second differential input amplifier (V2) of the corresponding two-wire data bus interface (OWSn) of the relevant bus node (BSn) under consideration and converted into a differential level signal (DPS). The third comparator (cmp3) of the corresponding two-wire data bus interface (OWSn) of the relevant bus node (BSn) under consideration compares the differential signal level (TOW) on the two-wire data bus of the two-wire data bus section (bn) before the bus node (BSn) under consideration with the value of the third threshold signal (i.e., the third threshold (V 2H In addition, the bus node (BSn) under consideration also has a second device, which compares the differential signal level (TOW) on the two-wire data bus of the two-wire data bus section (bn) before the bus node (BSn) under consideration in the form of the value of the differential level signal (DPS) with a second threshold value (V 2LThe second comparator (cmp2) of the corresponding two-wire data bus interface (OWSn) of the relevant bus node (BSn) under consideration compares the differential signal level (TOW) on the two-wire data bus (b1b2b3) of the two-wire data bus segment (bn) before the bus node (BSn) under consideration with the second threshold signal (V 2L ) value. If the third threshold (V 2H ) and the second threshold (V 2L ) are different and these thresholds (V 2L , V 2H ) is within the power supply voltage range according to the value, then these two thresholds (V 2H , V 2L ) defines and specifies three voltage value ranges (V B1 , V B2 , V B3 ), wherein the bus node in question determines the differential voltage on the two-wire data bus. In this case, the second and third comparators (cmp2, ​​cmp3) on the bus node side measure: in which voltage value range (V B1 , V B2 , V B3 ). The second and third thresholds (V 2L , V 2H ) thus defines the three signal voltage value ranges (V B1 , V B2 , V B3 ), and thus define three voltage ranges for the differential signal level (TOW) on the two-wire data bus (b1b2b3). The second amplifier (V2) and the first amplifier (V1) explained later are preferably designed so that they reduce the maximum expected differential overshoot (Hub) on the front two-wire data bus segment (bn) to less than the supply voltage (V bat ) is a simple numerical value relative to the second reference potential (GND). It should be noted here that due to the differential nature of the bus, the maximum level overshoot of the differential signal level (TOW) can be the operating voltage (V bat ) is twice the value of . For the sake of clarity, the middle voltage value range is named the second voltage value range (V B2 The second voltage value range is subject to the first voltage value range (V B1) limit. In this case, the “first voltage range (V B1 ) is greater than the second voltage range (V B2 ), that is, the voltage range of the intermediate voltage range being more positive or more negative is not determined because the system also operates with the opposite voltage polarity. At the same time, the corresponding second voltage value range (V B2 ) is limited by the other voltage side, that is, upward, that is, in the first voltage value range (V B1 ) in the opposite case, through the third voltage value range (V B3 ) restrictions. (See Figure 3 . )

[0157] In order to transmit data from the bus master (BM), i.e. the main processor, to the bus nodes (BS1, BS2, BS3), the data are now transmitted in at least three successive time slots (TIN0, TIN1, TDOz) by the bus master (BM) or the bus node in question (BS1, BS2, BS3) via a two-wire data bus (b1b2b3) or a two-wire data bus section (b1, b2, b3) of the two-wire data bus (b1b2b3) connected to the bus nodes (BS1, BS2, BS3), see Figure 5 and Figure 6In this case, who has the transmission authorization is defined by the time position of the respective time slot (TIN0, TIN1, TDOz) and the content of the respective bus node address register (BKADR) of the respective bus node (BS1, BS2, BS3) and the transmission address of the respective bus node (BS1, BS2, BS3) previously transmitted by the bus master (BM) to the respective bus node (BS1, BS2, BS3). In this case, in a grouping of three consecutive time slots (TIN0, TIN1, TDOz) for transmission purposes, typically two time slots (TIN0, TIN1) are allocated to the bus master (BM) and typically one time slot (TDOz) is allocated to the bus node (BS1, BS2, BS3) involved. According to the invention, the bus master (BM) transmits and stores data, which of the bus nodes (BS, BS2, BS3) is allowed to transmit in the corresponding bus node transmit time slot (TDOz), by means of data, namely the transmit address of the bus node (BS1, BS2, BS3) concerned, to all transmit registers (SR) of all reachable bus nodes (BS1, BS2, BS3) whose preceding two-wire data bus segments are just allowed to be connected to the bus master (BM). All bus nodes (BS1, BS2, BS3) compare the transmit address in their respective transmit register (SR) with their own bus node address stored in their bus node address register (BKADR) during bus initialization and transmit in the bus node transmit time slot (TDOz) and only at a predetermined time only if the transmitted transmit address in their transmit register (SR) coincides with their own bus node address stored in their bus node address register (BKADR). The relative time slot positions within the packet of at least three time slots (TIN0, TIN1, TDOz) are preferably, but not necessarily, always the same for as many bus nodes (BS1, BS2, BS3) as possible. Particularly preferably, the first time slot (TIN0) and the second time slot (TIN1) contain control data and / or first data transmitted from the bus master (BM) to the bus nodes (BS1, BS2, BS3), wherein the control data and the first data should in particular and preferably be compatible with the data of the IEEE 1149.14 line test data bus, and wherein the bus nodes (BS1, BS2, BS3) receive the control data and the first data. For example, bus node addresses, send addresses, lighting values, etc. can be transmitted in this way.

[0158] However, in contrast to the prior art, in the third time slot, i.e. the bus node transmit time slot (TDOz), only the second and third voltage value ranges (V B2 and V B3 ), rather than in the first voltage value range (V B1 ) from the bus node in question (BSn) to the bus master (BM). The bus node (BSn) under consideration comprises the address register (BKADRn) as a data register (DRn) of its JTAG interface. Therefore, the third time slot, i.e. the bus node send time slot (TDOz), contains according to the invention second data, which are transmitted from the bus node in question (BSn) to the bus master (BM), and the bus master (BM) receives the second data from the bus node in question (BSn), wherein the second data are only transmitted within a second voltage value range (V B2 ) and in the third voltage value range (V B3 ) is transmitted through the bus nodes (BSn) involved. At the same time, the clock is transmitted by the bus master (BM) in each time slot (TIN0, TIN1, TDOz), see Figure 5 The clock signal (TCK) is in this case signaled by a clock signal which is on the one hand at least two half-clock cycles (T 1H , T 2H ) in the first half clock cycle of the first voltage value range (V B1 ) and on the other hand at least two half clock cycles (T 1H , T 2H ) in the second half clock cycle (V B2 ) or the third voltage value range (V B3 The clock signal is detected by the following manner: the value of the differential voltage on the two-wire data bus (b1b2b3) or on the two-wire data bus segments (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is from the second voltage value range (V B2 ) or the third voltage value range (V B3 ) switches to the first voltage value range (V B1 ), and vice versa. The second threshold (V 2L ) can be detected by the corresponding threshold voltage crossing of the second comparator (cmp2, ​​see Fig. 9), i.e., an analog device. It is therefore possible to extract the system clock (TCK) safely on the bus node (BSn) side involved, i.e., on the integrated circuit side. Here, according to the invention, the clock injection configuration is selected in such a way that the clock transmitter can overwrite any other level source that can be activated in parallel at the two-wire data conductor on the bus master (BM) side compared to the injection configuration of other signals. Therefore, in reality, it may be necessary to provide external larger transistors for injecting clocks on the two-wire data bus (b1b2b3) or on the connected two-wire data bus sections (b1, b2, b3) of the two-wire data bus (b1b2b3) so as to be able to provide clocks to as many bus nodes (BS1, BS2, BS3) as possible. These external transistors should be selected so that they can overwrite all bus node current sources when all bus node current sources are activated simultaneously.

[0159] In a particular embodiment, such a data bus system is characterized in that during bidirectional transmission of data on a two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (b1, b2, b3) of a two-wire data bus (b1b2b3), three logic states are used by the bus master (BM) and the bus nodes (BS1, BS2, BS3), wherein the logic states have a hierarchical structure. A clock state, in this case a value of a differential signal level (TOW) of the two-wire data bus (b1b2b3) or of a connected two-wire data bus segment (b1, b2, b3) of the two-wire data bus (b1b2b3) is within a first voltage value range (V B1 ) has the highest priority and cannot be overwritten by other sending devices, such as sending devices of bus nodes (BS1, BS2, BS3). This ensures that the bus master (BM) and the bus nodes (BS1, BS2, BS3) can always work synchronously, at least in terms of the basic clock. This is a significant advantage, for example compared to the CAN bus, in which complex clock recovery is required in the bus nodes. In order to be able to establish a first logical state, in this first logical state the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus segments (b1, b2, b3) of the two-wire data bus (b1b2b3) is forced to be within a first voltage value range (V B1 ), the master two-wire data bus interface (OWM) of the bus master (BM) preferably has a first master switch in the form of a first transistor (T1a), see Figure 8 , for controlling a first single-line data bus (b1a, b2a, b3a, b4a), wherein the first dominant switch is switched on and off in at least two half clock cycles (T) of a corresponding time slot of a corresponding system basic clock cycle (T) 1H, T 2H ) in the half clock cycle of the dual-line data bus (b1b2b3), the first single-line data bus (b1a, b2a, b3a, b4a) is connected to the first reference potential, that is, the power supply voltage (V bat ) to make a relatively low-ohmic short circuit, see Figure 8 Furthermore, the master two-wire data bus interface (OWM) of the bus master (BM) preferably has a second master switch in the form of a first transistor (T1b), see Figure 8 , for controlling the second single-line data bus (b1b, b2b, b3b, b4b), the second dominant switch is at least two half clock cycles (T) of the corresponding time slot of the corresponding system basic clock cycle (T) 1H , T 2H ), a second single-line data bus (b1b, b2b, b3b, b4b) of the two-line data bus (b1b2b3) is short-circuited with a relatively low resistance, for example, relative to a second reference potential (GND), wherein the second reference potential is preferably opposite to the first reference potential in terms of voltage level, see Figure 8 When its internal resistance is higher than the internal resistance of the two leading first transistors (T1a, T1b) in the master two-wire data bus interface (OWM), the corresponding single-wire data bus is relative to the reference potential (V bat , GND) can no longer be overwritten by other transmitters, in particular the transmitters of the bus nodes (BS1, BS2, BS3). The first voltage divider consists of a first voltage divider resistor (R 1a ) relative to a voltage such as the positive supply voltage (V bat )) and the second voltage divider resistor (R 2a ) is formed relative to another voltage (for example, a second reference potential (GND)). The second voltage divider is formed by the additional first voltage divider resistor (R 1b ) relative to the voltage (e.g., the positive supply voltage (V bat )) and an additional second voltage divider resistor (R 2b ) is formed relative to another voltage, such as a second reference potential (GND). When no other transmitters (T1a, T2a, T3a, T1b, T2b, T3b) of the bus master (BM) or the bus node (BS1, BS2, BS3) are transmitting, the first voltage divider and the second voltage divider together keep the value of the differential signal level (TOW) of the two-wire data bus (b1b2b3) or the connected two-wire data bus segments (b1, b2, b3) of the two-wire data bus (b1b2b3) within the second voltage value range (V B2 ) or guide the value back to the second voltage value range (V B2 )middle.

[0160] Now, in order to transmit data, when the second voltage value range (V B2 ), the value of the differential signal level (TOW) on the two-line data bus (b1b2b3) or on the connected two-line data bus segments (b1, b2, b3) of the two-line data bus (b1b2b3) changes from the second voltage value range (V B2 ) is brought into a third voltage value range (V B3 ). For this purpose, the corresponding sending unit, that is to say the bus master (BM) or the bus node (BS1, BS2, BS3) concerned, feeds a current into the corresponding single-wire data bus of the two-wire data bus (b1b2b3) or into the connected single-wire data bus segments of the two-wire data bus segments (b1, b2, b3) concerned. The two fed-in currents lead to a voltage divider resistor (R 1a , R 2a ; R 1b+ , R 2b ) changes. In the case of a suitable polarity of the feed current, the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus segments (b1, b2, b3) of the two-wire data bus (b1b2b3) changes from the second voltage value range (V B2 ) moves to the third voltage value range (V B3 If simultaneous transmission occurs with the aid of such a data stream and simultaneous closing of the master switches (T1a, T1b), then: provided that the master switches are designed according to the invention to be sufficiently low-ohmic, the master switches (T1a, T1b) derive the transmission streams of the respective transmitters and thus rewrite the value of the differential signal level (TOW) and, if necessary, also the value of the differential signal level (TOW) via the voltage divider (R 1a , R 1b , R 2a , R 2b ) generates a differential signal level (TOW). However, a short circuit is not possible as in the prior art. In particular, a short circuit between the bus node side and the bus master transmitter known from US-A-2007 / 0033465 does not occur. Therefore, a special feature of the device is that the second of the three logic states on the two-wire data bus is realized by two first switchable current sources (preferably by a second transistor (T2a) and a further second transistor (T2b) in the bus master (BM) (cf. Figure 8)) and / or by two second switchable current sources (which are preferably implemented by a third transistor (T3a) and a further third transistor (T3b) (see Fig. 9 )) and is not generated by two voltage sources. At the same time, in one embodiment of the present invention, the differential pull circuit (R 1a+ , R 2a ; R 1b , R 2b ) generates the third of the three logic states on the data bus in the form of a first and a second voltage divider. Of course, other possibilities for such a differential pull-up circuit are also conceivable. In principle, the two voltage dividers (R 1a+ , R 2a ; R 1b , R 2b ) is a differential voltage source composed of two voltage sources, which places two single-wire data conductors of the two-wire data conductor on a second differential voltage, and the second differential voltage is within a second voltage value range (V B2 ). In this case, the differential voltage source has a corresponding internal resistance in each of its voltage sources, which is so large that the corresponding possible output current of the corresponding voltage source is limited, so that the switched current sources (T2a, T2b) and (T3a, T3b) respectively provide a current greater than that of the differential pull-up circuit (R 1a , R 2a ; R 1b , R 2b ) can draw out a larger current. Thus a clear hierarchy is obtained:

[0161] - First, the switch state of the dominant switch (T1a, T1b) of the bus master (BM) dominates, and then,

[0162] - as secondly, in a hierarchy of voltage-determining elements for a differential voltage on a two-wire data bus section (b1, b2, b3) on a two-wire data bus (b1b2b3) or on a connection of a two-wire data bus (b1b2b3), a switched current source (T2a, T2b) of the bus master and a switched current source (T3a, T3b) of the bus node under consideration, which typically have the same rights as one another, and

[0163] - As the third and final, differential pull-up circuit (here with a voltage divider (R 1a , R 2a ; R 1b , R 2b ) has the lowest priority, and the differential pull circuit is typically only set once per two-wire data bus segment.

[0164] Preferably, the first logic state corresponds to a first voltage value range (V B1 ) in the first differential voltage level (-V IO ), the second logic state corresponds to a second voltage value range (V ) on the two-wire data bus (b1b2b3) or on a two-wire data bus segment (b1, b2, b3) connected to the two-wire data bus (b1b2b3). B2 ) in the middle of the second differential voltage level (V M ), and the third logic state corresponds to a third voltage value range (V ) on the two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (b1, b2, b3) of the two-wire data bus (b1b2b3) B3 ) in the third differential voltage value level (V IO ), see below Figure 3 .

[0165] Advantageously, the first logic state of the data signal (e.g., "low") is transmitted using the second logic state, and the second logic state of the data signal (e.g., "high") is transmitted using the third logic state on the two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (b1, b2, b3) of the two-wire data bus (b1b2b3). If the two-wire data bus conductor is in the first logic state, this first logic state is not used for data transmission.

[0166] According to the present invention, a first logic state on a two-wire data bus (b1b2b3) or on a two-wire data bus segment (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is used to transmit a first logic state (e.g., "low") of a system clock signal, and a third or second logic state on a two-wire data bus (b1b2b3) or on a two-wire data bus segment (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is used to transmit a second logic state (e.g., "high") of the system clock signal. If the logic state on the two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (b1, b2, b3) of the two-wire data bus (b1b2b3) switches between a second or third logic state on the two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (b1, b2, b3) of the two-wire data bus (b1b2b3), the switch is not used for the transmission of the system clock and is typically also interpreted as the second logic state, for example “high”.

[0167] Therefore, the disclosed technology is a differential data bus system in one embodiment of the present invention, having a first single-wire data bus (b1a, b1b, b3a, b4a) and a second single-wire data bus (b1b, b2b, b3b, b4b) of a two-wire data bus (b1b2b3), for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular, transmitting data to a light-emitting device bus node. In this case, the first single-wire data bus (b1a, b1b, b3a, b4a) and the second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3) are respectively divided into at least two two-wire data bus sections (b1, b2, b3) by bus nodes (BS1, BS2, BS3), each two-wire data bus section having two single-wire data bus sections belonging to the two single-wire data buses. The two-wire data bus is terminated by a bus node, namely an end bus node (BS3). Each bus node (BS2, BS3) is connected to a preceding bus node (BS1, BS2, BS3) via a preceding two-wire data bus segment (b2, b3) of a two-wire data bus segment (b1, b2, b3) each consisting of two single-wire data bus segments, except for the first bus node (BS1). The first bus node (BS1) is connected to the bus master (BM) via a preceding first two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3). Each bus node (BS1, BS2) is connected to a succeeding bus node (BS2, BS3) of the bus node (BS1, BS2, BS3) via a succeeding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3), except for the ending bus node (BS3). This does not apply to the ending bus node (B3). The bus master (BM) is equipped with a master two-wire data bus interface (OWM), wherein the master two-wire data bus interface (OWM) is configured to bidirectionally transmit and receive data via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of a two-wire data bus segment (b1, b2, b3), hereinafter referred to as the two-wire data bus segment (b1, b2, b3) under consideration, by means of a data bus protocol using two or more physically differential voltage levels and / or current levels in terms of voltage values. The two-wire data bus segments under consideration (b1, b2, b3) in this case each comprise only two signal conductors, namely two single-wire data bus segments under consideration (bna, bnb).The two-wire data bus section (bn) under consideration is electrically connected to a two-wire data bus interface (OWSn) of the bus node (BSn) under consideration (hereinafter referred to as the bus node (BSn) under consideration) of the bus node (BS1, BS2, BS3) and a differential transmission gate (TGn) of the bus node (BSn) under consideration. The two-wire data bus interface (OWSn) of the bus node under consideration is configured to bidirectionally transmit and receive data via the two-wire data bus section (b1, b2, b3) under consideration by means of a data bus protocol using two or more numerically physically differential voltage levels and / or current levels. The differential transmission gate (TGn) of the bus node (BSn) under consideration is configured to connect the two-wire data bus section (b1, b2, b3) under consideration to the two-wire data bus section (b2). n ) and an optional subsequent two-wire data bus segment (b (n+1) ) is separated and / or electrically connected to the latter. The bus node (BSn) under consideration has a first transmission gate control register (TGCRn) respectively, which is designed to control the differential transmission gate (TGn) of the bus node (BSn) under consideration. The bus master (BM) can write to the differential transmission gate control register (TGCRn) of the bus node (BSn) under consideration via the master two-wire data bus interface (OWM) and the two-wire data bus (b1b2b3) or via the two-wire data bus segment (bn) under consideration and the two-wire data bus interface (OWSn) of the bus node (BSn) under consideration. Therefore, the bus master (BM) can control the state of the differential transmission gate (TGn) of the bus node (BSn) under consideration. In this case, the differential transmission gates (TGn) are respectively composed of two separate transmission gates, which are used to respectively connect the previous single-line data bus segment (bna, bnb) of the previous two-line data bus segment (bn) and the subsequent single-line data bus segment (b(n+1)a, b(n+1)b) of the subsequent two-line data bus segment (b(n+1)).

[0168] In another embodiment, the bus node (BSn) under consideration has internally at least one interface in accordance with IEEE 1149, also known as a JTAG interface, which is connected via a two-wire data bus interface (OWSn) of the bus node (BSn) under consideration to a two-wire data bus (b1b2b3) or at least a preceding two-wire data bus segment (bn) under consideration, so that a bus master (BM) can operate the JTAG interface via the two-wire data bus (b1b2b3) or at least a preceding two-wire data bus segment (bn) under consideration. In this case, the JTAG interface within the meaning of the invention is characterized in that it has a test controller (TAPCn) of the bus node (BSn) under consideration in the form of a finite state machine (i.e., a finite state machine) having a corresponding Figure 1 and the state diagrams described above in accordance with IEEE 1149.

[0169] In another advantageous embodiment, the data bus according to the invention is characterized in that the corresponding transmission gate control register (TGCRn) of the bus node (BSn) under consideration can be written by the bus master (BM) via at least one JTAG test interface of the bus node (BSn) under consideration via the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration.

[0170] In another advantageous embodiment, the data bus system according to the invention is characterized in that at least the bus node under consideration (BSn), i.e. the luminous device bus node, is configured to control the luminous device assigned to the luminous device bus node based on data transmitted from the bus master (BM) to the bus node under consideration via a two-wire data bus (b1b2b3) or a two-wire data bus segment (bn), hereinafter referred to as the luminous device under consideration.

[0171] In another advantageous embodiment, the data bus system according to the invention is characterized in that the JTAG interface of the bus node (BSn) under consideration comprises at least one lighting register (ILR) as a data register (DR) of the JTAG interface of the bus node (BSn) under consideration, and the control of the light-emitting device under consideration, in particular the control of the brightness and / or color temperature, by the bus node (BSn) under consideration with the aid of the PWM unit (PWM1, PWM2, PWM3) of the bus node (BSn) under consideration depends at least temporarily on the at least temporary content of the data register.

[0172] In another embodiment, the data bus system according to the invention is characterized in that the JTAG interface of the bus node (BSn) under consideration comprises at least one lighting command register (ILIRn) as a data register (DRn) of the JTAG interface of the bus node (BSn) under consideration and comprises a lighting register (ILRn) as a further data register (DRn) of the JTAG interface of the bus node (BSn) under consideration. Whether the lighting register (ILRn) of the bus node (BSn) under consideration receives serial lighting data for controlling the actuation of the lighting device under consideration by the bus master (BM) or another bus node (BS1, BS2, BS3) via the JTAG interface by means of a combined TMS-TDI signal (TMS_TDIn) of the JTAG interface of the bus node (BSn) under consideration or via a separate data input (SILDIn) of the bus node (BSn) under consideration depends at least on part of the content of the lighting command register (ILIRn) of the bus node (BSn) under consideration. In this case, the actuation of the luminous means under consideration by the bus node under consideration (BSn) depends at least temporarily on the at least temporary content of the lighting register (ILRn) of the bus node under consideration (BSn).

[0173] The differential data bus system according to the invention is provided with a two-wire data bus (b1b2b3), which is composed of a first single-wire data bus (b1a, b1b, b3a, b4a) and a second single-wire data bus (b1b, b2b, b3b), and is used to transmit data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular light-emitting device bus nodes. In this case, the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3). The two-wire data bus is terminated by a bus node, namely an end bus node (BS3). Each bus node (BS2, BS3) is connected to a preceding bus node (BS1, BS2, BS3) via a preceding two-wire data bus segment (b2, b3) of a two-wire data bus segment (b1, b2, b3) except for a first bus node (BS1). The first bus node (BS1) is connected to a bus master (BM) via a preceding first two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3). Each bus node (BS1, BS2) is connected to a subsequent bus node (BS2, BS3) of a bus node (BS1, BS2, BS3) via a subsequent two-wire data bus segment (b2, b3) of a two-wire data bus segment (b1, b2, b3) except for an end bus node (BS3). The data bus system has a bus master (BM) having a master two-wire data bus interface (OWM). In this case, the master two-wire data bus interface (OWM) is provided, as described above, for bidirectionally transmitting and receiving data via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of a two-wire data bus segment (b1, b2, b3), hereinafter referred to as the considered two-wire data bus segment (bn), by means of a data bus protocol using more than two physical voltage levels and / or current levels in numerical terms. The considered two-wire data bus segment (bn) comprises only two signal conductors. The two-wire data bus segment (bn) in question is electrically connected to a two-wire data bus interface (OWSn) of one of the bus nodes (BS1, BS2, BS3), hereinafter referred to as the considered bus node (BSn). A two-wire data bus interface (OWSn) of the bus node (BSn) under consideration is configured to receive data from the two-wire data bus segment (b1, b2, b3) under consideration by means of a data bus protocol using more than two numerically physically differential voltage levels and / or current levels.The bus node (BSn) under consideration comprises an address register (BKADRn) as a data register (DRn) of the JTAG interface, which can preferably only be written by the bus master (BM) when the differential transmission gate (TGn) of the bus node (BSn) under consideration is open, and "whether the two-wire data bus interface (OWSn) of the bus node (BSn) under consideration is allowed to output data to the two-wire data bus (b1b2b3) and / or to the two-wire data bus segment (b1, b2, b3) at a time point set for this and / or after specific data (e.g. a send address for a send register (SR) of the bus node) is sent by the bus master (BM) or another bus node in the bus nodes (BS1, BS2, BS3)" depends on the content of the address register and the content of the send register (SR) of the JTAG interface of the bus node (BSn) under consideration. The two-wire data bus interface (OWSn) of the bus node (BSn) under consideration is provided for transmitting data via the two-wire data bus section (bn) under consideration by means of a data bus protocol using at least two numerically physically differential voltage levels and / or current levels.

[0174] In a further suitable embodiment, the data bus system according to the invention is characterized in that the bus node (BSn) under consideration has internally at least one interface in accordance with IEEE 1149, also known as a JTAG interface, which is connected via a two-wire data bus interface (OWSn) of the bus node (BSn) under consideration to the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration, so that the bus master (BM) can operate the JTAG interface via the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration. In this case, the JTAG interface of the bus node (BSn) under consideration is characterized within the meaning of the invention in that it has a test controller (TAPCn) in the form of a finite state machine (i.e., a finite state machine) having a corresponding Figure 1 IEEE 1149 compliant state diagram.

[0175] In another advantageous embodiment, the data bus system according to the invention is characterized in that the two-wire data bus section (bn) under consideration is electrically connected to a differential transmission gate (TGn) of the bus node (BSn) under consideration. The differential transmission gate (TGn) of the bus node (BSn) under consideration is provided to separate the two-wire data bus section (bn) under consideration from an optional subsequent two-wire data bus section (b(n+1)) and / or to electrically connect the latter. In this case, the first single-wire data bus section (bna) under consideration of the two-wire data bus (bn) under consideration is respectively connected to or separated from the corresponding first single-wire data bus section (b(n+1)a) of the subsequent two-wire data bus (b(n+1)). Furthermore, in this case, the second single-wire data bus section (bnb) under consideration of the two-wire data bus (bn) under consideration is connected to or separated from the corresponding second single-wire data bus section (b(n+1)b) of the subsequent two-wire data bus (b(n+1)). The bus node (BS) under consideration has a transmission gate control register (TGCRn) as a data register (DRn) of a JTAG interface of the bus node (BSn) under consideration, which is designed to control a differential transmission gate (TGn) of the bus node (BSn) under consideration. The corresponding transmission gate control register (TGCRn) of the bus node (BSn) under consideration can be written to by means of at least one JTAG test interface of the bus node (BSn) under consideration via a two-wire data bus (b1b2b3) or at least a two-wire data bus segment (bn) under consideration, at least by a bus master (BM).

[0176] In another advantageous embodiment, the data bus system according to the invention is characterized in that at least the bus node under consideration (BSn), i.e. the luminous device bus node, is configured to control the luminous device (LMn) assigned to the luminous device bus node based on data transmitted from the bus master (BM) to the bus node under consideration via a two-wire data bus (b1b2b3) or the two-wire data bus segment under consideration (bn), hereinafter referred to as the luminous device (LMn) under consideration.

[0177] In a further advantageous embodiment, the data bus system according to the invention is characterized in that the JTAG interface of the bus node (BSn) in question comprises at least one illumination register (ILRn) as a data register (DRn) of the JTAG interface of the bus node (BSn) in question, the actuation of the lighting means (LMn) in question by the bus node (BSn) in question at least temporarily depending on the at least temporary content of the data register. This can be, for example, a duty cycle, an amplitude, a frequency and other parameters of a PWM actuation.

[0178] In another suitable embodiment, the data bus system according to the invention is characterized in that the JTAG interface of the bus node (BSn) under consideration comprises at least one lighting command register (ILIRn) as a data register (DRn) of the JTAG interface of the bus node (BSn) under consideration and comprises a lighting register (ILRn) as a data register of the JTAG interface of the bus node (BSn) under consideration. Whether the lighting command register (ILRn) of the bus node (BSn) under consideration receives the preferred serial lighting data for controlling the actuation of the lighting device under consideration by the bus master (BM) or another bus node (BS1, BS2, BS3) via the test data interface (TMS_TDIn) of the JTAG interface of the bus node (BSn) under consideration or via the separate differential data input (SILDI) of the bus node (BSn) under consideration depends at least on part of the content of the lighting command register (ILIRn) of the bus node (BSn) under consideration. In this case, the actuation of the luminous means (LMn) under consideration by the bus node (BSn) under consideration is at least temporarily dependent on the at least temporary content of the lighting register (ILR).

[0179] According to the invention, a JTAG interface of a bus node (BS1, BS2, BS3) for controlling the actuation of a light-emitting device (LM) via a bus node (BS1, BS2, BS3) of a light chain is characterized in that it comprises at least one lighting register (ILR) as a data register (DR) of the JTAG interface, the actuation of the light-emitting device (LM) via the respective bus node (BS1, BS2, BS3) being at least temporarily dependent on the at least temporary content of the lighting register. As mentioned above, the JTAG interface is characterized in that its test controller (TAPC) comprises a data register (DR) according to the IEEE 1149 standard (see also IEEE 1149). Figure 1 ) and in particular the state diagrams according to one or more of its sub-standards IEEE 1149.1 to IEEE 1149.8 and their developments. This definition of the identification of the JTAG interface applies to the entire document of the present invention.

[0180] Therefore, a method according to the invention for controlling a luminous means (LMn) by means of an electrical control device in a considered bus node (BSn) of a plurality of bus nodes (BS1, BS2, BS3) comprises the following steps:

[0181] Transmitting control data for adjusting the brightness value of at least one luminous means by actuating a JTAG controller (TAPCn) of a JTAG interface in the bus node (BSn) under consideration, said JTAG controller providing a controllable amount of electrical energy to at least one luminous means (LMn) according to these control data. In this case, the JTAG interface of the bus node (BSn) under consideration is again characterized as in the entire application in that the test controller (TAPCn) of the bus node (BSn) under consideration comprises a state diagram according to the IEEE 1149 standard and / or in particular according to its substandards IEEE 1149.1 to IEEE 1149.8 and their developments.

[0182] The JTAG interface according to the present invention for controlling the operating device of the lighting device via the bus node (BSn) of the lighting chain can also be characterized in that it includes at least one lighting control register (ILCR) as a data register of the JTAG interface, and a lighting register (ILIRn) as a data register of the JTAG interface. Thus, according to the present invention, the "lighting register (ILRn) is a test data interface (TMS_TDI) of the JTAG interface. n ), or via a separate data input (SILDI)" depends at least on part of the contents of the lighting control register (ILCR). These registers can also be subregisters of the instruction register (IRn) of the bus node (BSn) under consideration or subregisters of other data registers (DRn) of the JTAG interface of the bus node (BSn) under consideration. However, a separate implementation is generally preferred. Thus, the control of the light-emitting device (LMn) by the bus node (BSn) under consideration depends at least temporarily on the at least temporary contents of the lighting register (ILRn) of the bus node (BSn) under consideration. In this case, as described above, the JTAG interface of the bus node (BSn) under consideration is again characterized in that it includes a test controller (TAPCn) having a state diagram according to the IEEE 1149 standard and in particular according to its sub-standards IEEE 1149.1 to IEEE 1149.8 and their developments.

[0183] The differential data bus according to the invention between a first sub-device, i.e. a bus master (BM) and at least two other sub-devices, i.e. bus nodes (BS1, BS2, BS3), has a two-wire data bus (b1b2b3), which is composed of a first single-wire data bus (b1a, b2a, b3a) and a second single-wire data bus (b1b, b2b, b3b). The differential data bus is used for data transmission and system clock transmission between the bus master (BM) and the bus nodes (BS1, BS2, BS3). The two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3). Each bus node (BS2, BS3), except the first bus node (BS1), is connected to the preceding bus node (BS1, BS2) of the bus nodes (B1, B2, B3) via the preceding two-wire data bus section (b2, b3). A first bus node (BS1) is connected to a bus master (BM) via a preceding first two-wire data bus segment (b1). Each bus node (BS1, BS2) is connected to a subsequent bus node (BS2, BS3) via a subsequent two-wire data bus segment (b2, b3) with the exception of the end bus node (BS3). This is valid when the bus node is not the last bus node (B3) of a chain of bus nodes (BS1, BS2, BS3) starting from the bus master (BM) in the sequence of bus nodes (BS1, BS2, BS3). Data are transmitted or can be transmitted bidirectionally between the bus master (BM) and a bus node (hereinafter referred to as the bus node (BSn) under consideration) of the bus nodes (BS1BS2, BS3) via the two-wire data bus (b1b2b3) or via at least one two-wire data bus segment (b1, b2, b3) of the two-wire data bus segments (b1, b2, b3) (hereinafter referred to as the two-wire data bus segment (bn) under consideration). A system clock having a system clock cycle (T / 3) is additionally transmitted from the bus master (BM) to the bus node (BSn) in question via the two-wire data bus (b1b2b3) or at least via the two-wire data bus segment (bn) in question, the system clock cycle being divided into at least one first half clock cycle (T 1H ) and the second half clock cycle (T 2H), which may have different durations. At least the bus node (BSn) under consideration has a first device, in particular a third comparator (cmp3), which compares the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) in the form of a signal voltage difference between the potential of the first single-wire data bus segment (bna) of the two-wire data bus segment (bn) under consideration and the potential of the second single-wire data bus segment (bnb) of the two-wire data bus segment (bn) under consideration with the value of a third threshold value, in particular the potential of a third threshold signal, i.e. a third threshold value (V 2H The bus node (BSn) under consideration has a second device, in particular a second comparator (cmp2), which compares the value of the differential signal level (TOW) with the value of a second threshold value, in particular a second threshold signal (V 2L ) is compared with the voltage level of the third threshold (V 2H ) in this case is different from the second threshold value (V 2L ). In this case, the second and third thresholds (V 2L , V 2H ) defines three signal voltage value ranges (V B1 , V B2 , V B3 In this case, as the second voltage value range (V B2 ) is divided into the middle voltage value range of the first voltage value range (V B1 ) is limited downward. However, the second voltage value range (V B2 ) upward and in the first voltage value range (V B1 ) in the opposite case, through the third voltage value range (V B3) restrictions. In this case, the data on the two-wire data bus section (bn) under consideration are transmitted in a time-spaced manner or in successive time slot packets, wherein the successive time packets each have a duration of a system clock cycle (T / 3) including at least three consecutive time slots (TIN0, TIN1, TDOz). The first time slot (TIN0) and the second time slot (TIN1) contain at least one control data and / or first data, which are each transmitted from the bus master (BM) to the bus node (BS1, BS2, BS3) under consideration, wherein the control data and the first data can in particular be compatible with data of an IEEE 1149.14-wire test data bus or with other substandards of the IEEE 1149 standard, and wherein the bus node (BSn) under consideration receives the control data and the first data from the bus master (BM). The third time slot (TDOz) contains second data sent by the bus node (BSn) under consideration to the bus master (BM), wherein the bus master (BM) receives the second data from the bus node (BSn) under consideration, and wherein the second data is transmitted only within a second voltage value range (V B2 ) and the third voltage value range (V B3 ) is transmitted in the system basic clock cycle (T). Data transmission is performed in at least two half clock cycles (T 1H , T 2H ) in a half clock cycle. The system clock passes through the first voltage value range (V B1 ) in at least two half clock cycles (T 1H , T 2H ) during the corresponding other half clock cycle.

[0184] In another advantageous embodiment of the present invention, the two-wire data bus according to the present invention, which is arranged between a first sub-device, namely the bus master (BM), and at least two sub-devices, namely the bus nodes (BS1, BS2, BS3), is characterized in that at least three logical states are used when data is sent bidirectionally on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (b1, b2, b3) under consideration via the bus master (BM) and the bus nodes (BS1, BS2, BS3).

[0185] In another suitable embodiment of the invention, the data bus between the first sub-device, i.e. the bus master (BM), and the at least two further sub-devices, i.e. the bus nodes (BS1, BS2, BS3), is characterized in that a first logic state of the at least three logic states on the two-wire data bus (b1b2b3) or on at least the considered two-wire data bus segment (b1, b2, b3) is generated by a first dominant switch (T1a, T1b) of the bus master (BM), which forces the value of the potential difference between the first single-wire data bus (b1a, b2a, b3a) and the second single-wire data bus (b1b, b2b, b3b) or at least the value of the potential difference between the considered first single-wire data bus segment (bna) and the considered second single-wire data bus segment (bnb) to a first voltage value range (V B1 )middle.

[0186] In a suitable embodiment, the data bus according to the invention between a first subdevice, namely the bus master (BM), and at least two further subdevices, namely the bus nodes (BS1, BS2, BS3), is characterized in that a second of the at least three logic states on the two-wire data bus (b1b2b3) or on at least the considered two-wire data bus segment (b1, b2, b3) is generated by switching on a first switchable current source (T2a, T2b) in the bus master (BM) and / or by switching on a second switchable current source (T3a, T3b) in the bus nodes (BS1, BS2, BS3), see Figure 8 and Fig. 9 .

[0187] In another advantageous embodiment of the invention, the data bus according to the invention, which is arranged between a first sub-device, namely a bus master (BM), and at least two sub-devices, namely bus nodes (BS1, BS2, BS3), is characterized in that switching on a first switchable current source (T2a, T2b) in the bus master (BM) and / or switching on a second switchable current source (T3a, T3b) in one of the bus nodes (BS1, BS2, BS3) forces the value of the potential difference on the two-wire data bus (b1b2b3) or at least on the considered two-wire data bus segment (bn), that is, the value of the differential signal level (TOW), to a third voltage value range (V B3 ), provided that a first dominant switch (T1a, T1b) of the bus master (BM) is not turned on, said first dominant switch, when turned on, forcing the value of the differential signal level (TOW) on the two-wire data bus or at least the two-wire data bus segment (bn) under consideration to a first voltage value range and overwriting the switchable current source (T2a, T2b, T3a, T3b).

[0188] In a further advantageous embodiment, the data bus according to the invention arranged between a first slave, the bus master (BM), and at least two further slaves, the bus nodes (BS1, BS2, BS3), is characterized in that a third of the at least three logic states on the two-wire data bus (b1, b2, b3) or on at least the considered two-wire data bus segment (bn) is switched by a differential pull circuit (R 1a , R 2a ; R 1b , R 2b ) is generated by a differential pull circuit (R 1a , R 1b , R 2a , R 2b ) brings the value of the differential signal level (TOW) on the two-wire data bus or on at least the investigated two-wire data bus segment (bn) to a second voltage value range (V B2 ) in the second differential voltage level (V M ).

[0189] In another advantageous embodiment of the present invention, the data bus according to the present invention arranged between a first sub-device, namely the bus master (BM), and at least two further sub-devices, namely the bus nodes (BS1, BS2, BS3), is characterized in that one or more conversions from a second or third logic state on the two-wire data bus (b1, b2, b3) or at least on the considered two-wire data bus segment (bn) on the one hand to a first logic state on the two-wire data bus (b1, b2, b3) or at least on the considered two-wire data bus segment (bn) on the other hand and one or more conversions in reverse are used for transmitting the clock signal.

[0190] In another advantageous embodiment of the present invention, the data bus according to the present invention, which is arranged between a first sub-device, namely a bus master (BM), and at least two other sub-devices, namely bus nodes (BS1, BS2, BS3), is characterized in that one or more conversions from a second logical state on the two-wire data bus (b1, b2, b3) or at least on the two-wire data bus segment (bn) under consideration via a first logical state on the two-wire data bus (b1b2b3) to a third logical state on the two-wire data bus (b1, b2, b3) or at least on the two-wire data bus segment (bn) under consideration, and one or more conversions in the reverse direction are used to transmit data signals from the bus master (BM) to the bus node under consideration and / or from the bus node under consideration to the bus master (BM).

[0191] In a further advantageous embodiment of the invention, the data bus according to the invention arranged between a first sub-device, the bus master (BM), and at least two further sub-devices, the bus nodes (BS1, BS2, BS3), is characterized in that the data are transmitted in at least two half-clock cycles (T 1H , T 2H ) half clock cycle, and the system clock is transmitted in at least two half clock cycles (T 1H , T 2H ), wherein a time slot packet has a length of one system basic clock cycle (T), which has at least 3×2 half clock cycles (T 1H , T 2H ).

[0192] The data bus according to the invention extends between a first slave, namely a bus master (BM), and at least two further slaves, namely bus nodes (BS1, BS2, BS3), wherein the data bus has a two-wire data bus (b1b2b3) with two data conductors, which is divided into a plurality of paired single-wire data bus sections (b1a, b1b; b2a, b2b; b3a, b3b) by bus nodes (BS1, BS2, BS3) and ends by the last bus node (BS3) of the bus nodes (BS1, BS2, BS3), namely the end bus node (BS3). In this case, the data bus can also be characterized as follows: the bus master (BM) has a master two-wire data bus interface (OWM). The master two-wire data bus interface (OWM) further comprises a first differential switchable voltage source (T1a, T1b) having a first internal resistance, which can connect the two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) (hereinafter referred to as the two-wire data bus segment (bn) under consideration) to a pair of power supply conductors (V bat, GND). The master two-wire data bus interface (OWM) comprises a second switchable differential voltage source (T2a, T2b) with a second internal resistance, which voltage source can bring at least the considered two-wire data bus section (bn) or the two-wire data bus (b1b2b3) of the two-wire data bus (b1b2b3) to a second potential difference according to a numerical value, wherein the second switchable differential voltage source can also be a corresponding current source with a second internal resistance and a corresponding current value. At least one of the bus nodes (BS1, BS2, BS3), hereinafter referred to as the considered bus node (BSn), has a two-wire data bus interface (OWSn), hereinafter referred to as the considered two-wire data bus interface (OWSn). The considered two-wire data bus interface (OWSn) of at least the considered bus node (BSn) comprises a third switchable differential voltage source (T3a, T3b) with a third internal resistance, which voltage source can bring at least the considered two-wire data bus section (bn) of the two-wire data bus (b1b2b3) or the two-wire data bus (b1b2b3) to a third potential difference according to a value, which third potential difference is preferably equal to the second potential difference according to a value, and wherein the third switchable differential voltage source can also be a current source with a third corresponding internal resistance and an associated current value. The conversion of the value of the actual voltage source into the value of the actual current source is familiar to a person skilled in the art. At least the two-wire data bus (b1b2b3) or the considered two-wire data bus section (bn) of the two-wire data bus (b1b2b3) is switched via a fourth differential voltage source with a fourth internal resistance, in particular at a third differential voltage value level (V I0 ) and the first differential voltage level (-V IO ) between the differential signal level (TOW) on the differential pull circuit (R 1a , R 2a ; R 1b , R 2b ) and maintain the second differential voltage value level (V M ), the third differential voltage value level is preferably equal to the fourth and fifth voltage values ​​(V IO1 , V IO2 In this case, at the intermediate second differential voltage level (V M ) is at the first differential voltage level (-V IO ) and the fourth voltage value (V IO1 ) and / or at a first differential voltage value level (-V IO ) and the fifth voltage value (V IO2 ). In this case, the first internal resistance is smaller than the other internal resistances. The fourth internal resistance is larger than the other internal resistances.

[0193] Accordingly, the method according to the invention can be expressed as a method for operating a data bus between a first sub-device, namely a bus master (BM), and at least two further sub-devices, namely bus nodes (BS1, BS2, BS3). In this case, the data bus has a two-wire data bus (b1b2b3), which is divided into at least two two-wire data bus sections (b1, b2, b3) by at least two bus nodes (BS1, BS2, BS3) and ends by at least one bus node (BS3) of the bus nodes (BS1, BS2, BS3), namely an end bus node (BS3). The method comprises the steps of: as a first step, bidirectionally transmitting data between a bus master (BM) and at least one bus node (BS1, BS2, BS3) (hereinafter referred to as the bus node (BSn) under consideration) via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of the two-wire data bus segment (b1, b2, b3) (hereinafter referred to as the two-wire data bus segment under consideration); as a second step, simultaneously transmitting a clock signal from the bus master (BM) to at least the bus node (BSn) under consideration via the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (b1, b2, b3) in preferably three consecutive time slots of a time slot grouping using one system clock cycle (T / 3), wherein the time slot is divided into at least a first half clock cycle (T 1H ) and the second half clock cycle (T 2H ); as a third step, a third device, in particular a third comparator (cmp3), of the bus node (BS1, BS2, BS3) under consideration compares the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (b1, b2, b3) in the form of a differential signal voltage as a differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration with a third threshold value, in particular a third threshold signal (V 2H ) is compared with a third threshold value (V ) of the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration; as a fourth step, a second device of the bus node (BS1, BS2, BS3) under consideration, in particular a second comparator (cmp2) compares the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration in the form of a differential signal voltage on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration with a signal different from the third threshold value (V 2H )'s second threshold (V 2L ), especially the second threshold signal (V 2L ) is compared with the second threshold value. In this case, the third and second threshold values ​​(V 2L , V 2H) limits the three signal voltage value ranges (V B1 , V B2 , V B3 In this case, the middle voltage value range is used as the second voltage value range (V B2 ) is from the first voltage value range (V B1 ) is limited upward or downward. However, in this case, the second voltage value range (V B2 ) downward or upward with the first voltage value range (V B1 ) in the opposite case, through the third voltage value range (V B3 ) restrictions; as a fifth step, data are transmitted on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (bn) under consideration in time slot groups, each time slot group having a duration of a system basic clock cycle (T) comprising at least three consecutive time slots (TIN0, TIN1, TDOz), wherein the order of the time slots (TIN0, TIN1, TDOz) within the sequence of at least three time slots (TIN0, TIN1, TDOz) can be selected in a system-specific manner; as a sixth step, at least one control data and / or first data are transmitted from the bus master (BM) to the bus node (BS1, BS2, BS3) under consideration in the first time slot (TIN0) and in the second time slot (TIN1), wherein the control data and the first data can in particular be transmitted in accordance with IEEE 1149 standard, and wherein the bus node (BS1, BS2, BS3) under consideration receives the control data and the first data; in this case, at least two half-clock cycles (T of the system basic clock cycle (T) of the time slot in question 1H , T 2H ), a second voltage value range (V B2 ) and the third voltage value range (V B3 ), in the first and / or second time slot (TIN0, TIN1) of at least three consecutive time slots (TIN0, TIN1, TDOz), control data and / or first data are transmitted from the bus master (BM) to the bus node (BS1, BS2, BS3) under consideration, wherein the bus node (BS1, BS2, BS3) under consideration receives the control data and the first data, and wherein the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (b1, b2, b3) under consideration is within a second voltage value range (V B2 ) and on the other hand a third voltage value range (V B3 ) through the first voltage range (V B1) and one or more conversions in the opposite direction to perform the data transmission;

[0194] As a seventh step, during at least two half clock cycles (T 1H , T 2H ), in a half clock cycle of ), a second voltage value range (V B2 ) and the third voltage value range (V B3 ), in a third time slot (TDOz) of at least three consecutive time slots (TIN0, TIN1, TDOz), transmitting second data from the bus node under consideration (BS1, BS2, BS3) to the bus master (BM), wherein the bus master (BM) receives the second data;

[0195] As an eighth step, during at least two half clock cycles (T 1H , T 2H ), typically in each of at least three time slots (TIN0, TIN1, TDOz) a system clock is transmitted in the other half of the clock cycle of the at least three time slots (TIN0, TIN1, TDOz), wherein no data is sent in this half clock cycle, and wherein the transmission of the system clock in the time slot in question is achieved by the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) in a first voltage value range (V B1 ) and on the other hand the second voltage value range (V B2 ) and / or a third voltage value range (V B3 ) or by one or more conversions in the opposite direction.

[0196] A variant of the method is characterized in that three logic states are used when bidirectionally transmitting data on a two-wire data bus (b1b2b3) or at least the two-wire data bus segment (b1, b2, b3) by a bus master (BM) and the bus node under consideration, wherein a voltage value range (V) of the value of the differential signal level (TOW) of the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration is assigned to each logic state. B1 , V B2 , V B3 ), typically just one voltage value range.

[0197] Another variant of the method is characterized in that a dominant differential switch (T1a, T1b) of a bus master (BM) is temporarily closed, said dominant differential switch also being a MOS transistor or other semiconductor switch for temporarily generating a first logic state of three logic states on the two-wire data bus (b1b2b3) or at least the considered two-wire data bus segment (bn), wherein the value of the differential signal level (TOW) of the two-wire data bus (b1, b2, b3) or at least the considered two-wire data bus segment (bn) is forced to a first voltage value range (V B1 )middle.

[0198] Another variant of the method is characterized in that a first switchable current source (T2a, T2b) in the bus master (BM) and / or a second switchable current source (T3a, T3b) in the bus node under consideration is temporarily switched on to generate a third of three logic states on a two-wire data bus (b1b2b3) or at least on the two-wire data bus segment under consideration (b1, b2, b3).

[0199] Another variant of the method is characterized in that a first switchable current source (I1, S 1H ) and / or switching on a second switchable current source (I2, S 2H ) forces the potential on the single-wire data bus (b1, b2, b3) or at least the single-wire data bus section (b1, b2, b3) under consideration to a third potential, provided that the first dominant switch (S 1L ) is not turned on, the first dominant switch has the potential of the single-line data bus.

[0200] Another variant of the method is characterized in that a second logic state of at least three logic states is generated on the two-wire data bus (b1, b2, b3) or on at least the considered two-wire data bus section (bn) when no other logic state is present on the two-wire data bus (b1, b2, b3) or on at least the considered two-wire data bus section (bn), in particular by a differential pull circuit (R 1a , R 2a ; R 1b , R 2b ) is generated, in particular by a differential pull circuit (R 1a , R 2a ; R 1b , R 2b ) maintains the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on at least the investigated two-wire data bus segment (bn) within a second voltage value range (V B2) in the middle of the second differential voltage level (V M ).

[0201] Another variant of the method is characterized in that the system clock is transmitted by switching from a second or third logic state on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (bn) under consideration to a first logic state on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (bn) under consideration and vice versa.

[0202] Another variant of the method is characterized in that data is transmitted by converting from a second logic state on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (bn) under consideration via a first logic state on the two-wire data bus (b1b2b3) to a third logic state on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (bn) under consideration, and vice versa.

[0203] Another variant of the method is characterized in that the first or second data or control data or other data are transmitted in at least two half-clock cycles (T 1H , T 2H ), and the system clock is transmitted in at least two half-clock cycles (T IN0 , T IN1 , T DOz ) of the time slot of the at least three consecutive time slots (T IN0 , T IN1 , T DOz ). 1H , T 2H ), wherein a time slot packet has a length of one system basic clock cycle (T), which has at least 3×2 half clock cycles (T 1H , T 2H ).

[0204] Another aspect of the proposal according to the invention relates to a method for operating a two-wire data bus (b1b2b3) between a first slave, a bus master (BM), and at least two further slaves, bus nodes (BS1, BS2, BS3). The two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by at least two bus nodes (BS1, BS2) and terminated by at least one of the bus nodes (BS1, BS2, BS3), the end bus node (BS3). The method comprises, as a first step, temporarily connecting a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of a single-wire data bus segment, hereinafter referred to as the two-wire data bus segment under consideration, to a first switchable differential voltage source (T1a, T1b) of a bus master (BM), which voltage source has a first internal resistance and, when switched on, causes a first differential signal level (TOW) according to a numerical value on the two-wire data bus (b1b2b3). As a second step, the method comprises temporarily connecting the two-wire data bus (b1b2b3) or the two-wire data bus segment under consideration to a second switchable differential voltage source (T2a, T2b) of the bus master (BM), which voltage source has a second internal resistance and, when switched on, causes a second differential signal level (TOW) according to a numerical value on the two-wire data bus (b1b2b3). In this case, the second switchable differential voltage source can also be implemented as a differential current source (T2a, T2b) with a corresponding second internal resistance and a corresponding current value. As mentioned here, the conversion between the values ​​of the real current source and the voltage source is familiar to the person skilled in the art. As a third step, the method includes temporarily connecting the two-wire data bus (b1b2b3) or the two-wire data bus section under consideration (b1, b2, b3) to a third switchable differential voltage source (T3a, T3b) of the bus node (BS1, BS2, BS3) (hereinafter referred to as the bus node under consideration (BSn)). When the third switchable differential voltage source is switched on, it causes a third differential signal level (TOW) on the two-wire data bus (b1b2b3) according to the value. Preferably, the third differential signal level (TOW) is equal to the second differential signal level (TOW). The third switchable voltage source (T3a, T3b) has a third internal resistance in this case. The third switchable voltage source can also be considered as a current source (T3a, T3b) having a third internal resistance and a corresponding current value. As mentioned here, the conversion between the values ​​of real current sources and voltage sources is familiar to a person skilled in the art. As a fourth step, the method comprises a fourth differential voltage source having a fourth internal resistance (R0), in particular according to a value at the third differential voltage value level (V IO ) and the first differential voltage level (-V IO) between the differential pull circuit (R 1a , R 2a ; R 1b , R 2b ) temporarily maintains the value of the signal level (TOW) on the two-wire data bus (b1b2b3) or at least on the two-wire data bus segment (bn) under consideration at a second intermediate differential voltage value level (V M ), the third differential voltage value level is preferably equal to the fourth and fifth voltage values ​​(V IO1 , V IO2 In this case, the intermediate second differential voltage level (V M ) is at the first differential voltage level (-V IO ) and the fourth voltage value (V IO1 ) and / or at a first differential voltage value level (-V IO ) and the fifth voltage value (V IO2 ). In this case, the first internal resistance is smaller than the other internal resistances. The fourth internal resistance is larger than the other internal resistances.

[0205] The invention also includes a method for initializing such a two-wire data bus as described here between a first sub-device, i.e. a bus master (BM), and at least two further sub-devices, i.e. bus nodes (BS1, BS2, BS3). In this case, the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by at least two bus nodes (BS1, BS2, BS3). The two-wire data bus is terminated by at least one bus node (BS3), i.e. an end bus node (BS3), of the bus nodes (BS1, BS2, BS3). As a first step, the method comprises determining a new bus node address by the bus master (BM). This can be done, for example, by simply incrementing a value inside the bus master (BM). Next, as a second step, the bus node address is stored by the bus master (BM) in a bus node address register (BKADRn) of the bus node (BS1, BS2, BS3), i.e. the bus node (BSn) under consideration. In this case, the bus master (BM) and the bus node (BSn) under consideration are connected to one another in terms of data via one or more two-wire data bus segments (b1, b2, b3). The bus node address register (BKADRn) of the bus node (BSn) in question is preferably implemented as an independent data register (DR) in the bus node (BSn) in question. However, it can also be implemented as part of a data or instruction register (IRn) of the JTAG interface of the bus node (BSn) in question. However, programming would then become more complicated if necessary. As already mentioned, the JTAG interface of the bus node (BSn) in question is further characterized in the sense of the present invention in that the JTAG interface has a test controller (TAPCn) of the bus node (BSn) in question, which has a state diagram according to the IEEE 1149 standard or a substandard thereof, such as in combination with Figure 1As explained. Next, as a third step, after the bus address is given, one or more two-wire data bus segments (b1, b2, b3) that are already connected to the bus node (BSn) and the bus master (BM) are connected to one or more other two-wire data bus segments (b1, b2, b3) by closing the transmission gate (TGn) of the bus node (BSn) concerned. In order to prevent the previously given bus node address of the bus node (BSn) in the bus node address register (BKADRn) from being overwritten when the bus node address is given next time, the logic within the bus node (BSn) concerned always prevents such storage of the bus node address in the bus node address register (BKADRn) of the bus node (BSn) concerned as long as the transmission gate (TGN) of the bus node (BSn) concerned is closed. Therefore, writing to the bus node address register (BKADRn) of the bus node (BSn) concerned is only possible when the transmission gate (TGn) of the bus node (BSn) concerned is open.

[0206] As a further step, another embodiment of the method comprises storing a command for opening the transmission gate (TGn) of the bus node (BSn) in question in the instruction register (IRn) of the bus node (BSn) in question or in the transmission gate control register (TGCR) of the bus node (BSn) in question of the JTAG interface of the bus node (BSn). The bus master (BM) can thereby reinitialize the bus at any time. Preferably, the transmission gate control register (TGCRn) of the bus node (BSn) in question is used for this purpose and responds with the same command in the instruction register (IRn) of the bus node (BSn) in question.

[0207] As a further step, a further embodiment of the method comprises checking the correct addressing of at least one bus node (BSn) concerned, in particular a bypass register of the bus node (BSn) concerned, by cyclic writing and reading.

[0208] As a further step, another embodiment of the method comprises determining the number of correctly addressable bus nodes (BS1, BS2, BS3) by the bus master (BM). The number of correctly addressable bus nodes (BS1, BS2, BS3) is then compared with a setpoint number by the bus master (BM) or a connected system (e.g. a monitor counter) and at least one signal or measure is triggered as a function of the determined number.

[0209] A further embodiment of the method comprises, as a further first step, simultaneously transmitting the transmit address to all reachable bus nodes (BS1, BS2, BS3) by writing the transmit registers (SR) of all bus nodes (BS1, BS2, BS3) with the transmit address by the bus master (BM), wherein the respective transmit register (SRn) of the respective bus node (BSn) under consideration is a data register (DRn) or a part of a data register or a part of an instruction register (IRn) of the JTAG interface of the bus node (BSn) under consideration, and wherein the bus node address register (BKADRn) is not part of the relevant register of the bus node (BSn) under consideration. Subsequently, as a further second step, the transmit address in the respective transmit register (SR) is compared with the bus node address in the respective bus node address register (BKADR) by each bus node (BS1, BS2, BS3) by means of a predetermined comparison algorithm. Preferably, a check is made for equality. However, other algorithms are conceivable. Next, as a further third step, the sending capability for the respective bus node is activated at a time specified for this purpose if the comparison algorithm of the comparison previously performed by the respective bus node results in a sufficient match with the combination of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR) expected for a send permission, or as an alternative further third step, the sending capability for the respective bus node is deactivated if the comparison algorithm of the comparison previously performed by the respective bus node does not result in a sufficient match with the combination of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR) expected for a send permission. Preferably, only one bus node receives a send permission.

[0210] In order to ensure that only the bus node obtains the data for it, it is meaningful to control not only the sending of the bus node, but also the receiving of the bus node. For this purpose, a certain register of the bus node is prevented from being written by the bus master (BM) in whole or in part until the sending address in the sending register (SR) is consistent with the bus node address (BKADR). This prevention can involve the prevention of the shift register part of one or more data registers (DR), or the data transfer from the shift register part of one or more data registers (DR) or the instruction register to the shadow register of the bus node (BSn) involved. In this case, if necessary, it can also only involve a single or multiple bits by preventing the data transfer. It is necessary to always allow the transmission of a certain command, at least to allow the writing of the sending register (SR). Therefore, the transmission of commands or data to bus nodes that have not been called in advance starts as described above from the simultaneous transmission of the sending address to all reachable bus nodes by writing the sending registers (SR) of all bus nodes with the sending address by the bus master (BM). In this case, the corresponding transmit register (SR) of the bus node (BSn) in question is a data register or part of a data register or part of an instruction register (IRn) of the JTAG interface of the bus node (BSn) in question. As mentioned above, the bus address register (BKADRn) must not be part of the register in question. Next, the transmit address in the transmit register (SR) is compared with the bus node address in the bus node address register (BKADR) by each bus node again using the predetermined comparison algorithm. Finally, if the comparison algorithm of the comparison previously performed by the bus node (BSn) in question results in a sufficient match with the combination of the bus node address stored in its bus node address register (BKADR) and the transmit address stored in its transmit register (SRn) expected for a send permission, the receiving capability of the bus node (BSn) in question is activated for the content of the predetermined data register of the bus node (BSn) in question. In another case, the receiving capability of the corresponding bus node is deactivated for the contents of a predetermined data register of the corresponding bus node if a comparison algorithm of a comparison previously performed by the corresponding bus node does not result in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR).

[0211] As soon as writing to a part of the instruction register (IR) or a part of the data register is to be blocked or unlocked, a corresponding method begins by writing the send address by the bus master (BM) into the send register (SR) of all bus nodes (BS1, BS2, BS3) with the send address, and simultaneously transmitting the send address to all accessible bus nodes (BS1, BS2, BS3), wherein the respective send register (SR) of the respective bus node is a data register or a part of a data register or a part of the instruction register (IRn) of the JTAG interface of the bus node, and wherein the bus address register (BKADR) is not part of the register in question. Subsequently, the send address in the send register (SR) is compared with the bus node address in the bus node address register (BKADR) by each bus node again using the predetermined comparison algorithm. According to the result of this comparison, if the comparison algorithm of the comparison previously performed by the corresponding bus node results in a sufficient agreement with the combination of the bus node address stored in its bus node address register (BKADR) and the transmission address stored in its transmission register (SR) expected for the transmission permission, the receiving capability of the corresponding bus node is activated for the content of the predetermined content of the instruction register (IR) of the corresponding bus node to allow the predetermined instruction to be used for the instruction decoder (IRDC) of the JTAG interface of the corresponding bus node. In the other case, if the comparison algorithm of the comparison previously performed by the corresponding bus node does not result in a sufficient agreement with the combination of the bus node address stored in its bus node address register (BKADR) and the transmission address stored in its transmission register (SR) expected for the transmission permission, the receiving capability of the corresponding bus node is deactivated for the content of the predetermined content of the instruction register (IR) of the corresponding bus node to prohibit the predetermined instruction from being used for the instruction decoder (IRDC) of the JTAG interface of the corresponding bus node.

[0212] In another embodiment, the device comprises a data bus system with a two-wire data bus (b1b2b3) for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular light-emitting device bus nodes. In this embodiment, not only does the bus master (BM) itself act as a bus master, but each bus node can appear as a bus master relative to the subsequent bus nodes. This makes it possible, in particular, to transmit compressed data to a small number of special bus nodes, where they are decompressed and from there the decompressed data is transmitted to a small number of subsequent bus nodes. This significantly reduces the data load. As described above, the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3) evaluated thereby and ends by a bus node, namely the end bus node (BS3). Each bus node (BS1, BS2, BS3) except the first bus node (BS1) is connected to the preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via the preceding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3), while the first bus node (BS1) is connected to the bus master (BM) via the preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3). Each bus node (BS1, BS2, BS3) except the end bus node (BS3) is connected to the succeeding bus node (BS3, BS3) of the bus nodes (BS1, BS2, BS3) via the succeeding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3). In this case, however, the bus node no longer has a transmission gate, but a second JTAG interface, which is, however, a bus master interface (OWM1, OWM2, OWM3) (see Fig.14 ). As described above, the bus master (BM) has a master two-wire data bus interface (OWM) which is configured to bidirectionally send and receive data via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (b1, b2, b3) of a two-wire data bus segment (b1, b2, b3) (hereinafter referred to as the considered two-wire data bus segment (b1, b2, b3)) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels. As described above, the considered two-wire data bus segment (bn) comprises only two signal conductors.

[0213] As described above, the two-wire data bus interface (OWS1, OWS2, OWS3) of one of the bus nodes (BS1, BS2, BS3) (hereinafter referred to as the bus node (BSn) under consideration) of the bus nodes (BS1, BS2, BS3) is electrically connected to the two-wire data bus section (bn) under consideration. However, the transmission gate (TGn) of the bus node (BSn) under consideration is not provided. However, the transmission gate (TGn) of the bus node (BSn) under consideration can also be optionally added. The two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node (BSn) under consideration is again provided for receiving data from the two-wire data bus section (b1, b2, b3) under consideration by means of a data bus protocol using more than two differential physical voltage levels and / or current levels. The two-wire data bus interface (OWS1, OWS2, OWS3) of the bus node (BSn) under consideration is configured to transmit data via the two-wire data bus segment (b1, b2, b3) under consideration by means of a data bus protocol using more than two differential physical voltage levels and / or current levels. However, in contrast to the previously described configuration, the bus node (BS1, BS2, BS3) under consideration is now also equipped with a master two-wire data bus interface (OWMn) of the bus node (BSn) under consideration, to which the subsequent two-wire data bus segment (b(n+1)) is connected. The master two-wire data bus interface (OWMn) of the bus node (BSn) under consideration is configured to bidirectionally send data to and receive data from a subsequent bus node (BS(n+1)) via at least one of the subsequent two-wire data bus segments (b(n+1)) (hereinafter referred to as the subsequent two-wire data bus segment (b(n+1))) of the two-wire data bus segments (b1, b2, b3) by means of a data bus protocol using more than two differential physical voltage levels and / or current levels. The bus node (BSn) under consideration can thus appear as a bus master (BM) relative to the subsequent bus node (BS(n+1)). In this case, the bus node (BSn) under consideration can send data generated by itself to the subsequent bus node (BS(n+1)) and / or forward a send data stream, for example received from the bus master (BM), directly to the subsequent bus node (BS(n+1)) via its own bus master interface (OWMn).

[0214] In this case, the two-wire data bus interface (OWSn) of the bus node (BSn) under consideration works in combination with the master two-wire data bus interface (OWMn) of the bus node (BSn) under consideration, such as the corresponding transmission gate (TGn) of the bus node (BSn) under consideration.

[0215] In order to control the bus master interface (OWMn) of the bus node (BSn) under consideration, the bus node (BSn) under consideration preferably has a bus master control register (OWMCRn) and corresponding control lines (ctr1, ctr2, ctr3) (see Fig.14 and 15 ). The bus master control register (OWMCRn) of the bus node (BSn) under consideration is designed to control the master two-wire data bus interface (OWMn) of the bus node (BS) under consideration, wherein "control" may include complete disconnection of the interface. If the bus master interface (OWMn) in the bus node (BSn) under consideration is also equipped with a transmission gate (TGn), it is ensured by logic that:

[0216] a) Only the first three of the four possible states are allowed, i.e.

[0217] 1. The transmission gate (TGn) is open and the master bus interface (OWMn) is disconnected;

[0218] 2. The transmission gate (TGn) of the bus node (BSn) under consideration is closed and the master bus interface (OWMn) of the bus node (BSn) under consideration is open;

[0219] 3. The transmission gates (TG1, TG2, TG3) of the bus node (BSn) under consideration are opened and the master bus interface (OWMn) of the bus node (BSn) under consideration is switched on;

[0220] 4. The transmission gate (TGN) of the bus node (BSn) under consideration is closed and the master bus interface (OWMn) of the bus node (BSn) under consideration is switched on,

[0221] therefore

[0222] b) The state "transmission gate (TGn) of the bus node (BSn) under consideration closed and master bus interface (OWMn) of the bus node (BSn) under consideration switched on" is not possible in order to prevent bus conflicts.

[0223] In order to enable control, according to the present invention, the bus master (BM) can write to the bus master control register (OWMCRn) of the bus node (BSn) under consideration via the master two-wire data bus interface (OWM) and the two-wire data bus (b1b2b3) of the bus master (BM) or the two-wire data bus segment (b1, b2, b3) under consideration and the two-wire data bus interface (OWSn) of the bus node (BSn) under consideration and thereby control the state of the master two-wire data bus interface (OWMn) of the bus node (BSn) under consideration.

[0224] As described above, the invention also includes a matching housing (GH) for the bus node (BSn) under consideration. The bus node is provided for use in a data bus system for transmitting illumination data for luminous means (LM1, LM2, LM3) by means of a differential two-wire data bus (b1b2b3). In this case, the two-wire data bus (b1b2b3) is used to transmit data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular luminous means bus nodes. The two-wire data bus (b1b2b3) is again divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3). The two-wire data bus (b1b2b3) ends by a bus node, namely an end bus node (BS3). Preferably, each bus node (BS2, BS3) is connected to a preceding bus node (BS1, BS2, BS3) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus segment (b2, b3) of the two-wire data bus segments (b1, b2, b3). The first bus node (BS1) is connected to the bus master (BM) via a preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3). Preferably, each bus node (BS1, BS2, BS3) is connected to a succeeding bus node (BS2, BS3) of the bus nodes (BS1, BS2, BS3) via a succeeding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3) except for the ending bus node (BS3). The housing (GH) of a bus node (BSn) provided for use in such a data bus system preferably has at least two rows of terminals, namely a first row of terminals (LED1, LED2, GND, b1a, b1b, V bat ) and the second connection terminal row (LED3, LED4, GND, b2a, b2b, V bat At least two connection terminal rows are arranged opposite to each other on the housing (GH). Preferably, each connection terminal row comprises a connection terminal for a negative supply voltage, ie a second reference potential (GND) and a corresponding connection terminal for a positive supply potential (V bat ). In this case, if the connection terminal (GND) for the negative power supply voltage and the connection terminal for the second reference potential (GND) of the first connection terminal row are connected to the connection terminal (GND) for the negative power supply voltage and the connection terminal (GND) for the second reference potential of the second connection terminal row, and if the connection terminal for the positive power supply voltage (V bat ) and the second connection terminal for the positive power supply voltage (V bat), the connection for the negative supply potential and the connection for the positive supply potential are arranged in each connection terminal row in such a way that they can be connected without crossing. This has the advantage that in the case of a light-emitting device chain, the housings (GH) can be arranged continuously without through-hole contacts.

[0225] The two connections (b1a, b1b) of the first connection row for the preceding two-wire data bus section (bn) of the bus node (BSn) under consideration are arranged between a connection (GND) of the first connection row for a negative supply voltage and a connection for a second reference potential (GND) and a connection of the first connection row for a positive supply voltage (V bat ). As a result, the electromagnetic radiation of the two-wire data bus (b1b2b3) is minimized. The two connections (b2a, b2b) of the subsequent two-wire data bus section (b2) for the bus node in the second connection terminal row are arranged between the connection terminal for the negative supply voltage (GND) and the connection terminal for the second reference potential (GND) of the second connection terminal row and the connection terminal for the positive supply voltage (V bat ) between the connection terminals. This also minimizes the radiation of the two-wire data bus (b1b2b3).

[0226] The connections for supplying and / or controlling the luminous means (LED1, LED2, LED3, LED4) in their respective connection row are arranged such that the connection for the supply voltage in the respective connection row is located between two connections (b1a, b1b or b2a, b2b) for the associated two-wire data bus section (b1 or b2) and the connection for supplying and / or controlling the luminous means (LED1, LED2, LED3, LED4), wherein the current flowing through the luminous means (LED1, LED2, LED3, LED4) from these connections for supplying and / or controlling the luminous means (LED1, LED2, LED3, LED4) is in turn conducted via the supply voltage. This has the advantage that the luminous means (here the light-emitting diodes LED1, LED2, LED3, LED4) can be connected to the bus node without crossing.

[0227] A housing designed in this way is therefore suitable for minimizing parasitic electromagnetic radiation in cooperation with the bus system described here.

[0228] The proposed device also includes a light module having a housing (GH) for a bus node (BSn). The bus node (BSn) represents one of the above-mentioned bus nodes and is preferably implemented in the form of an integrated circuit. The light module is configured to be used in a data bus system for transmitting lighting data for light-emitting devices (LED1, LED2, LED3) by means of a differential two-wire data bus (b1b2b3). Preferably, the data bus is implemented differentially. The two-wire data bus (b1b2b3) is used in this case to transmit data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), here light-emitting device bus nodes. The two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by the bus nodes (BS1, BS2, BS3).

[0229] This makes it possible to automatically address the optical module. Various automatic addressing methods for users of serial bus systems are known from the prior art. As examples of automatic addressing methods from the prior art, the documents DE-B-10 256 631, DE-A-10 2014 003 066, EP-B-1 364 288 and EP-B-1 490 772 can be cited here.

[0230] A star structure is not suitable for automatic addressing. By means of the combination of the above-mentioned transmission gates and a dedicated bus master interface in the bus node, it is possible to switch between a linear structure and a star structure for automatic addressing during operation. This makes it possible to call up a very large number of bus nodes simultaneously via data commands during operation if necessary, without losing the advantages of automatic addressing.

[0231] Typically, each bus node (BS2, BS3) except the first bus node (BS1) is configured to be connected to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) or to a bus master (BM) via a preceding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3).

[0232] The housing (GH) of the bus node (BSn) has at least two rows of terminals, namely a first row of terminals (GND, b1a, b1b, V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ).

[0233] At least the at least two connection rows are arranged opposite each other on the housing (GH).

[0234] Each terminal row comprises a terminal (GND) for a negative supply voltage, ie, a second reference potential (GND), and a terminal (GND) for a positive supply potential (V bat ). If the connection terminal (GND) for the negative power supply voltage and the connection terminal for the second reference potential (GND) of the first connection terminal row are connected to the connection terminal (GND) for the negative power supply voltage and the connection terminal for the second reference potential (GND) of the second connection terminal row, respectively, and if the connection terminal for the positive power supply voltage (V bat ) and the second connection terminal for the positive power supply voltage (V bat ), the connection for the negative supply potential and the connection for the positive supply potential are arranged in each connection terminal row so that they can be connected without crossing. In the first connection terminal row, two connections (b1a, b1b) for the preceding two-wire data bus section (b1) of the bus node are arranged between the connection for the negative supply voltage (GND) and the connection for the second reference potential (GND) of the first connection terminal row and the connection for the positive supply voltage (V bat ). In the second terminal row, two terminals (b2a, b2b) for a subsequent two-wire data bus section (b2) of the bus node are arranged between the terminal for the negative supply voltage (GND) and the terminal for the second reference potential (GND) of the second terminal row and the terminal for the positive supply voltage (V bat ) between the connection ends.

[0235] At least one light emitting device (LED1, LED2, LED3) is arranged in a recess (ASP) of the housing. Such a housing offers the advantage that a large amount of data can be transmitted to the light emitting device with low parasitic radiation. Therefore, such a housing is particularly suitable for use in an imaging light module group. In this case, the light modules are arranged continuously in series.

[0236] In another embodiment of the housing, at least three light emitting devices (LEDL, LED2, LED3) are arranged in a recess (AS) of the housing. The at least three light emitting devices (LED1, LED2, LED3) preferably have different luminous colors perceived by humans, so that a color effect can be caused by adjusting different luminous intensities for different lighting devices.

[0237] The application of the above-mentioned device and the above-mentioned method now realizes a light module, which includes a housing (GH) for an integrated circuit as a bus node (BSn). The light module should be used in a multi-dimensional data bus system to transmit lighting data for light-emitting devices (LED1, LED2, LED3) by means of a differential two-wire data bus (b1b2b3). The bus structure proposed above allows automatic addressing to be performed even in the case of an array arrangement of light-emitting devices and broadcast messages to all light-emitting modules after initialization. The two-wire data bus (b1b2b3) is again configured to transmit data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3), in particular light-emitting bus nodes. The two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by bus nodes (BS1, BS2, BS3). However, these two-wire data bus sections no longer need to be arranged linearly in a row, but can be arranged in a chessboard shape. Initialization is only required at the beginning. Each bus node (BS2, BS3), except the first bus node (BS1), is now arranged to be connected to the preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) or to the bus master (BM) via the preceding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3). At least one bus node (BSn) can be connected to at least three two-wire data bus segments (b1, b2, b3). Branching of the data bus is thus possible. For this purpose, the bus node (BSn) concerned has two separate master two-wire data bus interfaces (OWMa, OWMb) and / or two transmission gates (TGa, TGb) in order to be able to control now two subsequent two-wire data bus segments. Another variant is a configuration with three separate master two-wire data bus interfaces (OWMa, OWMb, OWMc) and / or three transmission gates (TGa, TGb, TGc) in order to be able to control three subsequent two-wire data bus segments. However, this is not necessary. In principle, a configuration with two separate master two-wire data bus interfaces (OWMa, OWMb, OWMc) and / or two transmission gates (TGa, TGb, TGc) is sufficient to fill a two-dimensional surface with light modules. Therefore, the housing (GH) of the bus node (BSn) should have at least three rows of terminals, namely a first row of terminals (V bat , b1a, b1b), a second connection terminal row (GND, b2a, b2b) and a third connection terminal row (V bat, b3a, b3b), and optionally a fourth connection terminal row (GND, b4a, b4b). At least these at least three or four connection terminal rows on the housing (GH) are arranged at an angle of 90° to each other. In this case, two connection terminal rows are directly opposite each other. In this case, each of the three or four connection terminal rows has at least one adjacent connection terminal row, each connection terminal row being arranged at an angle of 90° to its adjacent connection terminal row. Each connection terminal row includes exactly one connection terminal row for the supply voltage (GND, V bat ). Each connection terminal row adjacent to another connection terminal row has a connection terminal for another power supply voltage, which is not a power supply voltage whose connection terminal is included by the adjacent connection terminal row. Such a connection terminal for the power supply voltage is the first connection terminal in the connection terminal row in the same counting direction in the clockwise or counterclockwise sense in all connection terminal rows. Each connection terminal row includes two connections of a two-wire data bus segment. The two connections of the one two-wire data bus segment are respectively adjacent to the connection terminal for the power supply voltage in the connection terminal row concerned. At least one light-emitting device (LED1, LED2, LED3) is arranged in a recess (AS) of a housing (GH) or on the housing (GH).

[0238] In a particular embodiment of the light-emitting module, a first connection terminal of a first power supply voltage is located in a first connection terminal row, and a second connection terminal of the first power supply voltage is located in a second connection terminal row. The first connection terminal row is arranged opposite the second connection terminal row. The first connection terminal is conductively connected to the opposite second connection terminal via a mounting bracket (English: Lead-Frame). As a result, the power supply wires can be laid without crossing.

[0239] It is particularly advantageous if the optical module is configured to utilize a power supply voltage connection (GND, V bat ) is constructed as a light module system with horizontal and vertical mirrored positions (see Fig.18 ). BRIEF DESCRIPTION OF THE DRAWINGS

[0240] The present invention will be explained in more detail below based on various embodiments and with reference to the accompanying drawings.

[0241] Figure 1 A state diagram of a test controller according to the IEEE 1149 standard is shown. Figure 1 Already explained in the introduction.

[0242] Figure 2 The basic signal waveform of the JTAG data protocol in the prior art is shown.

[0243] Figure 3The basic signal waveforms of a proposed data protocol are shown on a two-wire data bus (b1b2b3) or on connected two-wire data bus sections (b1, b2, b3) of a two-wire data bus (b1b2b3).

[0244] Figure 4 An exemplary level sequence of corresponding time slot groups of duration T, each consisting of three consecutive time slots, is shown.

[0245] Figure 5 The data extraction in the relevant bus node (BSn) for three consecutive time slots is shown by way of example.

[0246] Figure 6 An exemplary two-wire data bus system is schematically shown.

[0247] Figure 7 Details of an exemplary two-wire data bus system are shown: the connection of two consecutive bus nodes.

[0248] Figure 8 An exemplary implementation of a bus mastering two-wire data bus interface is schematically shown in simplified form.

[0249] Fig. 9 An exemplary implementation of a two-wire data bus interface of a bus node is schematically shown in simplified form.

[0250] Fig.10 A JTAG interface with an illumination register (ILR) according to the present invention is shown in simplified form.

[0251] Fig.11 A JTAG interface according to the present invention is shown in simplified form with an illumination register (ILR) and a separately accessible serial data input for the illumination register.

[0252] Fig.12 An exemplary two-wire data bus system having a separate serial data bus for lighting data is schematically illustrated.

[0253] Fig.13 A JTAG interface with an illumination register (ILR) and a transmission gate control register (TGCR) according to the present invention is shown in simplified form.

[0254] Fig.14 An exemplary two-wire data bus system is schematically shown, in which each bus node has a bus master interface for controlling a subsequent bus node.

[0255] Fig.15 A JTAG interface with an illumination register (ILR) and a bus master control register (OWMCR) according to the present invention is shown in simplified form.

[0256] Fig.16 A particularly advantageous arrangement of the connections for the device according to the invention is shown.

[0257] Fig.17 A particularly suitable housing (GH) for use with the data bus system described here is shown.

[0258] Fig.18 Two light modules for flat construction as panel lights are shown.

[0259] Fig.19 Shown according to Fig.18 The multiple light modules are used to construct a panel light.

[0260] Fig. 20 Shown according to Fig.17 A flat chain of six optical modules, each optical module having two two-wire bus master interfaces (OWM1a to OWM6a and OWM1b to OWM6b) and a two-wire data bus interface (OWS1 to OWS6).

[0261] Fig.21 A JTAG interface according to the invention is shown in simplified form with an illumination register (ILR), a bus node address register (BKADR) and a transmitter register (SR).

[0262] Figure 2

[0263] Figure 2 The basic signal waveform of the data protocol according to the present invention is shown on a two-wire data bus (b1b2b3) or on a connected two-wire bus segment (b1, b2, b3) of a two-wire data bus (b2b3b1). Figure 2 In the upper part of the diagram, signal waveforms of differential levels for a two-wire test bus similar to the IEEE 1149 standard are schematically drawn. The top signal (TDA) shows the data signal. The second signal (TCK) shows the associated system clock (TCK). Both signals are marked as prior art, even though they represent differential levels here and belong to the two-wire JTAG standard. Below this is an exemplary digital encoding. In this case, it is not yet shown whether the bus node (BSn) or bus master (BM) involved sends. Only the signal waveforms are drawn here.

[0264] Figure 3

[0265] Figure 3Suggested signal waveforms in the form of differential signal levels (TOW) on a two-wire data bus (b1b2b3) or on connected two-wire bus segments (b1, b2, b3) of a two-wire data bus (b2b3b1) are shown, combining clock and data.

[0266] Different differential voltage levels are plotted. The differential signal (TOW) has 3 differential voltage level values ​​when transmitted:

[0267] 1. The third differential voltage value level (V I0 ),

[0268] 2. The second differential voltage level in the middle (V M ),and

[0269] 3. The first differential voltage value level (-V I0 ).

[0270] To extract the system clock, the second threshold (V 2L ) is defined as a second threshold voltage value, which is located at the first differential voltage value level (-V IO ) and the second differential voltage level in the middle (V M )between.

[0271] In order to extract data, a first threshold voltage value of the bus master (BM) is defined, namely, the first threshold (V 1H ), and the third threshold voltage value of the bus nodes (BS1, BS2, BS3), namely the third threshold value (V 2H ), which are at a third differential voltage level (V I0 ) and the second differential voltage level in the middle (V M ) and should be roughly the same.

[0272] By means of a second threshold value (V 2L ) and the first differential voltage level (-V I0 ) to define and limit the first voltage value range (V B1 ).

[0273] On the one hand, the third threshold voltage value of the bus node (BS1, BS2, BS3), namely the third threshold value (V 2H ) or the first threshold (V 1H ) and on the other hand a second threshold voltage value (V 2L ) to define and limit the second voltage value range (V B2). On the one hand, the third threshold voltage value of the bus node (BS1, BS2, BS3), namely the third threshold value (V 2H ) or the first threshold voltage value (V 1H ) and on the other hand a third differential voltage value level (V I0 ) to define and limit the third voltage value range (V B3 ). The signals on the two-wire data bus (b1b2b3) or on the connected two-wire data bus segments (b1, b2, b3) of the two-wire data bus (b1b2b3) are divided in time into time slot groups having at least three time slots (TIN0, TIN1, TDOz). The time slot groups typically follow each other with a system basic clock cycle (T). The order of the time slots within a time slot group can be arbitrary for the system, but is preferably selected to be the same for all time slot groups. Each system basic clock cycle (T) is divided into at least three time slots, each time slot typically having two half clock cycles (T 1H , T 2H ), but preferably do not have to be of equal length.

[0274] At least two and a half clock cycles (T 1H , T 2H ) in the half clock cycle, the system clock is preferably transmitted separately.

[0275] In this case, within two half clock cycles (T 1H , T 2H ) within a half clock cycle of the two-wire data bus (b1b2b3) or the two-wire data bus segments (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is located in the first voltage value range (VB1). Thus, the first logic value of the system clock is transmitted. In this example, it is sufficient that the value of the signal level (TOW) on the two-wire data bus (b1b2b3) or the two-wire data bus segments (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is lower than the second voltage value threshold, i.e., the second threshold value (V 2L In many applications, the first voltage value range (V B1 ) can also be considered as open downwards.

[0276] During the at least two half clock cycles (T 1H , T 2H ), the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the two-wire data bus segments (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is within a second voltage value range (V B2) or the third voltage value range (V B3 ). Thus, a second logic value of the system clock is transmitted, which is different from the first logic value of the system clock. In this example, it is sufficient that the signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus segments (b1, b2, b3) of the two-wire data bus (b1b2b3) is located above the second threshold value (V 2L ) forms a second voltage value threshold. Upward by the power supply voltage (V bat ) or other upper limit (V I0 ) is limited to "the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the two-wire data bus segments (b1, b2, b3) of the connection of the two-wire data bus (b1b2b3) is within the second voltage value range (V B2 ), or the third voltage value range (V B3 ) is not important and is therefore not used in practice. Therefore, in many applications, the third voltage value range (V B3 ) can also be considered as upwardly open. Because for at least two and a half clock cycles (T 1H , T 2H ) in the other half clock cycle of the clock cycle, "the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the two-wire data bus segments (b1, b2, b3) connected to the two-wire data bus (b1b2b3) is within the third voltage value range (V B3 ), or the second voltage value range (V B2 ) is not important, so now it can be solved by running at least two and a half clock cycles (T 1H , T 2H ) in the other half of the clock cycle to distinguish the second voltage value range (V B2 ) and the third voltage value range (V B3 ) to transfer data.

[0277] At least two and a half clock cycles (T 1H , T 2H ), in the other half clock cycle of the two-line data bus (b1b2b3) or the two-line data bus segments (b1, b2, b3) of the two-line data bus (b1b2b3) connected thereto, when transmitting the first logic data value, the differential signal level (TOW) on the two-line data bus (b1b2b3) or the two-line data bus segments (b1, b2, b3) connected thereto is within the second voltage value range (V B2 ), and in the case of transmitting the second logic data value, it is in the third voltage value range (V B3 )middle.

[0278] To the right of the lower signal, exemplary logic states for three differential levels are drawn for greater clarity.

[0279] The upper differential levels correspond in this example to an exemplary logic value of 1 for the system clock (TCK) and an exemplary logic value of 1 for the data signal (TDA).

[0280] The intermediate differential level corresponds in this example to an exemplary logic value of 1 for the system clock (TCK) and an exemplary logic value of 0 for the data signal (TDA).

[0281] The lower differential level corresponds to an exemplary logic value of 0 for the system clock (TCK) which is 0 in this example.

[0282] Figure 4

[0283] Figure 4 An exemplary protocol sequence of three consecutive time slots (TINO, TIN1, TDOz) is shown. In other implementations of the invention, a time slot group may also include more than three time slots (TINO, TIN1, TDOz). In the first time slot (TINO), control data corresponding to a TMS signal of a standard boundary scan (IEEE 1149) is typically transmitted. This signal is typically based on Figure 1 The state diagram in controls the state of the finite state machine. In the second time slot (TIN1), data corresponding to the TDI signal of the standard boundary scan (IEEE 1149) is typically transmitted. In both time slots, the bus master (BM) transmits data to the bus node. If the bus node also transmits in parallel, the bus node will overwrite the bus master (BM) if the switchable current source (Tla, Tlb) of the bus node is disconnected. On the contrary, if the switchable current source (T3a, T3b) of the bus node is disconnected, the bus master (BM) can overwrite the bus node. The bus master (BM) can detect the overwriting of the bus master (BM) by the bus node in the following way, that is, by checking the logical content of the transmitted data (TMS_TDI) through the logic in the bus master (BM) to determine whether the transmitted data is consistent with the data received (TDo) in the half clock cycle involved, in which the system clock (TCK) does not close the dominant switch (T1a, T1b). In this asynchronous situation, the bus master (BM) permanently maintains the differential signal level (TOW) on the two-line data bus (b1b2b3) or on the connected two-line data bus segment (b1) of the two-line data bus (b1b2b3) within the third voltage value range (V B3), it can be resynchronized again if the state machine of the test controller (TAPC) of the bus node is designed appropriately. To this end, the state machine of the test controller (TAPC) of the bus node must be designed in such a way that the third voltage value range (V B3 ) leads to a reset in the form of a so-called "idle state" (TLR) as a wait state of the test controller (TAPC). This is the case in the state diagram of the JTAG controller according to the IEEE 1149 standard. The differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the two-wire data bus segment (b1) of the connection of the two-wire data bus (b1b2b3) is permanently maintained in a third voltage value range (V B3 ) can be performed by continuously switching on the switchable current source (T2a, T2b) of the bus master (BM) during the duration of the reset process.

[0284] Figure 5

[0285] Figure 5 An exemplary differential signal sequence according to the present invention is shown. The input is data based on two lines called "2-wire data", which is not differential. In this example, three consecutive time slot groups (n-1, n, n+1) are shown, each of which has three time slots (TIN0, TIN1, TDOz) as an example. It is of course conceivable that more than three time slots are used per time slot group. The meaning of the corresponding time slots within a time slot group depends only on the time position and does not change. When the first time slot (TIN0), the second time slot (TIN1) and the third time slot (TDOz) are mentioned in this specification, this is purely a term and does not involve the position within a time slot group. Preferably, the time positioning of each of the at least three time slots (TIN0, TIN1, TDOz) within the time slot group is always the same or at least predictable by an algorithm. In addition, the figure also shows the corresponding system clock (not a differential 2-wire clock). In the time slot group n-1, the bus node (BSn) involved is in the time slot TDO Z(N-1) Provides a logic 1 in time slot TDO in time slot group n Z(n) Provides logic 1 in time slot TDO in time slot group n+1 Z(n+1) Provides logic 0 in the TIN0 time slot. n-1 , TIN1 n-1 ,TIN0 n , TIN1 n ,TIN0 n+1 , TIN1 n+1The data transmitted in the two-wire data bus (b1b2b3 ... bn..bm) are not set by way of example in terms of their logical content and are therefore shaded. The signal denoted by "TOW" is intended to schematically show the differential potential curve of the differential signal level (TOW) on the two-wire data bus (b1b2b3 ... bn..bm) or on the n-th two-wire data bus segment (bn) of the connection of the two-wire data bus (b1b2b3 ... bn..bm). From the potential curve of the potential difference on the two-wire data bus segment (bn) in question, the third comparator (cmp3) of the bus node (BSn) in question generates by way of example the data (TMS_TDI) received by the bus node (BSn) in question. n The second comparator (cmp2) of the bus node (BSn) in question generates, by way of example, a clock signal (TCK) received via the bus node (BSn) in question from the differential potential profile of the differential signal level (TOW) on the two-wire data bus section (bn) in question. n ), which clock signal corresponds to the reconstructed system clock (TCK). In case the bus node (BSn) involved and the bus master (BM) are properly synchronized, the bus node (BSn) involved generates an internal system base clock (iTCK n ), the system basic clock is in the third time slot (TDO) of the system basic clock cycle (T) of the nth time slot group. z ) of the second half clock cycle (T 2H ) shows a pulse with a duration of half a clock period. With the rising edge of the system basic clock signal, the bus node (BSn) in question accepts the logical value of the data (TMS_TDIn) sent by the bus master (BM) in this example, which is detected with the aid of the falling edge of TCKn. With the clock signal (TCK n ) at the falling edge at the start of the next time slot packet, changes the value (TDO) to be sent by the bus node (BSn) involved in this example n ). However, if the bus node (BSn) involved is allowed to send, then TDO n In the third time slot (TDO) of the subsequent n+1th time slot group Z(n+1) ) becomes effective. It is clear to those skilled in the art that this control can be achieved not only by Figure 5 The system clock (TCK n )’s falling edge, and can also be achieved through the rising edge.

[0286] Figure 6

[0287] Figure 6An exemplary two-wire data bus (b1b2b3) is shown with three bus nodes (BS1, BS2, BS3), three two-wire data bus segments (b1, b2, b3) and one bus master (BM). The first two-wire data bus segment (b1) connects the bus master (BM) to the first bus node (BS1).

[0288] The second two-wire data bus section (b2) connects the second bus node (BS2) to the first bus node (BS1). The third two-wire data bus section (b3) connects the third bus node (BS3) to the second bus node (BS2).

[0289] The two-wire data bus is controlled by a bus master (BM) by means of a master two-wire data bus interface (OWM), to which the first two-wire data bus section (b1) is connected.

[0290] The first two-wire data bus interface (OWS1) is connected to the first two-wire data bus segment (b1). The first two-wire data bus interface receives data from the bus master via the first two-wire data bus segment (b1) and sends the data to the bus master. Internally, the first two-wire data bus interface provides a first reconstructed system clock (TCK1) with which the internal JTAG interface of the first bus node (BS1) is operated. In addition, the first two-wire data bus interface provides a first combined TMS-TDI signal (TMS_TDI1), which in this example includes a test mode signal (TMS) and a data input signal (TDI) in time multiplexing. The finite state machine of the test controller (TAPC) of the JTAG interface of the first bus node (BS1) is controlled by the test mode signal (TMS). The data of the TDI signal component is used to load the shift register of the JTAG interface of the first bus node (BS1). In turn, the JTAG interface returns data from the register of the JTAG interface of the first bus node (BS1) using a serial TDo output signal. By means of a first transmission gate (TG1), a first two-wire data bus segment (b1) can be connected to a subsequent second two-wire data bus segment (b2). To this end, the bus master (BM) writes to a transmission gate control register (TGCR) (not shown here) of the first bus node (BS1) via the two-wire data bus (b1) and sets a flag in the transmission gate control register (TGCR) of the first bus node (BS1), which sets or clears the first enable conductor (en1) in the first bus node (BS1). Depending on the first enable conductor (en1) of the first bus node (BS1), the first transmission gate (TG1) of the first bus node (BS1) opens and closes. Thus, by means of commands from the bus master (BM) to the first bus node (BS1), the two-wire data bus (b1b2b3) can be extended and shortened.

[0291] The second two-wire data bus interface (OWS2) is connected to the second two-wire data bus segment (b2). When the first bus node (BS1) closes its transmission gate (TG1), the second two-wire data bus interface receives data from the bus master (BM) via the second two-wire data bus segment (b2). The second two-wire data bus interface (OWS2) also sends these data to the bus master (BM). Internally, the second two-wire data bus interface provides a second reconstructed system clock (TCK2), which is used to operate the internal JTAG interface of the second bus node (BS2). The second two-wire data bus interface also provides a second combined TMS-TDI signal (TMS_TDI2), which in this example includes a test mode signal (TMS) and a data input signal (TDI) in a time-division multiplexed manner. The finite state machine of the test controller (TAPC) of the JTAG interface of the second bus node (BS2) is controlled by the test mode signal (TMS). The data of the TDI signal component is used to load the shift register of the JTAG interface of the second bus node (BS2). In turn, the JTAG interface of the second bus node (BS2) returns data from the register of the JTAG interface of the second bus node (BS2) using the serial TDo output signal. Through the second transmission gate (TG2), the second two-wire data bus segment (b2) can be connected to the third two-wire data bus segment (b3). To this end, the bus master (BM) writes to the transmission gate control register (TGCR) (not shown here) of the second bus node (BS2) via the first two-wire data bus segment (b1) and the second two-wire data bus segment (b2), and sets a flag in the transmission gate control register (TGCR) of the second bus node (BS2), which sets or clears the second enable wire (en2) of the second bus node (BS2). According to this second enable wire (en2) of the second bus node (BS2), the second transmission gate (TG2) of the second bus node (BS2) is opened and closed. Therefore, with the help of commands from the bus master (BM), the two-wire data bus (b1b2b3) can be further extended and shortened.

[0292] The third two-wire data bus interface (OWS3) is connected to the third two-wire data bus segment (b3). When the first bus node (BS1) closes its transmission gate (TG1) and when the second bus node (BS2) likewise closes its second transmission gate (TG2), the third two-wire data bus interface receives data from the bus master (BM) via the third two-wire data bus segment (b3). The third two-wire data bus interface (OWS3) also sends these data to the bus master (BM). Internally, the third two-wire data bus interface provides a third reconstructed system clock (TCK3) with which the internal JTAG interface of the third bus node (BS2) is operated. The third two-wire data bus interface also provides a third combined TMS-TDI signal (TMS_TDI3), which in this example includes in time division multiplexed form a data input signal (TDI) and a test mode signal (TMS) for the JTAG interface of the third bus node (BS3). The finite state machine (finite state machine) of the test controller (TAPC) of the JTAG interface of the third bus node (BS3) is controlled by the test mode signal (TMS). The data of the TDI signal component is used to load the shift register of the JTAG interface of the third bus node (BS3). In turn, the JTAG interface of the third bus node (BS3) returns the data from the register of the JTAG interface of the third bus node (BS3) by means of the serial TDo output signal. Through the third transmission gate (TG3) of the third bus node (BS3), the third two-wire data bus segment (b3) can be connected to another third two-wire data bus segment (bn). However, here the third bus node should exemplarily end the two-wire data bus (b1b2b3).

[0293] Each bus node (BS1, BS2, BS3) is connected to a group of lighting means (LM1, LM2, LM3) which are controlled by the respective bus node (BS1, BS2, BS3). Of course, other electrical energy consumers are conceivable.

[0294] Figure 7

[0295] Figure 7 Corresponding to the subsequent Fig. 9 The two right halves of the two bus nodes form a data bus interface arranged side by side. n ) is connected to the nth bus node (BSn). This nth bus node (BSn) can use its transmission gate (TGn) to connect the previous nth two-wire data bus segment (b n ) and the subsequent n+1th two-wire data bus segment (b (n+1)) connection. As long as the transmission gate (TGn) of the nth bus node (BSn) is open, the differential switch (not shown) connects the n+1th two-wire data bus segment (b (n+1) ) and thus all subsequent two-wire data bus segments (b (n+1) , where i>n+1) - if present or switched on by a transmission gate - is preferably set to a defined differential potential difference, thereby preventing unintended data transmission.

[0296] The n+1th bus node (BS (n+1) ) can be used with the help of its transmission gate (TG (n+1) ) again in the previous n+1th two-wire data bus segment (b (n+1) ) and the n+2th two-wire data bus segment (b (n+2) ) connection. As long as the n+1th bus node (BS (n+1) ) of the transmission gate (TG (n+1) ) is open, the differential switch (not shown) will switch the n+2nd two-wire data bus segment (b (n+2) ) and thus all subsequent two-wire data bus segments (b (n+3) ) - if present or switched on by a transmission gate - is placed at a defined differential potential difference, thus preventing unintended data transmission.

[0297] Figure 8

[0298] Figure 8 An implementation of the invention for a master two-wire data bus interface (OWM) is shown.

[0299] exist Figure 7 and Figure 8 1 shows the most important parts of an interface for implementing a protocol for a first two-wire data bus section (b1) of a connection, here exemplified, of a single-wire data bus or a two-wire data bus (b1b2b3) between a bus master and the bus node (BSn) in question. As reference potential for the signals on the two-wire data bus (b1b2b3) and the first two-wire data bus section (b1) of the connection of the two-wire data bus (b1b2b3), a second reference potential (GND) of a reference potential conductor (GND) is used here, which is connected to ground, for example.

[0300] By

[0301] a lower resistor (R2a) between a first single-wire data bus section (b1a) of the connection of the first single-wire data bus (b1a) and thus the first single-wire data bus (b1a, b2a, b3a) of the two-wire data bus (b1b2b3) and a reference potential conductor (GND) having a second reference potential (GND), and

[0302] a further lower resistor (R2b) between the second single-wire data bus (b1b, b2b, b3b) and the second single-wire data bus section (b1b) of the connection of the second single-wire data bus (b1b, b2b, b3b) of the two-wire data bus (b1b2b3) and the reference potential conductor (GND) having the second reference potential (GND), and

[0303] a first single-wire data bus (b1a) and thus a first single-wire data bus section (b1a) of the connection of the first single-wire data bus (b1a, b2a, b3a) of the two-wire data bus (b1b2b3) with a reference potential (V IO ) supply voltage (V bat ), and

[0304] a second single-wire data bus (b1b, b2b, b3b) and thus a second single-wire data bus section (b1b) of the connection of the second single-wire data bus (b1b, b2b, b3b) of the two-wire data bus (b1b2b3) to a reference potential (V IO ) supply voltage (V bat ) between the other upper resistor (R1b)

[0305] The differential voltage divider is formed such that the two-wire data bus (b1b2b3) in the form of the first two-wire data bus section (b1) connected is initially held at two potentials (-V I0 , V I0 ) between the second differential voltage level (V M ). On the host side, the system basic clock cycle (T) of the system basic clock is always three time slots, preferably at least two half clock cycles (T) per time slot. 1H , T 2H ). The dominant switch (T1a, T1b) is closed within one and a half clock cycle of the system reference clock cycle (T). This forces a maximum differential signal level (TOW) on the two-wire data bus (b1b2b3). Since the internal resistance of the dominant switch (T1a, T1b) is preferably smaller than the internal resistance of the differential voltage divider consisting of two upper resistors (R1a, R1b) and two lower resistors (R2a, R2b), the dominant switch (T1a, T1b) is closed within one and a half clock cycle of the system reference clock cycle (T).1H , T 2H ) during the half clock cycle involved in the step 200, by closing the dominant switch, the differential voltage level as the differential signal level (TOW) on the two-wire data bus (b1b2b3) is changed from the second voltage value range (V B2 ) in the middle of the second differential voltage value level (V M ) is at least pulled to a first voltage value range (V B1 ) in the first differential voltage level (-V IO ). The dominant switches (Tla, Tlb) are in this case controlled by the system clock (TCK) on the host side. If these dominant switches (T1a, T1b) are not closed, data can be transmitted in typically three time slots (TIN0, TIN1, TDOz) of the system reference clock cycle (T 1H , T 2H ) is transmitted bidirectionally in the other half of the clock cycle. For this reason, on the bus master side, if the transmission conductor (TMS_TDI) from the inside of the bus master (BM) is activated, the connected current source (T2a, T2b) feeds current into the two-wire data bus (b1b2b3). For this reason, the transmission conductor (TMS_TDI) from the inside of the bus master (BM) closes the switch (T2a, T2b) of the controllable current source. Therefore, it is preferably a transistor (specifically a MOS transistor), which operates as a current source in the on state. Therefore, the current mirror circuit is very suitable for its control. The transistor current source constructed in this way of the controllable differential current source (T2a, T2b) provides current to the two-wire data bus (b1b2b3). Preferably, the current is greater than the value of the current that can be drawn by the differential pull circuit composed of the upper resistor (R1a, R1b) and the lower resistor (R2a, R2b). In this case, therefore, the differential signal level (TOW) is in the form of a potential difference on the two-wire data bus (b1b2b3) or at least on the first two-wire data bus section (b1) of the connection of the two-wire data bus (b1b2b3) in the form of a potential difference from the second voltage value range (V B2 ) in the middle second differential voltage level (V M ) migrates to the third voltage value range (V B3 ) for the bus master (BM) switchable differential current source (T2a, T2b) supply voltage (V IO1). However, if the dominant switch (T1a, T1b) is closed, they will override the influence of the switchable differential current source (T2a, T2b) of the bus master (BM) and the pull-down circuit consisting of the upper resistor (R1a, R1b) and the lower resistor (R2a, R2b). In the case of a suitable design of the dominant switch (T1a, T1b), they cannot determine the value of the signal level (TOW) on the two-wire data bus (b1b2b3) or on the first two-wire data bus section (b1) of at least an exemplary connection of the two-wire data bus (b1b2b3) relative to the dominant switch (T1a, T1b).

[0306] Similarly, a second switchable current source operates on the bus node side, see Fig. 9 For this purpose, on the bus node side, if the send line (TDO n ) is active, the connected current sources (T3a, T3b) feed current into the two-wire data bus (b1b2b3) or the connected two-wire data bus segments (b1, b2, b3) of the two-wire data bus (b1b2b3). For this purpose, the transmission line (TDO) from within the bus node (BSn) under consideration is n ) closes the switch (T3a, T3b) of the controllable current source. Figure 8 The third transistor (T3a) and the further third transistor (T3b) shown in are operated as switchable current sources. Thus, the current source of the controllable current source (T3a, T3b) provides a current into the two-wire data bus (b1b2b3) or into the connected two-wire data bus segment (bn) of the single-wire data bus. Preferably, this current is again greater than the current that can be drawn by the pull-down circuit consisting of the upper resistor (R1a, R1b) and the lower resistor (R2a, R2b). Therefore, in this case, the value of the differential signal level (TOW) of the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (bn) ranges from the second voltage value range (V B2 ) in the middle second differential voltage level (V M ) migrates to the third voltage value range (V B3 ) for the supply voltage (V IO2). However, if the dominant switch (Tla, Tlb) in the bus master (BM) is closed, they again override the influence of the switchable current source (T3a, T3b) and the differential pull circuit (R1a, R1b, R2a, R2b) of the bus node (BSn) under consideration. In the case of a suitable design of the dominant switch (Tla, Tlb) the switchable differential current source and the differential pull circuit cannot determine the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on the connected two-wire data bus segment (b1) of the two-wire data bus (b1b2b3) relative to the dominant switch (Tla, Tlb) of the bus master (BM). Even if the switchable current sources (T2a, T2b) of the bus master (BM) are also switched on, they continue to determine the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (bn) of the two-wire data bus (b1b2b3) if the dominant switches (Tla, Tlb) of the bus master (BM) are suitably designed.

[0307] On the bus node side, a third comparator (cmp3) compares the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (bn) of the two-wire data bus (b1b2b3) with a third threshold value (V 2H At the same time, the second comparator (cmp2) compares the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the two-wire data bus segment (bn) connected to the two-wire data bus (b1b2b3) with the second threshold value (V 2L ) is compared. The second threshold (V 2L ) is different from the third threshold (V 2H ) and determine the first voltage value range (V B1 ) and the second voltage value range (V B2 ) between the boundaries. The third threshold (V 2H ) determines the second voltage value range (V B2 ) and the third voltage value range (V B3 ). The second comparator (cmp2) retrieves the system clock from the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (bn) of the two-wire data bus (b1b2b3). This signal is forwarded to the inside of the bus node (BSn) under consideration as the clock signal (TCK) received by the bus node under consideration. nThe third comparator (cmp3) retrieves data information from the differential signal level (TOW) on the two-wire data bus (b1b2b3) or on a connected two-wire data bus segment (bn) of the two-wire data bus (b1b2b3) as data (TMS_TDI) received via the bus node (BSn) under consideration. n ). In this case, the data received by the bus node (BSn) under consideration also contain a component of the system clock. This can be achieved, for example, by simple sampling in a trigger using the edge of a slightly delayed reconstructed system clock (TCKn) or alternatively by delaying the received data and sampling with the undelayed reconstructed system clock (TCKn). n ) sampling can be easily eliminated. If necessary, the signal must still be prepared before use.

[0308] In one embodiment, when the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the first two-wire data bus segment (bn) of the connection of the two-wire data bus (b1b2b3) is higher than the third threshold value (V 2H ), the data output signal (TMS_TDI n ) can be switched to 1 by the third comparator (cmp3), and when the value of the differential signal level (TOW) is less than the third threshold (V 2H In one embodiment, when the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the two-wire data bus segment (bn) of the connection of the two-wire data bus (b1b2b3) is higher than the second threshold value (V 2L ), the reconstructed system clock (TCK n ) can be switched to 1 by the second comparator (cmp2), and when the differential signal level (TOW) is less than the second threshold (V 2L ) and vice versa.

[0309] Similarly, the bus master (BM) samples the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (bn) of the two-wire data bus (b1b2b3) with the aid of the first comparator (cmp). To this end, the first comparator (cmp) compares the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (bn) of the two-wire data bus (b1b2b3) with the first threshold value (V 1H) and thus retrieve the data located on the data conductor, but these data also have a component of the system clock here. Suitable sampling also helps here. In this way, the data (TDo) received by the bus master (BM) is obtained. In one embodiment, when the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the two-wire data bus segment (bn) of the connection of the two-wire data bus (b1b2b3) is higher than the first threshold value (V 1H ), the data output signal (TDo) can be switched to 1 by the first comparator (CMP), and when the potential is lower than the first threshold (V 1H ), in contrast, it switches to 0. Except for a smaller tolerance range that is preferably significantly less than 25% of this value, the first threshold value (V 1H ) is preferably equal to the third threshold (V 2H ).

[0310] In further processing, the circuit from the prior art can now be used for a data bus with separate data conductors and system clock conductors, so that a description can be omitted here. For example, refer to WO 2006 / 102284 A2.

[0311] Now, the following table of numerical values ​​of signal levels (TOW) and logic values ​​is one possible implementation. Other signal levels (TOW) and corresponding logic values ​​are of course possible, as will be clear to a person skilled in the art. Note that here in this example, TCK=0 closes the dominant switches (T1a, T1b). Of course, this can also be implemented in reverse.

[0312]

[0313] Preferably, the third threshold (V 2H ) and the first threshold (V 1H ) are identical, so that the bus master (BM) and the bus nodes recognize the same data sequence. These data can then be appropriately assigned to the time slots (TINO, TIN1, TDOz) by correspondingly controlled time sampling.

[0314] Unlike German patents DE-B-10 2015 004 433, DE-B-10 2015 004 434, DE-B-10 2015004435 and DE-B-10 2015 004 436, the bus node according to the present invention typically has a differential transmission gate (TG) which has the function of two switches. The first switch can connect the preceding first single-wire data bus segment (bna) of the preceding two-wire data bus segment (bn) with the subsequent first single-wire data bus segment (b(n+1)a) of the subsequent two-wire data bus segment (b(n+1)). The second switch can connect the preceding second single-wire data bus segment (bnb) of the preceding two-wire data bus segment (bn) with the subsequent second single-wire data bus segment (b(n+1)b) of the subsequent two-wire data bus segment (b(n+1)). If the transmission gate (TGn) of the bus node (BSn) in question is open, then preferably two further switches (not shown) connect the subsequent two-wire data bus section (b(n+1)) to a holding potential or another suitable potential. As a result, the differential signal level of the subsequent two-wire data bus (b(n+1)) acquires a predefined signal level value without the need to transmit a system clock and therefore also without the need to transmit data.

[0315] Back to Figure 8 :Exemplarily, two voltage divider pairs forming a differential pull circuit are formed by a first resistor (R1a, R1b) and a second resistor (R2a, R2b) respectively. The differential pull circuit includes a first voltage divider pair having a first resistor (R1a) and a second resistor (R2a). The differential pull circuit also includes a second voltage divider pair having an additional first resistor (R2a) and an additional second resistor (R2b). When no other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) are activated, the differential pull circuit sets the value of the differential voltage level (TOW) on the two-wire data bus (b1b2b3) to within a second voltage value range (V B2 ) is maintained at the middle second differential voltage level (V M). Here, by way of example, the first two-wire data bus section (b1) is connected to the output of the master two-wire data bus interface (OWM). The data transmitter of the bus master is formed by the second transistors (T2a, T2b). The dominant clock transmitter is formed by the first transistors (Tla, Tlb). In this example, one second transistor (T2a) is a P-channel transistor. In this example, the other second transistor (T2b) is an N-channel transistor. In this example, one first transistor (Tla) is an N-channel transistor. In this example, the other first transistor (T1b) is a P-channel transistor. The first transistor (Tla) is controlled by the system clock (TCK) via an exemplary inverting buffer circuit (buf). In this example, the other first transistor (T1b) is directly controlled. When the system clock (TCK) is invalid, the second transistor (T2a) is controlled by the combined TMS-TDI signal (TMS_TDI) via a NOR gate (NOR). When the system clock (TCK) is inactive, the further second transistor (T2b) is driven via the exemplary inverting third buffer circuit (buf3). The first amplifier (VI) forms a differential level signal (DPSM) in the bus master interface (OWM) based on the differential voltage difference on the connected first two-wire data bus segment (b1). The reference voltage, i.e. the first threshold value (V 1H ), the first comparator (CMP) compares the differential signal level (TOW) in the form of the value of the differential level signal (DPSM) in the bus master interface (OWM) with the reference voltage and generates a data signal (TDo) for further processing in the bus master (BM). If necessary, the comparison result is delayed by a delay device (Δt).

[0316] Fig. 9

[0317] Fig. 9 The nth single-wire data bus interface (OWSn) of the nth bus node (BSn) of the bus nodes (BS1, BS2, BS3) is shown to match Figure 8The present invention discloses an exemplary implementation of a master two-wire data bus interface (OWM). The two-wire data bus interface (OWSn) of the nth bus node (BSn) is exemplarily connected to the nth two-wire data bus segment (bn). The data transmitter of the nth bus node (BSn) is formed by a third transistor (T3a, T3b). The internal resistance (resistance in the on state) of the third transistor is determined by the seventh resistor (R7a, R7b) connected in series as the corresponding third transistor (T3a, T3b), respectively. The second amplifier (V2) forms a differential level signal (DPS) in the bus node interface (OWSn) based on the differential voltage difference on the previously connected nth two-wire data bus segment (bn). The power supply voltage (V bat ) generates two reference voltages, namely the third threshold (V 2H ) and the second threshold (V 2L The second comparator (cmp2) and the third comparator (cmp3) compare the differential signal level (TOW) on the exemplary n-th two-wire data bus segment (bn) connected in front with the two reference voltages, i.e., the third threshold value (V 2H ) and the second threshold (V 2L ) are compared. These comparators generate the reconstructed system clock (TCK) of the nth bus node (BSn) from it. n ) and the nth combined TMS-TDI signal (TMS_TDI n ), for operating a test controller (TAPC) of a JTAG interface in the nth bus node (BSn). In this case, the clock and data are again delayed by a delay unit (Δt) for the combined TMS-TDI signal (TMS_TDI n ) and synchronized. In this example, the output signal of the JTAG interface of the nth bus node (BSn) is used to control the third transistor (T3a) and directly control the other third transistor (T3b) via the inverted second buffer circuit (buf2). It is easy for those skilled in the art to ensure the time structure of the signal through appropriate logic.

[0318] Fig.10

[0319] Fig.10 The internal structure of the JTAG interface according to the present invention is shown. The JTAG interface is compatible with the architecture set out in the IEEE 1149 standard, so that commercially available software can be used, which is a significant advantage.

[0320] In this example, the combined TMS-TDI signal (TMS_TDI n ) in the test data preparation (TB) and the reconstructed system clock (TCK n ) is synchronously decomposed into a test mode signal (TMS) and serial input data (TDI). Using the test mode signal (TMS), according to the prior art known and Figure 1 The state diagram discussed in the description of controls the test controller (TAPC) again synchronously with the clock. Within the meaning of the present invention, the state diagram of the test controller (TAPC) characterizes the JTAG interface, because software compatibility only occurs due to compliance with this state diagram. By means of a control signal (sir_sdr) for the first multiplexer (MUX1), switching between the instruction register (IR) and the data registers (BR, IDCR, RX, ILR) is performed by means of the first multiplexer (MUX1). The serial data input (TDI) is directed to all data registers (BR, IDCR, RX, ILR), the instruction register (IR) and, if necessary, additional data registers. All these registers are typically executed in two phases. This means that they have a shift register with a bit length of m and a shadow register with the same length m in parallel thereto. The shift register is used for data transmission, while the shadow register contains valid data. As described above, depending on the state of the test controller (TAPC), the data is loaded from the shift register into the shadow register or loaded or shifted from the shadow register into the shift register, or the data rests. In Fig.10 In the example of , the instruction decoder (IRDC) controls the JTAG interface depending on the content of the instruction register (IR). For example, it is conceivable that the bus node involved only allows transmission if a shadow register of the instruction register (IR) contains a certain value, i.e. a certain transmission address, at a certain bit position. However, this addressing can also be carried out in a separate transmission register (SR) (see Fig.21 ).

[0321] Particularly preferably, the JTAG interface has a bus node address register (BKADR). (See Fig.21) The bus node address register indicates the identification number of the bus node. In addition, the JTAG interface preferably has a send register (SR). The send register (SR) is set by the bus master (BM) and indicates the bus node number that should / is allowed to be sent. Only when the two addresses, namely the address in the bus node address register (BKADR) and the address in the send register (SR) are consistent, the bus node (BSn) involved is allowed to send at a predetermined time. In order to set the bus node address in the bus node address register (BKADR) when the two-wire data bus system is initialized, all transmission gates (TG) of all bus nodes (BS1, BS2, BS3) are opened at the beginning. This can preferably be done by sending a specific command to all JTAG interfaces according to the invention connected to the two-wire data bus (b1b2b3) and all reachable instruction registers (IR) of the reachable bus nodes. To this end, the instruction registers (IR) of these JTAG interfaces must be consistent in the least significant bit, which is the shift register bit that is written first. The bus master (BM) then assigns the first bus address according to a set algorithm to the first and only bus node (BS1), which is directly connected to the bus master by writing into the first bus node address register (BKADR) of the first bus node (BS1). The bus master (BM) then typically, but not necessarily, tests the connection. Preferably, the bus node address register (BKADR) of the bus node (BSn) in question can only be written if the transmission gate (TGn) of the bus node (BSn) in question is not closed. This ensures that only the last bus node, i.e. the first bus node in the sequence of bus nodes starting from the bus master whose transmission gate (TG) is not closed, accepts the bus node address into its bus node address register (BKADR). After such acceptance, the transmission gate (TG) is typically closed automatically or by a software command of the bus master (BM). This freezes the bus node address stored in the bus address register. At the same time, the subsequent bus nodes can now be addressed. In order to enable an orderly reset of the bus system, for example, an identical command is set in the instruction register (IR) for all bus nodes, which opens all transmission gates of all bus nodes so that addresses can be reassigned. As long as the bus node with the bus node address does not respond after address assignment, the bus node is defective or does not exist. In the latter case, the bus master then knows the location of all bus nodes and their number.

[0322] Fig.10The exemplary JTAG interface of includes a bypass register (BR) according to the standard, which is used to bypass data through the JTAG interface. In addition, in this example, the bypass register includes an identification register (IDCR) for reading the serial number of the circuit and an additional data register (RX) corresponding to the JTAG standard. These additional registers can be, for example, test registers and other registers.

[0323] According to the invention, an illumination register (ILR) is now provided. In the illumination register (ILR), the bus master (BM) stores data for regulating the power supply for the light emitting device (LM). Typically, the power supply is one or more (here three) pulse width modulation (PWM) drivers (PWM1, PWM2, PWM3) that generate a pulse width (PWM) modulated output voltage or a corresponding modulated current.

[0324] Fig.11

[0325] Fig.11 Shows Fig.10 , except that the JTAG interface additionally has an illumination instruction register (ILIR). The illumination instruction register controls a third multiplexer (MUX3). The third multiplexer can use an illumination data selection signal (ilds) to select the serial input data for the illumination register (ILR) at the illumination data serial input (SILDI n ) and the serial data input (TDI). At the same time, the output of the illumination register (ILR) is copied to the illumination data serial output (SILDO n ).

[0326] Fig.12

[0327] Fig.12 A plurality of circuits are shown connected via a chain with inputs (SILDI1, SILDI2, SILDI3) for lighting data and corresponding outputs (SILDO1, SILDO2, SILDO3) for lighting data. Fig.11 Possible direct connection of a JTAG controller.

[0328] This makes it possible to quickly transmit the data of an entire group of luminous means without complex addressing, since only one component still needs to be addressed.

[0329] Fig.13

[0330] Fig.13 It shows that Fig.10The JTAG interface shown in FIG. 1 is different in that the JTAG interface has a separate transmission gate control register (TGCR). Instead of placing a flag for opening and closing the transmission gate (TG) in the instruction register (IR), a separate transmission gate control register (TGCR) can also be set, which generates a corresponding enable line (enable) of the corresponding bus node (BSn). n ).

[0331] Fig.14

[0332] Fig.14 shows multiple circuits connected via a point-to-point link with Fig.15 The possible direct connection of a JTAG controller, in which data is transmitted bidirectionally and the clock is transmitted unidirectionally via a single-wire data bus segment (b1, b2, b3). Each bus node has a two-wire data bus interface (OWS1, OWS2, OWS3) and a two-wire bus master interface (OWM1, OWM2, OWM3). This forms a chain equivalent to the other figures.

[0333] Fig.15

[0334] Fig.15 Shown as Fig.10 The JTAG interface shown here differs in that it has a separate bus master control register (OWMCR). Instead of placing control bits for controlling the bus master interface (OWM1, OWM2, OWM3) of the bus node (BS1, BS2, BS3) in the instruction register (IR), a separate bus master control register (OWMCR) can also be provided which generates a corresponding control conductor (ctr) in the corresponding bus node (BSn). n ).

[0335] Fig.16

[0336] Fig.16 An exemplary housing for a bus node (BSn) is shown in plan view. The supply voltage conductor (V bat, GND) can be connected to each other without crossing. The LEDs can be connected to the corresponding connection terminals (LED1, LED2, LED3, LED4) without crossing and to the negative power supply voltage, i.e. the second reference potential (GND) of the reference potential conductor (GND). The two-wire data bus (b1, b2) can be guided without crossing between the bus nodes between the two power supply voltage conductors, which allows better shielding of the two-wire data bus and allows the use of microstrip conductors with defined characteristic impedance. This in turn makes it possible to define the connection terminals of the data bus. It is therefore particularly meaningful that the characteristic impedance of the two-wire data bus (b1b2b3) is consistent with the resistance of the differential pull circuit (R1a, R1b, R2a, R2b).

[0337] Fig.17 The plan view shows a lighting module for serial installation. Here, the two-wire data bus can preferably be introduced from the left. The subsequent two-wire data bus sections (b2a, b2b) are preferably connected on the right. The supply voltage line can be led from left to right. The light-emitting devices (LED1, LED2, LED3) can be installed in the recess (AS) of the housing (GH). They can also be installed on the housing (GH). It makes sense to use optical elements such as lenses and reflectors for beam modification.

[0338] Fig.18

[0339] Fig.18 Shows Fig.17 A further simplified version of . Fig.18 The left case is about the bus node supply voltage (V bat ) and the right version of the connection terminal of the reference potential (GND) vertically and horizontally mirrored. As a result, the housing can be installed in a planar manner, and only 12 connection terminals are required instead of 16 connection terminals. However, the disadvantage is that on the one hand, a crossover is required, but this crossover can be achieved, for example, via a bare chip island representing an integrated circuit of the bus node. For example, it is meaningful that the integrated circuit of the bus node is installed on a bare chip island, which is connected to a negative power supply voltage, that is, a second reference potential (GND) of the reference potential conductor (GND). The bare chip island can be used as a bridge between the opposite power supply voltage connection terminals of the negative power supply voltage. If the bare chip island is electrically insulated from the printed circuit, the positive power supply voltage can be guided under the optical module on the printed circuit. In order to be able to install a two-wire data bus without crossing, non-mirrored and mirrored variants need to be constructed in a checkerboard shape on the printed circuit for forming the optical module arrangement.

[0340] exist Fig.18 Also shown is the connection terminal (V bat) are electrically connected to each other, and in the same way the reference potential connection terminals (GND) of each housing (GH) are electrically connected to each other. In this case, the reference potential connection terminals (GND) for the power supply potential (V bat ) or the two second power supply potential terminals (GND) are electrically connected via the so-called die carrier of the lead frame. The remaining power supply potential terminals (which are not electrically connected to each other via the lead frame) can be connected to each other, for example, via integrated circuits in the die or via printed conductors on a printed circuit board (PCB).

[0341] Fig.19

[0342] Fig.19 Shown according to Fig.18 How to arrange the two optical modules in an array. Fig.19 In the arrangement of Fig.18 The optical module of the right optical module type is located Fig.18 Therefore, according to Fig.18 In the array arrangement of Fig.18 The optical module of the left optical module type is located Fig.18 Above and below the right optical module.

[0343] Fig. 20

[0344] Fig. 20 Shown according to Fig.18 The panel-like chain of 6 optical modules, each optical module has two two-wire bus master control interfaces (OWM1a to OWM6a and OWM1b to OWM6b) and a two-wire data bus interface (OWS1 to OWS6). Fig. 20 shows a plurality of circuits with Fig.14 The JTAG controllers are connected directly via a chain by means of point-to-point connections, in which data is transmitted bidirectionally and the clock is transmitted unidirectionally via a single-wire data bus segment. Each bus node (BS1, BS2, BS3, BS4, BS5, BS6) has a two-wire data bus interface (OWS1, OWS2, OWS3, OWS4, OWS5, OWS6) and a first two-wire bus master interface (OWM1a, OWM2a, OWM3a, OWM4a, OWM5a, OWM6a) and a second two-wire bus master interface (OWM1b, OWM2b, OWM3b, OWM4b, OWM5b, OWM6b). (Further two-wire data bus interfaces are conceivable, but are not shown here for simplicity). This forms a planar chain equivalent to the other figures.

[0345] Fig.21

[0346] Fig.21 The JTAG interface according to the invention is shown in simplified form with an illumination register (ILR), a bus node address register (BKADR) and a send register (SR).

[0347] The invention can also be alternatively developed by one of the feature groups described below, wherein the feature groups can be combined with one another as desired and individual features of a feature group can also be combined with one or more other feature groups and / or one or more features of one or more of the above-described embodiments.

[0348] 1. A data bus system having a differential two-wire data bus (b1b2b3) for transmitting data between a bus master (BM) and at least two bus nodes (BS1, BS2, BS3),

[0349] a) wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by a bus node (BS1, BS2, BS3), and

[0350] b) wherein the two-wire data bus (b1b2b3) ends at one of the bus nodes (BS1, BS2, BS3), namely the end bus node (BS3), and

[0351] c) wherein each bus node (BS1, BS2, BS3) except the first bus node (BS1) is connected to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3), and

[0352] d) wherein the first bus node (BS1) is connected to the bus master (BM) via the preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3), and

[0353] e) wherein each bus node (BS1, BS2, BS3) is connected to a subsequent bus node (BS3, BS4) of the bus node (BS1, BS2, BS3) by way of a subsequent two-wire data bus segment (b2, b3) of the two-wire data bus segment (b1, b2, b3), except for the end bus node (BS3), and

[0354] f) wherein the two-wire data bus system (b1, b2, b3) has a bus master (BM) with a master two-wire data bus interface (OWM), and

[0355] g) wherein the master two-wire data bus interface (OWM) of the bus master (BM) is configured to bidirectionally transmit and receive data via a two-wire data bus (b1b2b3) or via at least one two-wire data bus segment (b1, b2, b3) of the two-wire data bus segments (b1, b2, b3) (hereinafter referred to as the considered two-wire data bus segment (b1, b2, b3)) by means of a data bus protocol using more than two differential physical signal levels (TOW), and h) wherein the considered two-wire data bus segment (bn) comprises two signal conductors (bna, bnb), and i) wherein a two-wire data bus interface (OWSn) of a considered bus node (BS1, BS2, BS3) is electrically connected to the considered two-wire data bus segment (bn), and

[0356] j) wherein the two-wire data bus interface (OWSn) of the bus node (BSn) under consideration is configured to receive data from the two-wire data bus segment (bn) under consideration by means of a data bus protocol using more than two differential physical signal levels (TOW), and

[0357] k) wherein the two-wire data bus interface (OWSn) of the bus node (BSn) under consideration is configured to transmit data via the two-wire data bus segment (bn) under consideration by means of a data bus protocol using more than two differential physical signal levels (TOW), and

[0358] l) wherein the bus node (BSn) under consideration is in turn equipped with a master two-wire data bus interface (OWMn), and

[0359] m) wherein the master two-wire data bus interface (OWMn) of the bus node (BSn) under consideration is configured to bidirectionally transmit and receive data to and from a subsequent bus node (BS(n+1)) via at least one subsequent two-wire data bus segment (b(n+1)) of the two-wire data bus segment (b1, b2, b3) (hereinafter referred to as subsequent two-wire data bus segment (b(n+1)) by means of a data bus protocol using more than two differential physical signal levels (TOW), and n) wherein the bus node (BSn) under consideration has a first bus master control register (OWMCRn) which is configured to control the bus node (BSn) under consideration The invention relates to a bus master (BM) which can write to a bus master control register (OWMCRn) of the bus node (BSn) under investigation via the master two-wire data bus interface (OWMn) of the bus master (BM) and the two-wire data bus (b1b2b3) or the two-wire data bus segment (b1, b2, b3) under investigation and the two-wire data bus interface (OWSn) of the bus node (BSn) under investigation, and thus can control the state of the master two-wire data bus interface (OWMn) of the bus node (BSn) under investigation.

[0360] 2. A method for operating a data bus between a first slave device, the bus master (BM), and at least two further slave devices, the bus nodes (BS1, BS2, BS3),

[0361] a) wherein the data bus comprises a two-wire data bus (b1b2b3) which is divided into at least two two-wire data bus sections (b1, b2, b3) by at least two bus nodes (BS1, BS2, BS3), and

[0362] b) wherein the data bus ends via at least one bus node (BS1, BS2, BS3), namely the end bus node (BS3), and

[0363] Includes steps:

[0364] c) bidirectionally transmitting data between a bus master (BM) and at least one bus node (BS1, BS2, BS3) (hereinafter referred to as the bus node (BSn)) via a two-wire data bus (b1b2b3) or at least one two-wire data bus segment (bn) of the two-wire data bus segments (b1, b2, b3) (hereinafter referred to as the two-wire data bus segment (bn) under consideration) by means of a data protocol using more than two physically differential signal levels (TOW);

[0365] d) simultaneously transmitting a clock signal (TCK) from a bus master (BM) to at least the bus node (BSn) under consideration via a two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) using a system basic clock cycle (T) divided into at least three time slots (TIN0, TIN1, TDOz), wherein each time slot is divided into at least a first half clock cycle (T 1H ) and the second half clock cycle (T 2H );

[0366] e) comparing the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration with a third threshold value (V 2H ) for comparison;

[0367] f) comparing, by means of a second device of the bus node (BSn) under consideration, the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (b1, b2, b3) under consideration with a value different from a third threshold value (V 2H )'s second threshold (V 2L ) is compared, where the third threshold (V 2H ) and the second threshold (V 2L ) limits three signal voltage ranges (V B1 , V B2 , V B3 ), these signal voltage ranges are within the operating voltage (V IO ,V IO1 ,V IO2 ) and the reference potential (-V IO ), and

[0368] g) The middle voltage range is used as the three signal voltage ranges (V B1 , V B2 , V B3 ) of the second voltage range (V B2 ) and consists of three signal voltage ranges (V B1 , V B2 , V B3 ) of the first voltage range (V B1 ) is limited upward or downward, and the second voltage range (V B2 ) downward or upward, that is, in the first voltage range (V B1 ) in opposite directions through three signal voltage ranges (V B1 , V B2 , V B3 ) of the third voltage range (V B3 )limit,

[0369] h) transmitting data on a two-wire data bus (b1b2b3) or at least a considered two-wire data bus segment (bn) in time slot packets, said time slot packets having a total duration of a system clock cycle (T) comprising at least three consecutive time slots (TIN0, TIN1, TDOz), wherein the order of the time slots (TIN0, TIN1, TDOz) within a sequence of at least three time slots (TIN0, TIN1, TDOz) within a time slot packet can be selected in a system-specific manner,

[0370] i. comprising transmitting at least one control data and / or first data from the bus master (BM) to the bus node under consideration (BS1, BS2, BS3) in a first time slot (TIN0) and in a second time slot (TIN1), wherein the bus node under consideration (BSn) receives the control data and / or the first data, and

[0371] ii. comprising transmitting, in a third time slot (TDOz) of at least three consecutive time slots (TIN0, TIN1, TDOz), on a two-wire data bus (b1b2b3) or at least on a two-wire data bus segment (b1, b2, b3) under consideration, a signal in a second voltage range (V B2 ) and the third voltage range (V B3 ), wherein the bus master (BM) receives the second data,

[0372] iii. wherein at least two half-clock cycles (T 1H , T 2H ), by varying the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the two-wire data bus segment (bn) under consideration in a second voltage range (V B2 ) and on the other hand the third voltage range (V B3 ) through the first voltage range (V B1 ) and the differential signal level (TOW) is converted via the first voltage range (V B1 ) in the opposite direction to transmit the first data and / or the second data,

[0373] iv. wherein at least two half-clock cycles (T 1H , T 2H), wherein no data is sent in this half-clock cycle, and wherein the transmission of the system clock in the time slot concerned is performed by changing the differential signal level (TOW) on the two-wire data bus (b1b2b3) or at least the considered two-wire data bus segment (bn) to a first voltage range (V B1 ) and on the other hand the second voltage range (V B2 ) and / or a third voltage range (V B3 3. A housing (GH) for a bus node (BSn) in a data bus system for transmitting lighting data for lighting means (LM1, LM2, LM3) by means of a differential two-wire data bus (b1b2b3) according to the preceding figures, a) wherein the two-wire data bus (b1b2b3) is provided for transmitting data between a bus master (BM) and one of the bus nodes (BS1, BS2, BS3) on the one hand and between at least two bus nodes (BS1, BS2, BS3) on the other hand, and

[0374] b) wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by bus nodes (BS1, BS2, BS3), and

[0375] c) wherein the housing (GH) of the bus node (BSn) has at least two rows of terminals, namely a first row of terminals (GND, b1a, b1b, V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ),and

[0376] d) wherein at least two of the connection terminals are arranged opposite each other on the housing (GH), and

[0377] e) wherein each terminal row comprises a terminal for a first, in particular negative, supply voltage (GND) and a terminal for a second, in particular positive, supply potential (V bat ),

[0378] f) wherein not only the first connection terminal row (GND, b1a, b1b, V bat ) for the first power supply potential connection terminal (GND) and the second connection terminal row (GND, b2a, b2b, V bat ) for the first power supply potential connection terminal (GND), and the first connection terminal row (GND, b1a, b1b, V bat ) for the second power supply potential connection terminal (V bat ) and the second connection terminal row (GND, b2a, b2b, V bat) for the second power supply potential connection terminal (V bat ) are connected without crossing each other, and

[0379] g) First connection terminal row (GND, b1a, b1b, V bat ) for a two-wire data bus section (b1) upstream of the bus node, two terminals (b1a, b1b) are arranged between a terminal for a first supply potential (GND) and a terminal for a second supply voltage (V bat ) and

[0380] h) On the second connection line (GND, b2a, b2b, V bat ) for a two-wire data bus section (b2) downstream of the bus node, are arranged between a connection for a first supply potential (GND) and a connection for a second supply potential (V bat ) and

[0381] i) wherein the connections for connecting or for controlling the luminous means (LED1, LED2, LED3, LED4) in their respective connection row are arranged such that the connection for the power supply potential in the respective connection row is located between two connections (b1a, b1b or b2a, b2b) for the associated two-wire data bus section (b1 or b2) and the connection for connecting or for controlling the luminous means (LED1, LED2, LED3, LED4), wherein the current flowing through the luminous means (LED1, LED2, LED3, LED4) from these connections for operating and / or for controlling the luminous means (LED1, LED2, LED3, LED4) is to be led off via the power supply potential. 4. A light module, comprising a housing (GH) for a bus node (BSn) in a data bus system according to numeral 1 for transmitting illumination data for the luminous means (LED1, LED2, LED3) by means of a differential two-wire data bus (b1b2b3),

[0382] a) wherein a two-wire data bus (b1b2b3) is provided for transmitting data between a bus master (BM) and between at least two bus nodes (BS1, BS2, BS3), and

[0383] b) the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by bus nodes (BS1, BS2, BS3), and

[0384] c) wherein each bus node (BS2, BS3) except the first bus node (BS1) is configured to be connected to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus segment (b2, b3) of the two-wire data bus segments (b1, b2, b3), and the first bus node (BS1) is configured to be connected to a bus master (BM) via a preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3), and

[0385] d) wherein the housing (GH) of the bus node (BSn) has at least two rows of terminals, namely a first row of terminals (GND, b1a, b1b, V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ),and

[0386] e) wherein at least two of the connection terminals are arranged opposite each other on the housing (GH), and

[0387] f) wherein each connection terminal row comprises a connection terminal for a first supply potential (GND), and

[0388] g) wherein each terminal row comprises a terminal for a second supply potential (V bat ),and

[0389] h) If the first connection terminal row (GND, b1a, b1b, V bat ) for the first power supply potential connection terminal (GND) and the second connection terminal row (GND, b2a, b2b, V bat ) is connected to the connection terminal (GND) for the first power supply voltage, and if the first connection terminal row (GND, b1a, b1b, V bat ) for the second power supply voltage connection terminal (V bat ) and the second connection terminal row (GND, b2a, b2b, V bat ) for the second power supply potential connection terminal (V bat ), the connection terminals for the first power supply potential and the connection terminals for the second power supply potential are arranged in each connection terminal row as follows, that is, they can be connected without crossing, and

[0390] i) The first connection terminal row (GND, b1a, b1b, V bat ) for the bus node in the first two-wire data bus section (b1) are arranged in a first terminal row (GND, b1a, b1b, V bat ) for the first power supply voltage connection terminal (GND) and the first connection terminal row (GND, b1a, b1b, Vbat ) for the second power supply potential connection terminal (V bat ) and

[0391] j) The second connection terminal row (GND, b2a, b2b, V bat ) for the subsequent two-wire data bus section (b2) of the bus node is arranged in a second terminal row (GND, b2a, b2b, V bat ) for the first power supply potential connection terminal (GND) and the second connection terminal row (GND, b2a, b2b, V bat ) for the second power supply voltage connection terminal (V bat ) and

[0392] k) At least one luminous means (LED1, LED2, LED3) is arranged in a recess (ASP) of the housing or on the housing (GH).

[0393] 5. The light module according to any of the preceding numbers, wherein at least three light-emitting devices (LEDL, LED2, LED3) are arranged in a recess (ASP) of the housing, and the at least three light-emitting devices (LED1, LED2, LED3) respectively have different luminous colors perceived by humans.

[0394] 6. A light module comprising a housing (GH) for a bus node (BSn) in a data bus system for transmitting lighting data for lighting means (LED1, LED2, LED3) by means of a differential two-wire data bus (b1b2b3) according to one of the preceding figures,

[0395] a) wherein a two-wire data bus (b1b2b3) is provided for transmitting data between a bus master (BM) and between at least two light-emitting bus nodes (BS1, BS2, BS3), and

[0396] b) wherein the two-wire data bus (b1b2b3) is divided into at least two two-wire data bus sections (b1, b2, b3) by bus nodes (BS1, BS2, BS3), and

[0397] c) wherein each bus node (BS2, BS3) except the first bus node (BS1) is configured to be connected to a preceding bus node (BS1, BS2) of the bus nodes (BS1, BS2, BS3) via a preceding two-wire data bus segment (b2, b3) of the two-wire data bus segments (b1, b2, b3), and the first bus node (BS1) is configured to be connected to a bus master (BM) via a preceding two-wire data bus segment (b1) of the two-wire data bus segments (b1, b2, b3), and

[0398] d) wherein at least one bus node (BSn) can be connected to at least three two-wire data bus segments (b1, b2, b3), and

[0399] e) wherein the housing (GH) of the bus node (BSn) has at least three rows of terminals, namely a first row of terminals (V bat , b1a, b1b), a second connection terminal row (GND, b2a, b2b) and a third connection terminal row (V bat , b3a, b3b), and if necessary a fourth connection terminal row (GND, b4a, b4b), and

[0400] f) wherein each of the three or four rows of connection terminals on the housing (GH) has at least one adjacent row of connection terminals which is arranged at an angle of 90° to said row of connection terminals, and

[0401] g) wherein each connection terminal row comprises exactly one connection terminal for a supply potential (GND, V bat ) and

[0402] h) wherein each connection terminal row adjacent to another connection terminal row has connections for a further supply potential which is different from the supply potential whose connections are included by the adjacent connection terminal row, and

[0403] i) wherein the connection for the supply potential is the first connection in a row of connections in all rows of connections with the same counting direction in the clockwise or counterclockwise sense, and

[0404] j) wherein each terminal row comprises two terminals of a two-wire data bus section, and

[0405] k) wherein two terminals of the one two-wire data bus section are adjacent to terminals for a supply potential in the terminal row, and

[0406] 1) wherein at least one luminous means (LED1, LED2, LED3) is arranged in a recess (AS) of a housing (GH) or on the housing (GH).

[0407] 7. An optical module according to any of the preceding numbers,

[0408] a) has a mounting carrier (English: Lead-Frame, lead frame),

[0409] b) wherein the first connection terminal of the first power supply potential (GND or V bat ) is located in the first connection terminal row, and

[0410] c) wherein the second connection terminal of the first power supply potential (GND or V bat ) is located in the second connection terminal row, and

[0411] d) wherein the first row of connection terminals is arranged opposite the second row of connection terminals, and

[0412] e) The first terminal is electrically conductively connected to an opposite second terminal via a mounting carrier (English: Lead-Frame).

[0413] 8. An optical module comprising a housing (GH) for a bus node (BSn) in a data bus system according to one of the preceding numbers,

[0414] a) having connection terminals (b1a, b1b, b2a, b2b) for receiving lighting data via a differential two-wire data bus (b1b2b3),

[0415] b) wherein the connections (b1a, b1b, b2a, b2b) of the two-wire data bus (b1b2b3) are arranged at the supply potential connection (V bat ) and a supply potential connection terminal (GND) for a first supply potential, and

[0416] c) having at least one light emitting device (LED1, LED2, LED3), and

[0417] d) has an illumination register (ILR) that is writable via a two-wire data bus (b1b2b3), and

[0418] e) Having means for operating light emitting devices (LED1, LED2, LED3), wherein the brightness of the light emitting devices depends on the data content of an illumination register (ILR).

[0419] 9. A light module according to any of the preceding figures, wherein the light module has at least two light-emitting devices (LED1, LED2, LED3), wherein the brightness thereof can be adjusted differently by adjusting the different luminous intensities of the light-emitting devices LED1, LED2, LED3) according to the data content of an illumination register (ILR).

[0420] Reference numerals list

[0421] AS housing recess

[0422] b1b2b3 two-wire data bus

[0423] b1b2b3b4 two-wire data bus

[0424] b1 First two-wire data bus segment

[0425] b1a The first single-wire data bus segment of the first two-wire data bus segment (b1)

[0426] b1b The second single-wire data bus segment of the first two-wire data bus segment (b1)

[0427] b2 Second two-wire data bus segment

[0428] b2a The first single-wire data bus segment of the second two-wire data bus (b2)

[0429] b2b The second single-wire data bus segment of the second two-wire data bus segment (b2)

[0430] b3 The third two-wire data bus segment

[0431] b3a The first single-wire data bus segment of the third two-wire data bus segment (b3)

[0432] b3b Second single-wire data bus segment of the third two-wire data bus (b3)

[0433] b4 Fourth two-wire data bus segment

[0434] b4a first single-wire data bus segment of the fourth two-wire data bus (b4)

[0435] b4b Second single-wire data bus segment of the fourth two-wire data bus segment (b4)

[0436] b5 Fifth two-wire data bus segment

[0437] b6 Sixth two-wire data bus segment

[0438] bn nth two-wire data bus segment

[0439] bna The first single-wire data bus segment of the nth two-wire data bus segment (bn)

[0440] bnb Second single-wire data bus segment of the nth two-wire data bus (bn)

[0441] b(n+1) The (n+1)th two-wire data bus segment

[0442] b(n+1) The first single-wire data bus segment of the (n+1)th two-wire data bus segment (b(n+1))

[0443] b(n+1)b The second single data bus segment of the (n+1)th two-wire data bus segment (b(n+1))

[0444] BKADR Bus Node Address Register

[0445] BKADRn Bus node address register of the bus node (BSn) under consideration

[0446] BM Bus Master

[0447] BR Bypass Register

[0448] BRn Bypass register of the bus node (BSn) under consideration

[0449] BS1 Exemplary first bus node

[0450] BS2 Exemplary second bus node

[0451] BS3 Exemplary third bus node

[0452] BS4 Exemplary fourth bus node

[0453] BS5 Exemplary fifth bus node

[0454] BS6 Exemplary sixth bus node

[0455] BSn is an exemplary nth bus node (the relevant or considered bus node is denoted by BS in various places of the present invention). n denoted by ). Therefore, it is any one of the bus nodes (BS1, BS2, BS3). The number of bus nodes may be different from 3.

[0456] BS(n+1) Exemplary (n+1)th Bus Node

[0457] buf buffer circuit

[0458] buf2 second buffer circuit

[0459] buf3 third buffer circuit

[0460] Bus Node Bus Node Circuit A bus node is typically an integrated circuit or other electrical system that is controlled by a main processor, the bus master, via a two-wire data bus (b1b2b3) or at least one connected two-wire data bus segment (b1, b2, b3).

[0461] Bus Master The Bus Master (BM) is typically the main processor, via which the integrated circuit, ie the bus node (BSn) in question, is controlled.

[0462] The first comparator compares the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (b1, b2, b3) in the form of the value of the differential level signal (DPSM) in the bus master interface (OWM) with the first threshold (V 1H) and forwards the data signal (TDo) received by the bus master (BM) to the circuit inside the bus master (BM), which is typically a main processor. The first comparator detects the value of the signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segments (b1, b2, b3) from a third voltage value range (V B3 ) to the other side of the first voltage value range (V B1 ) or the second voltage value range (V B2 ) and vice versa.

[0463] The second comparator on the cmp2 bus node side compares the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (b1, b2, b3) in the form of the value of the differential level signal (DPS) with the second threshold value (V 2L ) and compares the reconstructed system clock (TCK) received by the bus node (BSn) under consideration. n ) is forwarded to the circuit of the bus node (BSn) under investigation, which is typically an integrated circuit or a control system to be controlled. The second comparator detects the two-wire data bus

[0464] (b1b2b3) or the differential signal level (TOW) on the connected two-wire data bus segment (b1, b2, b3) is from a first voltage value range (V B1 ) to the other side, the second voltage value range (V B2 ) or the third voltage value range (V B3 ) and vice versa.

[0465] The third comparator on the cmp3 bus node side compares the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segment (b1, b2, b3) in the form of the value of the differential level signal (DPSn) of the bus node (BSn) under consideration with a third threshold value (V 2H ) and compares the data signal (TMS_TDI) received by the bus node (BSn) under consideration n ) is forwarded to the circuit of the bus node under consideration (BSn), which is typically an integrated circuit or a system to be tested or controlled. A third comparator detects the value of the differential signal level (TOW) on the two-wire data bus (b1b2b3) or the connected two-wire data bus segments (b1, b2, b3) from a third voltage value range (V B3 ) to the other side of the first voltage value range (V B1 ) or the second voltage value range (VB2 ) and vice versa.

[0466] CIR Test Controller (TAPC) status "Load Instruction Register Data"

[0467] Status of CDR Test Controller (TAPC) "Load Data Register Data"

[0468] ctr1 is a control conductor for controlling the bus master interface (OWM1) of the first bus node (BS1)

[0469] ctr1a is a control line for controlling a first bus master interface (OWM1a) of a first bus node (BS1)

[0470] ctr1b is a control conductor for controlling the second bus master interface (OWM1b) of the first bus node (BS1)

[0471] ctr2 is used to control the control line of the bus master interface (OWM2) of the second bus node (BS2)

[0472] ctr2a is a control conductor for controlling the first bus master interface (OWM2a) of the second bus node (BS2)

[0473] ctr2b is a control conductor for controlling the second bus master interface (OWM2b) of the second bus node (BS2)

[0474] ctr3 is used to control the control line of the bus master interface (OWM3) of the third bus node (BS3)

[0475] ctr3a is a control line for controlling the first bus master interface (OWM3a) of the third bus node (BS3)

[0476] ctr3b is a control conductor for controlling the second bus master interface (OWM3b) of the third bus node (BS3)

[0477] ctr4 is used to control the control line of the bus master interface (OWM4) of the fourth bus node (BS4)

[0478] ctr4a is a control line for controlling a first bus master interface (OWM4a) of a fourth bus node (BS4)

[0479] ctr4b is a control line for controlling a second bus master interface (OWM4b) of a fourth bus node (BS4)

[0480] ctr5 is used to control the control line of the bus master interface (OWM5) of the fifth bus node (BS5)

[0481] ctr5a is a control line for controlling the first bus master interface (OWM5a) of the fifth bus node (BS5)

[0482] ctr5b is a control line for controlling the second bus master interface (OWM5b) of the fifth bus node (BS5)

[0483] ctr6 is used to control the control line of the bus master interface (OWM6) of the sixth bus node (BS6)

[0484] ctr6a is a control line for controlling the first bus master interface (OWM5a) of the sixth bus node (BS5)

[0485] ctr6b is a control line for controlling a second bus master interface (OWM6b) of a sixth bus node (BS2)

[0486] ctr n For controlling the nth bus node (BS n ) bus master interface (OWM n ) control wire

[0487] The level signal of the DPS bus node. This level signal is generated by the corresponding two-wire data bus interface (OWS n ) is formed by the output of the second differential input amplifier (V2).

[0488] DPSn is the level signal of the bus node (BSn) under consideration. This level signal is generated by the corresponding two-wire data bus interface (OWS n ) is formed by the output of the second differential input amplifier (V2n) of the bus node (BSn) under consideration.

[0489] The level signal of the bus master (BM) involved in the DPSM is formed by the output of the first differential input amplifier (V1) of the bus master (BM) of the corresponding two-wire data bus interface (OWM) of the bus master (BM).

[0490] DR Data register of the JTAG interface. (Typically, multiple data registers are connected in parallel and are selected via a second multiplexer (MUX2) during a read of the data register (DR).

[0491] DRn is the data register of the JTAG interface of the bus node (BSn) under consideration. (Typically, a plurality of data registers are connected in parallel and are selected during reading of the data register (DR) via a second multiplexer (MUX2n) of the bus node (BSn) under consideration.)

[0492] drs is the selection signal for the data register that should be read

[0493] Δt is used for the combined TMS-TDI signal (TMS_TDI n ) or the delay unit of the TDo signal in the bus master

[0494] Status "Data Register Exit 1" of the EDR1 Test Controller (TAPC)

[0495] Status "Data Register Exit 2" of the EDR2 Test Controller (TAPC)

[0496] Status "Instruction Register Exit 1" of the EIR1 Test Controller (TAPC)

[0497] Status "Instruction Register Exit 2" of the EIR2 Test Controller (TAPC)

[0498] en1 is used to open and close the first enable conductor of the first transmission gate (TG1) of the first bus node (BS1)

[0499] en2 is used to open and close the second enable conductor of the second transmission gate (TG2) of the second bus node (BS2)

[0500] en3 is used to open and close the third enable conductor of the third transmission gate (TG3) of the third bus node (BS3)

[0501] en n For opening and closing the nth bus node, the bus node under consideration (BS n )

[0502] Transmission gate (TGn) nth enable wire

[0503] GH housing

[0504] GND reference potential conductor. Typically, but not necessarily, this reference potential conductor is connected to ground.

[0505] It has a second reference potential (GND).

[0506] iTCK n The internal system base clock of the bus node (BSn) under consideration

[0507] IDCR Identification Register

[0508] IDCRn Identification register of the bus node (BSn) under consideration

[0509] Ilds lighting data selection signal

[0510] Ildsn Illumination data selection signal of the bus node (BSn) under consideration

[0511] ILR Lighting Register

[0512] ILRn Illumination register of the bus node (BSn) considered

[0513] ILIR lighting instruction register

[0514] Lighting command register of the bus node (BSn) under consideration by ILIRn

[0515] IRJTAG interface instruction register

[0516] IRn Instruction register IRDC instruction decoder of the JTAG interface of the bus node (BSn) under consideration

[0517] The command decoder of the bus node (BSn) considered by IRDCn

[0518] LED light emitting diode. Within the meaning of the invention, this can also be a parallel and / or series circuit of a plurality of LEDs.

[0519] LED1 is used for connecting the first LED group (one LED or multiple LEDs connected in series and / or in a row)

[0520] LED2 is used for the connection terminal of the second LED group (one LED or multiple LEDs connected in series and / or in a row)

[0521] LED3 is used for the connection terminal of the third LED group (one LED or multiple LEDs connected in series and / or in a row)

[0522] LED4 is used for the connection terminal of the fourth LED group (one LED or multiple LEDs connected in series and / or in a row)

[0523] LM1 is a light emitting device group 1 controlled by the first bus node (BS1) LM2 is a light emitting device group 2 controlled by the second bus node (BS2) LM3 is a light emitting device group 3 controlled by the third bus node (BS3) LM4 is a light emitting device group 4 controlled by the fourth bus node (BS4) LM5 is a light emitting device group 5 controlled by the fifth bus node (BS5) LM6 is a light emitting device group 6 controlled by the sixth bus node (BS6) LMn light emitting device group, which is controlled by the bus node (BSn) under consideration

[0524] MUX1 The first multiplexer in the JTAG interface, used to switch between the data register (DR) and the instruction register (IR)

[0525] MUX12 Second multiplexer in the JTAG interface to select the active data register (DR) MUX3 The third multiplexer used to switch between the illumination data serial input (SILDI) and the serial input data (TDI)

[0526] MUXn is used to serially input the illumination data (SILDI n ) and the serial input data (TDIn) of the bus node under consideration.

[0527] NOR inverted OR circuit

[0528] OWM master control two-wire data bus interface

[0529] OWM1 master two-wire data bus interface of the first bus node (BS1)

[0530] OWM1a First bus node (BS1) first main line two-wire data bus interface OWM1b Second master two-wire data bus interface of the first bus node (BS1) OWM2 Master two-wire data bus interface for the second bus node (BS2)

[0531] OWM2a First master two-wire data bus interface of the second bus node (BS2) OWM2b Second master two-wire data bus interface of the second bus node (BS2) OWM3 Master two-wire data bus interface for the third bus node (BS3)

[0532] OWM3a 3rd bus node (BS3) first master two-wire data bus interface OWM3b Second master two-wire data bus interface of the third bus node (BS3) OWM4 Master two-wire data bus interface for bus node 4 (BS4) OWM4a First master two-wire data bus interface of the fourth bus node (BS4) OWM4b Second master two-wire data bus interface of the fourth bus node (BS4) OWM5 Master two-wire data bus interface for the fifth bus node (BS5) OWM5a First master two-wire data bus interface of the fifth bus node (BS5) OWM5b Second master two-wire data bus interface of the fifth bus node (BS5) OWM6 Master two-wire data bus interface for bus node 6 (BS6) OWM6a First master two-wire data bus interface of the sixth bus node (BS6) OWM6b Second master two-wire data bus interface of the sixth bus node (BS6) OWMn Master two-wire data bus interface of the bus node (BSn) under consideration OWMCR Bus Master Control Register

[0533] The bus master control register of the bus node (BSn) examined by OWMCRn OWS1 Two-wire data bus interface of the first bus node (BS1) OWS2 Two-wire data bus interface for the second bus node (BS2) OWS3 Two-wire data bus interface for the third bus node (BS3) OWS4 Two-wire data bus interface for the fourth bus node (BS4) OWS5 Two-wire data bus interface for the fifth bus node (BS5) OWS6 Two-wire data bus interface for the sixth bus node (BS6) OWS n Two-wire data bus interface of the bus node (BSn) under consideration PCM Pulse Code Modulation

[0534] PDM pulse density modulation

[0535] Status of the PDR Test Controller (TAPC) "Pause Data Register"

[0536] PFM Pulse Frequency Modulation

[0537] Status of the PIR Test Controller (TAPC) "Pause Command Register"

[0538] POM pulse on-time modulation and / or pulse off-time modulation

[0539] PWM Pulse Width Modulation. (Within the meaning of the present invention, this term includes all known types of pulse modulation, such as PFM, PCM, PDM, POM, etc.).

[0540] PWM1 first PWM unit

[0541] PWM2 second PWM unit

[0542] PWM3 The third PWM unit

[0543] PWM unit of the bus node (BSn) considered by PWMn

[0544] R0 pull circuit (R 1a , R 1b , R 2a , R 2b ) internal resistance, if the other transmitters (T1a, T1b, T2a, T2b, T3a, T3b) are not activated, the pull circuit acts as a fourth actual voltage source to keep the two-wire data bus (b1b2b3) or the connected two-wire data bus segments (b1, b2, b3) at the middle second differential voltage value level (V M ). (not shown in the figure)

[0545] R1a is the upper resistor of the first voltage divider, which forms a differential pull circuit together with the second voltage divider. The differential pull circuit converts the second voltage value range (V B2 ) is maintained at the value of the differential signal level (TOW) on the two-line data bus (b1b2b3b4) in the middle of the second differential voltage value level (V M ) if no other transmitter (T1a, T1b, T2a, T2b, T3a, T3b) is activated.

[0546] R1b is the upper resistor of the second voltage divider, which forms a differential pull circuit together with the first voltage divider. The differential pull circuit converts the second voltage value range (V B2 ) is maintained at the value of the differential signal level (TOW) on the two-line data bus (b1b2b3b4) in the middle of the second differential voltage value level (V M ) if no other transmitter (T1a, T1b, T2a, T2b, T3a, T3b) is activated.

[0547] R2a is the lower resistor of the first voltage divider, which forms a differential pull circuit together with the second voltage divider. The differential pull circuit converts the second voltage value range (V B2 ) is maintained at the value of the differential signal level (TOW) on the two-line data bus (b1b2b3b4) in the middle of the second differential voltage value level (V M ) if no other transmitter (T1a, T1b, T2a, T2b, T3a, T3b) is activated.

[0548] R2b is the lower resistor of the second voltage divider, which forms a differential pull circuit together with the first voltage divider. The differential pull circuit converts the second voltage value range (V B2) is maintained at the value of the differential signal level (TOW) on the two-line data bus (b1b2b3b4) in the middle of the second differential voltage value level (V M ) if no other transmitter (T1a, T1b, T2a, T2b, T3a, T3b) is activated.

[0549] R1 first resistor

[0550] R 1H The internal resistance of the second switchable real voltage source in the switched-on state, which is formed by the switchable current sources of the bus master (BM), namely the transistors (T1a, T1b). (not shown in the figure)

[0551] R2 second resistor

[0552] R 2H The internal resistance of a third switchable real voltage source in the switched-on state, which is formed by a switchable current source, ie a transistor (T3a, T3b), of the bus node (BSn) under consideration. (not shown in the figure)

[0553] R3 voltage divider

[0554] R4 fourth resistor

[0555] R5 fifth resistor

[0556] R6 Sixth resistor

[0557] R7a seventh resistor, for adjusting the internal resistance of the switch of the controllable current source (T3a) for the transmitter of the bus node (BSn) under consideration

[0558] R7b seventh resistor, used to adjust the internal resistance of the switch of the controllable current source (T3b) for the transmitter of the bus node (BSn) under consideration

[0559] RUN Test Controller (TAPC) status "Waiting"

[0560] RX Additional Data Register (DR) according to JTAG standard

[0561] Additional data register (DRn) according to the JTAG standard of the bus node (BSn) considered by RXn

[0562] Status "Data register shift started" in SDRS test controller (TAPC)

[0563] SILDIn is used for the serial input of the lighting data of the bus node (BSn) under consideration

[0564] SILDI1 is used for serial input of lighting data of the first bus node (BS1)

[0565] SILDI2 is used for serial input of lighting data of the second bus node (BS2)

[0566] SILDI3 is used for serial input of lighting data of the third bus node (BS3)

[0567] SILDOn for serial output of the lighting data of the bus node (BSn) under consideration

[0568] SILDO1 is used for serial output of lighting data of the first bus node (BS1)

[0569] SILDO2 is used for serial output of lighting data of the second bus node (BS2)

[0570] SILDO3 is used for serial output of lighting data of the third bus node (BS3)

[0571] Status "Instruction register shift started" in SIRS Test Controller (TAPC)

[0572] Status "Instruction Register Shift" of the SIR Test Controller (TAPC)

[0573] sir_sdr is the control signal for the first multiplexer (MUX1) between the instruction register (IR) and the data register (DR).

[0574] Status "Data Register Shift" of SDR Test Controller (TAPC)

[0575] SR Send Register

[0576] The transmit register of the bus node (BSn) considered by SRn

[0577] TSystem basic clock cycle

[0578] T1a is a first transistor for controlling a first single-wire data bus (b1a, b2a, b3a, b4a) of a two-wire data bus (b1b2b3b4) to send a system clock from a bus master (BM) to a bus node. The first transistor forms a dominant switch relative to other transmitters (T2a, T3a, R1a, R2a) on the first single-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4).

[0579] T1b is used to control another first transistor of a second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) to send a system clock from a bus master (BM) to a bus node. The other first transistor forms a dominant switch relative to other transmitters (T2b, T3b, R1b, R2b) on the second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4).

[0580] T 1H At least two and a half clock cycles of the system clock period (T 1H , T 2H )'s first half clock cycle

[0581] T2a is a second transistor for controlling a first single-line data bus (b1a, b2a, b3a, b4a) of a two-line data bus (b1b2b3b4) for transmitting data from a bus master (BM) to a bus node. The second transistor forms a dominant switch relative to a voltage divider of a differential pull circuit (R1a, R2a) on the first single-line data bus (b1a, b2a, b3a, b4a) of the two-line data bus (b1b2b3b4). The internal resistance of the second transistor in the on state is set so that the first transistor (T1a) can cover one or more second and third transistors transmitting on the first single-line data bus (b1a, b2a, b3a, b4a) of the two-line data bus (b1b2b3b4). The second transistor is preferably equally authorized relative to the third transistor (T3a).

[0582] T2b is a second additional transistor for controlling a second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) for transmitting data from the bus master (BM) to the bus node. The second additional transistor forms a dominant switch relative to a voltage divider of a differential pull circuit (R1b, R2b) on the second single-wire data bus of the two-wire data bus (b1b2b3b4). The internal resistance of the second additional transistor in the switched-on state is set such that the first additional transistor (T1a) can cover one or more second additional and third additional transistors transmitting on the second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4). The second additional transistor is preferably equally authorized relative to the third additional transistor (T3a).

[0583] T 2H At least two and a half clock cycles of the system clock period (T 1H , T 2H )'s second half clock cycle

[0584] T3a is a third transistor for controlling a first single-wire data bus (b1a, b2a, b3a, b4a) of a two-wire data bus (b1b2b3b4) for transmitting data from a bus node (BSn) under consideration to a bus master (BM). The third transistor forms a dominant switch relative to a voltage divider of a differential pull circuit (R1a, R2a) on the first single-wire data bus of the two-wire data bus (b1b2b3b4). The internal resistance of the third transistor in the on state is set such that the first transistor (T1a) can cover one or more second and third transistors transmitting on the first single-wire data bus (b1a, b2a, b3a, b4a) of the two-wire data bus (b1b2b3b4). The third transistor is preferably equally authorized relative to the second transistor (T3a).

[0585] T3b is a further third transistor for controlling a second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4) for transmitting data from the bus node (BSn) under consideration to the bus master (BM). The further third transistor forms a dominant switch with respect to a voltage divider of a differential pull circuit (R1b, R2b) on the second single-wire data bus (b1b, b2b, b3b, b4b) of the two-wire data bus (b1b2b3b4). The internal resistance of the further third transistor in the switched-on state is set such that the further first transistor (T1a) can cover one or more further second and further third transistors transmitting on the second single-wire data bus of the two-wire data bus (b1b2b3b4). The further third transistor is preferably equally authorized with respect to the further second transistor (T3a).

[0586] TAPC Test Controller

[0587] Test controller for the bus node (BSn) investigated by TAPCn

[0588] TB data preparation

[0589] TCK clock input (test clock input) and system clock and clock signal (system clock) to be sent by the bus master (BM)

[0590] TCK1 Reconstructed system clock in the first bus node (BS1)

[0591] TCK1i Reconstructed system clock in the first bus node (BS1), from the first two-wire data bus interface (OWS1) of the first bus node (BS1)

[0592] TCK1o Reconstructed system clock in the first bus node (BS1) for the master two-wire data bus interface (OWM1) of the first bus node (BS1)

[0593] TCK1ao Reconstructed system clock in the first bus node (BS1) for the first master two-wire data bus interface (OWM1a) of the first bus node (BS1)

[0594] TCK1bo Reconstructed system clock in the first bus node (BS1) for the second master two-wire data bus interface (OWM1b) of the first bus node (BS1)

[0595] TCK2 Reconstructed system clock in the second bus node (BS2)

[0596] TCK2i Reconstructed system clock in the second bus node (BS2), from the second two-wire data bus interface (OWS2) of the second bus node (BS2)

[0597] TCK2o Reconstructed system clock in the second bus node (BS2) for the master two-wire data bus interface (OWM2) of the second bus node (BS2)

[0598] TCK2ao Reconstructed system clock in the second bus node (BS2) for the second master two-wire data bus interface (OWM2a) of the second bus node (BS2)

[0599] TCK2bo Reconstructed system clock in the second bus node (BS2) for the second master two-wire data bus interface (OWM2b) of the second bus node (BS2)

[0600] TCK3 Reconstructed system clock in the third bus node (BS3)

[0601] TCK3i Reconstructed system clock in the third bus node (BS3), from the third two-wire data bus interface (OWS3) of the third bus node (BS3)

[0602] TCK3o Reconstructed system clock in the third bus node (BS3) for the master two-wire data bus interface (OWM3) of the third bus node (BS3)

[0603] TCK3ao Reconstructed system clock in the third bus node (BS3) for the first master two-wire data bus interface (OWM3a) of the third bus node (BS3)

[0604] TCK3bo Reconstructed system clock in the third bus node (BS3) for the second master two-wire data bus interface (OWM3b) of the third bus node (BS3)

[0605] TCK4 Reconstructed system clock in the fourth bus node (BS4)

[0606] TCK4i Reconstructed system clock in the fourth bus node (BS4), from the fourth two-wire data bus interface (OWS4) of the fourth bus node (BS4)

[0607] TCK4o Reconstructed system clock in the fourth bus node (BS4) for the master two-wire data bus interface (OWM4) of the fourth bus node (BS4)

[0608] TCK4ao Reconstructed system clock in the fourth bus node (BS4) for the first master two-wire data bus interface (OWM4a) of the fourth bus node (BS4)

[0609] TCK4bo Reconstructed system clock in the fourth bus node (BS4) for the second master two-wire data bus interface (OWM4b) of the fourth bus node (BS4)

[0610] TCK5 Reconstructed system clock in the fifth bus node (BS5)

[0611] TCK5i Reconstructed system clock in the fifth bus node (BS5), from the fifth two-wire data bus interface (OWS5) of the fifth bus node (BS5)

[0612] TCK5o Reconstructed system clock in the fifth bus node (BS5) for the master two-wire data bus interface (OWM5) of the fifth bus node (BS5)

[0613] TCK5ao Reconstructed system clock in the fifth bus node (BS5) for the first master two-wire data bus interface (OWM5a) of the fifth bus node (BS5)

[0614] TCK5bo Reconstructed system clock in the fifth bus node (BS5), used for the second master two-wire data bus interface (OWM5b) of the fifth bus node (BS5)

[0615] TCK6 Reconstructed system clock in the sixth bus node (BS6)

[0616] TCK6i Reconstructed system clock in the sixth bus node (BS6), from the sixth two-wire data bus interface (OWS6) of the sixth bus node (BS6)

[0617] TCK6o Reconstructed system clock in the sixth bus node (BS6), used for the master two-wire data bus interface (OWM6) of the sixth bus node (BS6)

[0618] TCK6ao reconstructed system clock in the sixth bus node (BS6), used for the first master two-wire data bus interface (OWM6a) of the sixth bus node (BS6)

[0619] TCK6bo reconstructed system clock in the sixth bus node (BS6), used for the second master two-wire data bus interface (OWM6b) of the sixth bus node (BS6)

[0620] TCK n Reconstructed system clock in the considered bus node (BSn)

[0621] TDI serial data input (test data input)

[0622] TDOz Third time slot or bus node send time slot. The third time slot is typically used to transmit the TDO signal of the JTAG test port according to IEEE Standard 1149 from the bus node with the call for send authorization to the bus master (BM). However, it is not mandatory to place this time slot in the third time position. Other time sequences are also possible.

[0623] TDo serial data output (test data output) and data signal received by bus master (BM)

[0624] TDO1i comes from the first two-wire data bus interface (OWS1) of the first bus node (BS1),

[0625] Reconstructed data signal in the first bus node (BS1)

[0626] TDO1o is used for the master two-wire data bus interface (OWM1) of the first bus node (BS1),

[0627] Reconstructed data signal in the first bus node (BS1)

[0628] TDO1ao is used for the first master two-wire data bus interface (OWM1a) of the first bus node (BS1), the reconstructed data signal in the first bus node (BS1)

[0629] TDO1bo is used for the reconstructed data signal in the first bus node (BS1) of the second master two-wire data bus interface (OWM1b) of the first bus node (BS1)

[0630] TDO2i is from the second two-wire data bus interface (OWS2) of the second bus node (BS2),

[0631] The reconstructed data signal in the second bus node (BS2)

[0632] TDO2o is used for the master two-wire data bus interface (OWM2) of the second bus node (BS2).

[0633] The reconstructed data signal in the second bus node (BS2)

[0634] TDO2ao is used for the reconstructed data signal in the second bus node (BS2) of the first master two-wire data bus interface (OWM2a) of the second bus node (BS2)

[0635] TDO2bo is used for the reconstructed data signal of the second bus node (BS2) of the second master two-wire data bus interface (OWM2b) and the second bus node (BS2)

[0636] TDO3i is from the third two-wire data bus interface (OWS3) of the third bus node (BS3).

[0637] Reconstructed data signal in the third bus node (BS3)

[0638] TDO3o is used for the data signal reconstructed in the third bus node (BS3) of the master two-wire data bus interface (OWM3) of the third bus node (BS3)

[0639] TDO3ao is used for reconstructing the data signal in the third bus node (BS3) of the first master two-wire data bus interface (OWM3a) of the third bus node (BS3)

[0640] TDO3bo is used for reconstructing the data signal in the third bus node (BS3) of the second master two-wire data bus interface (OWM3b) of the third bus node (BS3)

[0641] TDO4i Reconstructed data signal from the fourth bus node (BS4) of the fourth two-wire data bus interface (OWS4) of the fourth bus node (BS4)

[0642] TDO4o is used for reconstructing the data signal in the fourth bus node (BS4) of the master two-wire data bus interface (OWM4) of the fourth bus node (BS4)

[0643] TDO4ao is used for reconstructing the data signal in the fourth bus node (BS4) of the first master two-wire data bus interface (OWM4a) of the fourth bus node (BS4)

[0644] TDO4bo is used for reconstructing the data signal in the fourth bus node (BS4) of the second master two-wire data bus interface (OWM4b) of the fourth bus node (BS4)

[0645] TDO5i Reconstructed data signal in the fifth bus node (BS5) from the fifth two-wire data bus interface (OWS5) of the fifth bus node (BS5)

[0646] TDO5o is used for reconstructing the data signal in the fifth bus node (BS5) of the master two-wire data bus interface (OWM5) of the fifth bus node (BS5)

[0647] TDO5ao is used for reconstructing the data signal in the fifth bus node (BS5) of the first master two-wire data bus interface (OWM5a) of the fifth bus node (BS5)

[0648] TDO5bo is used for reconstructing the data signal in the fifth bus node (BS5) of the second master two-wire data bus interface (OWM5b) of the fifth bus node (BS5)

[0649] TDO6i Reconstructed data signal in the sixth bus node (BS6) from the sixth two-wire data bus interface (OWS6) of the sixth bus node (BS6)

[0650] TDO6o is used for reconstructing the data signal in the sixth bus node (BS6) of the master two-wire data bus interface (OWM6) of the sixth bus node (BS6)

[0651] TDO6ao is used for reconstructing the data signal in the sixth bus node (BS6) of the first master two-wire data bus interface (OWM6a) of the sixth bus node (BS6)

[0652] TDO6bo is used for reconstructing the data signal in the sixth bus node (BS6) of the second master two-wire data bus interface (OWM6b) of the sixth bus node (BS6)

[0653] TDO n The serial data to be transmitted from the bus node (BSn) under consideration TIN0 first time slot. The first time slot is typically used to transmit the TMS signal of the JTAG test port according to IEEE Standard 1149 from the bus master (BM) to the corresponding bus node (BS1, BS2, BS3). However, it is not mandatory to put this time slot in the first time position. Other time sequences are also possible.

[0654] TINI1 second time slot. The second time slot is typically used to send a signal from the bus master to the bus nodes (BS1, BS2,

[0655] BS3) transmits the TDI signal of the JTAG test port according to IEEE Standard 1149. However, it is not mandatory to place this time slot in the second time position. Other time sequences are also possible.

[0656] TLR status "Test logic reset"

[0657] TMS mode input (test mode input) or test mode signal

[0658] TMS_TDI1 Combined TMS_TDI signal in the first bus node (BS1)

[0659] TMS_TDI1i Combined TMS_TDI signal in the first bus node (BS1) from the first two-wire data bus interface (OWS1) of the first bus node (BS1)

[0660] TMS_TDI1o Combined TMS_TDI signal in the first bus node (BS1) for the master two-wire data bus interface (OWM) of the first bus node (BS1)

[0661] TMS_TDI1ao Combined TMS_TDI signal in the first bus node (BS1) for the first master two-wire data bus interface (OWM1a) of the first bus node (BS1)

[0662] TMS_TDI1bo Combined TMS_TDI signal in the first bus node (BS1) for the second master two-wire data bus interface (OWM1b) of the first bus node (BS1)

[0663] TMS_TDI2 Combined TMS_TDI signal in the second bus node (BS2)

[0664] TMS_TDI2i Combined TMS_TDI signal in the second bus node (BS2) from the second two-wire data bus interface (OWS2) of the second bus node (BS2)

[0665] TMS_TDI2o Combined TMS_TDI signal in the second bus node (BS2) for the master two-wire data bus interface (OWM) of the second bus node (BS2)

[0666] TMS_TDI2ao Combined TMS_TDI signal in the second bus node (BS2) for the first master two-wire data bus interface (OWM2a) of the second bus node (BS2)

[0667] TMS_TDI2bo Combined TMS_TDI signal in the second bus node (BS2) for the second master two-wire data bus interface (OWM2b) of the second bus node (BS2)

[0668] TMS_TDI3 Combined TMS_TDI signal in the third bus node (BS3)

[0669] TMS_TDI3i Combined TMS_TDI signal in the third bus node (BS3) from the third two-wire data bus interface (OWS3) of the third bus node (BS3)

[0670] TMS_TDI3o Combined TMS_TDI signal in the third bus node (BS3) for the master two-wire data bus interface (OWM) of the third bus node (BS3)

[0671] TMS_TDI3ao Combined TMS_TDI signal in the third bus node (BS3) for the first master two-wire data bus interface (OWM3a) of the third bus node (BS3)

[0672] TMS_TDI3bo Combined TMS_TDI signal in the third bus node (BS3) for the second master two-wire data bus interface (OWM3b) of the third bus node (BS3)

[0673] TMS_TDI4 Combined TMS_TDI signal in the fourth bus node (BS4)

[0674] TMS_TDI4i Combined TMS_TDI signal in the fourth bus node (BS4) from the fourth two-wire data bus interface (OWS4) of the fourth bus node (BS4)

[0675] TMS_TDI4o Combined TMS_TDI signal in the fourth bus node (BS4) for the master two-wire data bus interface (OWM) of the fourth bus node (BS4)

[0676] TMS_TDI4ao Combined TMS_TDI signal in the fourth bus node (BS4) for the first master two-wire data bus interface (OWM4a) of the fourth bus node (BS4)

[0677] TMS_TDI4bo Combined TMS_TDI signal in the fourth bus node (BS4) for the second master two-wire data bus interface (OWM4b) of the fourth bus node (BS4)

[0678] TMS_TDI5 Combined TMS_TDI signal in the fifth bus node (BS5)

[0679] TMS_TDI5i Combined TMS_TDI signal in the fifth bus node (BS5) from the fifth two-wire data bus interface (OWS5) of the fifth bus node (BS5)

[0680] TMS_TDI5o Combined TMS_TDI signal in the fifth bus node (BS5) for the master two-wire data bus interface (OWM) of the fifth bus node (BS5)

[0681] TMS_TDI5ao Combined TMS_TDI signal in the fifth bus node (BS5) for the first master two-wire data bus interface (OWM5a) of the fifth bus node (BS5)

[0682] TMS_TDI5bo Combined TMS_TDI signal in the fifth bus node (BS5) for the second master two-wire data bus interface (OWM5b) of the fifth bus node (BS5)

[0683] TMS_TDI6 Combined TMS_TDI signal in the sixth bus node (BS6)

[0684] TMS_TDI6i Combined TMS_TDI signal in the sixth bus node (BS6) from the sixth two-wire data bus interface (OWS6) of the sixth bus node (BS6)

[0685] TMS_TDI6o Combined TMS_TDI signal in the sixth bus node (BS6) for the master two-wire data bus interface (OWM6) of the sixth bus node (BS6)

[0686] TMS_TDI6ao Combined TMS_TDI signal in the sixth bus node (BS6) for the first master two-wire data bus interface (OWM6a) of the sixth bus node (BS6)

[0687] TMS_TDI6bo Combined TMS_TDI signal in the sixth bus node (BS6) for the second master two-wire data bus interface (OWM6b) of the sixth bus node (BS6)

[0688] TMS_TDI n At the bus node under consideration (BS n ) combined in the TMS_TDI signal

[0689] TRST Optional reset input (test reset input)

[0690] TG1 Example of a transmission gate of the first bus node (BS1)

[0691] TG2 Example of a transmission gate of the second bus node (BS2)

[0692] TG3 Example of a transmission gate of the third bus node (BS3)

[0693] TGn Example of the transmission gate of the bus node (BSn) under consideration

[0694] TGCR Transmission Gate Control Register

[0695] The transmission gate control register of the bus node (BSn) under consideration by TGCRn

[0696] TOW differential signal level. The differential signal level on the two-wire data bus (b1b2b3b4) is the potential difference between the first single-wire data bus and the second single-wire data bus of the two-wire data bus (b1b2b3b4).

[0697] UDR2 Test Mode Controller Status "Write Data Register"

[0698] UIR2 Test Mode Controller Status "Write Instruction Register"

[0699] V bat Supply voltage of the bus node

[0700] V M. In the second voltage value range (V B2 ) which occurs when no other transmitter (T1a, T1b, T2a, T2b, T3a, T3b) is activated and therefore the pull circuit (R1a, R1b, R2a, R2b)) is turned on.

[0701] V 1H The first threshold value is a third voltage value range (V B3 ) and on the other hand the first voltage value range (V B1 ) and the second voltage value range (V B2 ) is separated. The first threshold is preferably equal to or similar to the third threshold (V 2H ). It is used to transfer data.

[0702] V 2L The second threshold value is the first voltage value range (V B1 ) and on the other hand the third voltage value range (V B3 ) and the second voltage value range (V B2 ) is separated. It is used to transmit the clock.

[0703] V 2H The third threshold value is a third voltage value range (V B3 ) and on the other hand the first voltage value range (V B1 ) and the second voltage value range (V B2 ) is separated. The third threshold is preferably equal to or similar to the first threshold (V1H ). It is used to transfer data.

[0704] V B1 The first voltage value range is towards the second voltage value range (V B2 ) passes the second threshold (V 2L ) limit. It is used to transmit the clock.

[0705] V B2 The first voltage range (V B1 ) and the third voltage value range (V B3 ) between the second voltage value range, which is towards the first voltage value range (V B1 ) passes the second threshold (V 2L ) limit and towards the third voltage value range (V B3 ) through the third threshold (V 2H ) and / or by a first threshold (V 1H ) restrictions. It is used to transfer data.

[0706] V B3 The third voltage value range is towards the second voltage value range (V B2 ) through the third threshold (V 2H ) and / or by a first threshold (V 1H ) restrictions. It is used to transfer data.

[0707] V ext1 External power supply voltage

[0708] -V IO First differential voltage value level

[0709] V IO A third differential voltage value level and a supply voltage for a pull circuit, where the pull circuit is a voltage divider (R1a, R2a; R1b, R2b).

[0710] V IO1 The power supply voltage of the switchable current source (T2a, T2b) of the bus master, ie the main processor. The voltage level is in the third voltage value range (V B3 )middle.

[0711] V IO2 Switchable current source of a bus node, ie an integrated circuit or a system to be tested or controlled

[0712] (T3a, T3b) power supply voltage. The voltage level is in the third voltage value range (V B3 )middle.

[0713] VREF reference voltage

Claims

1. A method for initializing a differential two-wire data bus, wherein: The differential two-wire data bus is located between a first sub-device as a bus master (BM) and at least two other sub-devices as bus nodes, the differential two-wire data bus comprises a first single-wire data bus and a second single-wire data bus, the second single-wire data bus is divided by at least two bus nodes into at least two two-wire data bus sections having a first single-wire data bus section and a second single-wire data bus section, and is terminated by at least one bus node of the bus nodes as an end bus node, The following steps are included: Determining a new bus node address by the bus master; storing the bus node address by the bus master (BM) in a bus node address register (BKADR) of a bus node which is the bus node under consideration, wherein the bus master (BM) and the bus node under consideration are connected to one another via one or more two-wire data bus segments, and the bus node address register (BKADR) is a data register (DR) of a modified JTAG interface or a part of a data register (DR) of a modified JTAG interface of the bus node under consideration or a part of an instruction register (IR) of a modified JTAG interface of the bus node under consideration, wherein the modified JTAG interface is characterized in that it has a test controller with a state diagram according to the IEEE 1149 standard or a substandard thereof; One or more two-wire data bus segments are connected to one or more further two-wire data bus segments by closing a transmission gate (TG) of the bus node under consideration, wherein, while the transmission gate (TG) is closed, the bus node is prevented from storing a bus node address in a bus node address register (BKADR) of the bus node under consideration by the bus master (BM).

2. The method for initializing a differential two-wire data bus according to claim 1, comprising the step of storing a command for opening a transmission gate (TG) in the instruction register (IR) or in the transmission gate control register (TGCR) of the modified JTAG interface of the bus node under consideration.

3. A method for initializing a differential two-wire data bus according to claim 1, comprising the step of checking correct addressing of at least one bus node by cyclically writing and reading.

4. The method for initializing a differential two-wire data bus according to claim 3 comprises the steps of determining the number of correctly addressable bus nodes by the bus master (BM), comparing the number of correctly addressable bus nodes with a rated number, and triggering at least one signal or at least one measure by the bus master or a connected system based on the number.

5. The method for initializing a differential two-wire data bus according to claim 3 or 4, wherein: Correct addressing of at least one bus node is checked by cyclic writing and reading of the bypass register.

6. A method for transmitting data after initializing the differential two-wire data bus according to the method for initializing the differential two-wire data bus according to any one of claims 1 to 4, comprising the following steps: transmitting a transmit address to all reachable bus nodes simultaneously by the bus master (BM) writing the transmit address into transmit registers (SR) of all bus nodes, wherein the respective transmit register (SR) of the respective bus node is part of an instruction register (IR) or a data register or a part of a data register of a modified JTAG interface of the bus node, and wherein the bus node address register (BKADR) is not part of the register in question; By means of a predetermined comparison algorithm, the send address in the send register (SR) is compared by each bus node with the bus node address in the bus node address register (BKADR); activating the sending capability for the respective bus node at a time specified for this purpose, if the comparison algorithm of the comparison previously carried out by the respective bus node results in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR); If the comparison algorithm of the comparison previously performed by the respective bus node does not result in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR), the send capability for the respective bus node is deactivated.

7. A method for transmitting data after initializing the differential two-wire data bus according to the method for initializing the differential two-wire data bus according to any one of claims 1 to 4, comprising the following steps: transmitting a transmit address to all reachable bus nodes simultaneously by the bus master (BM) writing the transmit address into transmit registers (SR) of all bus nodes, wherein the respective transmit register (SR) of the respective bus node is part of an instruction register (IR) or a data register or a part of a data register of a modified JTAG interface of the bus node, and wherein the bus node address register (BKADR) is not part of the register in question; By means of a predetermined comparison algorithm, the send address in the send register (SR) is compared by each bus node with the bus node address in the bus node address register (BKADR); activating the receiving capability of the respective bus node for the content of a predetermined data register of the respective bus node if the comparison algorithm of the comparison previously carried out by the respective bus node results in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR); If the comparison algorithm of the comparison previously performed by the corresponding bus node does not result in a sufficient match with the combination expected for a send permission, consisting of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR), the receive capability of the corresponding bus node is deactivated with respect to the contents of the predetermined data register of the corresponding bus node for the send capability of the corresponding bus node.

8. A method for transmitting data after initializing the differential two-wire data bus according to the method for initializing a differential two-wire data bus according to any one of claims 1 to 4, comprising the following steps: transmitting a transmit address to all reachable bus nodes simultaneously by the bus master (BM) writing the transmit address into transmit registers (SR) of all bus nodes, wherein the respective transmit register (SR) of the respective bus node is part of an instruction register (IR) or a data register or a part of a data register of a modified JTAG interface of the bus node, and wherein the bus node address register (BKADR) is not part of the register in question; By means of a predetermined comparison algorithm, the send address in the send register (SR) is compared by each bus node with the bus node address in the bus node address register (BKADR); activating the receiving capability of the respective bus node for the content of the predetermined content of the instruction register (IR) of the respective bus node to allow a predetermined command to the instruction decoder (IRDC) of the modified JTAG interface of the respective bus node, if the comparison algorithm of the comparison previously performed by the respective bus node results in a sufficient match with the combination of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR) expected for a send permission; If the comparison algorithm of the comparison previously performed by the corresponding bus node does not result in a sufficiently consistent combination with the combination of the bus node address stored in its bus node address register (BKADR) and the send address stored in its send register (SR) expected for the send permission, the receiving capability of the corresponding bus node is deactivated for the content of the predetermined content of the instruction register (IR) of the corresponding bus node in order to inhibit the predetermined command of the instruction decoder (IRDC) of the modified JTAG interface of the corresponding bus node.

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