Method for writing electrically erasable programmable non-volatile memory and integrated circuit

Abstract

Embodiments of the present disclosure relate to methods and integrated circuits for writing to electrically erasable programmable non-volatile memory. In one embodiment, the method includes: operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus; generating an oscillating signal by the oscillator circuit; and conditioning the oscillating signal by the filter circuit to generate a clock signal for timing a write cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French patent application No. 1903667, filed on April 5, 2019, which is incorporated herein by reference. Technical Field

[0003] Implementations and embodiments relate to integrated circuits of non-volatile memory, and in particular, to writing to electrically erasable programmable read-only memory (EEPROM). Background Art

[0004] An integrated circuit of an EEPROM memory generally includes a memory plane for storing stored data, a decoder for accessing the data in the memory plane, and a peripheral part.

[0005] The peripheral part usually includes a logic part, which is for example for a 5V power supply, which usually includes control components and a communication interface such as an I2C ("Inter-Integrated Circuit", a standard well known to those skilled in the art) bus interface. The peripheral part also includes an analog part, which includes a high voltage or voltage ramp generator, an amplifier and a reference current generator. Summary of the invention

[0006] It is desirable to reduce the overall size of integrated circuit devices.

[0007] Techniques have been provided for reducing the size of an EEPROM memory plane.

[0008] However, for a given total memory capacity, the advantage of reducing the memory plane is offset by the overall size of the peripheral portion. This phenomenon is more severe for the lowest memory densities.

[0009] An efficiency parameter may be defined for the area of ​​a memory plane "AE", where AE specifies the ratio of (area of ​​memory plane + area of ​​decoder) / (total area of ​​memory).

[0010] For example, for 128 kbit memory, AE>50% in 0.18 μm technology and AE<30% in 0.11 μm technology.

[0011] Therefore, shrinking the memory plane does not lead to significant gains in the overall product, especially with respect to low density.

[0012] Furthermore, many constraints prevent reducing the size of components in the peripheral portion.

[0013] The peripheral part includes high-voltage components, the size of which cannot be reduced in practice due to voltage stability constraints. The peripheral part also includes analog components subject to matching constraints (which specify the design of its components according to common terms, with little variation in characteristics from each other), which require large-sized components.

[0014] Components that meet standards such as communication interfaces (eg, I2C interfaces) are provided with components dedicated to their use, and these components do not benefit, or only slightly benefit, from manipulating their design in order to reduce their size.

[0015] However, it is desirable to reduce the overall size of the peripheral portion of the EEPROM memory in order to improve the area efficiency parameter AE of the memory plane.

[0016] EEPROM memories usually require an oscillator for activating the charge pump. The oscillator is preferably relatively fast. The oscillation frequency may be of moderate precision (eg, between 20 MHz and 30 MHz).

[0017] Furthermore, EEPROM memories typically require a clock for timing write operations, and advantageously the write time is derived from this clock as accurately as possible. The clock may be slow (typically of the order of 1 MHz), but is preferably accurate.

[0018] In the context of EEPROM technology, and within the constraints of minimum size, it is difficult to produce an accurate oscillator, especially if the oscillator should be fast.

[0019] Therefore, an EEPROM memory usually includes a stable signal generator dedicated to clock signal generation, while other generators are used to generate other oscillating signals, especially other oscillating signals with a high frequency.

[0020] Embodiments provide for generating a stable frequency based on a time reference that already exists on the circuit and is used for other purposes, and when the time reference is used to stabilize the frequency, it is not used for its original purpose.

[0021] A further embodiment provides that the area of ​​the peripheral portion can be reduced and the area efficiency parameter AE of the memory plane can be improved.

[0022] According to one embodiment, in this regard, a method of writing to an electrically erasable programmable read-only memory (EEPROM) is provided, the method comprising: in a write cycle: operably connecting a filter circuit belonging to a communication interface to an oscillator circuit, the communication interface being physically connected to a bus; and generating an oscillating signal via the oscillator circuit, and regulating the oscillating signal using the filter circuit to generate a clock signal for timing the write cycle.

[0023] A write cycle designates a phase dedicated to writing data into the memory, and typically includes erasing followed by programming of one or more memory cells.

[0024] Preferably, the communication interface is of the I2C type, ie of the “Inter-Integrated Circuit” type.

[0025] Thus, according to this embodiment, there is provided the use of a filter circuit provided for the communication interface to condition the oscillating signal, thereby generating a sufficiently stable clock signal for timing the write cycle.

[0026] The method according to this embodiment thus enables the above two constraints to be met using only a single oscillator circuit.

[0027] According to one implementation, the filter circuit is operably disconnected from the communication interface before operably connecting the filter circuit to the oscillator circuit.

[0028] During a write cycle, exchanges on the bus via the communication interface are ignored, which is conventionally done, for example, by forcing a reset of an output flip-flop for generating a circuit selection signal, thereby preventing, for the duration of the write cycle, the circuit from being selected by commands transmitted to a communication interface of I2C type. However, false signals originating from the outside can be transmitted on the bus and operatively disconnect the filter circuit from the communication interface, thereby preventing disturbances in the filter circuit originating from the outside.

[0029] For example, before operably connecting the filter circuit to the oscillator circuit, the filter circuit is operably disconnected from the oscillator circuit and the filter circuit is operably connected to the communication interface.

[0030] Rather, this allows communication on the bus with a communication interface using the filter circuit to not be disturbed by the oscillation signal of the oscillator circuit.

[0031] According to one implementation, operatively connecting the filter circuit and the oscillator circuit includes: utilizing the mode selection signal to perform a logic operation on a signal originating from the oscillator circuit and intended for the filter circuit, thereby delivering the signal to the filter circuit based on the signal originating from the oscillator circuit. Similarly, operatively connecting the filter circuit and the oscillator circuit includes: utilizing the mode selection signal to perform a logic operation on a signal originating from the filter circuit and intended for the oscillator circuit, thereby delivering the signal to the oscillator circuit based on the signal originating from the filter circuit.

[0032] According to one implementation, operably disconnecting the filter circuit and the communication interface includes: utilizing a mode selection signal to perform a logical operation on a signal originating from the communication interface and intended for the filter circuit, the mode selection signal determining a result of the logical operation on the signal having a constant arbitrary value; and utilizing a mode selection signal to perform a logical operation on a signal originating from the filter circuit and intended for the communication interface, the mode selection signal determining a result of the logical operation on the signal having a constant arbitrary value.

[0033] According to one implementation, the filter circuit has an adjustable time constant, and the time constant is adjusted to a given value with a given accuracy before adjusting the oscillating signal with the filter circuit.

[0034] In practice, this makes it possible to improve the accuracy of the clock signal thus generated via this adjustment, the time constant of the filter circuit being able to withstand slight instabilities in the manufacturing process, which are thus corrected by this adjustment, but being otherwise very stable with respect to temperature, power supply and aging conditions.

[0035] According to an alternative, the frequency of the oscillating signal is dynamically adjustable, and the regulation of the oscillating signal comprises a dynamic adjustment of the frequency of the oscillating signal relative to a time constant of the filter circuit.

[0036] According to one implementation defined below, this alternative may advantageously correspond to the use of an oscillator circuit capable of generating a high frequency for clocking the charge pump.

[0037] Thus, the frequency of the oscillating signal can be dynamically calibrated with respect to instantaneous changes (eg, due to temperature, voltage, and aging conditions) based on the above-mentioned time constants which are inherently stable with respect to the above-mentioned conditions.

[0038] According to one implementation of this alternative, the above-mentioned adjustment of the oscillator signal is performed at the beginning of each write cycle.

[0039] Calibration once per write cycle is sufficient to compensate for the period during which frequency changes occur.

[0040] According to one implementation of this alternative scheme, the above-mentioned dynamic adjustment of the frequency of the oscillation signal includes: counting the number of cycles of the oscillation signal within the duration of the time constant, adjusting the frequency level of the oscillation frequency, and repeating the counting and adjustment until the number of count cycles closest to the preset target number is reached.

[0041] According to one implementation of this alternative solution, generating the clock signal further includes: dividing the frequency of the adjusted oscillation signal.

[0042] According to one implementation of this alternative, the method further comprises, in a write cycle, generating a write high voltage, the generating the write high voltage comprising switching the capacitive element to the supply voltage, the switching being timed by an oscillation signal generated by the oscillator circuit.

[0043] According to another alternative, generating the oscillating signal comprises an accumulation of basic delays, and adjusting the oscillating signal comprises inserting in said accumulation an additional delay equal to a time constant of the filter circuit, the accumulation of basic delays being negligible in duration relative to the additional delays.

[0044] This alternative corresponds to the use of a conventional ring oscillator for generating the clock signal, but has the advantage that the filter circuit of the communication interface is reused when the communication interface is not used for this purpose.

[0045] According to another embodiment, an integrated circuit of an electrically erasable programmable non-volatile memory is provided, the integrated circuit including: a state machine configured to control a write operation in a write cycle, the write cycle being timed by a clock signal; a communication interface including a filter circuit, and the communication interface being physically connected to a bus; and a component for generating a clock signal, which includes an oscillator circuit and is configured to: in a write cycle: operably connect the filter circuit to the oscillator circuit, generate an oscillation signal using the oscillator circuit, and regulate the oscillation signal using the filter circuit, thereby generating a clock signal.

[0046] According to one embodiment, the means for generating the clock signal is configured to operatively disconnect the filter circuit from the communication interface before operatively connecting the filter circuit to the oscillator circuit.

[0047] According to one embodiment, the filter circuit is intended to be operatively disconnected from the oscillator circuit and to be operatively connected to the communication interface before it is operatively connected to the oscillator circuit.

[0048] According to one embodiment, in order to operatively connect the filter circuit and the oscillator circuit, the means for generating the clock signal comprises: a logic gate connected to the input of the filter circuit, the logic gate being configured to generate a signal on the input of the filter circuit in the presence of a mode selection signal, in dependence on a signal originating from the oscillator circuit. And, the means for generating the clock signal further comprises: a logic gate connected to the output of the filter circuit, the logic gate being configured to generate a signal on the input of the oscillator circuit in the presence of a mode selection signal, in dependence on a signal on the output of the filter circuit.

[0049] According to one embodiment, in order to operably disconnect the filter circuit and the communication interface, the component for generating a clock signal includes: logic gates connected to the input of the filter circuit and the output of the filter circuit, respectively, and these logic gates are configured to generate a signal with a constant arbitrary value in the presence of a mode selection signal, which is the same for the signal intended for the filter circuit, the signal originating from the communication interface or the signal at the output of the filter.

[0050] According to one embodiment, the filter circuit has an adjustable time constant, and the means for generating the clock signal is configured to adjust the time constant to a given value with a given accuracy.

[0051] According to a first alternative, the oscillator circuit comprises adjustment means capable of dynamically adjusting the frequency of the oscillating signal on command, and the means for generating the clock signal are configured to control the dynamic adjustment of the frequency of the oscillating signal relative to the time constant of the filter circuit for regulating the oscillating signal.

[0052] According to one embodiment of the first alternative, the adjustment component of the oscillator circuit comprises a capacitive element with a controllable capacitance value, or a supply current generator with a controllable current strength.

[0053] According to an embodiment of the first alternative, the means for generating a clock signal are configured to adjust the oscillating signal at the beginning of each write cycle.

[0054] According to an embodiment of the first alternative, the adjustment component of the oscillator circuit includes a counter, which is configured to count the number of cycles of the oscillation signal within the duration of the time constant, and the counter is configured to adjust the frequency of the oscillation signal to a basic level, and is configured to repeat counting and adjustment until the number of count cycles closest to the preset target number is reached.

[0055] According to one embodiment of the first alternative, the means for generating a clock signal further comprises a frequency divider configured to divide the frequency of the regulated oscillation signal.

[0056] According to an embodiment of the first alternative, the integrated circuit further comprises a charge pump circuit configured to generate the write high voltage, the generating the write high voltage comprising switching the capacitive element to the supply voltage, the switching being timed by an oscillation signal generated by the oscillator circuit.

[0057] According to another alternative, the oscillator circuit comprises a ring oscillator configured to generate an accumulation of basic delays on the signal, and the means for generating the clock signal is configured to connect a filter circuit to the ring oscillator circuit, thereby introducing an additional delay equal to a time constant of the filter circuit, the accumulation of basic delays being negligible in duration relative to the additional delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Other advantages and features of the invention will emerge in a non-limiting manner from the detailed description of embodiments and implementations in the accompanying drawings, in which:

[0059] Figure 1-Figure 5 , Fig. 6A and Figure 6B An implementation according to an embodiment is illustrated. DETAILED DESCRIPTION

[0060] Figure 1 An implementation of a method of writing to an electrically erasable programmable read-only memory "EEPROM" is illustrated. The EEPROM memory comprises in particular: a memory plane comprising memory cells, which are units in which bits can be recorded; an oscillator circuit 31; and a communication interface 80 comprising a filter circuit 33. The communication interface 80 is intended for communication on a bus BUS and is physically connected to the bus BUS. The filter circuit 33 may conventionally comprise a capacitive element and a resistive element. Exchanges on the bus BUS via the communication interface 80 are intended to be ignored during a write cycle.

[0061] The write cycle of the write method includes, for example, erasing followed by programming of one or more memory cells.

[0062] The method comprises the following steps in a write cycle 100: operatively connecting 20 a filter circuit 33 belonging to a communication interface 80 with an oscillator circuit 31, the communication interface 80 being physically connected to a bus BUS; and generating an oscillation signal Fosc via the oscillator circuit 31, and regulating 35 the oscillation signal Fosc using the filter circuit 33, thereby generating 30 a clock signal CLK for timing 40 the write cycle.

[0063] An independent base clock of the state machine may, for example, make it possible to time the implementation of the method before generating the clock signal for timing 40 the write cycle.

[0064] In this example, the filter circuit 33 has an adjustable time constant T and, before the oscillating signal Fosc is conditioned 35 by means of the filter circuit 33 , the time constant T is adjusted to a given value Tosc with a given accuracy.

[0065] Adjusting the time constant T can be achieved by means of an adjustment bit (according to the usual terminology, a "trimming bit") stored in a non-volatile register (e.g., a portion of a memory plane dedicated to this purpose). The adjustment bit can control the switching of the corresponding capacitive or resistive element in order to compensate for variations in the effective capacitance value or the effective resistance value due to the manufacturing method. The adjustment bit is factory-set as a function of the effective capacitance value or the effective resistance value and the target time constant Tosc.

[0066] exist Figure 1 In the representation of , the adjustment of the time constant T to the value Tosc is performed in step 20, which is provided for operatively connecting the filter circuit 33 with the oscillator circuit 31. However, the adjustment of the time constant T is not necessarily performed at the same time as the operative connection of the filter circuit and the oscillator circuit, but the adjustment of the time constant T can be performed before or after the above connection.

[0067] Prior to operatively connecting 20 the filter circuit to the oscillator circuit, it is advantageous to operatively disconnect the filter circuit 33 and the communication interface 80 .

[0068] In fact, before the filter circuit 33 is operably connected to the oscillator circuit 31, the configuration of the device can make the filter circuit 33 operably disconnected from the oscillator circuit 31 and make the filter circuit 33 operably connected to the communication interface 80 according to the first destination of the filter circuit 33.

[0069] The write cycle 100 for erasing and programming the memory cell may further comprise generating 90 a write high voltage HV, which is advantageously performed with the aid of a charge pump. In this case, generating the write high voltage HV comprises switching a capacitive element to provide the voltage, the switching being timed by a fast oscillating signal Fosc (e.g., in the order of 10 MHz to 100 MHz). The stability of the fast oscillating signal is not critical for generating the write high voltage using a charge pump, and the frequency of the fast oscillating signal may vary by about 25% without affecting the operation of the charge pump.

[0070] However, the time constant of the filter circuit Tosc is itself very stable and the fast oscillating signal can be stabilized via the above-mentioned regulation 35 for obtaining a sufficiently stable clock signal CLK for timing 40 the write cycle.

[0071] In a specific example, the fast oscillation signal Fosc is generated by an oscillator circuit 31 , and generating 30 the clock signal further comprises: adjusting the frequency (not shown) of the adjusted (fast) oscillation signal Fosc.

[0072] In practice, the frequency of the clock signal CLK used for timing the write cycle is conventionally much lower than the frequency of the fast oscillating signal Fosc. For example, the frequency of the clock signal CLK is not greater than 2 MHz, or even not greater than 1 MHz.

[0073] Figure 2 One embodiment of an integrated circuit of an electrically erasable and programmable non-volatile memory NVM is illustrated.

[0074] The integrated circuit NVM comprises: a state machine ME configured to control write operations in a write cycle timed by a clock signal CLK; a communication interface INTB comprising a filter circuit RFt and physically connected to a bus BUS; and means for generating a clock signal GENCLK comprising an oscillator circuit RGOSC.

[0075] As previously mentioned, the state machine ME may include an independent basic clock for timing the initial operation, so that the generation of the clock signal CLK may be introduced ( Figure 1 method).

[0076] The component for generating the clock signal GENCLK is configured to: operatively connect the filter circuit RFt with the oscillator circuit RGOSC; generate an oscillation signal Fosc using the oscillator circuit RGOSC; and adjust the oscillation signal using the filter circuit RFt to generate the clock signal CLK in a write cycle.

[0077] The communication interface INTB is an interface having, for example, an I2C type (ie “Inter-Integrated Circuit” type) serial bus BUS and communicating according to a protocol of the same name.

[0078] The I2C bus BUS includes two horizontal channels: a serial data channel SDA and a serial clock channel SCL. The two channels carry signal frames that can have a high level or a low level.

[0079] The low pass filter circuit LPF is intended to filter positive pulses on a low level or negative pulses on a high level less than 50ns at the SDA input and the SCL input.

[0080] In communications according to the I2C protocol, a frame start condition (according to the official term "START") known to those skilled in the art includes a high-to-low transition (falling edge) on SDA when SCL is high, and a frame stop condition (according to the official term "STOP") includes a low-to-high transition (rising edge) on SDA when SCL is high.

[0081] Internal delays are added to the SDA and SCL signals to ensure that an SDA transition close to an SCL transition does not generate a START or STOP condition. An SDA transition can occur at time t after the SCL rising edge, or at time t before the SCL falling edge, to trigger a START or STOP condition.

[0082] This is confirmed by delaying the SCL rising edge by duration 2t using filter circuit R2t, and delaying the SDA rising and falling edges by period t through filter circuit RFt.

[0083] The delayed SCL signal is the input of a dual edge triggered D-type flip-flop FFD, whose clocks are the delayed SDA signal and its complement respectively. The output of the flip-flop FFD forms the input of an RS-type flip-flop FFRS, which generates a chip select signal CSR and resets the flip-flop FFD.

[0084] According to one feature of EEPROM memory integrated circuits that communicate via the I2C protocol, a write cycle begins after receiving a legitimate write command that ends with a STOP condition.

[0085] During the write operation (which usually lasts a few milliseconds), the memory does not respond to any commands from the I2C bus. This means that the SDA and SCL data, as well as the detection of START and STOP conditions, will be ignored.

[0086] Depending on the architecture used, the write circuit relies on a clock based sequencer comprising an independent base clock of the state machine ME and a clock input to a counter (not shown) which determines the erase pulse time and / or the programming pulse time and / or the write cycle time.

[0087] By operatively connecting the filter circuit RFt to the oscillator circuit RGOSC, the time constant T of the filter circuit RFt, R2t (in this example the filter circuit RFt) of the communication interface INTB which is not used during the write cycle is in this respect re-used.

[0088] The low pass filter circuits LPF are also not used during the write cycle and their time constants can also be reused for generating a clock signal to time the write cycle.

[0089] In fact, any element with a time constant that is not used in the write cycle (usually a filter circuit) can be used to generate the clock signal.

[0090] Furthermore, it is conceivable to use a combination of filters by cascading filters in two-by-two, three-by-three, or four-by-four configurations.

[0091] For example, before operatively connecting the filter circuit RFt with the oscillator circuit RGOSC, the means for generating the clock signal GENCLK is configured to operatively disconnect the filter circuit RFt from the communication interface INTB.

[0092] Indeed, in this example, before being operatively connected to the oscillator circuit RGOSC, the filter circuit RFt is intended to be operatively disconnected from the oscillator circuit RGOSC and operatively connected to the communication interface INTB.

[0093] Of course, "operably connected" and "operably disconnected" should be understood to mean that connection and disconnection are not physically performed, but rather mean that access to the filter functionality (for example by means of a selection logic signal (wrt)) is enabled or disabled in a circuit physically connected to all its constituent elements (filter circuit RFt, communication interface INTB and oscillator circuit RGOSC).

[0094] For example, in order to operatively connect the filter circuit RFt and the oscillator circuit RGOSC, the means for generating the clock signal GENCLK comprises a logic gate, in particular a NAND gate controlled by the mode selection logic signal wrt=1.

[0095] The logic gate is connected to an input inRFt of the filter circuit and to an output outOSC of the oscillator circuit and is configured to supply a signal to the input inRFt of the filter circuit in dependence on a signal outOSC originating from the oscillator circuit RGOSC and intended for the filter circuit RFt.

[0096] In fact, reference Figure 2 , the mode selection signal wrt=1 and the oscillation signal outOSC from the oscillator circuit are applied to the input of the NAND gate NE1, thereby generating the inversion of the signal outOSC. The output from the NAND gate NE1 is inverted by the NAND gate NE2, and the NAND gate NE2 receives the signal set to 1 from the NAND gate NE3, and the NAND gate NE3 receives the signal wrtN=0 inverted from wrt=1 by the inverter IV3.

[0097] Furthermore, a logic gate is connected to an input inOSC of the oscillator circuit and to an output outRFt of the filter circuit and is configured to generate a signal from the signal at the output outRFt of the filter circuit and intended for the oscillator circuit.

[0098] In fact, reference Figure 2, the mode selection signal wrt=1 and the signal originating from the output outRFt of the filter circuit are applied to the input of the NAND gate NE4, thereby generating an inverted signal of the signal inOSC, which itself is inverted by the inverter IV 4 at the input inOSC of the oscillator circuit.

[0099] Meanwhile, in order to operably disconnect the filter circuit RFt and the communication interface INTB, the means for generating the clock signal GENCLK includes the above-mentioned logic gate controlled by the mode selection signal wrt=1.

[0100] In the case wrt=1, the logic gate is configured to supply a signal with a constant arbitrary value, regardless of the value at the filter input, originating from the SDA communication interface, or the output value outRFt from the filter intended for the communication interface.

[0101] In fact, as described above, the inverter IV3 transmits the signal wrtN=0 to the input of the NAND gate NE3, which thereby generates a signal having a constant arbitrary value set to 1, regardless of the value of the SDA signal originating from the communication interface INTB on its other input. In addition, the signal wrtN=0 is applied to the input of the logic gate NE5, which thereby generates a signal having a constant arbitrary value set to 1 to the flip-flop FFD (the two flip-flops FFD receive opposite signals, and the signal of the constant arbitrary value is inverted for one of the two flip-flops FFD), regardless of the value of the signal originating from the output of the filter circuit outRFt applied to its other input.

[0102] Furthermore, when the filter circuit RFt is operatively connected to the oscillator circuit RGOSC, the reset signal of the RS flip-flop FFRS is active (set to 1). The reset signal is active in response to an active STOP condition, so that writing in the memory plane is started before the filter circuit RFt is connected to the oscillator circuit RGOSC. The reset signal will return to 0 at the end of the write cycle, after the filter circuit RFt has been operatively reconnected to the interface INTB.

[0103] Thus, during a write cycle, any possible parasitic signals originating from the outside via the bus BUS (in particular the SDA line) do not disturb the regulation performed by the filter circuit RFt. And conversely, outside a write cycle, communication on the bus with the communication interface using the filter circuit is not disturbed by the oscillation signal of the oscillator circuit.

[0104] Furthermore, the time constant T of the filter circuit RFt is adjustable. In order to fully control the value of the time constant T of the write cycle, the means for generating the clock signal GENCLK is configured to adjust the time constant T to a given value Tosc with a given accuracy.

[0105] To avoid confusion, Tosc does not specify the period of the signal Fosc (Tosc≠1 / Fosc). Tosc specifies the time constant of the filter circuit RFt, while Fosc specifies the oscillation signal or the frequency of the oscillation signal, and the generation of the oscillation signal Fosc is not only based on the time constant Tosc of the filter circuit RFt.

[0106] The adjusted value Tosc corresponds to the value on which the regulation of the oscillating signal Fosc is based, and the precision corresponds to the elementary increment for modifying the time constant.

[0107] As previously mentioned Figure 1 According to the method described, the filter circuit RFt can actually provide adjustment of its time constant through internal components, and the adjustment can be achieved by modifying the connection of the transistor, resistor or capacitor of the filter circuit using a switch controlled by the adjustment bit BitTr stored in the non-volatile register NVREG.

[0108] This embodiment of the memory integrated circuit NVM corresponds to a first alternative. In this alternative, the oscillator circuit RGOSC comprises a ring oscillator RGOSC configured to generate an accumulation of a basic delay t on a signal in order to generate an oscillation signal Fosc. The basic delay t is the switching time of the various inverters connected in series in the ring.

[0109] In practice, the ring oscillator RGOSC comprises a series of odd-numbered inverters IV1, IV2, NE0, the inverter NE0 being a NAND gate controlled in operation by the start signal RunOsc=1. Furthermore, the NAND gates NE1, NE2, NE4 and the inverter IV4, in addition to their function of operatively connecting and disconnecting the filter circuit RFt, form the series of odd-numbered inverters mentioned above (in addition to the inverters IV1, IV2, NE0 mentioned above). The inverters IV1, IV2 are optional and can be removed in order to reduce the number of elementary delays in the ring.

[0110] The means for generating the clock signal GENCLK are then configured to operatively connect the filter circuit RFt in the circuit of the ring oscillator RGOSC, thereby introducing an additional delay Tosc equal to the time constant of the filter circuit RFt. The accumulation of the basic delay t is negligible in duration relative to the additional delay Tosc, which therefore produces the above-mentioned adjustment of the oscillation signal Fosc, thereby generating a clock signal CLK capable of timing the write cycle.

[0111] Figure 3 In relation to the above Figure 2 Another alternative oscillator circuit OSC in the same embodiment as described above. In addition to the oscillator circuit OSC, the memory integrated circuit NVM comprises a Figure 2 The same elements as in the described embodiments are designated by reference numerals and will not be described again in detail here.

[0112] In this alternative, the oscillator circuit OSC comprises adjustment means MDYN capable of dynamically adjusting the frequency of the oscillation signal Fosc according to command.

[0113] In order to regulate the oscillating signal Fosc, the means for generating the clock signal GENCLK is configured to control a dynamic adjustment of the frequency of the oscillating signal Fosc relative to the time constant Tosc of the filter circuit RFt.

[0114] The component for generating the clock signal GENCLK is configured, for example, by means of Figure 2 The described logic gates and the mode selection signal wrt operatively connect the filter circuit RFt with the dynamic adjustment component MDYN of the oscillator circuit OSC.

[0115] Therefore, the dynamic adjustment component MDYN can calibrate the frequency of the oscillation signal Fosc based on the time constant Tosc of the filter circuit RFt. In this regard, reference may be made to the following description of Figure 4 and Figure 5 Description.

[0116] The integrated circuit may further include a charge pump circuit PCHV ( Fig. 6A ), the charge pump circuit PCHV is configured to generate a write high voltage, and the generation of the write high voltage includes switching the capacitive element to the power supply voltage, and the switching is timed by the oscillation signal Fosc generated by the oscillator circuit OSC.

[0117] In this respect, the oscillator circuit OSC is advantageously configured to generate an oscillating signal Fosc having a frequency of 10 MHz to 100 MHz.

[0118] The means for generating the clock signal GENCLK then advantageously comprise a frequency divider FDIV configured to divide the frequency of the conditioned oscillating signal Fosc for obtaining a clock signal CLK capable of timing the write cycle.

[0119] Oscillator circuits of this type, which are usually provided for charge pumps, can generate an oscillation signal Fosc which can vary by up to 25% if the oscillator circuit is not regulated.

[0120] Figure 4 An advantageous implementation allowing a precise adjustment of such an oscillating signal Fosc is illustrated.

[0121] The adjustment of the oscillating signal comprises comparing the number of periods in the oscillating signal Fosc with the duration of the time constant of the filter circuit Tosc 306. In other words, step 306 makes it possible to evaluate the effective frequency of the oscillating signal Fosc relative to a time base given by the time constant Tosc of the filter circuit.

[0122] The dynamic adjustment of the frequency of the oscillation signal Fosc is performed relative to the above-mentioned time constant Tosc.

[0123] For example, the adjustment of the oscillation signal is performed at the beginning of each write cycle.

[0124] In this example, dynamic adjustment of the frequency of the oscillating signal Fosc begins with initialization 300 in which an iteration counter is initialized with i=0 and the frequency of the oscillating signal Fosc is by default greater than the desired frequency of the regulated clock signal CLK (initially, K>N, see below).

[0125] The dynamic adjustment of the frequency of the oscillating signal Fosc includes: adjusting 302 the frequency of the oscillating signal at a basic level.

[0126] For example, connecting the capacitance element Ci or the power supply current generator Irefi in the oscillator circuit OSC makes it possible to reduce the frequency of the oscillation signal Fosc by a level.

[0127] The number K of periods of the oscillating signal Fosc is then counted 304 over the duration of the time constant Tosc of the filter circuit RFt.

[0128] The modifying 302 and counting 304 are then repeated until the counted number of cycles K closest to the preset target number N is reached.

[0129] The target number N is preset according to the desired frequency of the clock signal CLK and the duration of the time constant Tosc of the filter circuit RFt.

[0130] If K>N 306, and if the iteration counter i has not reached the maximum possible iteration limit (i=I) 308, the iteration counter is incremented i=i+1, and the modifying 302, counting 304 and testing 306, 308 are repeated.

[0131] If K≦N (test 306 ), the counted number of cycles K closest to the preset target number N is considered to have been reached, and the dynamic adjustment process of the frequency of the oscillating signal Fosc ends 314 .

[0132] When the iteration counter i reaches the limit i=I, the dynamic adjustment process of the frequency of the oscillation signal Fosc 314 ends. As a protection against blocking, I is provided so that it is usually not reached (eg, I=16).

[0133] Therefore, reference Figure 3 The described oscillator circuit OSC may include a counter configured to count 304 a number of periods K of an oscillation signal Fosc within a duration of a time constant Tosc, and configured to adjust 302 the frequency of the oscillation signal Fosc at a level, and configured to repeat counting 304 and adjusting 302 until a counted number of periods K closest to a preset target number is reached.

[0134] Figure 5 The realization of the dynamic adjustment process of the frequency of the oscillation signal Fosc is represented in time.

[0135] In each repetition step i (i=0 to 5) of the process, the oscillation signal with a frequency of approximately 32 cycles is updated, the number of cycles of the oscillation signal is counted Cnt during the duration of the time constant Tosc, and the choice of performing or not performing the adjustment according to step i+1 is made based on a comparison of the final count Cnt.

[0136] The total duration of the method makes it possible to generate a clock signal for timing the write cycle, which in this implementation includes: the dynamic adjustment process of the frequency of the oscillation signal Fosc should not last more than 5% of the total duration of the write cycle, i.e. a maximum of 0.2 ms (considering that the write cycle has a total maximum of 4 ms).

[0137] Fig. 6A and Figure 6B An example of a first alternative and an example of a second alternative of the EEPROM memory NVM integrated circuit CI are respectively illustrated.

[0138] In both alternatives, the integrated circuit C1 contains a memory plane PM as well as row and column decoders XDEC, YDEC, a charge pump PCHV and a state machine ME which controls the decoders XDEC, YDEC and the charge pump PCHV. The state machine ME distributes the voltage of the charge pump PCHV to the decoders XDEC, YDEC and is timed by the clock signal CLK.

[0139] As previously mentioned Figures 1 to 5 As described, the clock signal CLK is generated by the clock signal generating component GENCLK. The clock signal generating component GENCLK is therefore particularly configured to operably connect a filter circuit belonging to a communication interface INTB with an oscillator circuit (via a mode selection signal wrt), the communication interface INTB is physically connected to the bus BUS, and the clock signal generating component GENCLK is configured to use the filter circuit to adjust the oscillation signal generated by the oscillator circuit, thereby generating the clock signal CLK.

[0140] Fig. 6A The diagram shows the Figure 2 An example of the first alternative. In the first alternative, the fast oscillator OSC is exclusively intended to supply the charge pump PCHV and is used to generate the oscillator circuit (RGOSC, Figure 2 ) is included in a generating component module GENCLK such as a ring oscillator circuit.

[0141] Figure 6B The diagram shows the Figure 3 An example of the second alternative is particularly described. In the second alternative, the generating means GENCLK comprises a fast oscillator (OSC, Figure 3 ), and enables it to be used both for supplying a regulated fast oscillation signal Fosc to the charge pump and for generating a clock signal CLK after its frequency Fosc is divided by a frequency divider FDIV.

[0142] In summary, embodiments and implementations have been described that allow a stable frequency to be generated based on a time base that already exists on a circuit for other purposes and when that time base is used to stabilize the frequency is not used for its original purpose.

[0143] This is possible because the stabilization of the oscillator frequency is performed during the execution of the write operation and, for example, when this time base is present in the filter used in the I2C interface. In fact, the EEPROM memory performing the write cycle ignores the command transmitted via the I2C bus, thereby releasing the time base present in the filter.

[0144] In a first approach, stabilization is performed by inserting a time base into the ring oscillator. With regard to the stability constraints mentioned, the duration of this stabilization will be significant for all propagation delays of the gates in the ring, which is preferably suitable for relatively slow oscillators (clocks). Faster oscillators for charge pumps may require separate circuitry that cannot benefit from this stabilization.

[0145] In a second solution, stabilization is performed before each use of the oscillator by comparing a multiple of the period of the oscillator with the time base and by adjusting the frequency according to the result of this comparison. The context in which the write operation is performed (short duration such as 4 ms, constant supply voltage and temperature during the period of use of the oscillator) means that the initial calibration is valid at the end of the write cycle. This second solution is suitable for fast oscillators (for example, intended for charge pumps) and can generate the clock signal by frequency division, thus ensuring additional space savings.

[0146] In both solutions provided, calibration of the time base can be performed by loading a pre-set "factory" setting before the oscillator is started, or before its dynamic calibration, for improving the accuracy of the frequency. When the time base is used in a communication interface, this calibration is usually not necessarily required, the accuracy required is usually coarser (calibration parameters are then not used).

[0147] Of course, the invention is not limited to these implementations and embodiments, but covers all variants and can be applied, for example, to other types of non-volatile memories, the oscillator circuit can have another design that can be adjusted according to the invention, the filter circuit used for adjustment can belong to an element of the integrated circuit other than the communication interface, or with respect to Figure 4 and Figure 5 The described process of dynamic adjustment of the frequency of the oscillating signal may vary.

Claims

1. A method for writing to an electrically erasable programmable non-volatile memory, the method comprising: operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, and wherein operatively connecting the filter circuit comprises transitioning the filter circuit from a disabled state to an enabled state, wherein the enabled state comprises enabling access to functions of the filter circuit, wherein the disabled state comprises disabling access to functions of the filter circuit; generating, by the oscillator circuit, an oscillation signal, wherein generating the oscillation signal comprises accumulating elementary delays; as well as The oscillating signal is conditioned by the filter circuit to generate a clock signal for timing a write cycle, wherein the conditioning comprises inserting an additional delay equal to a time constant of the filter circuit into an accumulation of the basic delays, and wherein the accumulation of the basic delays is negligible in duration relative to the additional delay.

2. The method according to claim 1, further comprising: The filter circuit is operably disconnected from the communication interface prior to operably connecting the filter circuit to the oscillator circuit.

3. The method of claim 2, wherein operably disconnecting the filter circuit from the communication interface comprises: providing a signal originating from the communication interface to the filter circuit using a mode selection signal, the mode selection signal determining a signal having a constant arbitrary value; as well as The signal originating from the filter circuit is provided to the communication interface by means of the mode selection signal, the mode selection signal determining a signal having a constant arbitrary value.

4. The method according to claim 1, further comprising: Prior to operably connecting the filter circuit to the oscillator circuit, the filter circuit is operably disconnected from the oscillator circuit and the filter circuit is operably connected to the communication interface.

5. The method of claim 1 , wherein operatively connecting the filter circuit to the oscillator circuit comprises: providing a signal originating from the oscillator circuit to the filter circuit using a mode selection signal; as well as The oscillator circuit is provided with a signal originating from the filter circuit using the mode selection signal.

6. The method according to claim 1, further comprising: Before adjusting the oscillating signal by means of the filter circuit, the time constant is adjusted to a given value with a given accuracy, wherein the filter circuit includes the adjustable time constant.

7. A method for writing to an electrically erasable programmable non-volatile memory, the method comprising: operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, and wherein operatively connecting the filter circuit comprises transitioning the filter circuit from a disabled state to an enabled state, wherein the enabled state comprises enabling access to functions of the filter circuit, wherein the disabled state comprises disabling access to functions of the filter circuit; generating an oscillation signal by means of the oscillator circuit; conditioning the oscillating signal by dynamically adjusting the frequency of the oscillating signal relative to a time constant of the filter circuit to generate a clock signal for timing a write cycle, wherein generating the clock signal further comprises: dividing the conditioned frequency of the oscillating signal; and A write high voltage is generated in the write cycle by switching a capacitive element to a supply voltage, wherein switching of the capacitive element is timed by the oscillating signal.

8. The method of claim 7, wherein adjusting the oscillating signal comprises: The oscillating signal is adjusted at the beginning of each write cycle.

9. The method of claim 7, wherein dynamically adjusting the frequency of the oscillating signal comprises: counting the number of cycles of the oscillating signal over a duration of the time constant; adjusting a level of the frequency of the oscillation signal; and repeating the counting and the adjusting until a counted number of cycles closest to a preset target number is reached.

10. An integrated circuit comprising: a state machine configured to control write operations in a write cycle, the write cycle being timed by a clock signal; a communication interface including a filter circuit and configured to be physically connected to the bus; as well as a clock signal generator, comprising an oscillator circuit and a logic gate, the logic gate being connected to an input of the filter circuit and to an output of the filter circuit, respectively, the logic gate being configured to generate a signal having a constant arbitrary value in the presence of a mode selection signal so as to operatively disconnect the filter circuit from the communication interface, the clock signal generator being configured to: operatively disconnecting the filter circuit from the communications interface; operatively connecting the filter circuit to the oscillator circuit after operatively disconnecting the filter circuit from the communication interface, wherein operatively connecting the filter circuit comprises transitioning the filter circuit from a disabled state to an enabled state, the enabled state comprising enabling access to functions of the filter circuit, the disabled state comprising disabling access to functions of the filter circuit; generating an oscillating signal; as well as conditioning the oscillating signal by the filter circuit to generate the clock signal during the write cycle; The integrated circuit is an electrically erasable and programmable non-volatile memory integrated circuit.

11. The integrated circuit of claim 10, wherein the filter circuit is configured to be operably disconnected from the oscillator circuit, and the filter circuit is configured to be operably connected to the communication interface before being operably connected to the oscillator circuit.

12. The integrated circuit of claim 10, wherein the clock signal generator comprises: a logic gate connected to an input of the filter circuit, wherein the clock signal generator is configured to generate a signal to the input of the filter circuit in the presence of a mode select signal; and a logic gate connected to the output of the filter circuit, wherein the clock signal generator is configured to generate a signal to the input of the oscillator circuit in the presence of the mode selection signal so as to operatively connect the filter circuit to the oscillator circuit.

13. The integrated circuit of claim 10, wherein the filter circuit comprises an adjustable time constant, and wherein the clock signal generator is configured to adjust the time constant to a given value with a given accuracy.

14. An integrated circuit according to claim 10, wherein the oscillator circuit includes an adjustment module, which is configured to dynamically adjust the frequency of the oscillation signal according to a command; and wherein the clock signal generator is configured to control the dynamic adjustment of the frequency of the oscillation signal relative to the time constant of the filter circuit for regulating the oscillation signal. 15 . The integrated circuit according to claim 14 , wherein the adjustment module comprises a capacitive element with a controllable capacitance value, or a power current generator with a controllable current strength. 16 . The integrated circuit of claim 14 , wherein the clock signal generator is configured to adjust the oscillating signal at the beginning of each write cycle.

17. The integrated circuit of claim 14, wherein the adjustment module comprises a counter configured to: counting the number of cycles of the oscillating signal during the duration of the time constant; adjusting the frequency of the oscillating signal to a base level; and The counting and the adjusting are repeated until the counted number of cycles closest to the preset target number is reached. 18 . The integrated circuit of claim 14 , wherein the clock signal generator further comprises a frequency divider configured to divide the frequency of the adjusted oscillation signal.

19. The integrated circuit of claim 18, further comprising a charge pump circuit configured to generate a write high voltage, generating the write high voltage comprising switching a capacitive element to a supply voltage, the switching being timed by the oscillation signal generated by the oscillator circuit.

20. The integrated circuit of claim 10, wherein the oscillator circuit comprises a ring oscillator circuit configured to generate an accumulation of fundamental delays on a signal, and wherein the clock signal generator is configured to connect the filter circuit to the ring oscillator circuit so as to introduce an additional delay equal to a time constant of the filter circuit, the accumulation of the fundamental delay being negligible in duration relative to the additional delay.

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