Serial System

Abstract

A serial system includes a logical physical layer and an electrical physical layer. The logical physical layer provides a first clock and parallel data. The electrical physical layer provides a second clock, including a clock phase tracking circuit and a transmitter. The clock phase tracking circuit includes a shift register, a phase detection circuit and a selection circuit. The shift register samples the parallel data according to the first clock to generate first sampled data, second sampled data and third sampled data. The phase detection circuit generates a detection signal according to the phase difference between the first clock and the second clock. The selection circuit selects a group from the first sampled data, the second sampled data and the third sampled data as output data according to the detection signal. The transmitter serializes the output data to generate serial data.

Description

Technical Field

[0001] The present invention relates to a serial system. Background Art

[0002] Generally speaking, a serial system includes a logical physical layer (LPHY) and an electrical physical layer (EPHY). When the operating clocks of the logical physical layer and the electrical physical layer are not synchronized, the electrical physical layer cannot recognize the data output by the logical physical layer. Summary of the invention

[0003] The present invention provides a serial system, including a logical physical layer and an electrical physical layer. The logical physical layer provides a first clock and parallel data. The electrical physical layer provides a second clock, including a clock phase tracking circuit and a transmitting end. The clock phase tracking circuit includes a shift register, a phase detection circuit and a selection circuit. The shift register samples the parallel data according to the first clock to generate the first sampling data, the second sampling data and the third sampling data. The phase detection circuit generates a detection signal according to the phase difference between the first clock and the second clock. The selection circuit selects a group from the first sampling data, the second sampling data and the third sampling data as output data according to the detection signal. The transmitting end serializes the output data to generate serial data. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 Schematic diagram of a serial system of the present invention.

[0005] Figure 2 It is a schematic diagram of the internal channel of the electrical physical layer of the present invention.

[0006] Figure 3A This is a possible embodiment of the shift register of the present invention.

[0007] Figure 3B This is another possible embodiment of the shift register unit of the present invention.

[0008] Figure 4A This is a possible embodiment of the selection circuit of the present invention.

[0009] Figure 4B This is a possible embodiment of the selection circuit of the present invention.

[0010] Figure 5A This is a possible embodiment of the phase detection circuit of the present invention.

[0011] Figure 5B This is another possible embodiment of the phase detection circuit of the present invention.

[0012] Fig. 6A FIG. 4 is a possible schematic diagram of the phase and frequency detector of the present invention.

[0013] Figure 6B for Fig. 6A Schematic diagram of the operation of the frequency detector and phase detector. DETAILED DESCRIPTION

[0014] In order to make the purpose, features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each component in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the correlation between different embodiments.

[0015] Figure 1 FIG. 1 is a schematic diagram of a serial system 100 of the present invention. As shown in the figure, the serial system 100 includes a logical physical layer (LPHY) 110 and an electrical physical layer (EPHY) 120. The logical physical layer 110 includes a controller 111 and a plurality of channels LL1 to LL2. n . The controller 111 uses channels LL1 to LL n Communicates with the electrical physical layer 120. Among them, Figure 1 The serial system shown may be used in a serializer / deserializer (SerDes) system to perform serial operations in the serializer / deserializer system.

[0016] Taking channel LL1 as an example, channel LL1 outputs clock LP1_CLK and parallel data LP1_TCAD<19:0> to the electrical physical layer 120. In one possible embodiment, the clock LP1_CLK and the parallel data LP1_TCAD<19:0> are generated by the controller 111. In addition, channel LL1 also receives clock EP1_CLK and parallel data EP1_RCAD<19:0> from the electrical physical layer 120. In one possible embodiment, the controller 111 operates according to the clock EP1_CLK and the parallel data EP1_RCAD<19:0>.

[0017] In this embodiment, the electrical physical layer 120 includes a phase-locked loop (PLL) 121 and a plurality of channels EL1-EL2. n The phase-locked loop 121 is used to generate a clock PLL_CLK for channels EL1 to EL2. n .

[0018] Channel EL1~EL n Receive clock LP1_CLK~LP n _CLK and parallel data LP1_TCAD<19:0>~LP n _TCAD<19:0>. In this embodiment, channels EL1~EL n It also provides clock EP1_CLK~EP n _CLK and parallel data EP1_RCAD<19:0>~EP n _RCAD<19:0> gives channels LL1 to LL2 of the logical physical layer 110 n .

[0019] In this embodiment, channels EL1 to EL n Each includes a frequency divider, a clock phase tracking circuit, a transmitting end, and a receiving end. Taking channel EL1 as an example, channel EL1 includes a frequency divider 125, a clock phase tracking circuit 122, a transmitting end 123, and a receiving end 124. The frequency divider 125 divides the clock PLL_CLK to generate a clock TPLL1_CLK. The clock phase tracking circuit 122 samples the parallel data LP1_TCAD<19:0> according to the clock TPLL1_CLK to generate a plurality of sampled data, and selects appropriate sampled data according to the phase difference between the clock TPLL1_CLK and the clock LP1_CLK and outputs it to the transmitting end 123.

[0020] According to an embodiment of the present invention, depending on the architecture of the serialization circuit in the transmitting end 123, the clock TPLL1_CLK and the clock LP1_CLK are different in most serial systems, but the frequency of the clock TPLL1_CLK is the same as the frequency of the clock LP1_CLK. i1 _CLK is the same, clock TPLL1_CLK~TPLL i1 _CLK is the same, clock LP1_CLK~LP i1 _CLK and clock TPLL1_CLK~TPLL i1 When the remaining channels (i2-i1) use another communication protocol, the clock LP i1 _CLK~LP i2 _CLK is the same as the aforementioned clock LP1_CLK~LP i1 _CLK is different, clock TPLL i1 _CLK~TPLL i2 _CLK is the same as the aforementioned clock TPLL1_CLK~TPLL i1 _CLK is different, clock LP i1_CLK~LP i2 _CLK and clock TPLL i1 _CLK~TPLL i2 _CLK has the same frequency as the aforementioned clock LP1_CLK~LP i The frequencies of _CLK are different, where 1<=i1<=i2<=n.

[0021] The transmitting end 123 serializes the sampled data output by the clock phase tracking circuit 122 according to the clock PLL_CLK to generate and output serial data SO1_DT to an external circuit (not shown). In one possible embodiment, the serial data SO1_DT is a differential signal. The present invention does not limit the circuit architecture of the transmitting end 123. Any circuit that can serialize parallel data into serial data can be used as the transmitting end 123.

[0022] The receiving end 124 receives the serial data SI1_DT. The serial data SI1_DT may be a differential signal. In one possible embodiment, the receiving end 124 processes the serial data SI1_DT to recover the clock and data from the serial data SI1_DT. In this example, the receiving end 124 provides parallel data EP1_RCAD<19:0> and clock EP1_CLK to the channel LL1. The present invention does not limit the circuit architecture of the receiving end 124. Any circuit that can convert serial data into parallel data can be used as the receiving end 124.

[0023] Figure 2 Schematic diagram of the internal channel of the electrical physical layer of the present invention. n The architecture is the same, so Figure 2 Only the internal structure of the channel EL1 is shown. As shown in the figure, the channel EL1 includes a frequency divider 125, a clock phase tracking circuit 122, a transmitting end 123 and a receiving end 124.

[0024] The clock phase tracking circuit 122 includes a shift register 211, a phase detection circuit 212, and a selection circuit 213. The shift register 211 samples the parallel data LP1_TCAD<19:0> according to the clock LP1_CLK to generate the sampled data SP1<19:0>~SP3<19:0>. The phase detection circuit 212 generates a detection signal SD according to the phase difference between the clock LP1_CLK and the clock TPLL1_CLK. The selection circuit 213 selects one group of the sampled data SP1<19:0>~SP3<19:0> as the output data OT<19:0> according to the detection signal SD.

[0025] For example, when the phase difference between the clock LP1_CLK and the clock TPLL1_CLK is within a preset range, the phase detection circuit 212 instructs the selection circuit 213 to select the sampled data SP2<19:0> according to the detection signal SD. Therefore, the selection circuit 213 uses the sampled data SP2<19:0> as the output data OT<19:0>. However, when the clock LP1_CLK is ahead of the clock TPLL1_CLK and the phase difference between the clock LP1_CLK and the clock TPLL1_CLK is not within the preset range, the phase detection circuit 212 instructs the selection circuit 213 to select the sampled data SP3<19:0> as the output data OT<19:0> according to the detection signal SD. In other embodiments, when the clock LP1_CLK lags behind the clock TPLL1_CLK and the phase difference between the clocks LP1_CLK and TPLL1_CLK is not within a preset range, the phase detection circuit 212 instructs the selection circuit 213 to select the sampled data SP1<19:0> as the output data OT<19:0> according to the detection signal SD.

[0026] Since the phase detection circuit 212 instructs the selection circuit 213 to select appropriate sampling data according to the phase difference between the clock LP1_CLK and the clock TPLL1_CLK, it can ensure that the data output by the electrical physical layer 120 is synchronized with the clock PLL_CLK. Furthermore, since the clock phase tracking circuit 122 works in an open circuit, it has higher stability and the circuit design is relatively simple. In addition, the clock phase tracking circuit 122 has the advantages of low power consumption and small area.

[0027] The present invention does not limit the number of groups of sampled data. In this embodiment, the number of groups of sampled data is an odd number. In addition, the present invention does not limit the architecture of the phase detection circuit 212. As long as it can generate a suitable detection signal SD and allow the selection circuit 213 to select suitable sampled data from multiple groups of sampled data, the circuit can be used as the phase detection circuit 212.

[0028] For example, when the shift register 211 generates three groups of sampled data, such as SP1<19:0>~SP3<19:0>, the detection signal SD generated by the phase detection circuit 212 includes at least two detection signals UP and DN, so that the selection circuit 213 selects one group from the sampled data SP1<19:0>~SP3<19:0> as the output data OT<19:0> according to the two detection signals UP and DN of the detection signal SD. In another embodiment, when the shift register 211 may generate five groups of sampled data (such as SP1<19:0>~SP5<19:0>). In this example, the phase detection circuit 212 needs to generate the detection signal SD including at least four detection signals UP1, UP2, DN1, and DN2. In this example, the selection circuit 213 selects one group from the sampled data SP1<19:0>~SP5<19:0> as the output data OT<19:0> according to the four detection signals UP1, UP2, DN1, and DN2 of the detection signal SD. The detection signal SD includes (k-1) detection signals, k is the number of groups of sampling data generated by the shift register 211, and the (k-1) detection signals include UP1 to UP (k-1) / 2 and DN1~DN (k-1) / 2 .

[0029] The transmitting end 123 includes a serialization circuit 221 and a driver 222. The serialization circuit 221 serializes the parallel data LP1_TCAD<19:0> according to the clock PLL_CLK to generate the serial data SO1_DT. The present invention does not limit the architecture of the serialization circuit 221. In one possible embodiment, the serialization circuit 221 includes at least one data receiving unit (not shown). In this example, the data receiving unit may be a buffer, a D flip-flop, a register, or a latch.

[0030] In this example, the driver 222 is used to output serial data SO1_DT to an external circuit according to the clock PLL_CLK. In addition, in other embodiments, the driver 222 also modulates the signal to meet the electrical specifications required by a specific protocol, such as meeting the requirements of the specific protocol for output impedance, signal amplitude, slew rate, balance granularity, balance amplitude, ESD specifications, short-circuit current, etc.

[0031] The receiving end 124 includes a receiver 231 and a clock data recovery (CDR) circuit 232. The receiver 231 receives the serial data SI1_DT. The clock data recovery circuit 232 analyzes the serial data SI1_DT to recover the clock and data from the serial data SI1_DT. In this embodiment, the clock data recovery circuit 232 generates the clock EP1_CLK and the parallel data EP1_RCAD<19:0>.

[0032] Figure 3A 211 is a shift register according to an embodiment of the present invention. Figure 3A As shown, the shift register 211 includes shift buffer units SR0-SR 19 The present invention does not limit the number of shift register units. In this embodiment, since the parallel data LP1_TCAD<19:0> has 20 bits, the shift register 211 correspondingly includes 20 shift register units.

[0033] Shift register unit SR0~SR 19 The parallel data LP1_TCAD<19:0> is sampled according to the clock LP1_CLK. For example, the shift register unit SR0 samples the least significant bit (LSB) of the parallel data LP1_TCAD<19:0>, hereinafter referred to as bit data LP1_TCAD <0> The shift buffer unit SR1 samples the least significant bit adjacent to the parallel data LP1_TCAD<19:0>, hereinafter referred to as the bit data LP1_TCAD <1> Shift register unit SR 18 The most significant bit (MSB) adjacent bits of the sampled parallel data LP1_TCAD<19:0>, hereinafter referred to as bit data LP1_TCAD <18> Shift register unit SR 19 The most significant bit of the sampled parallel data LP1_TCAD<19:0>, hereinafter referred to as bit data LP1_TCAD <19> .

[0034] Since the shift register units SR0~SR 19 The circuit architectures of the shift register unit SR0 are the same, so only the circuit architecture of the shift register unit SR0 is described below. In this embodiment, the shift register unit SR0 includes sampling circuits 310, 320 and 330. The present invention does not limit the number of sampling circuits in the shift register unit SR0. When the number of sampling circuits is greater, the shift register unit SR0 can provide more sampling data. In a possible embodiment, the number of sampling circuits in each shift register unit is an odd number.

[0035] The sampling circuit 310 samples the bit data LP1_TCAD according to the first falling edge of the clock LP1_CLK. <0> , used to generate the first data Q1. In this embodiment, the first data Q1 is the least significant bit SP1 of the sampled data SP1<19:0>. <0> The present invention does not limit the architecture of the sampling circuit 310. In this embodiment, the sampling circuit 310 includes a D flip-flop 311. In this example, the data input terminal D of the D flip-flop 311 receives the bit data LP1_TCAD <0> , a clock input terminal Clk of the D flip-flop 311 receives the clock LP1_CLK, and an output terminal Q of the D flip-flop 311 outputs the first data Q1.

[0036] The sampling circuit 320 samples the first data Q1 according to the first rising edge of the clock LP1_CLK to generate the second data Q2, wherein the first rising edge is the first rising edge after the first falling edge. In this embodiment, the second data Q2 is used as the least significant bit SP2 of the sampled data SP2<19:0>. <0> The present invention does not limit the architecture of the sampling circuit 320. In this embodiment, the sampling circuit 320 includes a D flip-flop 321. In this example, the data input terminal D of the D flip-flop 321 receives the first data Q1, the clock input terminal Clk of the D flip-flop 321 receives the clock LP1_CLK, and the output terminal Q of the D flip-flop 321 outputs the second data Q2. In other embodiments, the sampling circuit 320 includes a latch 321.

[0037] The sampling circuit 330 samples the second data Q2 according to the second falling edge of the clock LP1_CLK to generate the third data Q3, wherein the second falling edge is the first falling edge after the first rising edge. In this embodiment, the third data Q3 is used as the least significant bit SP3 of the sampled data SP3<19:0>. <0> The present invention does not limit the architecture of the sampling circuit 330. In this embodiment, the sampling circuit 330 includes a D flip-flop 331. In this example, the data input terminal D of the D flip-flop 331 receives the second data Q2, the clock input terminal Clk of the D flip-flop 331 receives the clock LP1_CLK, and the output terminal Q of the D flip-flop 331 outputs the third data Q3. In other embodiments, the sampling circuit 320 includes a latch 331.

[0038] In this embodiment, the shift register units SR0 to SR 19The first data Q1 generated respectively constitutes the sampled data SP1<19:0>, the second data Q2 constitutes the sampled data SP2<19:0>, and the third data Q3 constitutes the sampled data SP3<19:0>. In other embodiments, the reset terminals R of the D flip-flops 311, 321, and 331 receive the reset signal RST. In this example, when the reset signal RST is enabled, the output terminals Q of the D flip-flops 311, 321, and 331 return to a preset level, for example, to a low level.

[0039] Figure 3B FIG. 1 is a schematic diagram of a shift register unit according to another embodiment of the present invention. 19 The architecture is the same, so Figure 3B Only the shift register unit SR0 is shown. In this embodiment, the shift register unit SR0 further includes sampling circuits 340 and 350 .

[0040] The sampling circuit 340 samples the third data Q3 according to the second rising edge of the clock LP1_CLK to generate the fourth data Q4, wherein the second rising edge is the first rising edge after the second falling edge. In this embodiment, the fourth data Q4 is the least significant bit SP4 of the sampled data SP4<19:0>. <0> The present invention does not limit the architecture of the sampling circuit 324. In this embodiment, the sampling circuit 340 includes a D flip-flop 341. In this example, the data input terminal D of the D flip-flop 341 receives the third data Q3, the clock input terminal Clk of the D flip-flop 341 receives the clock LP1_CLK, and the output terminal Q of the D flip-flop 341 provides the fourth data Q4. In other embodiments, the sampling circuit 340 includes a latch 341.

[0041] The sampling circuit 350 samples the fourth data Q4 according to the third falling edge of the clock LP1_CLK to generate the fifth data Q5, wherein the third falling edge is the first falling edge after the second rising edge. In this embodiment, the fifth data Q5 is the least significant bit SP5 of the sampled data SP5<19:0>. <0> The present invention does not limit the architecture of the sampling circuit 350. In this embodiment, the sampling circuit 350 includes a D flip-flop 351. In this example, the data input terminal D of the D flip-flop 351 receives the fourth data Q4, the clock input terminal Clk of the D flip-flop 351 receives the clock LP1_CLK, and the output terminal Q of the D flip-flop 351 provides the fifth data Q5. In other embodiments, the sampling circuit 350 includes a latch 351.

[0042] Figure 4A FIG. 2 is a schematic diagram of a possible embodiment 213A of the selection circuit 213 of the present invention. Figure 4A As shown, the selection circuit 213A includes a decoder 410A and selectors SA0-SA19 The decoder 410A decodes the detection signal SD to generate the switching signal SWA. In this embodiment, the detection signal SD includes detection signals UP and DN.

[0043] Selector SA0~SA 19 According to the switching signal SWA, a group of the sampled data SP1<19:0> to SP3<19:0> is selected as the output data OT<19:0>. The present invention does not limit the selectors SA0 to SA1. 19 In this embodiment, selectors SA0 to SA 19 is a multiplexer. In addition, the present invention does not limit the number of selectors. In a possible embodiment, the number of selectors is the same as the number of bits of the parallel data LP1_TCAD<19:0>.

[0044] The present invention does not limit the selectors SA0 to SA 19 How to select a group of sampled data SP1<19:0>~SP3<19:0> according to the switching signal SWA. In one possible embodiment, when the detection signals UP and DN are both at the first level, for example, both at the low level, it means that the phase difference between the clock LP1_CLK and the clock TPLL1_CLK is within a preset range. Therefore, the decoder 410A instructs the selectors SA0~SA1 through the switching signal SWA. 19 Select the sample data SP2<19:0> as the output data OT<19:0>. When the detection signal UP is at the second level, such as a high level, and the detection signal DN is at the first level, such as a low level, it indicates that the clock LP1_CLK lags behind the clock TPLL1_CLK and the phase difference between the clock LP1_CLK and the clock TPLL1_CLK is not within the preset range. Therefore, the decoder 410A instructs the selectors SA0 to SA1 according to the switching signal SWA. 19 Select the sampled data SP1<19:0> as the output data OT<19:0>. When the detection signal UP is at a first level, such as a low level, and the detection signal DN is at a second level, such as a high level, it indicates that the clock LP1_CLK may be ahead of the clock TPLL1_CLK and the phase difference between the clock LP1_CLK and the clock TPLL1_CLK is not within a preset range. Therefore, the decoder 410A instructs the selectors SA0 to SA1 according to the switching signal SWA. 19 The sampled data SP3<19:0> is selected as the output data OT<19:0>.

[0045] Figure 4B FIG. 2 is a schematic diagram of another possible embodiment 213B of the selection circuit 213 of the present invention. Figure 4BAs shown, the selection circuit 213A includes a decoder 410B and selectors SB0-SB 19 . In this embodiment, the detection signal SD includes detection signals UP1, UP2, DN1 and DN2. In this example, the decoder 410B adjusts the switching signal SWB according to the different states of the detection signals UP1, UP2, DN1 and DN2 to select a group of sampled data SP1<19:0>~SP5<19:0> as the output data OT<19:0>. Specifically, when the detection signals UP1, UP2, DN1, DN2 are all at the first level, such as a low level, the decoder 410B instructs the selectors SB0~SB1 according to the switching signal SWB. 19 Select the sample data SP3<19:0> as the output data OT<19:0>. When the detection signal UP1 among the detection signals UP1, UP2, DN1, and DN2 is at the second level, such as a high level, and the others are at the first level, such as a low level, the decoder 410B instructs the selectors SB0 to SB1 according to the switching signal SWB. 19 Select the sample data SP2<19:0> as the output data OT<19:0>. When the detection signals UP1, UP2, DN1, and DN2 are at the second level, such as a high level, and the others are at the first level, such as a low level, the decoder 410B instructs the selectors SB0 to SB1 according to the switching signal SWB. 19 Select the sample data SP1<19:0> as the output data OT<19:0>. When the detection signal DN1 among the detection signals UP1, UP2, DN1, and DN2 is at the second level, such as a high level, and the others are at the first level, such as a low level, the decoder 410B instructs the selectors SB0 to SB1 according to the switching signal SWB. 19 Select the sample data SP4<19:0> as the output data OT<19:0>. When the detection signals DN1 and DN2 of the detection signals UP1, UP2, DN1, and DN2 are at the second level, such as a high level, and the others are at the first level, such as a low level, the decoder 410B instructs the selectors SB0 to SB1 according to the switching signal SWB. 19 The sampled data SP5<19:0> is selected as the output data OT<19:0>.

[0046] Figure 5A FIG. 2 is a schematic diagram of a possible embodiment 212A of the phase detection circuit 212 of the present invention. In this embodiment, the phase detection circuit 212A includes a phase frequency detector (PFD) 510A, a low pass filter (LPF) 520A, a comparison circuit 530A, and a synchronization circuit 540A.

[0047] The phase detector 510A detects the phase difference between the clock LP1_CLK and the clock TPLL1_CLK, and generates the pulse signals PS1 and PS2 according to the phase difference between the clock LP1_CLK and the clock TPLL1_CLK. In one possible embodiment, when the phase difference between the clock LP1_CLK and the clock TPLL1_CLK exceeds the linear range of the phase detector 510A, the pulse signals PS1 and PS2 cannot reflect the real phase difference between the clock TPLL1_CLK and the clock LP1_CLK. In this case, a phase detector with a higher linear range can be used, or the clock LP1_CLK and the clock TPLL1_CLK can be divided before detection.

[0048] The present invention does not limit the type of the phase frequency detector 510A. In one possible embodiment, the type of the phase frequency detector 510A is related to the number of sampled data. For example, when the shift register 211 provides 3 groups of sampled data, the linear range of the phase frequency detector 510A must be between -π and +π. When the shift register 211 provides 5 groups of sampled data, the linear range of the phase frequency detector 510A must be between -2π and +2π. Among them, when the number of sampled data groups is k, the linear range of the phase frequency detector 510A must be between -(k-1)π / 2 and +(k-1)π / 2. The linear range is the range of the phase difference between the clock LP1_CLK and the clock TPLL1_CLK that enables the voltage of the DC signal (i.e., the filtered signals FT1 and FT2 below) in the output signal of the phase frequency detector 510A to maintain continuous linearity.

[0049] The low-pass filter 520A removes the high-frequency signals of the pulse signals PS1 and PS2 to generate DC filtered signals FT1 and FT2. In this embodiment, the DC signals after filtering out the high-frequency signals, i.e., the filtered signals FT1 and FT2, are proportional to the pulse widths of the pulse signals PS1 and PS2, and also represent the phase difference between the clock LP1_CLK and the clock TPLL1_CLK.

[0050] The comparison circuit 530A compares the filter signal FT1 with the reference signal VREF to generate a comparison result CP1, and compares the filter signal FT2 with the reference signal VREF to generate a comparison result CP2. In this embodiment, the comparison circuit 530A includes comparators 531 and 532. Figure 5A As shown, the inverting input terminal of the comparator 531 receives the reference signal VREF, and the non-inverting input terminal of the comparator 531 receives the filtered signal FT1. The inverting input terminal of the comparator 532 receives the reference signal VREF, and the non-inverting input terminal of the comparator 532 receives the filtered signal FT2.

[0051] The synchronization circuit 540A synchronizes the comparison results CP1 and CP2 according to the clock TPLL1_CLK to generate a detection signal SD. In the present embodiment, the detection signal SD includes detection signals UP and DN. In this example, the detection signals UP and DN are used to represent the phase difference between the clock LP1_CLK and the clock TPLL1_CLK. The present invention does not limit the architecture of the synchronization circuit 540A. In one possible embodiment, the synchronization circuit 540A includes D flip-flops 541 and 542. In this example, the D flip-flop 541 samples the comparison result CP1 according to the clock TPLL1_CLK to generate the detection signal UP. The D flip-flop 542 samples the comparison result CP2 according to the clock TPLL1_CLK to generate the detection signal DN.

[0052] In other embodiments, the phase detection circuit 212A further includes a voltage generating circuit 550A. The voltage generating circuit 550A is used to generate a reference signal VREF. In one embodiment, the reference signal VREF is approximately 1 / 4 of VDD, where VDD is the operating voltage of the phase frequency detector 510A.

[0053] Figure 5B FIG. 2 is a schematic diagram of another possible embodiment 212B of the phase detection circuit 212 of the present invention. In this embodiment, the detection signal SD generated by the phase detection circuit 212B includes detection signals UP1, UP2, DN1 and DN2, which are used to select one group from five groups of sampled data. Figure 5B As shown in FIG. 2 , the phase detection circuit 212B includes a phase detector 510B, a low-pass filter 520B, a comparison circuit 530B, and a synchronization circuit 540B. Figure 5A The characteristics of the frequency detector 510A and the low-pass filter 520A are similar, so they are not repeated here.

[0054] In this embodiment, the comparison circuit 530B includes comparators 533 to 536. The inverting input terminal of the comparator 533 receives the reference signal VREF1, the non-inverting input terminal of the comparator 533 receives the filtered signal FT1, and the output terminal of the comparator 533 provides a comparison result CP3. The inverting input terminal of the comparator 534 receives the reference signal VREF1, the non-inverting input terminal of the comparator 534 receives the filtered signal FT2, and the output terminal of the comparator 534 provides a comparison result CP4. The inverting input terminal of the comparator 535 receives the reference signal VREF2, the non-inverting input terminal of the comparator 535 receives the filtered signal FT1, and the output terminal of the comparator 535 provides a comparison result CP5. The inverting input terminal of the comparator 536 receives the reference signal VREF2, the non-inverting input terminal of the comparator 536 receives the filtered signal FT2, and the output terminal of the comparator 536 provides a comparison result CP6.

[0055] The synchronization circuit 540B synchronizes the comparison results CP3-CP6 according to the clock TPLL1_CLK to generate a detection signal SD. In this embodiment, the detection signal SD includes detection signals UP1, UP2, DN1 and DN2. The present invention does not limit the architecture of the synchronization circuit 540B. In a possible embodiment, the synchronization circuit 540B includes D flip-flops 543-546.

[0056] The D flip-flop 543 samples the comparison result CP3 according to the clock TPLL1_CLK to generate the detection signal UP1. The D flip-flop 544 samples the comparison result CP4 according to the clock TPLL1_CLK to generate the detection signal DN1. The D flip-flop 545 samples the comparison result CP5 according to the clock TPLL1_CLK to generate the detection signal UP2. The D flip-flop 546 samples the comparison result CP6 according to the clock TPLL1_CLK to generate the detection signal DN2.

[0057] In this embodiment, the phase detection circuit 212B further includes a voltage generating circuit 550B. The voltage generating circuit 550B is used to generate reference signals VREF1 and VREF2. In one possible embodiment, the reference signal VREF1 is approximately 1 / 4 of VDD, and the reference signal VREF2 is approximately 3 / 4 of VDD, where VDD is the operating voltage of the phase frequency detector 510B.

[0058] In other embodiments, the detection signal SD includes more detection signals to select appropriate sampling data from more sampling data. For example, when each shift buffer unit has 7 sampling circuits, the detection signal SD includes 6 detection signals. In this example, the voltage generating circuit provides 3 reference signals, wherein the first reference signal is 1 / 6 of VDD, the second reference signal is 3 / 6, i.e., 1 / 2 of VDD, and the third reference signal is 5 / 6 of VDD. In another embodiment, when each shift buffer unit has 9 sampling circuits, the detection signal SD has 8 detection signals. In this example, the voltage generating circuit provides 4 reference signals, wherein the first reference signal is 1 / 8 of VDD, the second reference signal is 3 / 8 of VDD, the third reference signal is 5 / 8 of VDD, and the fourth reference signal is 7 / 8 of VDD. Among them, when the number of sampling circuits is k, the shift buffer unit will generate k groups of sampling signals, and the detection signal SD includes (k-1) detection signals, and the voltage generating circuit is required to provide (k-1) / 2 reference signals, where these reference signals VREF are successively taken as m / (k-1) VDD, where VDD is the operating voltage of the frequency detector 510B, and m takes the odd numbers in the interval [1, k), which can also be expressed as m=1, 3...k-4, k-2.

[0059] Fig. 6A6 is a possible schematic diagram of a phase frequency detector of the present invention. As shown in the figure, the phase frequency detector 600 includes a D flip-flop 610, a D flip-flop 620 and a logic gate 630. The data input terminal D of the D flip-flop 610 receives the working voltage VDD, the clock input terminal Clk of the D flip-flop 610 receives the clock LP1_CLK, the output terminal Q of the D flip-flop 610 outputs the pulse signal PS1, and the reset terminal R of the D flip-flop 610 is coupled to the output terminal of the logic gate 630. The data input terminal D of the D flip-flop 620 receives the working voltage VDD, the clock input terminal Clk of the D flip-flop 620 receives the clock TPLL1_CLK, the output terminal Q of the D flip-flop 620 outputs the pulse signal PS2, and the reset terminal R of the D flip-flop 620 is coupled to the output terminal of the logic gate 630. The logic gate 630 receives the pulse signals PS1 and PS2. In this embodiment, the logic gate 630 is an AND gate.

[0060] Figure 6B for Fig. 6A The waveform diagram of the phase frequency detector 600 is shown in FIG. When the clock LP1_CLK rises from a low level to a high level, the pulse signal PS1 becomes a high level. When the clock TPLL1_CLK rises from a low level to a high level, the pulse signal PS2 becomes a high level. When the pulse signals PS1 and PS2 are at a high level, the logic gate 630 resets the D flip-flops 610 and 620, so that the pulse signals PS1 and PS2 return from a high level to a low level.

[0061] Figure 6B 1 shows the state where LP1_CLK leads TPLL1_CLK when TPLL1_CLK is triggered by LP1_CLK. The pulse width difference between the pulse signal PS1 and the pulse signal PS2 represents the phase difference between the clock LP1_CLK and the clock TPLL1_CLK. For example, when the phase difference between the clock LP1_CLK and the clock TPLL1_CLK is larger, the pulse width difference between the pulse signal PS1 and the pulse signal PS2 is larger.

[0062] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art to which the present invention belongs. In addition, unless expressly indicated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or overly formal tone.

[0063] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A serial system comprising: The logical physical layer provides the first clock and parallel data; as well as The electrical physical layer provides a second clock, including: A clock phase tracking circuit, comprising: A shift register, sampling the parallel data according to the first clock, to generate first sampling data, second sampling data and third sampling data; A phase detection circuit generates a detection signal according to a phase difference between the first clock and the second clock; and A selection circuit selects a group of the first sampling data, the second sampling data and the third sampling data as output data according to the detection signal; and The transmitting end serializes the output data to generate serial data.

2. The serial system as claimed in claim 1, wherein when the phase difference is within a preset range, the selection circuit selects the second sampled data as the output data; when the first clock is ahead of the second clock and the phase difference is not within the preset range, the selection circuit selects the third sampled data as the output data; when the first clock lags behind the second clock and the phase difference is not within the preset range, the selection circuit selects the first sampled data as the output data. 3 . The serial system as claimed in claim 1 , wherein the shift register comprises a plurality of shift register units, each of the shift register units comprises a plurality of sampling circuits, and the number of the plurality of sampling circuits is an odd number.

4. The serial system as claimed in claim 3, wherein each of the shift register units comprises: A first sampling circuit samples one bit of the parallel data according to a first falling edge of the first clock to generate first data; A second sampling circuit samples the first data according to a first rising edge of the first clock to generate second data; as well as The third sampling circuit samples the second data according to the second falling edge of the first clock to generate third data. The first sampling data includes a plurality of first data generated by the plurality of shift register units, the second sampling data includes a plurality of second data generated by the plurality of shift register units, and the third sampling data includes a plurality of third data generated by the plurality of shift register units. 5 . The serial system as claimed in claim 4 , wherein the first sampling circuit, the second sampling circuit, and the third sampling circuit comprise flip-flops. 6 . The serial system as claimed in claim 4 , wherein the first sampling circuit comprises a flip-flop, and the second sampling circuit and the third sampling circuit comprise latches.

7. The serial system as claimed in claim 1, wherein the phase detection circuit comprises: A frequency detector and a phase detector, generating a first pulse signal and a second pulse signal according to a phase difference between the first clock and the second clock; A low-pass filter processes the first pulse signal and the second pulse signal to generate a first filtered signal and a second filtered signal; A comparison circuit, comparing the first filtered signal with a reference signal to generate a first comparison result, and comparing the second filtered signal with the reference signal to generate a second comparison result; as well as The synchronization circuit synchronizes the first and second comparison results according to the second clock to generate the detection signal.

8. The serial system of claim 7, wherein the synchronization circuit comprises: A first trigger, sampling the first comparison result according to the second clock, to generate a first detection signal; as well as The second trigger samples the second comparison result according to the second clock to generate a second detection signal. The detection signal includes the first detection signal and the second detection signal.

9. The serial system as claimed in claim 8, wherein the selection circuit comprises: A decoder, decoding the detection signal to generate a switching signal; as well as The selector selects a group of the first sampling data, the second sampling data and the third sampling data as the output data according to the switching signal.

10. The serial system as claimed in claim 1, wherein the transmitting end comprises: A serialization circuit, serializing the output data to generate the serial data; as well as The driver is used to output the serial data.

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