Performance Analysis

Abstract

An apparatus includes: a processing unit configured to execute a plurality of threads; and an analysis unit configured to: analyze the operation of the processing unit over a time period to generate an activity profile indicating when each of the plurality of threads was executed by the processing unit during the time period; analyze the generated activity profile to determine whether the signature of the thread execution of the processing unit during the time period matches the signature of a baseline indicating the thread execution of the processing unit; and if the signature of the thread execution of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, output an alarm signal.

Description

Technical Field

[0001] This invention relates to monitoring the performance of a processing unit when it is executing multiple threads. Background Technology

[0002] Computing devices typically include one or more processing units that execute program instructions to perform tasks specified by those instructions. Processing units can be, for example, a central processing unit (CPU) or a graphics processing unit (GPU).

[0003] A processing unit can support multithreading, which is the ability of a processing unit to execute instructions using multiple threads. To this end, the processing unit can schedule threads for executing instructions so that a single thread is executed by the processing unit at any given time. A thread can be "swapped out," meaning that the execution of that thread stops, and another thread is "swapped in," meaning that the execution of that thread begins. Within a given time period, a thread can be swapped in or out once or more. In other words, a processing unit can perform multithreading by executing different threads interleaved over time.

[0004] While the thread executing instructions in the processing unit is in operation, it may be desirable to obtain information about the processing unit's performance. This could be for the purpose of monitoring the processing unit's performance level and / or as part of threat and security management. Summary of the Invention

[0005] According to the present invention, an apparatus is provided, comprising:

[0006] A processing unit configured to execute multiple threads;

[0007] The analysis unit is configured as follows:

[0008] The analysis process unit runs over a period of time to generate an activity profile that indicates when each of the multiple threads was executed by the processing unit during that period of time.

[0009] Analyze the generated activity profile to determine whether the signature of the thread execution of the processing unit during that time period matches the signature of the baseline indicating the thread execution of the processing unit.

[0010] If the signature of the thread execution of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, an alarm signal is output.

[0011] The activity overview can indicate the number of processing unit clock cycles spent executing each thread within that time period.

[0012] The analysis unit can be configured to analyze the operation of the processing unit by identifying each thread that the processing unit is executing within that time period in order to generate an activity profile.

[0013] The device may be an integrated circuit chip including interconnect circuitry, and the analysis unit may be configured to monitor traffic via the interconnect circuitry of the integrated circuit chip to identify each thread being executed by the processing unit during that time period.

[0014] The processing unit can be configured to maintain the storage location of the thread being executed, and the analysis unit is configured to identify each thread being executed by accessing the storage location.

[0015] The analysis unit can be configured to identify each thread being executed from sideband signals transmitted from the processing unit.

[0016] The analysis unit can be configured to store the generated activity profile as a data array.

[0017] The analysis unit can be configured to use data processing algorithms on the data array to analyze the generated activity profile to determine whether the activity profile can be classified as a baseline for instructing the execution of threads in the processing unit.

[0018] The data processing algorithm is a trained data classification model.

[0019] The analysis unit can be configured to use a data processing algorithm to calculate the difference between a data array and each of a group of one or more template data arrays, each of which indicates the baseline of thread execution of the processing unit. If the difference between the data array and at least one of the template arrays is less than a specified threshold, the data array is classified as the baseline indicating thread execution.

[0020] The analysis unit can be configured to: use a data processing algorithm to extract the values ​​of one or more parameters from a data array, the values ​​representing the signature of the thread execution of the processing unit during the time period; and compare the extracted values ​​with the corresponding parameter values ​​of the signature indicating the baseline of thread execution.

[0021] The group of one or more parameters includes one or more of the following: the total number of thread switches during the time period; the average length of thread execution during the time period; the maximum length of thread execution during the time period; the minimum length of thread execution during the time period; the average frequency of thread switches during the time period; the maximum and / or minimum frequency of thread switches during the time period; and the order of thread execution during the time period.

[0022] The analysis unit can be configured to output an alarm signal if the data array is classified as not representing the baseline of thread execution of the processing unit.

[0023] The data array may be an image depicting when each thread is executed by the processing unit within that time period, and the data processing algorithm may be an image processing algorithm.

[0024] The analysis unit can be configured to use image processing algorithms on the generated image to analyze the generated activity profile in order to determine whether the generated image can be classified as a baseline for depicting the thread execution of the processing unit.

[0025] The image processing algorithm can be a trained image classification model.

[0026] The analysis unit can be configured to use an image processing algorithm to calculate the difference between the generated image and each of a group of one or more template images, each of which represents the baseline of the thread execution of the processing unit. If the difference between the image and at least one of the template images is less than a specified threshold, the image is classified as representing the baseline of the thread execution.

[0027] According to the second aspect, a method for monitoring the performance of a processing unit executing multiple threads is provided, the method comprising:

[0028] The analysis process unit runs over a period of time to generate an activity profile that indicates when each of the multiple threads was executed by the processing unit during that period of time.

[0029] Analyze the generated activity profile to determine whether the signatures of thread executions within a processing unit during that time period match the signature of the baseline indicating the thread execution of the processing unit; and

[0030] If the signature of the thread execution of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, an alarm signal is output.

[0031] The analysis steps may include identifying each thread being executed by the processing unit during that time period to generate an activity profile.

[0032] The processing unit may be part of an integrated circuit chip, and the method may include identifying the thread being executed by monitoring traffic via the interconnect circuitry of the integrated circuit chip.

[0033] The method may include identifying each thread being executed by the processing unit by accessing a storage location maintained by the processing unit, which indicates the thread being executed by the processing unit.

[0034] This method may include identifying each thread being executed by the processing unit from the sideband signals transmitted from the self-processing unit.

[0035] The method may also include storing the generated activity profile as a data array.

[0036] The steps of analyzing the generated activity profile may include using data processing algorithms on the data array to determine whether the activity profile can be classified as a baseline indicating the execution of threads in a processing unit.

[0037] The data processing algorithm can be a trained data classification model.

[0038] The method may include using a data processing algorithm to calculate the difference between a data array and each of a group of one or more template data arrays, each of which indicates the baseline of thread execution of a processing unit, wherein if the difference between the data array and at least one of the template arrays is less than a specified threshold, the data array is classified as the baseline indicating thread execution.

[0039] The method may include: using a data processing algorithm to extract the value of a group of one or more parameters from a data array, the value representing the signature of the thread execution of the processing unit within the time period; and comparing the extracted value with the corresponding parameter value of the signature indicating the baseline of the thread execution.

[0040] The method may include: outputting an alarm signal if the data array is classified as not representing the baseline of thread execution of a processing unit.

[0041] The data array may be an image depicting when each thread is executed by the processing unit within that time period, and the data processing algorithm may be an image processing algorithm.

[0042] The steps of analyzing the generated activity profile may include using image processing algorithms on the generated image to determine whether the generated image can be classified as a baseline depicting the thread execution of the processing unit.

[0043] The image processing algorithm can be a trained image classification model.

[0044] Image processing algorithms can calculate the difference between a generated image and each of a group of one or more template images, each of which represents the baseline of the thread execution of the processing unit. If the difference between the image and at least one of the template images is less than a specified threshold, the image is classified as representing the baseline of the thread execution.

[0045] According to a third aspect, a non-transitory computer-readable storage medium is provided, having stored thereon computer instructions that, when executed by a computing unit including a processing unit configured to execute multiple threads, cause the computing unit to perform a method for monitoring the performance of the processing unit, the method comprising:

[0046] The analysis process unit runs over a period of time to generate an activity profile that indicates when each of the multiple threads was executed by the processing unit during that period of time.

[0047] Analyze the generated activity profile to determine whether the signatures of thread executions within a processing unit during that time period match the signature of the baseline indicating the thread execution of the processing unit; and

[0048] If the signature of the thread execution of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, an alarm signal is output. Attached Figure Description

[0049] The invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

[0050] Figure 1 This is a schematic diagram of the architecture of an example integrated circuit chip.

[0051] Figure 2 This is a schematic diagram of the architecture of an example integrated circuit chip.

[0052] Figure 3 This is a schematic diagram of an analysis unit used to analyze the performance of a processing unit that executes multiple threads.

[0053] Figure 4 An example is shown where a processing unit executes five threads in an interleaved manner over a period of time.

[0054] Figure 5 A flowchart illustrating the steps of a method for analyzing the performance of a processing unit that executes multiple threads is shown. Detailed Implementation

[0055] The following disclosure describes an analysis architecture for profiling the performance of a processing unit executing multiple instruction threads. The analysis architecture and processing unit may be part of an integrated circuit chip (ICC), i.e., implemented on an integrated circuit chip (ICC). The integrated circuit chip may be a System-on-a-Chip (SoC) or a Multi-Chip Module (MCM). The analysis architecture includes an analysis unit that monitors the performance of the processing unit to obtain an activity profile of the processing unit as the processing unit executes threads interleaved within a specified time period. The activity profile indicates when each thread is being executed by the processing unit within that time period; that is, it contains information describing the interleaved execution of threads. The analysis unit can analyze the processing unit to generate the activity profile in a non-intrusive manner, i.e., without interrupting the execution of instructions performed by the processing unit. This can be accomplished, for example, by implementing the analysis unit as a hardware block that monitors traffic via interconnect circuitry while the processing unit executes threads. Once the activity profile has been generated, the analysis unit analyzes the profile to determine whether the signature used for thread execution within that time period matches a signature indicating a specified operating mode. The specified operating mode may be a “normal” or “safe” operating mode of the processing unit. A signature can refer to a thread execution mode, or more generally, information representing that mode. If the analysis unit determines that the signature used for thread execution during the monitored period does not match the signature indicating a specified operating mode, the analysis unit generates an output signal. The output signal indicates that the processing unit is not operating according to the specified operating mode. For example, the output signal may indicate that the processing unit is not operating in a normal or safe operating mode; that is, it is operating in an abnormal manner. The signal may be output to another component of the ICC or to a component located outside the chip.

[0056] Figures 1 to 3 These are schematic diagrams of the ICC architecture and its components. The structure is presented in the form of functional blocks. Some functional blocks performing functions well-known in the art have been omitted. Functional blocks may not depict different physical structures and may not define strict divisions between different logical elements of the ICC device. Each functional block may be implemented in hardware, software, or a combination thereof.

[0057] Figure 5 A flowchart illustrating the steps of a method for monitoring the performance of a processing unit is provided. However, this flowchart is not intended to necessarily restrict the order in which the steps of the method can be performed. The steps of the method can be in conjunction with... Figure 5 The steps of this method can be executed in different orders as shown. The steps can also be implemented concurrently with each other, allowing the implementation of different steps to at least partially overlap in time.

[0058] Figure 1The overall structure of an exemplary analysis architecture for ICC 100 is shown. ICC may be a system-on-a-chip (SoC) device. ICC 100 includes system circuitry 102 and analysis unit 104.

[0059] System circuit 102 includes multiple processing units. In this example, there are three processing units: 106, 108, and 110. Each processing unit can be, for example, a CPU (e.g., a single-core CPU, a dual-core CPU, a quad-core CPU, etc.) or a GPU. The processing units can each be arranged to support multithreading by interleaving multiple threads in time. In the example described herein, each processing unit executes five threads; however, it should be understood that this number was chosen solely for illustrative purposes. System circuit 102 may include additional components, which, for clarity, are... Figure 1 Not shown in the image.

[0060] The analysis unit 104 is configured to analyze the performance of one or more of the processing units 106-110, and generate an output signal if it determines that the signature of the thread executed by the processing unit indicates that the processing unit is not operating in a normal or safe manner, i.e., it is operating in an abnormal manner.

[0061] Figure 2 A more detailed view of the exemplary architecture of ICC 100 is shown. System circuitry is shown including processing units 106, 108, and 110; core device 202; interconnect circuitry 202; memory 206; and communication interface 208. It should be understood that, depending on the implementation, any number of core devices can be suitably implemented within the ICC. Exemplary core devices include DSPs (Digital Signal Processors), video processors, system memory, buses, software, data, custom circuitry, and data engines. This list of examples is non-limiting, and any component of the ICC is suitable to be incorporated as a core device. Figure 2 In the architecture shown, the core device can be an emulator or simulator of other devices on the chip. For example, the core device can emulate a processor. It should be noted that processing units 106-110, memory 206, and interconnect circuitry 204 are also examples of core devices, but they are omitted for clarity. Figure 2 It is shown as a separate component.

[0062] Processing units 106-110 and core device 202 are shown connected to interconnect circuitry 204. Interconnect circuitry 204 can be a bus or a bus network. Optionally, interconnect circuitry can be a network of nodes (e.g., a mesh network of nodes), a ring network, or a shared hub. Optionally, interconnect circuitry can include any combination of one or more shared hubs, buses, ring networks, and mesh networks.

[0063] Interconnect circuit 204 transmits data between components of ICC 100. Data can be transmitted via interconnect circuit 204 in the form of discrete messages. Messages can form part of a service between components of the ICC managed by a service protocol. That is, a service may include transmitting one or more messages between components of the ICC. In other words, the interconnect circuit can transmit data as a service between components of the ICC according to a service protocol. The interconnect circuit may, for example, support services between different core devices. Each service message transmitted via the interconnect circuit may include multiple fields. Each message may, for example, include an address field. The address field may contain an indication of a source address and / or a destination address. The address field may, for example, store a source ID, i.e., the ID of the device / component that initiated the message communication. The device or component that initiated the message communication may be referred to as the initiator. Therefore, the address field may contain the initiator's ID. The address field may additionally store a destination ID, i.e., the ID of the intended receiving device / component of the message. The device / component that initiated the service may be referred to herein as the master device / component. Alternatively, or additionally, the address field may contain an indication of the address of a device or component within ICC 100 that is a party to the service but does not initiate the service (which may be referred to here as a slave device / component). For example, the address field may contain the ID of one or each (slave) device / component that is a party to the service. Thus, the master device can initiate (and terminate) the service. Where the message originates from one of the processing devices 106-110, the message may contain an indication of the thread executed by the processing unit that caused the message to be transmitted. This indication may be in the form of a thread ID.

[0064] A slave device can listen to the interconnect circuit to receive messages. A slave device can be a device addressed by a master device. Each device in ICC 100 can also be a transmitter device, a receiver device, or both. A transmitter device is a device that sends messages to the interconnect circuit 204. A receiver device is a device that receives data from the interconnect circuit 204. A transmitter device / receiver device does not necessarily have to be a master device / slave device, respectively. For example, a master device can operate as a receiver device; similarly, a slave device can operate as a transmitter device. In some examples, the communication protocol managing services through the interconnect circuit 204 may specify that only one master device can be active at a time.

[0065] Memory 206 is shown connected to interconnect circuitry 204. Memory 206 may be non-volatile memory. Memory 206 may be the system memory of ICC 100. Although the system memory has been described above as an example of a core device, for clarity, memory 206 (such as interconnect circuitry 204) is shown as a separate component. Memory 206 may be formed from one or more physical storage devices, which may be physically connected or separate. Memory 206 may be formed from multiple sub-regions or portions referred to as memory blocks. That is, a memory block may be referred to herein as part of the memory. Memory 206 may be formed from multiple blocks. These blocks may have the same size as each other or different sizes from each other.

[0066] Analysis unit 104 can be connected to interconnect circuit 204 or directly to processing unit (for clarity, in...). Figure 2 The diagram shows the connection to only one processing unit (106). Therefore, the analysis unit 104 is a hardware block, i.e., it is a hardware circuit. If connected to the interconnect circuit 204, the analysis unit 104 can be said to be connected to the processing unit via the interconnect circuit 204. The possible connections of the analysis unit 104 to the system circuit will be explained in more detail below.

[0067] Analysis unit 104 is also shown connected to communication interface 208. Communication interface 208 can be configured to communicate with entities outside the chip (i.e., entities outside chip 100). For example, analysis unit 104 can communicate with an external debug controller 210 via communication interface 208, for example, by transmitting information about the performance of the analyzed processing units 106, 108, and 110. Communication interface 208 can also be configured to communicate with other entities on the chip. For example, analysis unit 104 can communicate with an on-chip debug controller via communication interface 208. Figure 2 (not shown in the image) communicates. Although... Figure 2 One communication interface is shown, but any number of communication interfaces can be integrated onto the ICC 100. The implemented communication interface is selected based on the type of connection to be established. Exemplary communication interfaces include: traditional debug interfaces such as JTAG, parallel trace input / output, and Aurora-based high-speed serial interfaces; and reused system interfaces such as USB, Ethernet, RS232, PCIe, and CAN.

[0068] A method will now be described in which analysis unit 104 analyzes the operation of a processing unit to detect whether the processing unit is operating according to a specified operating mode (e.g., a safe or normal operating mode) or is operating in an abnormal manner. (See also...) Figure 5The method is described using a flowchart. In this example, the processing unit being analyzed is processing unit 106. This processing unit is chosen for illustrative purposes only, and it should be understood that one or more processing units 108 and 110 can be analyzed in a similar manner.

[0069] At step 501, the analysis unit 104 analyzes the operation of the processing unit 106 over a time period to generate an activity overview. This time period may be referred to herein as the "analysis time period".

[0070] The time period can be a specified time period. The value of the time period can be specific to the implementation method. The value of the time period can be set by the analysis unit 104. It can be programmable.

[0071] The activity profile indicates when each of the multiple instruction threads is being executed by processing unit 106 within the analysis period. In other words, the activity profile describes (e.g., specifies) the interleaved execution of threads by processing unit 106. The activity profile can indicate the time interval for each thread to be executed by processing unit 106. That is, the activity profile can indicate the start and end times of execution for each thread within the analysis period. The granularity of the activity profile can vary depending on the implementation, but at its finest granularity, it can indicate the number of clock cycles taken by processing unit 106 to execute each thread within that time period. That is, the activity profile can indicate the time interval for each thread to be executed by the processing unit in clock cycles.

[0072] Figure 3 An example internal architecture of the analysis unit 104 is shown. It includes a thread identification unit 302, a memory 304, and a processing unit 306. The memory 304 may be internal memory of the analysis unit 104 or a part thereof. The memory 304 stores data defining an activity summary. For each thread, the memory 304 stores information indicating when the thread is executed by the processing unit 106 during the analysis period. As mentioned above, this information may be in the form of an execution time interval or an execution start time and end time. In the example shown, the memory 304 includes a set of entries, each corresponding to a specific thread executed by the processing unit 106. The analysis unit 104 may store timing information for executing the associated thread within each entry.

[0073] To analyze the performance of processing unit 106, analysis unit 104 tracks the threads executed by processing unit 106 during the specified time period. In other words, analysis unit 104 identifies each thread currently being executed by processing unit 106 during the specified time period. This allows it to determine the time interval during which each thread is being executed and write it to memory 304.

[0074] The thread identification unit 302 performs the identification of the thread currently being executed by the processing unit 106. One way to identify the thread being executed by the processing unit 106 is to monitor traffic transmitted via the interconnect circuit 204. This is possible if the analysis unit 104 is connected to the interconnect circuit 204. As described above, a message that constitutes part of traffic caused by the execution of an instruction by the processing unit may contain an indication of the thread to which that instruction constitutes part. Therefore, by monitoring traffic transmitted via the interconnect circuit, the thread identification unit 302 (and thus more generally the analysis unit 104) can determine when and which thread is being executed by the processing unit. Alternatively, the identifier (e.g., ID) of the thread being executed by the processing unit 106 may be transmitted in a sideband signal transmitted via the interconnect circuit 204, which may be monitored by the analysis unit 104. An example of an interconnect circuit that supports sideband signal transmission is an AXI bus. Sideband signals can refer to signals that are not part of the bus standard used to form part of the interconnect circuit, but are transmitted between two components via the bus and are understandable to the component to which they are transmitted (i.e., carry meaningful data). “Monitoring” the interconnect circuit can mean that analysis unit 104 observes communications (e.g., traffic and / or sideband signals) via the interconnect circuit without extracting those communications from the interconnect circuit. For example, copies of those communications can be generated by the analysis unit and analyzed to identify threads. After analysis, the analysis unit can then discard those copies of communications. This is convenient because it allows the interconnect circuit to be observed without interfering with communication transmissions on ICC 100.

[0075] Alternatively, thread identification unit 302 can identify the thread being executed by processing unit 106 by observing or monitoring an indication of the thread ID stored in a memory area maintained by processing unit 106. In other words, processing unit 106 can maintain a memory area storing an indication of the thread currently being executed by the processing unit. This memory area can be a hardware cache or a register. For example, it can be a status register, such as the CPU status register if processing unit 106 is a CPU. It can be internal to the processing unit, or it can be external but accessible to the processing unit. The memory area forms part of ICC 100. Figure 2In the example shown, this memory region forms part of memory 206. The thread identification unit 302 can observe the thread ID stored in the maintained memory region from signals transmitted from the processing unit 106. The observed signals may be, for example, signals transmitted by the processing unit 106 to update or set the thread ID stored in the memory region. Alternatively, the thread identification unit 302 can access the maintained memory region to determine the thread being executed by the processing unit 106. The thread identification unit 302 can access this memory region periodically.

[0076] After identifying the thread being executed by processing unit 106, thread identification unit 302 transmits the thread's indication to memory 304. Memory 304 can then identify the start time of the thread's execution, for example, using a clock signal from clock 308. Although clock 308 is shown as part of analysis unit 104 in this example, it should be understood that in other examples, the memory may receive a clock signal from an external clock source. In response to receiving an indication from thread identification unit 302 that the currently executing thread has changed, memory 304 uses the received clock signal to record the execution stop time of the previous thread and the execution start time of the next thread. Therefore, in general, in response to receiving an indication from thread identification unit 302 that a specific thread is being executed by processing unit 106, memory 304 uses the received clock signal to perform the following actions: 1) record the execution end time of the previous thread in the associated entry; 2) record the execution start time of the specific thread in the associated entry.

[0077] The above-described method for thread execution in analysis processing unit 106 can be conveniently executed in a non-intrusive manner. That is, analysis unit 104 can analyze thread execution without interrupting thread execution. This is because analysis unit 104 is either a hardware component that enables analysis by monitoring, for example, traffic or signals transmitted through interconnect circuits, or a memory maintained by the processing unit. In contrast, a typical method for analysis interrupts the execution of instructions at the processing unit to enable the running of analysis software, which is intrusive.

[0078] After generating an activity profile representing the threads executed interleaved in time by processing unit 106 during the analysis period, analysis unit 104 stores the activity profile. The activity profile can be stored in memory, for example, the local memory of analysis unit 104. Figure 3(Not shown in the image) or some other memory in the ICC 100, such as memory 206. Activity profiles can be stored as data arrays containing information about the number of times each thread was executed by the processing unit during the analysis period. Examples of different types of data arrays will be explained in more detail below.

[0079] Return to Figure 5 In step 503, analysis unit 104 analyzes the activity overview to determine whether the signatures executed by the thread during the analysis period match the baseline signature. This step can be performed by processing unit 306.

[0080] The signature of thread execution in processing unit 106 refers to the mode of thread execution in processing unit 106, or more generally, the characteristics of the mode of thread execution. The mode of thread execution in processing unit can be characterized relative to a group of one or more parameters relating to thread execution. These parameters may include, for example, one or more of the following: the total number of thread switches; the average length of thread execution; the maximum length of thread execution; the minimum length of thread execution; the average frequency of thread switches; the maximum and / or minimum frequency of thread switches; the order of thread execution, etc.

[0081] A baseline signature can refer to a signature indicating the operating baseline (i.e., thread execution) used for processing unit 106, where the operating baseline / thread execution is the type of operating / thread execution of processing unit 106, which serves as the basis for comparing or measuring changes or deviations. Therefore, the operating baseline / thread execution can be the normal, typical, or expected operating / thread execution used for processing unit 106.

[0082] Analysis unit 104 may store a set of one or more baseline signatures for processing unit 106. In some examples, the baseline signatures may be generated by analysis unit 104 by analyzing processing unit 106 over time. For example, analysis unit 104 may update the baseline signatures over time by analyzing processing unit 106 over multiple analysis periods. In other examples, the baseline signatures may be pre-generated and stored.

[0083] If the signature determined from the activity profile matches the baseline signature within a specified amount or threshold, the analysis unit 104 can determine that the signature determined from the activity profile matches the baseline signature. In other words, if the signature determined from the activity profile deviates from or differs from the baseline signature by more than a predetermined amount, the analysis unit 104 can determine that the signature determined from the activity profile does not match the baseline signature. The analysis unit 104 uses a comparison between the baseline signature and the thread execution signature determined from the activity profile to determine whether the processing unit 106 is running in a specified operating mode corresponding to a normal, typical, or expected operating mode. If the analysis unit 104 determines that the signature from the activity profile does not match at least one of the baseline signatures, it determines that the processing unit 106 is not running in a normal or typical manner, i.e., it is running in an abnormal manner. Conversely, if the analysis unit determines that the signature from the activity profile does match at least one of the baseline signatures, it determines that the processing unit 106 is running in a normal or typical manner, i.e., it is not running in an abnormal manner.

[0084] The analysis of an activity profile can be performed in different ways depending on how the data for the activity profile is stored.

[0085] In one set of examples, the analysis cell stores the activity overview as a data array. This data array can be a linear or two-dimensional array. It can be in tabular form, such as a CSV file.

[0086] Processing unit 306 can use a data processing algorithm to analyze the data array to determine whether the activity profile can be categorized as indicating baseline thread execution. To this end, the data processing algorithm may analyze the data array to determine the signatures of thread executions indicated by the data array during the analysis period. These signatures can then be used to determine whether the thread executions during the analysis period match baseline thread executions.

[0087] The data processing algorithm can be a trained data classification model. This model can be trained, for example, using machine learning or deep learning techniques. It can be trained to classify an array of input data into either indicative of baseline thread execution or not. The model can be trained using a desired baseline or a specified baseline that specifically indicates thread execution. Therefore, in this example, the signature of thread execution is not explicitly determined but is implicitly extracted and analyzed using the trained data classification model.

[0088] Alternatively, the data processing algorithm can calculate the difference between a data array and each of a group of one or more template data arrays, each data array indicating the baseline of thread execution. If the difference between the array and at least one template array is less than a specified threshold, the data processing algorithm can classify the data array of the activity profile as the baseline indicating thread execution. This difference can be calculated on an array-by-array basis. For example, the difference can be calculated as the sum of the absolute differences between the arrays.

[0089] In another example, the data processing algorithm can extract the values ​​of one or more parameters from a data array, representing the signature of the thread execution within the analysis period indicated by the data array (i.e., the parameters identified above). The data processing algorithm can then compare the values ​​of those parameters with the stored values ​​of the baseline signature to determine if the signatures match. Thus, the signature of the thread execution can be explicitly determined. If the parameter group contains more than one parameter, the extracted values ​​are compared with the corresponding values ​​in the baseline signature.

[0090] In one set of examples, the data array could be an image (e.g., a digital image). This image depicts when each thread is executed by processing unit 106 during the analysis period. In other words, the image depicts the temporal crossover of threads executed by processing unit 106. Examples of such images are... Figure 4 This is shown at position 401. Here, solid blocks indicate the time interval during which a thread is being executed by a processing unit. In this example, five threads are executed.

[0091] If the data array is stored as an image such as image 401, the data processing algorithm executed by processing unit 306 can be an image processing algorithm. For example, the data processing algorithm can be a trained image classification model that classifies the input image as an indication of whether a baseline thread is being drawn or not. The image classification model can be trained using images that do indeed depict the baseline of thread execution.

[0092] Alternatively, the image processing algorithm can calculate the difference between an image (e.g., image 401) and each of a group of one or more template images, each template image representing the baseline of thread execution. If the difference between the image and at least one of the template images is less than a specified threshold, the data processing algorithm can classify the image of the activity profile as representing the baseline of thread execution. This difference can be calculated on an entry-by-entry basis (e.g., in blocks, where a block is a block of one or more pixels). For example, the difference can be calculated as the sum of the absolute differences between the images.

[0093] Image processing algorithms can analyze an image (e.g., perform image or object recognition) to extract the values ​​of a set of one or more parameters that characterize features of a signature used for execution by a thread depicted by the image, such as the parameters identified above. The image processing algorithm can then compare the values ​​of those parameters with stored values ​​of a baseline signature to determine if the signatures match (and thus determine if the image obtained from the activity profile depicts the baseline of thread execution).

[0094] At step 505, if processing unit 306 determines that the signature of the thread execution of processing unit 106 does not match the baseline signature, an alarm signal is generated. In other words, processing unit 306 generates an alarm signal only if it determines from its analysis that the signature of the thread execution of the processing unit during the analysis period does not match the baseline signature or has deviated from the baseline signature. The alarm signal can therefore indicate that processing unit 106 is not operating in baseline operating mode, such as not operating in the expected, typical, or normal manner. In other words, the alarm signal may indicate that the processing unit is operating in an abnormal manner.

[0095] Alarm signals can be transmitted via communication interface 208 to an on-chip or off-chip entity. The alarm signal can trigger the receiving component to perform a response action. For example, the alarm signal can indicate that processing unit 106 has been compromised, in which case the response action could be to disable the processing unit, for example, by powering it off or preventing it from executing further instructions. Alternatively, the response action could be to lock the data path from processing unit 106 to interconnect circuitry to prevent data from processing unit 106 from propagating through the ICC.

[0096] Processing unit 306 may alternatively or additionally analyze the activity profile to determine whether any thread has been executing for an unusually long period of time. For example, the processing unit may determine whether a thread has any consecutive execution periods exceeding a specified threshold. Each thread may be associated with the same threshold or a corresponding threshold. Processing unit 306 may generate an output signal in response to detecting that a thread has been executing for a consecutive period of time exceeding the threshold. The output signal may contain an indication (e.g., ID) of the thread that exceeded its threshold. If more than one thread exceeds its threshold, the output signal may contain an indication of each of those threads.

[0097] The analysis unit 104 described herein can be configured to operate for chip security, chip safety, or chip analysis purposes. In the context of this disclosure, chip security may involve detecting data errors on the chip that have the potential malicious intent to be obtained by a third party. Chip safety may involve detecting data errors on the chip that have more serious potential consequences, such as the dangerous impact on a wider system in which the chip is implemented. Chip analysis may involve analyzing the behavior of the chip to gain a further understanding of how the chip works or operates. Chip analysis can be performed by dedicated analysis software that may execute outside the chip.

[0098] The response action triggered by an alarm signal from the analysis unit can depend on the environment in which the analysis unit is operating (i.e., chip security, chip analysis, or chip security environment). For chip security, the response action can prevent a security breach. For example, in a chip security environment, a data error could lead to a more severe response action, such as shutting down or disabling the chip (or at least a portion of the chip).

[0099] Figures 1 to 3 Each component of the ICC shown can be implemented in dedicated hardware. Alternatively, Figures 1 to 3 Each component of the SoC shown can be implemented in software. Some components can be implemented in software, while others can be implemented in dedicated hardware.

[0100] The analysis unit 104, including any sub-units and communication interfaces, can be a hardware circuit constituting part of the ICC 100. Components of the analysis unit used for controlling and / or monitoring complex core devices and peripheral devices (e.g., processors) can use appropriately complex state machines as part of their control units. Appropriately, the communication interface uses an appropriately complex state machine to implement its complex protocol. Various methods for implementing state machines are known. Such a state machine can be implemented using: (i) logic gates only; (ii) a combination of logic gates and memory, where the memory is used to contain tables of values ​​to simplify the operation of the state machine or to make it programmable; or (iii) a processor core that executes software stored in memory. When using a processor core, it can: (i) be integrated with sub-units, communication interfaces, or other monitoring circuitry; or (ii) be shared among several units to reduce its implementation resources and costs.

[0101] The described ICC can be incorporated into a computing-based device. A computing-based device can be an electronic device, such as a smartphone, smartwatch, laptop, PC, or other devices that form part of a broader computing system, such as a video processor, control system (e.g., for controlling an electric motor, battery, energy management system in automotive applications), engine control unit (ECU), etc. Suitablely, a computing-based device includes one or more processors or computing units for processing computer-executable instructions to control the operation of the device to implement the methods described herein. The computer-executable instructions can be provided using any computer-readable medium (e.g., memory). The computer-readable medium can be non-transitory. The methods described herein can be executed by software in a machine-readable form on a tangible storage medium. Software can be provided at the computing-based device to implement the methods described herein.

[0102] The above description portrays system circuitry and analysis units as residing on the same ICC. In alternative embodiments, system circuitry and analysis units are implemented on two or more integrated circuit chips of the MCM. In an MCM, integrated circuit chips are typically stacked or placed adjacent to each other on an interposer substrate. Some system circuitry may reside on one integrated circuit chip, while other system circuitry may reside on different integrated circuit chips of the MCM. Similarly, analysis units can be distributed across more than one integrated circuit chip of the MCM. Therefore, the methods and apparatus described above in the SoC environment are also applicable to the MCM environment.

[0103] The applicant hereby separately discloses each individual feature described herein, as well as any combination of two or more such features, to the extent that such features or combinations can be performed on the basis of this specification as a whole, based on knowledge known to those skilled in the art, without regard to whether such features or combinations of features solve any problem disclosed herein, and not to limit the scope of the claims. The applicant notes that aspects of the invention can consist of any such individual feature or combination of features. In view of the foregoing description, it will be apparent to those skilled in the art that various modifications can be made within the scope of the invention.

Claims

1. An apparatus comprising: A processing unit configured to execute multiple threads; The analysis unit is configured as follows: The operation of the processing unit is analyzed over a time period to generate an activity profile, which indicates when each of the plurality of threads was executed by the processing unit during the time period. The generated activity profile is analyzed to determine whether the signature of the thread execution of the processing unit during the time period matches the signature of the baseline indicating the thread execution of the processing unit, wherein the signature of the thread execution of the processing unit represents the characteristics of the thread execution mode of the processing unit, and the signature of the baseline indicating the thread execution of the processing unit represents the characteristics of the expected thread execution mode of the processing unit. If the signature executed by the thread of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, an alarm signal is output.

2. The apparatus according to claim 1, wherein, The activity overview indicates the number of processing unit clock cycles required to execute each thread within the time period.

3. The apparatus according to claim 1 or 2, wherein, The analysis unit is configured to analyze the operation of the processing unit by identifying each thread being executed by the processing unit within the time period in order to generate the activity overview.

4. The apparatus according to claim 3, wherein, The device is an integrated circuit chip including interconnect circuitry, and the analysis unit is configured to: monitor traffic via the interconnect circuitry of the integrated circuit chip to identify each thread being executed by the processing unit during the time period.

5. The apparatus according to claim 3, wherein, The processing unit is configured to maintain a storage location indicating the thread being executed, and the analysis unit is configured to identify each thread being executed by accessing the storage location.

6. The apparatus according to claim 3, wherein, The analysis unit is configured to identify each thread being executed from sideband signals, wherein the sideband signals are transmitted from the processing unit.

7. The apparatus according to claim 1 or 2, wherein, The analysis unit is configured to store the generated activity profile as a data array.

8. The apparatus according to claim 7, wherein, The analysis unit is configured to use a data processing algorithm on the data array to analyze the generated activity profile to determine whether the activity profile can be classified as a baseline for instructing the execution of threads of the processing unit.

9. The apparatus according to claim 8, wherein, The data processing algorithm is a trained data classification model.

10. The apparatus according to claim 8, wherein, The analysis unit is configured to use the data processing algorithm to calculate the difference between the data array and each of a group of one or more template data arrays, wherein each of the template data arrays indicates the baseline of thread execution of the processing unit, and if the difference between the data array and at least one of the template data arrays is less than a specified threshold, the data array is classified as the baseline indicating thread execution.

11. The apparatus according to claim 8, wherein, The analysis unit is configured to: extract the values ​​of one or more sets of parameters from the data array using the data processing algorithm, which characterize the signature executed by the thread of the processing unit during the time period; and compare the extracted values ​​with the corresponding parameter values ​​of the signature indicating the baseline of the thread execution.

12. The apparatus according to claim 11, wherein, The group of one or more parameters includes one or more of the following: the total number of thread switches during the time period; the average length of thread execution during the time period; the maximum length of thread execution during the time period; the minimum length of thread execution during the time period; the average frequency of thread switches during the time period; the maximum and / or minimum frequency of thread switches during the time period; and the order of thread execution during the time period.

13. The apparatus according to claim 8, wherein, The analysis unit is configured to output the alarm signal if the data array is classified as not representing the baseline of thread execution of the processing unit.

14. The apparatus according to claim 8, wherein, The data array is an image depicting when each thread is executed by the processing unit within the time period, and the data processing algorithm is an image processing algorithm.

15. The apparatus according to claim 14, wherein, The analysis unit is configured to use the image processing algorithm on the generated image to analyze the generated activity profile in order to determine whether the generated image can be classified as a baseline depicting the thread execution of the processing unit.

16. The apparatus according to claim 15, wherein, The image processing algorithm is a trained image classification model.

17. The apparatus according to claim 15, wherein, The analysis unit is configured to use the image processing algorithm to calculate the difference between the generated image and each of a group of one or more template images, wherein each of the one or more template images depicts the baseline of thread execution of the processing unit, and if the difference between the generated image and at least one of the template images is less than a specified threshold, the generated image is classified as depicting the baseline of thread execution.

18. A method for monitoring the performance of a processing unit executing multiple threads, the method comprising: The operation of the processing unit is analyzed over a time period to generate an activity profile, which indicates when each of the plurality of threads was executed by the processing unit during the time period. The generated activity profile is analyzed to determine whether the signature of the thread execution of the processing unit during the time period matches the signature of the baseline indicating the thread execution of the processing unit, wherein the signature of the thread execution of the processing unit represents the characteristics of the thread execution mode of the processing unit, and the signature of the baseline indicating the thread execution of the processing unit represents the characteristics of the expected thread execution mode of the processing unit. and If the signature executed by the thread of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, an alarm signal is output.

19. A non-transitory computer-readable storage medium storing computer instructions thereon, the computer instructions, when executed by a computing unit including a processing unit configured to execute multiple threads, causing the computing unit to perform a method of monitoring the performance of the processing unit, the method comprising: The operation of the processing unit is analyzed over a time period to generate an activity profile, which indicates when each of the plurality of threads was executed by the processing unit during the time period. The generated activity profile is analyzed to determine whether the signature of the thread execution of the processing unit during the time period matches the signature of the baseline indicating the thread execution of the processing unit, wherein the signature of the thread execution of the processing unit represents the characteristics of the thread execution mode of the processing unit, and the signature of the baseline indicating the thread execution of the processing unit represents the characteristics of the expected thread execution mode of the processing unit. and If the signature executed by the thread of the processing unit during the time period does not match the signature of the baseline indicating the thread execution of the processing unit, an alarm signal is output.

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