Semiconductor memory module

Abstract

A semiconductor memory module is disclosed. The semiconductor memory module includes a memory printed circuit board (PCB) including a plurality of first connectors configured to be connectable with an external device, a second connector, and a third connector, memory devices mounted on the memory PCB and connected with the plurality of first connectors, and a power management integrated circuit mounted on the memory PCB, receiving a first voltage through the second connector, generating a second voltage from the first voltage, and providing the second voltage to the plurality of memory devices. The power management integrated circuit adjusts the second voltage according to a difference between a signal received through the third connector and the second voltage.

Description

Technical Field

[0001] This disclosure relates to semiconductor circuits, and more specifically, to semiconductor memory modules including power management integrated circuits. Background Technology

[0002] In response to the increasing demand for devices with lower power consumption, power management integrated circuits (PMICs) that reduce power consumption by regulating voltage levels are being developed. Many recent computing devices have been designed to incorporate power management integrated circuits.

[0003] Dual in-line memory modules (DIMMs) are being used as main memory in computing devices. By mounting various volatile or non-volatile memories on DIMMs, they provide storage space for main memory in computing devices.

[0004] As an example of dynamic random access memory (DRAM), Double Data Rate 5 (DDR5) Synchronous Dynamic Random Access Memory (SDRAM) is being developed. To correspond with and support the features of DDR5 SDRAM, DIMMs for DDR5 SDRAM are also being developed. DIMMs for DDR5 SDRAM are being designed to allow power management integrated circuits to be mounted on them. Summary of the Invention

[0005] Embodiments of the inventive concept provide a semiconductor memory module with lower power consumption and improved reliability.

[0006] According to an exemplary embodiment, a semiconductor memory module includes: a memory printed circuit board (PCB) including a plurality of first connectors, a second connector, and a third connector configured to connect to an external device; a plurality of memory devices mounted on the memory PCB and connected to the plurality of first connectors; and a power management integrated circuit mounted on the memory PCB. The power management integrated circuit is configured to: receive a first voltage through the second connector to generate a second voltage from the first voltage, and supply the second voltage to the plurality of memory devices. The power management integrated circuit is further configured to: adjust the second voltage based on the difference between a signal received through the third connector and the second voltage.

[0007] According to an exemplary embodiment, a semiconductor memory module includes: a memory printed circuit board (PCB) including a plurality of first connectors and a second connector configured to connect to an external device; a plurality of memory devices mounted on the memory PCB and connected to the plurality of first connectors; and a power management integrated circuit mounted on the memory PCB. The power management integrated circuit is configured to: receive a first voltage through the second connectors, generate a second voltage from the first voltage, and supply the second voltage to the memory devices. The power management integrated circuit may be configured to: adjust the second voltage according to the amount of current flowing during idle time.

[0008] According to an exemplary embodiment, a semiconductor memory module includes: a memory printed circuit board (PCB) including a plurality of first connectors, a second connector, and a third connector configured to connect to an external device; a plurality of memory devices mounted on the memory PCB and connected to the plurality of first connectors; and a power management integrated circuit mounted on the memory PCB. The power management integrated circuit is configured to: receive a first voltage through a second connector, generate a second voltage from the first voltage, and supply the second voltage to the memory devices. In a first mode, the power management integrated circuit is configured to: adjust the second voltage based on the difference between a signal received through the third connector and the second voltage. In a second mode, the power management integrated circuit is configured to: adjust the second voltage based on the amount of current flowing during idle time. Attached Figure Description

[0009] The above and other objects and features of the inventive concept will become clear by describing in detail the exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0010] Figure 1 A computing system according to some embodiments of the inventive concept is shown.

[0011] Figure 2 A computing system according to some embodiments of the inventive concept is shown.

[0012] Figure 3 A computing system according to some embodiments of the inventive concept is shown.

[0013] Figure 4 A computing system according to some embodiments of the inventive concept is shown.

[0014] Figure 5 A computing system according to some embodiments of the inventive concept is shown.

[0015] Figure 6 A computing system according to some embodiments of the inventive concept is shown.

[0016] Figure 7A computing system according to some embodiments of the inventive concept is shown.

[0017] Figure 8 A computing system according to some embodiments of the inventive concept is shown.

[0018] Figure 9 Examples of the structures of controllers and memory devices that can be used to generate DC current are shown.

[0019] Figure 10 A computing system according to some embodiments of the inventive concept is shown.

[0020] Figure 11 A computing system according to some embodiments of the inventive concept is shown.

[0021] Figure 12 A computing system according to some embodiments of the inventive concept is shown.

[0022] Figure 13 A computing system according to some embodiments of the inventive concept is shown.

[0023] Figure 14 This is a flowchart illustrating the operation method of a memory module according to some embodiments of the inventive concept. Detailed Implementation

[0024] The aspects of this disclosure will now be described in detail and clearly to the extent that those skilled in the art can readily implement the inventive concept.

[0025] Figure 1 A computing system 100 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 1 The computing system 100 may include a host device 110 and a semiconductor memory module 120. For example, the host device 110 may include various computing devices (such as computers, laptops, workstations, application servers, data servers, smartphones, smart tablets, smartwatches).

[0026] The host device 110 may include a host printed circuit board (PCB) 111, a power supply 112, a system power management integrated circuit (SPMIC) 113, a processor 114, and a device driver 117.

[0027] Power supply 112, SPMIC 113, processor 114, device driver 117, semiconductor memory module 120, or a connection device may be mounted on the host PCB 111, and the connection device is configured to be connected to power supply 112, SPMIC 113, processor 114, device driver 117, and semiconductor memory module 120.

[0028] The host PCB 111 may include a board implemented with an insulator (such as plastic) and wires for electrically connecting devices configured to connect to a power supply 112, an SPMIC 113, a processor 114, a device driver 117, and a semiconductor memory module 120.

[0029] Power supply 112 can be obtained from Figure 1 The system shown externally receives power POR and can output internal power IPOR based on the power POR. SPMIC 113 can receive the internal power IPOR and can generate host voltage VDDQ1 from the internal power IPOR. Host voltage VDDQ1 can be supplied to processor 114.

[0030] Processor 114 may include a central processing unit (CPU) or application processor (AP) that executes an operating system or application of the host device 110. Processor 114 may include a graphics processing unit (GPU) or neural processing unit (NPU) that processes a specific task in response to a request from the CPU or AP.

[0031] Processor 114 may include controller 115. Processor 114 can access semiconductor memory module 120 through controller 115. Processor 114 can access peripheral devices through device driver 117. For example, peripheral devices may include storage devices, user interfaces for exchanging information with users, etc.

[0032] Processor 114 may include controller 115. Controller 115 may be connected via multiple wires 116 on host PCB 111 to a first connector C1, a second connector C2, or a third connector C3 of semiconductor memory module 120, or to a connection device configured such that connectors C1 to C3 are connected to the connection device. Controller 115 may exchange signals with semiconductor memory module 120 via wires 116.

[0033] In one embodiment, controller 115 may be configured to exchange signals with semiconductor memory module 120 by using host voltage VDDQ1 received from SPMIC 113 as a high-level voltage and ground voltage as a low-level voltage.

[0034] The semiconductor memory module 120 may include a memory PCB 121, multiple memory devices 122, a register clock driver (RCD) 123, and a memory power management integrated circuit (MPMIC) 125.

[0035] Memory devices 122, RCD 123, MPMIC 125, or connection devices configured to connect to memory devices 122, RCD 123, MPMIC 125, may be mounted on memory PCB 121. Memory PCB 121 may include a plurality of first connectors C1, a plurality of second connectors C2, and a plurality of third connectors C3 configured to connect to (or attach to) host device 110.

[0036] The memory PCB 121 may include: a board implemented with an insulator (such as plastic); a plurality of connection devices configured to be connected to the memory device 122, RCD 123, MPMIC 125; and a plurality of wires electrically connecting the first connector C1, the second connector C2, and the third connector C3.

[0037] The memory device 122 can be connected to the first connector C1 via wires on the memory PCB 121. The first connector C1 may include the gold fingers of a dual in-line memory module (DIMM). The memory device 122 can exchange data DQ and data strobe signals DQS with an external device via the first connector C1.

[0038] The memory device 122 may include various types of memory (such as dynamic random access memory (DRAM), phase change RAM (PRAM), ferroelectric RAM (FRAM), magnetic RAM (MRAM), resistive RAM (RRAM) and flash memory).

[0039] RCD 123 can be mounted on memory PCB 121. RCD 123 can be connected to second connector C2 via wires on memory PCB 121. Second connector C2 may include the gold fingers of DIMM. RCD 123 can receive address ADDR and command CMD from host device 110 via second connector C2.

[0040] RCD 123 can also receive various signals (e.g., including clock signals and control signals) from host device 110 via second connector C2. RCD 123 can transmit address ADDR, command CMD and various signals to memory device 122 via first wire 124 on memory PCB 121.

[0041] MPMIC 125 can be mounted on memory PCB 121. MPMIC 125 can be connected to third connector C3 via wires on memory PCB 121. Third connector C3 may include the gold fingers of DIMM.

[0042] MPMIC 125 can receive input voltage VIN via third connector C3. MPMIC 125 can generate various voltages, including memory voltage VDDQ2, from input voltage VIN. MPMIC 125 can supply various voltages, including memory voltage VDDQ2, to memory device 122 and RCD 123.

[0043] For example, the input voltage VIN can include the bulk input voltage VIN_Bulk and the management input voltage VIN_mgmt. The bulk input voltage VIN_Bulk has a normal operating level of 12V and an allowable range of 10V to 13.8V in normal operating mode, and a normal operating level of 5V and an allowable range of 4.25V to 13.8V in low-power and catastrophic modes. The management input voltage VIN_mgmt has a normal operating level of 3.3V and an allowable range of 3.0V to 3.6V.

[0044] MPMIC 125 can interact with capacitors and inductors mounted on the memory PCB 121 to generate and output various voltages, including the memory voltage VDDQ2. For example, MPMIC 125 can output a voltage of 1.1V as the memory voltage VDDQ2. Furthermore, MPMIC 125 can generate and output various voltages, such as a 1.0V supply voltage VDD, a 1.8V high voltage VPP, a 1.1V output voltage VOUT_1.1V, and a 1.8V output voltage VOUT_1.8V.

[0045] Memory device 122 and RCD 123 can exchange signals with external devices using a memory voltage VDDQ2 as a high level and a ground voltage as a low level. For example, memory device 122 can exchange data DQ and data strobe signal DQS with controller 115 through first connector C1 based on memory voltage VDDQ2.

[0046] RCD 123 can receive address ADDR and command CMD through the second connector C2 based on memory voltage VDDQ2, and can exchange various signals with controller 115.

[0047] References can be organized based on register-based DIMMs (RDIMMs). Figure 1 The semiconductor memory module 120 is described. (See reference...) Figure 1 As described, the semiconductor memory module 120 can be configured to include a separate MPMIC 125, separate from the SPMIC 113. Specifically, in conjunction with the development of DIMMs corresponding to DDR5 SDRAM, this disclosure provides a configuration in which the MPMIC 125 is disposed on the semiconductor memory module 120.

[0048] exist Figure 1 In the computing system 100, the controller 115 uses the host voltage VDDQ1 as a high level when exchanging signals via the first connector C1 or the second connector C2. The memory device 122 or RCD 123 uses the memory voltage VDDQ2 as a high level when exchanging signals via the first connector C1 or the second connector C2.

[0049] When there is a difference between the host voltage VDDQ1 and the memory voltage VDDQ2, unintended direct current (DC) may flow between the memory device 122 and the controller 115, or between the RCD 123 and the controller 115. For example, the memory device 122 may be driven by a high level to drive the first connector C1, and the controller 115 may be driven by a high level to drive the first connector C1.

[0050] In this configuration, when the memory voltage VDDQ2 is lower than the host voltage VDDQ1, DC current can flow from the controller 115 to the memory device 122. Conversely, when the memory voltage VDDQ2 is higher than the host voltage VDDQ1, DC current can flow from the memory device 122 to the controller 115. The same phenomenon can occur between the RCD 123 and the controller 115.

[0051] Unintended DC current can lead to power consumption. In addition, unintended DC current can act as stress on the semiconductor memory module 120 or the controller 115, thereby reducing the reliability of the semiconductor memory module 120 or the controller 115.

[0052] To address the above problems, a semiconductor memory module according to some embodiments of the inventive concept can be configured to detect the difference between the host voltage VDDQ1 and the memory voltage VDDQ2, and adjust the memory voltage VDDQ2 to reduce the voltage difference.

[0053] Figure 2 A computing system 200 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 2 The computing system 200 may include a host device 210 and a semiconductor memory module 220. The host device 210 may include a host PCB 211, a power supply 212, an SPMIC 213, a processor 214, and a device driver 217. Each of the host PCB 211, power supply 212, SPMIC 213, processor 214, and device driver 217 is compatible with... Figure 1 Their corresponding components are similar, as shown.

[0054] Processor 214 may include controller 215. Controller 215 can be connected to semiconductor memory module 220 via multiple wires 216. In addition to the first connectors C1 to the third connectors C3 connected to semiconductor memory module 220, controller 215 can be connected to a fourth connector C4 via some corresponding wires of the wires 216. Controller 215 can send a reset signal RST to semiconductor memory module 220 via the fourth connector C4.

[0055] The reset signal RST can be an active low signal that is inactive when high and active when low. The controller 215 is configured to use the host voltage VDDQ1 as a high level. Therefore, the reset signal RST can be high in the inactive state and can have the host voltage VDDQ1.

[0056] In addition to sending the reset signal RST to the fourth connector C4, the host device 210 can also communicate with the reference. Figure 1 The host device 110 described is configured and operated in the same or similar manner. Therefore, additional descriptions will be omitted to avoid redundancy. Unless otherwise stated... Figure 1 The description given for the host device 110 is consistent with Figure 2 The description of the host device 210 is significantly different; otherwise, regarding... Figure 1 The configuration, operation, and characteristics described for the host device 110 can be applied without modification. Figure 2 The main unit 210.

[0057] The semiconductor memory module 220 may include a memory PCB 221, multiple memory devices 222, an RCD 223, and an MPMIC 225. The memory PCB 221 may include a first connector C1, a second connector C2, a third connector C3, and a fourth connector C4.

[0058] The configuration and operation of semiconductor memory module 220 can be referenced. Figure 1 The semiconductor memory module 120 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless otherwise stated... Figure 1 The description given for semiconductor memory module 120 is consistent with... Figure 2 The description of the semiconductor memory module 220 is significantly different, otherwise regarding Figure 1 The configuration, operation, and characteristics described for the semiconductor memory module 120 can be applied without modification. Figure 2 Semiconductor memory module 220.

[0059] and Figure 1Compared to memory PCB 121, memory PCB 221 may further include wires connecting the fourth connector C4 to RCD 223 and MPMIC 225. The reset signal RST received through the fourth connector C4 can be transmitted to RCD 223 and MPMIC 225.

[0060] The reset signal RST is shown separately to more clearly illustrate the technical concept of the invention; however, in some embodiments, the reset signal RST may be included in the reference... Figure 1 Among the various signals received via the second connector C2, RCD 223 can transmit a reset signal RST to memory device 222 via the first wire 224.

[0061] Memory device 222 and RCD 223 can perform initialization operations in response to activation and / or deactivation of reset signal RST (e.g., when reset signal RST is activated and then deactivated). For example, memory device 222 and RCD 223 can be used by controller 215 to perform initialization operations including mode register setting, write equalization, ZQ calibration, and DQ training.

[0062] The MPMIC 225 may include a register REG and a comparator CP. The register REG stores information about the level of the memory voltage VDDQ2 generated by the MPMIC 225. The MPMIC 225 generates the memory voltage VDDQ2 based on the information stored in the register REG.

[0063] For example, register REG can be a non-volatile memory device that stores the level information of memory voltage VDDQ2. Alternatively, the level information of memory voltage VDDQ2 can be stored in a separate non-volatile memory (not shown) within MPMIC 225, and can be loaded from the separate non-volatile memory into register REG after the input voltage VIN is supplied to MPMIC 225.

[0064] For example, register REG can store information about the default level of memory voltage VDDQ2, that is, information about the same level as host voltage VDDQ1. MPMIC 225 can generate memory voltage VDDQ2 based on the information about the default level stored in register REG.

[0065] However, due to variations in process, voltage, and temperature (PVT), the actual memory voltage VDDQ2 generated by the MPMIC 225 may differ from the host voltage VDDQ1. The MPMIC 225 can adjust the memory voltage VDDQ2 so that it is the same as the host voltage VDDQ1, or as similar as possible to the host voltage VDDQ1 within resolution limitations.

[0066] The comparator CP of the MPMIC 225 can receive a reset signal RST. As described above, the reset signal RST can have a host voltage VDDQ1 in an inactive state. The comparator CP can compare the inactive reset signal RST with the memory voltage VDDQ2 to detect the difference between the host voltage VDDQ1 and the memory voltage VDDQ2.

[0067] Based on the detected voltage difference, the MPMIC 225 can update the level information of the memory voltage VDDQ2 stored in the REG register. For example, when the detected difference is greater than a threshold, the MPMIC 225 can update the level information in the REG register. The threshold can be determined based on the smallest unit (e.g., resolution) at which the MPMIC 225 can adjust the memory voltage VDDQ2. When the level information is updated, the MPMIC 225 can adjust the level of the memory voltage VDDQ2.

[0068] For example, when the memory voltage VDDQ2 is lower than the host voltage VDDQ1, the MPMIC 225 can update the level information of the REG register, causing the memory voltage VDDQ2 to increase. When the memory voltage VDDQ2 is higher than the host voltage VDDQ1, the MPMIC 225 can update the level information of the REG register, causing the memory voltage VDDQ2 to decrease.

[0069] Here, the operation by which the MPMIC 225 compares the memory voltage VDDQ2 with the inactive reset signal RST and adjusts it to the required memory voltage VDDQ2 based on the comparison result can be called a "calibration operation".

[0070] In one embodiment, the MPMIC 225 can update the level information of the REG register such that the memory voltage VDDQ2 is adjusted to the level corresponding to the detected voltage difference. Alternatively, the MPMIC 225 can update the level information of the REG register such that the memory voltage VDDQ2 is adjusted in specific units (e.g., calibration units).

[0071] The MPMIC 225 can update the level information of register REG so that the memory voltage VDDQ2 is adjusted in a first unit (e.g., coarse calibration), and then update the level information of register REG so that the memory voltage VDDQ2 is adjusted in a second unit smaller than the first unit (e.g., fine calibration).

[0072] The MPMIC 225 can perform calibration operations on the memory voltage VDDQ2 at different times. For example, the MPMIC 225 can always compare the memory voltage VDDQ2 with the inactive reset signal RST. The MPMIC 225 can be configured to perform a calibration operation on the memory voltage VDDQ2 in response to detecting a difference between the memory voltage VDDQ2 and the inactive reset signal RST.

[0073] For example, MPMIC 225 can perform a calibration operation on the memory voltage VDDQ2 after the reset signal RST is activated and then deactivated. For example, after the reset signal RST is activated and then deactivated, memory devices 222 and RCD 223 may not communicate with controller 215 for a given time (e.g., 500 microseconds (μs)). During the given time, MPMIC 225 can perform a calibration operation on the memory voltage VDDQ2.

[0074] MPMIC 225 can perform a calibration operation on the memory voltage VDDQ2 under the control of RCD 223. RCD 223 can allow MPMIC 225 to perform a calibration operation on the memory voltage VDDQ2 when it is predicted that there will be no communication with controller 215 for a period of time. For example, when entering a self-refresh operation, RCD 223 can allow MPMIC 225 to perform a calibration operation on the memory voltage VDDQ2.

[0075] For example, the calibration operation performed by MPMIC 225 on memory voltage VDDQ2 can be activated and deactivated by controller 215. Controller 215 can activate or deactivate the calibration operation of MPMIC 225 during initialization or at the necessary timing.

[0076] For example, RCD 223 can allow MPMIC 225 to perform a calibration operation upon request from controller 215. RCD 223 can allow MPMIC 225 to perform a calibration operation when a specific control signal in the control signals received through the second connector C2 is activated.

[0077] like Figure 2 The description given indicates that the MPMIC 225 receives a reset signal RST and performs a calibration operation by comparing the memory voltage VDDQ2 with the inactive state of the reset signal RST. However, the MPMIC 225 can be modified or altered to perform the calibration operation based on the result of comparing the memory voltage VDDQ2 with any other signal that is primarily characterized by a high level, instead of the reset signal RST. For example, the MPMIC 225 can be modified or altered to perform the calibration operation by comparing the memory voltage VDDQ2 with a signal such as a storage signal (e.g., Save) or an alarm signal.

[0078] like Figure 2 The description given indicates that MPMIC 225 directly receives the reset signal RST via the fourth connector C4. However, RCD 223 can be modified or altered to output the reset signal RST received via the fourth connector C4 to MPMIC 225. Furthermore, MPMIC 225 can be modified or altered to compare the memory voltage VDDQ2 with the reset signal RST received from RCD 223.

[0079] like Figure 2 The description given is that the MPMIC 225 regulates the memory voltage VDDQ2. However, the MPMIC 225 can be configured to regulate various voltages in addition to the memory voltage VDDQ2 (such as the power supply voltage VDD, the high voltage VPP, the 1.1V output voltage VOUT_1.1V, and the 1.8V output voltage VOUT_1.8V).

[0080] References can be organized based on RDIMM. Figure 2 The semiconductor memory module 220 is described.

[0081] Figure 3 A computing system 300 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 3 The computing system 300 may include a host device 310 and a semiconductor memory module 320. The host device 310 may include a host PCB 311, a power supply 312, an SPMIC 313, a processor 314, and a device driver 317.

[0082] Processor 314 may include controller 315. Controller 315 may be connected to semiconductor memory module 320 via multiple wires 316. The configuration and operation of host device 310 can be compared with reference to... Figure 2 The host device 210 described is identical in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for the host device 210 is consistent with Figure 3 The description of the host device 310 is significantly different; otherwise, regarding... Figure 2 The configuration, operation, and characteristics described in the host device 210 can be applied without modification. Figure 3 The main unit 310.

[0083] The semiconductor memory module 320 may include a memory PCB 321, multiple memory devices 322, an RCD 323, and an MPMIC 325. The memory PCB 321 may include a first connector C1, a second connector C2, a third connector C3, and a fourth connector C4.

[0084] The configuration and operation of the semiconductor memory module 320 can be referenced. Figure 2 The semiconductor memory module 220 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for semiconductor memory module 220 is consistent with... Figure 3 The description of the semiconductor memory module 320 is significantly different, otherwise regarding Figure 2 The configuration, operation, and characteristics described for the semiconductor memory module 220 can be applied without modification. Figure 3 Semiconductor memory module 320.

[0085] and Figure 2 Compared to the semiconductor memory module 220, the semiconductor memory module 320 may further include multiple data buffers (DBs) 326. Each data buffer 326 may correspond to a memory device 322. The data buffers 326 may be inserted between the memory device 322 and the first connector C1, and may be configured to relay (or transmit) data DQ and data strobe signals DQS.

[0086] The memory PCB 321 may also include a second wire 327 connecting the RCD 323 and the data buffer 326. The RCD 323 can simultaneously send buffer commands (e.g., BCOM) to the data buffer 326 via the second wire 327 to control the data buffer 326.

[0087] For reference Figure 2 As described, the MPMIC 325 may include a register REG and a comparator CP. When the input voltage VIN is supplied, the MPMIC 325 can generate and output a default level memory voltage VDDQ2.

[0088] The MPMIC 325 can compare the memory voltage VDDQ2 with the inactive reset signal RST to detect a voltage difference. When the detected voltage difference is greater than a threshold, the MPMIC 325 can update the level information of the REG register so that the memory voltage VDDQ2 is the same as (or similar to) the voltage of the inactive reset signal RST, depending on the resolution.

[0089] For reference Figure 2As described, when the memory voltage VDDQ2 is adjusted to the level corresponding to the detected voltage difference or adjusted in a specific unit, the MPMIC 325 can update the level information of the REG register. The MPMIC 325 can update the level information of the REG register such that the memory voltage VDDQ2 is adjusted in a first unit and a second unit smaller than the first unit.

[0090] The MPMIC 325 can perform calibration operations on the memory voltage VDDQ2 at different times. The MPMIC 325 can perform calibration operations on the memory voltage VDDQ2 under the control of the RCD 323. The RCD 323 can authorize the MPMIC 325 to perform calibration operations upon request from the controller 315. The calibration operations performed by the MPMIC 325 on the memory voltage VDDQ2 can be activated and deactivated by the controller 315.

[0091] For reference Figure 2 As described, the reset signal RST can be replaced by any other signal that is primarily high. The MPMIC 325 can be modified or altered to compare the memory voltage VDDQ2 with any other signal that is primarily high.

[0092] like Figure 3 The description given is that the MPMIC 325 regulates the memory voltage VDDQ2. However, the MPMIC 325 can be configured to regulate various voltages in addition to the memory voltage VDDQ2 (such as the power supply voltage VDD, the high voltage VPP, the 1.1V output voltage VOUT_1.1V, and the 1.8V output voltage VOUT_1.8V).

[0093] References can be organized based on low-load DIMMs (LRDIMMs). Figure 3 The semiconductor memory module 320 is described.

[0094] Figure 4 A computing system 400 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 4 The computing system 400 may include a host device 410 and a semiconductor memory module 420. The host device 410 may include a host PCB 411, a power supply 412, an SPMIC 413, a processor 414, and a device driver 417.

[0095] Processor 414 may include controller 415. Controller 415 can be connected to semiconductor memory module 420 via multiple wires 416. Controller 415 can send various signals, including command CMD, address ADDR, and reset signal RST, to first connector C1 via wires 416. Controller 415 can send input voltage VIN to third connector C3 via wires 416.

[0096] The configuration and operation of the main unit 410 can be referenced. Figure 2 The host device 210 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for the host device 210 is consistent with Figure 4 The description of the host device 410 is significantly different, otherwise regarding Figure 2 The configuration, operation, and characteristics described in the host device 210 can be applied without modification. Figure 4 The main unit 410.

[0097] The semiconductor memory module 420 may include a memory PCB 421, multiple memory devices 422, and an MPMIC 425. The memory PCB 421 may include a first connector C1.

[0098] The configuration and operation of the semiconductor memory module 420 can be referenced. Figure 2 The semiconductor memory module 220 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for semiconductor memory module 220 is consistent with... Figure 4 The semiconductor memory module 420 is significantly different, otherwise regarding Figure 2 The configuration, operation, and characteristics described for the semiconductor memory module 220 can be applied without modification. Figure 4 Semiconductor memory module 420.

[0099] and Figure 2 Compared to semiconductor memory module 220, semiconductor memory module 420 does not include RCD 223, second connector C2, fourth connector C4, and first wire 224. In addition to exchanging data DQ and data strobe signal DQS with first connector C1, memory device 422 can receive various signals from first connector C1, including command CMD, address ADDR, and reset signal RST.

[0100] At least one of the wires on the memory PCB 421 that transmits the reset signal RST between the memory device 422 and the first connector C1 can be extended to the MPMIC 425. That is, the MPMIC 425 can receive the reset signal RST from at least one of the first connectors C1.

[0101] For reference Figure 2As described, the MPMIC 425 may include a register REG and a comparator CP. When the input voltage VIN is supplied, the MPMIC 425 can generate and output a default level memory voltage VDDQ2.

[0102] The MPMIC 425 can compare the memory voltage VDDQ2 with the inactive reset signal RST to detect a voltage difference. When the detected voltage difference is greater than a threshold, the MPMIC 425 can update the level information of the REG register so that the memory voltage VDDQ2 is the same as (or similar to) the voltage of the inactive reset signal RST, depending on the resolution.

[0103] For reference Figure 2 As described, the MPMIC 425 can update the level information of register REG so that the memory voltage VDDQ2 is adjusted to the level corresponding to the detected voltage difference, or adjusted in specific units. The MPMIC 425 can update the level information of register REG so that the memory voltage VDDQ2 is adjusted in a first unit and a second unit smaller than the first unit.

[0104] The MPMIC 425 can perform calibration operations on the memory voltage VDDQ2 at different times. The calibration operations performed by the MPMIC 425 on the memory voltage VDDQ2 can be activated and deactivated by the controller 415.

[0105] For reference Figure 2 As described, the reset signal RST can be replaced by any other signal that is primarily high. The MPMIC 425 can be modified or altered to compare the memory voltage VDDQ2 with any other signal that is primarily high.

[0106] like Figure 4 The description given is that the MPMIC 425 regulates the memory voltage VDDQ2. However, the MPMIC 425 can be configured to regulate various voltages in addition to the memory voltage VDDQ2 (such as the power supply voltage VDD, the high voltage VPP, the 1.1V output voltage VOUT_1.1V, and the 1.8V output voltage VOUT_1.8V).

[0107] References can be organized based on unbuffered DIMMs (UDIMMs). Figure 4 The semiconductor memory module 420 is described.

[0108] Reference Figures 2 to 4Semiconductor memory modules based on RDIMM, LRDIMM, and UDIMM are described. However, the inventive concept is not limited to RDIMM, LRDIMM, and UDIMM. The inventive concept can be applied to any other DIMM-based memory module (e.g., non-volatile DIMM (NVDIMM) and small outline DIMM (SODIMM)). Furthermore, the inventive concept can be applied to memory modules that include independent power management integrated circuits.

[0109] Figure 5 A computing system 500 according to some embodiments of the inventive concept is shown. (See also...) Figure 5 The computing system 500 may include a host device 510 and a semiconductor memory module 520. The host device 510 may include a host PCB 511, a power supply 512, an SPMIC 513, a processor 514, and a device driver 517.

[0110] Processor 514 may include controller 515. Controller 515 can be connected to semiconductor memory module 520 via multiple wires 516. Controller 515 can send data DQ and data strobe signal DQS to first connector C1 via wires 516. Controller 515 can send various signals, including command CMD and address ADDR, to second connector C2 via wires 516. Controller 515 can send input voltage VIN to third connector C3 via wires 516. Controller 515 can send reset signal RST to fourth connector C4 via wires 516.

[0111] The configuration and operation of the main unit 510 can be referenced. Figure 2 The host device 210 described is identical in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for the host device 210 is consistent with Figure 5 The description of the host device 510 is significantly different; otherwise, regarding... Figure 2 The configuration, operation, and characteristics described in the host device 210 can be applied without modification. Figure 5 The main unit 510.

[0112] The semiconductor memory module 520 may include a memory PCB 521, multiple memory devices 522, an RCD 523, and an MPMIC 525. The memory PCB 521 may include a first connector C1, a second connector C2, a third connector C3, a fourth connector C4, and a first wire 524.

[0113] The configuration and operation of the semiconductor memory module 520 can be referenced. Figure 2The semiconductor memory module 220 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for semiconductor memory module 220 is consistent with... Figure 5 The description of the semiconductor memory module 520 is significantly different, otherwise regarding Figure 2 The configuration, operation, and characteristics described for the semiconductor memory module 220 can be applied without modification. Figure 5 Semiconductor memory module 520.

[0114] For reference Figure 2 As described, the reset signal RST is shown to be transmitted to the RCD 523 via the fourth connector C4. However, the reset signal RST may be included among various signals transmitted to the RCD 523 via the second connector C2.

[0115] The RCD 523 may include a comparator CP. The MPMIC 525 may include a register REG. When the input voltage VIN is supplied, the MPMIC 525 can generate and output a default level memory voltage VDDQ2.

[0116] RCD 523 can compare the memory voltage VDDQ2 with the inactive reset signal RST to detect a voltage difference. When the detected voltage difference is greater than a threshold, RCD 523 can generate a first code CD1 to update the level information stored in register REG, and can send the first code CD1 to MPMIC 525. MPMIC 525 can update the level information in register REG based on the first code CD1 received from RCD 523.

[0117] Except for the calibration operation associated with memory voltage VDDQ2, which is controlled by RCD 523, the calibration operation performed by semiconductor memory module 520 on memory voltage VDDQ2 can be compared with a reference. Figure 2 The calibration operations described are the same.

[0118] For reference Figure 2 As described, the RCD 523 can update the level information of the REG register so that the memory voltage VDDQ2 is adjusted to the level corresponding to the detected voltage difference or adjusted in specific units. The RCD 523 can update the level information of the REG register so that the memory voltage VDDQ2 is adjusted in a first unit and a second unit smaller than the first unit.

[0119] RCD 523 can perform calibration operations on the memory voltage VDDQ2 at different times. RCD 523 can perform calibration operations upon request from controller 515. The calibration operation performed by RCD 523 on the memory voltage VDDQ2 can be activated and deactivated by controller 515. (See reference...) Figure 2 As described, any other signal that is primarily high can be used in place of the reset signal RST.

[0120] like Figure 5 The description given is that the RCD 523 regulates the memory voltage VDDQ2. However, the RCD 523 can be configured to regulate various voltages in addition to the memory voltage VDDQ2 (such as the power supply voltage VDD, the high voltage VPP, the 1.1V output voltage VOUT_1.1V, and the 1.8V output voltage VOUT_1.8V).

[0121] References can be organized based on RDIMM. Figure 5 The semiconductor memory module 520 is described. However, as referenced... Figure 3 and Figure 4 As described, the semiconductor memory module 520 can be implemented using various memory modules (such as LRDIMM and NVDIMM) that all include RCD 523.

[0122] Figure 6 A computing system 600 according to some embodiments of the inventive concept is shown. (See also...) Figure 6 The computing system 600 may include a host device 610 and a semiconductor memory module 620. The host device 610 may include a host PCB 611, a power supply 612, an SPMIC 613, a processor 614, and a device driver 617.

[0123] Processor 614 may include controller 615. Controller 615 is connected to semiconductor memory module 620 via multiple wires 616. Controller 615 transmits data DQ and data strobe signal DQS to first connector C1 via wires 616. Controller 615 transmits various signals, including command CMD, address ADDR, and reset signal RST, to second connector C2 via wires 616. Controller 615 transmits input voltage VIN to third connector C3 via wires 616. Controller 615 transmits host voltage VDDQ1 to fifth connector C5 via wires 616.

[0124] To transmit the host voltage VDDQ1, at least one of the solder balls of the processor 614 may be assigned to the output of the host voltage VDDQ1. A dedicated wire for connecting the at least one solder ball thus assigned and the fifth connector C5 may be provided on the host PCB 611 as part of the wire 616.

[0125] The configuration and operation of the main unit 610 can be referenced. Figure 2 The host device 210 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for the host device 210 is consistent with Figure 6 The description of the host device 610 is significantly different; otherwise, regarding... Figure 2 The configuration, operation, and characteristics described in the host device 210 can be applied without modification. Figure 6 The main unit 610.

[0126] The semiconductor memory module 620 may include a memory PCB 621, a memory device 622, an RCD 623, and an MPMIC 625. The memory PCB 621 may include a first connector C1, a second connector C2, a third connector C3, a fifth connector C5, and a first wire 624.

[0127] The configuration and operation of the semiconductor memory module 620 can be referenced. Figure 2 The semiconductor memory module 220 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for semiconductor memory module 220 is consistent with... Figure 6 The description of the semiconductor memory module 620 is significantly different, otherwise regarding Figure 2 The configuration, operation, and characteristics described for the semiconductor memory module 220 can be applied without modification. Figure 2 Semiconductor memory module 620.

[0128] The memory PCB 621 may also include a conductor for transmitting the host voltage VDDQ1 supplied via the fifth connector C5 to the MPMIC 625. The MPMIC 625 can compare the memory voltage VDDQ2 with the host voltage VDDQ1 instead of the reset signal RST, and can detect the voltage difference. When the detected difference is greater than a threshold, the MPMIC 625 can update the level information of the REG register so that the memory voltage VDDQ2 is the same as (or similar to) the host voltage VDDQ1, depending on the resolution.

[0129] Unlike the signals used for communication between the semiconductor memory module 620 and the host device 610, the host voltage VDDQ1 can always maintain a consistent level. Therefore, the MPMIC 625 can perform calibration operations at any time when power POR is supplied to the computing system 600.

[0130] For reference Figure 2 As described, the MPMIC 625 can update the level information of register REG so that the memory voltage VDDQ2 is adjusted to the level corresponding to the detected voltage difference, or adjusted in specific units. The MPMIC 625 can update the level information of register REG so that the memory voltage VDDQ2 is adjusted in a first unit and a second unit smaller than the first unit.

[0131] The MPMIC 625 can perform calibration operations on the memory voltage VDDQ2 at different times. The MPMIC 625 can perform calibration operations on the memory voltage VDDQ2 under the control of the RCD 623. The RCD 623 can authorize the MPMIC 625 to perform calibration operations upon request from the controller 615. The calibration operations performed by the MPMIC 625 on the memory voltage VDDQ2 can be activated and deactivated by the controller 615.

[0132] like Figure 6 The description given is that the MPMIC 625 regulates the memory voltage VDDQ2. However, the MPMIC 625 can be configured to regulate various voltages in addition to the memory voltage VDDQ2 (such as the power supply voltage VDD, the high voltage VPP, the 1.1V output voltage VOUT_1.1V, and the 1.8V output voltage VOUT_1.8V).

[0133] References can be organized based on RDIMM. Figure 6 The semiconductor memory module 620 is described. However, as referenced... Figure 3 and Figure 4 As described, the semiconductor memory module 620 can be implemented using various memory modules (such as LRDIMM, UDIMM, SODIMM and NVDIMM).

[0134] Figure 7 A computing system 700 according to some embodiments of the inventive concept is shown. (See also...) Figure 7 The computing system 700 may include a host device 710 and a semiconductor memory module 720. The host device 710 may include a host PCB 711, a power supply 712, an SPMIC 713, a processor 714, and a device driver 717.

[0135] Processor 714 may include controller 715. Controller 715 is connected to semiconductor memory module 720 via multiple wires 716. Controller 715 transmits data DQ and data strobe signal DQS to first connector C1 via wires 716. Controller 715 transmits various signals, including command CMD, address ADDR, and reset signal RST, to second connector C2 via wires 716. Controller 715 transmits input voltage VIN to third connector C3 via wires 716. Controller 715 transmits host voltage VDDQ1 to fifth connector C5 via wires 716.

[0136] The configuration and operation of the main unit 710 can be referenced. Figure 6 The host device 610 described is identical in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 6 (or indirectly refer to any other accompanying drawings) regarding Figure 6 The description given for the host device 610 is consistent with Figure 7 The description of the host device 710 is significantly different; otherwise, regarding... Figure 6 The configuration, operation, and characteristics described in the host device 610 can be applied without modification. Figure 7 The main unit 710.

[0137] The semiconductor memory module 720 may include a memory PCB 721, multiple memory devices 722, an RCD 723, and an MPMIC 725. The memory PCB 721 may include a first connector C1, a second connector C2, a third connector C3, a fifth connector C5, and a first wire 724.

[0138] Besides comparing the memory voltage VDDQ2 with the host voltage VDDQ1 instead of the reset signal RST, the configuration and operation of the computing system 700 can be compared with a reference. Figure 5 The configuration and operation of the described computing system 500 are similar. Furthermore, except that the comparator CP is located in the RCD 723, the configuration and operation of the computing system 700 are comparable to those described above. Figure 6 The configuration and operation of the described computing system 600 are similar.

[0139] Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly about) Figure 5 or Figure 6 (or indirectly refer to any other attached diagram) regarding Figure 5 The computing system 500 or Figure 6 The description given by the computing system 600 is consistent with Figure 7 The description of the computing system 700 is significantly different; otherwise, regarding... Figure 5 The computing system 500 or Figure 6The configuration, operation, and characteristics described in the computing system 600 can be applied without modification. Figure 7 The computing system 700.

[0140] Figure 8 A computing system 800 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 8 The computing system 800 may include a host device 810 and a semiconductor memory module 820. The host device 810 may include a host PCB 811, a power supply 812, an SPMIC 813, a processor 814, and a device driver 817.

[0141] Processor 814 may include controller 815. Controller 815 is connected to semiconductor memory module 820 via multiple wires 816. Controller 815 transmits data DQ and data strobe signal DQS to first connector C1 via wires 816. Controller 815 transmits various signals, including command CMD, address ADDR, and reset signal RST, to second connector C2 via wires 816. Controller 815 transmits input voltage VIN to third connector C3 via wires 816.

[0142] The configuration and operation of the main unit 810 can be referenced. Figure 2 The host device 210 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for the host device 210 is consistent with Figure 8 The description of the host device 810 is significantly different; otherwise, regarding... Figure 2 The configuration, operation, and characteristics described in the host device 210 can be applied without modification. Figure 8 The main unit 810.

[0143] The semiconductor memory module 820 may include a memory PCB 821, multiple memory devices 822, an RCD 823, and an MPMIC 825. The memory PCB 821 may include a first connector C1, a second connector C2, a third connector C3, and a first wire 824.

[0144] The configuration and operation of the semiconductor memory module 820 can be referenced. Figure 2 The semiconductor memory module 220 described is similar in configuration and operation. Therefore, additional descriptions will be omitted to avoid redundancy. Unless (directly related to) Figure 2 (or indirectly refer to any other accompanying drawings) regarding Figure 2 The description given for semiconductor memory module 220 is consistent with... Figure 8 The description of the semiconductor memory module 820 is significantly different, otherwise regarding Figure 2 The configuration, operation, and characteristics described for the semiconductor memory module 220 can be applied without modification. Figure 8 Semiconductor memory module 820.

[0145] The MPMIC 825 may include a register REG and a detector DT. When the input voltage VIN is supplied, the MPMIC 825 can generate and output a default level memory voltage VDDQ2.

[0146] The detector DT can be configured to detect the amount of current output from the MPMIC 825 during idle periods. For example, the detector DT can detect the amount of current output from the MPMIC 825 when the semiconductor memory module 820 is not communicating with the controller 815 and / or when multiple memory devices are in standby mode.

[0147] The current flowing through the semiconductor memory module 820 when it is not communicating with the controller 815 (e.g., during a no-communication cycle) can be considered as the DC current between the semiconductor memory module 820 and the controller 815 as described above. When the amount of current thus detected is greater than a threshold, the MPMIC 825 can update the level information stored in the register REG.

[0148] For example, when the memory voltage VDDQ2 is lower than the host voltage VDDQ1, DC current can flow from the controller 815 to the semiconductor memory module 820. In this case, the amount of current output from the MPMIC 825 during the absence of a communication cycle may be nonexistent or may be small.

[0149] When the memory voltage VDDQ2 is higher than the host voltage VDDQ1, DC current can flow from the semiconductor memory module 820 to the controller 815. In this case, the amount of current output from the MPMIC 825 during the absence of a communication cycle can exceed a threshold.

[0150] During calibration, the MPMIC 825 can detect changes in current while adjusting the level information in register REG. The MPMIC 825 can adjust the level information so that the memory voltage VDDQ2 gradually increases from a level information corresponding to a situation where the current may be absent or possibly small in the absence of a communication cycle.

[0151] The MPMIC 825 can detect level information corresponding to a current exceeding a threshold during a communication cycle. The MPMIC 825 can update the level information to indicate a level slightly lower than the memory voltage VDDQ2 corresponding to the detected level information.

[0152] The MPMIC 825 can update the level information of register REG so that the memory voltage VDDQ2 is adjusted in a first unit (e.g., coarse calibration), and can subsequently update the level information of register REG so that the memory voltage VDDQ2 is adjusted in a second unit smaller than the first unit (e.g., fine calibration).

[0153] The MPMIC 825 can perform calibration operations on the memory voltage VDDQ2 at different times. For example, the MPMIC 825 can perform calibration operations on the memory voltage VDDQ2 during a given time period after the reset signal RST is activated and then deactivated.

[0154] In one embodiment, RCD 823 can detect no communication cycle and allow MPMIC 825 to perform a calibration operation on memory voltage VDDQ2. RCD 823 allows MPMIC 825 to perform a calibration operation on memory voltage VDDQ2 during a given time period after the reset signal RST is activated and then deactivated.

[0155] RCD 823 can allow MPMIC 825 to perform calibration operations upon request from controller 815. For example, RCD 823 can allow MPMIC 825 to perform calibration operations on memory voltage VDDQ2 when a specific signal in the control signals received through the second connector C2 is activated.

[0156] The calibration operation can be activated or deactivated by the controller 815. When the calibration operation is activated, the MPMIC 825 can perform the calibration operation in response to an event that the conditions for performing the calibration operation are met. When the calibration operation is deactivated, the MPMIC 825 may not perform the calibration operation even if the conditions for performing the calibration operation are met. The conditions for performing the calibration operation may include the time, request, etc., as described above.

[0157] like Figure 8 The description given is that the MPMIC 825 regulates the memory voltage VDDQ2. However, the MPMIC 825 can be configured to regulate various voltages in addition to the memory voltage VDDQ2 (such as the power supply voltage VDD, the high voltage VPP, the 1.1V output voltage VOUT_1.1V, and the 1.8V output voltage VOUT_1.8V).

[0158] References can be organized based on RDIMM. Figure 8 The semiconductor memory module 820 is described. However, as referenced... Figure 3 and Figure 4 As described, the semiconductor memory module 820 can be implemented using various memory modules (e.g., LRDIMM and NVDIMM) that all include the RCD 823.

[0159] Figure 9 An example of the structure of a controller 815 and a memory device 822 capable of generating DC current is shown. In one embodiment, in Figure 9 An example of a transmit and receive block of controller 815 and a transmit and receive block of memory device 822 is shown. (See reference...) Figure 8 and Figure 9 The transmit and receive blocks of controller 815 may include a first transmitter TX1 and a first receiver RX1.

[0160] The transmit and receive blocks of memory device 822 may include a second transmitter TX2 and a second receiver RX2. The transmit and receive blocks of controller 815 and memory device 822 may be connected via a modeled transmission line TL.

[0161] The first transmitter TX1 and the first receiver RX1 of controller 815 can be stopped using the host voltage VDDQ1. The second transmitter TX2 and the second receiver RX2 of memory device 822 can be stopped using the memory voltage VDDQ2. The structure in which different devices connected via transmission line TL are stopped by a high-level voltage can be a pseudo-open-drain (POD) structure.

[0162] With the transmit and receive blocks of controller 815 and memory device 822 stopped by host voltage VDDQ1 and memory voltage VDDQ2 respectively, and controller 815 and semiconductor memory module 820 electrically connected, DC current can flow when there is a difference between host voltage VDDQ1 and memory voltage VDDQ2. Therefore, DC current can be easily detected and calibration operations can be performed.

[0163] Figure 10 A computing system 900 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 10 The computing system 900 may include a host device 910 and a semiconductor memory module 920. The host device 910 may include a host PCB 911, a power supply 912, an SPMIC 913, a processor 914, and a device driver 917.

[0164] Processor 914 may include controller 915. Controller 915 may be connected to semiconductor memory module 920 via multiple wires 916. Semiconductor memory module 920 may include memory PCB 921, multiple memory devices 922, RCD 923, and MPMIC 925. Memory PCB 921 may include a first connector C1, a second connector C2, a third connector C3, and a first wire 924.

[0165] In addition to the detector DT being set in the RCD 923, the computing system 900 and the reference Figure 8The computing system described is the same as 800. The detector DT can detect the current quantity in the absence of a communication cycle. The RCD 923 can output either the detected current quantity or a third code CD3 used to update the level information to the MPMIC 925. When the third code CD3 includes information about the current quantity, the MPMIC 925 can update the level information based on the third code CD3.

[0166] Unless (directly about) Figure 8 (or indirectly refer to any other accompanying drawings) regarding Figure 8 The description given by the computing system 800 is consistent with Figure 10 The description of the computing system 900 is significantly different; otherwise, regarding... Figure 8 The configuration, operation, and characteristics described in the computing system 800 can be applied without modification. Figure 10 The computing system 900.

[0167] Figure 11 A computing system 1000 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 11 The computing system 1000 may include a host device 1010 and a semiconductor memory module 1020. The host device 1010 may include a host PCB 1011, a power supply 1012, an SPMIC 1013, a processor 1014, and a device driver 1017.

[0168] Processor 1014 may include controller 1015. Controller 1015 may be connected to semiconductor memory module 1020 via wire 1016. Semiconductor memory module 1020 may include memory PCB 1021, multiple memory devices 1022, RCD 1023, and MPMIC 1025. Memory PCB 1021 may include a first connector C1, a second connector C2, a third connector C3, and a first wire 1024.

[0169] In addition to the detector DT being located in at least one of the multiple memory devices 1022, the computing system 1000 and the reference Figure 8 The computing system 800 described is identical. The detector DT can detect the current quantity in the absence of a communication cycle. At least one memory device 1022 can output either the detected current quantity or a fourth code CD4 for updating level information. When the fourth code CD4 includes information about the current quantity, the MPMIC 1025 can update the level information based on the fourth code CD4.

[0170] Unless (directly about) Figure 8 (or indirectly refer to any other accompanying drawings) regarding Figure 8 The description given by the computing system 800 is consistent with Figure 11 The description of the computing system 1000 is significantly different; otherwise, regarding... Figure 8The configuration, operation, and characteristics described in the computing system 800 can be applied without modification. Figure 11 The computing system 1000.

[0171] Figure 12 A computing system 1100 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 12 The computing system 1100 may include a host device 1110 and a semiconductor memory module 1120. The host device 1110 may include a host PCB 1111, a power supply 1112, an SPMIC 1113, a processor 1114, and a device driver 1117.

[0172] Processor 1114 may include controller 1115. Controller 1115 may be connected to semiconductor memory module 1120 via multiple wires 1116. Semiconductor memory module 1120 may include memory PCB 1121, multiple memory devices 1122, RCD 1123, MPMIC 1125, and multiple data buffers 1126. Memory PCB 1121 may include a first connector C1, a second connector C2, a third connector C3, multiple first wires 1124, and multiple second wires 1127.

[0173] In addition to the data buffer 1126 and the detector DT, the computing system 1100 and the reference Figure 8 The computing system 800 described is identical. The detector DT can be located in at least one of a plurality of data buffers 1126. The detector DT can detect the amount of current in the absence of a communication cycle.

[0174] At least one data buffer 1126 can output the detected current quantity or a fifth code CD5 for updating level information. When the fifth code CD5 includes information about the current quantity, the MPMIC 1125 can update the level information based on the fifth code CD5.

[0175] Data buffer 1126 can be configured to transfer data DQ and data strobe signal DQS between memory device 1122 and first connector C1. Data buffer 1126 can be controlled by buffer command BCOM transmitted from RCD 1123 via second wire 1127.

[0176] Unless (directly about) Figure 8 (or indirectly refer to any other accompanying drawings) regarding Figure 8 The description given by the computing system 800 is consistent with Figure 12 The description of the computing system 1100 is significantly different; otherwise, regarding... Figure 8 The configuration, operation, and characteristics described in the computing system 800 can be applied without modification. Figure 12 The computing system 1100.

[0177] Figure 13 A computing system 1200 according to some embodiments of the inventive concept is shown. (Refer to...) Figure 13 The computing system 1200 may include a host device 1210 and a semiconductor memory module 1220. The host device 1210 may include a host PCB 1211, a power supply 1212, an SPMIC 1213, a processor 1214, and a device driver 1217.

[0178] Processor 1214 may include controller 1215. Controller 1215 may be connected to semiconductor memory module 1220 via multiple wires 1216. Semiconductor memory module 1220 may include memory PCB 1221, multiple memory devices 1222, RCD 1223, MPMIC 1225, and multiple data buffers 1226. Memory PCB 1221 may include a first connector C1, a second connector C2, a third connector C3, multiple first wires 1224, and multiple second wires 1227.

[0179] For reference Figures 2 to 8 As described, the semiconductor memory module 1220 can perform a calibration operation on the memory voltage VDDQ2 based on a voltage difference. A comparator CP can be located in either RCD 1223 or MPMIC 1225. The memory voltage VDDQ2 can be compared with a reset signal RST received via a fourth connector C4 or a host voltage VDDQ1 received via a fifth connector C5.

[0180] For reference Figures 8 to 12 As described, the semiconductor memory module 1220 can perform a calibration operation on the memory voltage VDDQ2 based on the current quantity. The detector DT can be disposed in the MPMIC 1225, RCD 1223, at least one memory device 1222, or at least one data buffer 1226.

[0181] Unless mentioned as related to Figure 2 The computing system 200 to Figure 12 The description given by the computing system 1100 is significantly different; otherwise, regarding Figure 2 The computing system 200 to Figure 12 The configuration, operation, and characteristics described in the computing system 1100 can be applied without modification. Figure 13 The computing system 1200.

[0182] Figure 14 This is a flowchart illustrating the operation of a semiconductor memory module 1220 according to some embodiments of the inventive concept. (Refer to...) Figure 13 and Figure 14In operation S110, the semiconductor memory module 1220 can receive mode setting information from the controller 1215. The mode setting information can be used to set the mode of the calibration operation of the semiconductor memory module 1220. The mode setting information can be received at any necessary time or immediately after the initialization operation.

[0183] When the mode setting information indicates the first mode, in operation S120, the semiconductor memory module 1220 can activate the voltage-based calibration operation and deactivate the current-based calibration operation. That is, the comparator CP can be activated and the detector DT can be deactivated.

[0184] When the mode setting information indicates the second mode, in operation S130, the semiconductor memory module 1220 can activate the current-based calibration operation and deactivate the voltage-based calibration operation. That is, the comparator CP can be deactivated and the detector DT can be activated.

[0185] When the mode setting information indicates the third mode, in operation S140, the semiconductor memory module 1220 can activate both voltage-based calibration operation and current-based calibration operation. That is, both the comparator CP and the detector DT can be activated.

[0186] Furthermore, in the third mode, based on the mode setting information, the semiconductor memory module 1220 can select from voltage-based calibration operations and current-based calibration operations which will be applied first, and then select the calibration operation to be used for verification.

[0187] In addition to the first, second, and third modes, another mode (e.g., the fourth mode) can be set based on mode setting information, in which both voltage-based calibration operations and current-based calibration operations are deactivated.

[0188] According to the inventive concept, the power management integrated circuit of the semiconductor memory module can adjust the memory voltage to correspond to the host voltage. Therefore, since no DC current is generated, a semiconductor memory module with reduced power consumption and improved reliability is provided.

[0189] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the scope of the inventive concept as set forth in the appended claims.

Claims

1. A semiconductor memory module, comprising: A memory printed circuit board includes a second connector, a third connector, and a plurality of first connectors configured to connect to an external device; Multiple memory devices are mounted on a memory printed circuit board and connected to the multiple first connectors included in the memory printed circuit board; as well as A power management integrated circuit, mounted on a memory printed circuit board, is configured to: receive a first voltage via a second connector included in the memory printed circuit board, generate a second voltage from the first voltage, and supply the second voltage to the plurality of memory devices. The power management integrated circuit is also configured to adjust the second voltage based on the difference between a signal received through a third connector included in the memory printed circuit board and the second voltage.

2. The semiconductor memory module according to claim 1, wherein, The power management integrated circuit is also configured to receive the signal directly from the third connector and compare the signal with a second voltage to detect the difference.

3. The semiconductor memory module according to claim 2, wherein, The signal includes a reset signal to be supplied to the plurality of memory devices.

4. The semiconductor memory module according to claim 1, wherein, The signal includes a reset signal, and The semiconductor memory module further includes a driver, mounted on a memory printed circuit board, and configured to receive a reset signal and transmit the reset signal to the plurality of memory devices.

5. The semiconductor memory module according to claim 4, further comprising: Multiple data buffers are connected between the multiple first connectors and the multiple memory devices.

6. The semiconductor memory module according to claim 1, wherein, The signal includes the power supply voltage supplied from an external device.

7. The semiconductor memory module according to claim 1, further comprising: The driver is configured to: receive the signal from a third connector, receive a second voltage from a power management integrated circuit, compare the signal with the second voltage to detect the difference, and transmit a code indicating the difference to the power management integrated circuit.

8. The semiconductor memory module according to claim 7, wherein, The signal includes a reset signal, and The driver is also configured to transmit a reset signal to the plurality of memory devices.

9. The semiconductor memory module according to claim 7, wherein, The signal includes the power supply voltage supplied from an external device.

10. The semiconductor memory module according to claim 1, wherein, The power management integrated circuit is configured to regulate the second voltage in response to being activated and then deactivated by a reset signal.

11. A semiconductor memory module, comprising: A memory printed circuit board includes a second connector configured to connect to an external device and a plurality of first connectors; Multiple memory devices are mounted on a memory printed circuit board and connected to the multiple first connectors included in the memory printed circuit board; as well as A power management integrated circuit, mounted on a memory printed circuit board, is configured to: receive a first voltage via a second connector included in the memory printed circuit board, generate a second voltage from the first voltage, and supply the second voltage to the plurality of memory devices. The power management integrated circuit is also configured to adjust the second voltage based on the amount of current flowing through it during idle time.

12. The semiconductor memory module according to claim 11, wherein, Idle time includes the time when the plurality of memory devices are in standby mode and when the semiconductor memory module is in a state where there is no communication with external devices.

13. The semiconductor memory module according to claim 11, wherein, The power management integrated circuit is configured to detect the amount of current flowing during idle time and to adjust a second voltage when the amount of current is greater than a threshold.

14. The semiconductor memory module according to claim 11, wherein, The memory printed circuit board also includes a third connector configured to connect to an external device. The semiconductor memory module further includes a driver configured to receive addresses and commands via a third connector and transmit the addresses and commands to the plurality of memory devices. The driver is also configured to detect the current quantity and, when the current quantity is greater than a threshold, send a code requesting adjustment of a second voltage to the power management integrated circuit.

15. The semiconductor memory module according to claim 11, wherein, At least one of the plurality of memory devices is further configured to: detect the current quantity, and when the current quantity is greater than a threshold, send a code requesting adjustment of a second voltage to the power management integrated circuit.

16. The semiconductor memory module according to claim 11, further comprising: Multiple data buffers are connected between the multiple first connectors and the multiple memory devices. At least one of the plurality of data buffers is further configured to: detect the current quantity, and when the current quantity is greater than a threshold, send a code requesting adjustment of a second voltage to the power management integrated circuit.

17. The semiconductor memory module according to claim 11, wherein, The semiconductor memory module is configured to stop the plurality of first and second connectors using a second voltage based on pseudo-open-drain.

18. A semiconductor memory module, comprising: A memory printed circuit board includes a second connector, a third connector, and a plurality of first connectors configured to connect to an external device; Multiple memory devices are mounted on a memory printed circuit board and connected to the multiple first connectors included in the memory printed circuit board; as well as A power management integrated circuit, mounted on a memory printed circuit board, is configured to: receive a first voltage via a second connector included in the memory printed circuit board, generate a second voltage from the first voltage, and supply the second voltage to the plurality of memory devices. In the first mode, the power management integrated circuit is further configured to adjust the second voltage based on the difference between the level of the second voltage and a signal received through a third connector included in the memory printed circuit board. In the second mode, the power management integrated circuit is also configured to adjust the second voltage based on the amount of current flowing through the power management integrated circuit during idle time.

19. The semiconductor memory module according to claim 18, wherein, The memory printed circuit board also includes a fourth connector configured to connect to an external device, and The semiconductor memory module includes: The driver is configured to: receive addresses and commands via a fourth connector, and transmit addresses and commands to the plurality of memory devices; and Multiple data buffers are connected between the multiple memory devices and the multiple first connectors and are configured to operate under the control of a driver.

20. The semiconductor memory module according to claim 19, wherein, In the first mode, the power management integrated circuit or driver detects the difference between the level of the second voltage and the signal, and In the second mode, the power management integrated circuit, the driver, at least one of the plurality of memory devices, or at least one of the plurality of data buffers detects the current quantity.

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