Power management integrated circuit PMIC and memory module including PMIC

Abstract

A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a counting register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage and determine whether the feedback voltage is outside a threshold voltage range at each periodic interval. The counting register is configured to store a count value indicating the number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.

Description

Technical Field

[0001] Embodiments of the inventive concepts described herein relate to a power management integrated circuit (PMIC), to a memory module and a computing system including the PMIC, and to a method of operating a memory system including the PMIC. Background Art

[0002] A power management integrated circuit (PMIC) is primarily used to provide and distribute appropriate power supply voltages to various semiconductor devices included in a system. In particular, a PMIC can regulate the level of the power supply voltage and / or the amount of current to be provided to a given semiconductor device within the system. However, due to many factors including the operating environment, operating state, workload, operating frequency, etc., the power integrity (PI) of the power supply voltage provided by the PMIC may be adversely affected. Summary of the invention

[0003] According to one aspect of the inventive concept, a power management integrated circuit (PMIC) is provided, which includes a voltage regulator, a monitoring circuit and a counting register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage and determine whether the feedback voltage is outside a threshold voltage range at each periodic interval. The counting register is configured to store a count value indicating the number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.

[0004] According to another aspect of the inventive concept, a dynamic access memory (DRAM) module includes a DRAM device and a power management integrated circuit (PMIC), which is configured to provide an operating voltage to the DRAM device. The PMIC includes a voltage regulator, a monitoring circuit, a counting register, and an interface (I / F). The voltage regulator is configured to output an operating voltage to the DRAM device. The monitoring circuit is configured to receive a feedback voltage of the operating voltage and determine whether the feedback voltage is outside a threshold voltage range at each periodic interval. The counting register is configured to store a count value indicating the number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range. The I / F is configured to output monitoring data corresponding to the count value stored in the register to the outside of the DRAM module.

[0005] According to another aspect of the inventive concept, a dynamic random access memory (DRAM) module is provided, which includes a module board, a DRAM device mounted on the module board, and a power management integrated circuit (PMIC) mounted on the module board. The DRAM device includes a plurality of operating voltage terminals, and the PMIC is configured to generate a plurality of operating voltages applied to the corresponding plurality of operating voltage terminals of the DRAM, and receive a plurality of feedback voltages of the corresponding plurality of operating voltages. The PMIC includes a monitoring circuit, which is configured to determine the number of times each of the plurality of feedback voltages is outside a corresponding threshold voltage range, and store the number in a counting register.

[0006] According to another aspect of the inventive concept, a computing system is provided, which includes a host device and a plurality of memory modules. Each of the plurality of memory modules includes a memory device and a power management integrated circuit (PMIC), the PMIC includes a voltage regulator, which is configured to provide an operating voltage to the memory device, and the PMIC outputs monitoring data to the host device, the monitoring data indicating the number of voltage range violations of the operating voltage at a plurality of periodic intervals. The host device is configured to maintain the power integrity of each memory module based on the monitoring data output by the PMIC.

[0007] According to another aspect of the inventive concept, a computing system is provided, which includes a host device, a plurality of first memory modules, and a plurality of second memory modules. The host device includes a processor and first and second memory controllers operably connected to the processor. The plurality of first memory modules are operably connected to the first memory controller via a first channel, and each of the first memory modules includes a plurality of first memory devices and a first power management integrated circuit (PMIC) operably connected to the first channel and the plurality of first memory modules. The plurality of second memory modules are operably connected to the second memory controller via a second channel, and each of the second memory modules includes a plurality of second memory devices and a second PMIC operably connected to the second channel and the plurality of second memory modules. The first PMIC of each first memory module includes a first voltage regulator configured to provide a first operating voltage to the first memory device, and a first monitoring circuit configured to count the number of voltage range violations of the first operating voltage at periodic intervals, and output monitoring data indicating the number of voltage range violations to the host device via the first channel. The second PMIC of each second memory module includes a second voltage regulator configured to provide a second operating voltage to the second memory device, and a second monitoring circuit configured to count the number of voltage range violations of the second operating voltage at periodic intervals and output monitoring data indicating the number of voltage range violations to the host device through the second channel.

[0008] According to another aspect of the inventive concept, a method for operating a memory system is provided. The memory system includes a host device and a memory module, the memory module including a memory device and a power management integrated circuit (PMIC). The method includes: providing an operating voltage from the PMIC to the memory device; sending a read / write command from the host to the memory device, and processing the read / write command to output the read data from the memory device to the host, or write the data from the host to the memory device. The method also includes monitoring the feedback voltage of the operating voltage by the PMIC during the processing of the read / write command to determine whether the feedback voltage is outside the threshold voltage range at each periodic interval. The method also includes sending monitoring data representing a count value from the PMIC to the host, the count value corresponding to the number of times the feedback voltage is determined to be outside the threshold voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and 1B A block diagram of a computing system according to an embodiment of the inventive concept is shown.

[0010] Figure 2 The embodiment according to the present invention is shown Figure 1A and Figure 1B Block diagram of the PMIC.

[0011] Figure 3 The embodiment according to the present invention is shown Figure 2 The PMIC monitors the circuits and registers.

[0012] Figure 4 The embodiment according to the present invention is shown Figure 1A and Figure 1B A flow chart of the operating method of the PMIC.

[0013] Figure 5 The embodiment according to the present invention is shown Figure 1A and Figure 1B Flowchart of a PMIC monitoring feedback voltage.

[0014] Figure 6 A block diagram of a PMIC according to another embodiment of the inventive concept is shown.

[0015] Figure 7 The embodiment according to the present invention is shown Figure 6 The PMIC monitors the circuits and registers.

[0016] Figure 8 A block diagram of a PMIC according to another embodiment of the inventive concept is shown.

[0017] Fig. 9The embodiment according to the present invention is shown Figure 8 The PMIC monitors the circuits and registers.

[0018] Fig.10 A block diagram of a test system according to an embodiment of the inventive concept is shown.

[0019] Fig.11 A block diagram of a test system according to another embodiment of the inventive concept is shown.

[0020] Fig.12 The embodiment according to the present invention is shown Fig.11 A block diagram of a memory device.

[0021] Fig.13 The embodiment according to the present invention is shown Fig.12 Flowchart of a method of operation of a test system.

[0022] Fig.14 A block diagram of a computing system according to another embodiment of the inventive concept is shown.

[0023] Fig.15 A block diagram of a computing system according to another embodiment of the inventive concept is shown.

[0024] Fig.16 A flowchart illustrating an operating method of a computing system according to an embodiment of the inventive concept.

[0025] Fig.17 Another embodiment of the present invention is shown. Fig.15 A flowchart of a method of operation of a computing system.

[0026] Fig.18 A block diagram of a computing system according to another embodiment of the inventive concept is shown.

[0027] Fig.19 A block diagram of a computing system according to another embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0028] Figure 1A and Figure 1B Block diagrams of computing systems 1a and 1b according to embodiments of the inventive concept are shown respectively. Computing systems 1a and 1b may also be referred to as “electronic systems”, “memory systems”, “communication systems”, “test systems”, etc. Computing systems 1a and 1b may be implemented in electronic devices, desktop computers, laptop computers, servers, workstations, mobile devices, etc.

[0029] refer to Figure 1A and Figure 1B, the computing systems 1a and 1b may include a host 10, a power management integrated circuit (PMIC) 100, and a load device 500. Compared with the computing system 1a, the computing system 1b may further include a voltage divider 50.

[0030] The host 10 is a master device that can communicate with the PMIC 100. For example, the host 10 can drive a serial clock line SCL and a serial data line SDA between the host 10 and the PMIC 100 according to a given communication protocol such as a serial peripheral interface (SPI) protocol, an inter-integrated circuit (I2C) protocol, or an I3C protocol. The host 10 can send an SCL signal (clock signal) to the PMIC 100 through SCL, and can send an SDA signal (data signal) synchronized with the SCL signal to the PMIC 100 through SDA.

[0031] The host 10 may initiate communication by driving SCL to a first logic state (e.g., logic high) and driving SDA from the first logic state to a second logic state (e.g., logic low). The host 10 may send an SDA signal including an address bit of the PMIC 100 and an R / W bit indicating a read operation or a write operation to the PMIC 100. As will be described in more detail later, the host 10 may write setting information to the PMIC 100 and may read count information from the PMIC 100. The host 10 may receive an SDA signal including an acknowledgement (ACK) bit from the PMIC 100. The host 10 may check (or determine) whether the address bit and the R / W bit are successfully sent to the PMIC 100 by using the ACK bit.

[0032] When the R / W bit indicates a write operation, the host 10 may send an SDA signal including a write data bit to the PMIC 100. The host 10 may receive an SDA signal including an ACK bit from the PMIC 100, the ACK bit indicating whether the write data was successfully sent. When the R / W bit indicates a read operation, the host 10 may receive an SDA signal including a read data bit from the PMIC 100. The host 10 may send an SDA signal including an ACK bit to the PMIC 100, the ACK bit indicating successful reception of the read data. The host 10 may initiate the end of the communication by driving SCL to a first logic state and driving SDA from a second logic state to a first logic state. However, the communication protocol between the host 10 and the PMIC 100 is not limited to the above description or example.

[0033] The PMIC 100 is a slave device that can communicate with the host 10. The PMIC 100 may include an SCL pin terminal connected to SCL and receiving an SCL signal and an SDA pin terminal connected to SDA and receiving an SDA signal or outputting an SDA signal. The PMIC 100 may also include: a VIN pin terminal that receives an input voltage VIN, a GND pin terminal that receives a ground voltage GND, a VOUT pin terminal that outputs an output voltage VOUT, and a VFB pin terminal that receives a feedback voltage VFB. The PMIC 100 may generate an output voltage VOUT based on the input voltage VIN, and may provide the output voltage VOUT to the load device 500. The input voltage VIN may be a power supply voltage of the PMIC 100. The PMIC 100 may receive a feedback voltage VFB based on the output voltage VOUT. Figure 1A and Figure 1B Unlike the illustrated example, the host 10 may be the load device 500. In this case, the PMIC 100 may provide the output voltage VOUT to the host 10.

[0034] The feedback voltage VFB is a feedback voltage of the output voltage VOUT. That is, the feedback voltage VFB may be a voltage corresponding to the output voltage fed back to the PMIC 100 after the output voltage VOUT is provided to the load device 500. Figure 1A , the output voltage VOUT can be directly provided to the PMIC 100, and the level of the feedback voltage VFB can be the same as the level of the output voltage VOUT. Figure 1B , the output voltage VOUT may be indirectly provided to the PMIC 100. For example, the output voltage VOUT may be provided to the PMIC 100 through a voltage divider 50 or a filter circuit including passive elements (e.g., resistors, capacitors, inductors, etc.). In this case, the voltage divider 50 or the filter circuit may be placed on a substrate on which the PMIC 100 and the load device 500 are mounted. In this case, the level of the feedback voltage VFB may be different from the level of the output voltage VOUT. In any case, based on the feedback voltage VFB, the PMIC 100 may monitor the output voltage VOUT, may adjust the level of the output voltage VOUT, or may determine whether to continue to provide the output voltage VOUT.

[0035] The load device 500 may operate based on the output voltage VOUT provided from the PMIC 100. The output voltage VOUT may be a power supply voltage of the load device 500. The load device 500 may be any electronic device provided with a power supply voltage. For example, the load device 500 may be a semiconductor device or an electronic device such as a host 10, a processor, a memory controller, a memory module, a memory device, a storage device, etc.

[0036] When the load device 500 performs operations accompanied by various workloads, the PMIC 100 can provide a numerical basis for checking or evaluating the power integrity (PI) of the output voltage VOUT and managing and improving the PI. In addition, the user can directly set a reference for monitoring the output voltage VOUT in the PMIC 100 through the host 10. That is, the PMIC 100 can monitor the output voltage VOUT according to the setting information set according to the user's request.

[0037] Figure 2 The embodiment according to the present invention is shown Figure 1A and Figure 1B The PMIC 100 may include a regulator 110, an interface circuit 120, a monitoring circuit 130, and a counter register 141. The PMIC 100 and the components 110, 120, 130, and 141 may all be implemented in hardware.

[0038] The regulator 110 may generate an output voltage VOUT based on an input voltage VIN, and may adjust the level of the output voltage VOUT to a target level. The target level may be determined as specified by a load device 500, which is provided with an output voltage VOUT from the PMIC 100. As an example, the regulator 110 may be a low-dropout (LDO) regulator, a buck regulator, a boost regulator, etc. The regulator 110 may include a voltage generator 111, a comparator 112, and a driver 113.

[0039] The voltage generator 111 may generate a reference voltage VREF having a reference level corresponding to a target level of the output voltage VOUT. When the output voltage VOUT is directly provided to the PMIC 100, the level of the feedback voltage VFB may be the same as the level of the output voltage VOUT, and the level of the reference voltage VREF may be the same as the target level. As described above, when the output voltage VOUT is not directly provided to the PMIC 100 but is provided to the PMIC 100 through a voltage divider or a filter circuit, the level of the feedback voltage VFB may be different from the level of the output voltage VOUT, and the level of the reference voltage VREF may be different from the target level. Separately, as an example, the voltage generator 111 may include a bandgap reference (BGR) circuit.

[0040] The comparator 112 may compare the feedback voltage VFB with the reference voltage VREF. The comparator 112 may determine whether the level of the feedback voltage VFB is higher (larger) or lower (smaller) than the level of the reference voltage VREF. For example, the comparator 112 may include an operational amplifier that amplifies the voltage level difference between the feedback voltage VFB and the reference voltage VREF.

[0041] The driver 113 may drive the output voltage VOUT based on the comparison result between the comparator 112 and the input voltage VIN. When the level of the feedback voltage VFB is lower than the reference level, the driver 113 may increase (raise) the level of the output voltage VOUT; when the level of the feedback voltage VFB is higher than the reference level, the driver 113 may decrease (lower) the level of the output voltage VOUT. The driver 113 may include a switching element (e.g., a power transistor) and a passive element.

[0042] The interface circuit 120 may receive an SCL signal and an SDA signal through an SCL pin terminal and an SDA pin terminal, respectively. The interface circuit 120 may receive an address, write data, a command, an ACK bit, etc. from the host 10 based on the SCL signal and the SDA signal. The interface circuit 120 may send read data, an ACK bit, etc. to the host 10 based on the SCL signal and the SDA signal. The interface circuit 120 may include a command decoder that decodes a command of the host 10. The command decoder may control any other component of the PMIC 100 based on a command of the host 10.

[0043] The monitoring circuit 130 may monitor the feedback voltage VFB corresponding to the output voltage VOUT which is fed back to the PMIC 100 again after the output voltage VOUT is output from the PMIC 100. The monitoring circuit 130 may monitor whether the feedback voltage VFB based on the output voltage VOUT exceeds the reference voltage range at the monitoring interval during the monitoring time. The monitoring circuit 130 may store the number of times the feedback voltage VFB exceeds the reference voltage range (hereinafter referred to as a “violation count”) CNT V The reference voltage range may be determined according to the tolerance of the output voltage VOUT required by the user. The reference voltage range may be narrower than the protection range of the output voltage VOUT of the PMIC 100 to protect the load device 500. The counter register 141 may store the monitoring result (e.g., the violation count CNT V ). The counting register 141 can be implemented by using a static random access memory (SRAM), a flip-flop, a latch, etc. Violation count CNT VThe interface circuit 120 may be a quantified indicator of the level of the PI of the output voltage VOUT to be managed. V Sent to the host 10 or external device.

[0044] Figure 3 Shown in detail Figure 2 The monitoring circuit and register of the PMIC of the present invention. Except for the monitoring circuit 130 and the counting register 141, the remaining components of the PMIC 100 are not shown. The PMIC 100 may also include a setting register 142. The monitoring circuit 130 may include a controller 131, a voltage generator 132, a comparator 133, a counter 134, a comparator 135, and a counter 136.

[0045] The controller 131 may read the setting information stored in the setting register 142. The setting information may include operating parameters for controlling the operation of monitoring the output voltage VOUT. The operating parameters may include a threshold voltage range, a duration of each periodic interval, a monitoring time for the monitoring circuit to operate, a deviation from a target feedback voltage defining the threshold voltage range, a monitoring start trigger for starting monitoring of the monitoring circuit, and at least one of a monitoring stop trigger for stopping monitoring of the monitoring circuit. The host 10 may send the setting information to the PMIC 100. The setting register 142 may store the setting information sent from the host 10.

[0046] For example, refer to Figure 3 In the specific example shown in the setting register, the controller 131 can be based on the reference voltage range V RANGE The value and resolution V RANGE_STEP The voltage generator 132 can generate reference voltages VH and VL under the control of the controller 131. One voltage generator 132 can generate all reference voltages VH and VL, such as Figure 3 As shown, the two voltage generators 132 may generate reference voltages VH and VL, respectively. For example, the voltage generator 132 may include a digital to analog converter (DAC). The voltage difference between the reference voltages VH and VL may correspond to the reference voltage range V RANGE . Reference voltage range V RANGE It can be a percentage of the level of the feedback voltage VFB corresponding to the target level of the output voltage VOUT. Resolution V RANGE_STEP The value can be adjusted (adjusted) to the reference voltage range V RANGE The reference voltage range is V RANGE The unit and resolution of the value V RANGE_STEPEach of the units of the value of may be a percentage of the level of the feedback voltage VFB corresponding to the target level of the output voltage VOUT. The host 10 may be configured to generate a feedback voltage VFB according to the resolution V RANGE_STEP The value of V RANGE value to change the reference voltage range V RANGE .

[0047] The controller 131 may monitor the time T MONITORING The value of the monitoring interval T SENSE The value of the trigger bit T TRIGGER To control comparators 133 and 135. Controller 131 can refer to trigger bit T TRIGGER Start, initiate or trigger a monitoring operation. For example, when the host 10 triggers bit T TRIGGER When the host 10 sets the trigger bit T TRIGGER When set to the second logic value, the controller 131 may terminate the monitoring operation.

[0048] The controller 131 may monitor the time T MONITORING During each monitoring interval T SENSE The comparators 133 and 135 are activated (or enabled), and then the activated (or enabled) comparators 133 and 135 can be deactivated (or disabled). SENSE When the corresponding time has passed, the controller 131 may activate the comparators 133 and 135, and then may deactivate the activated comparators 133 and 135. The comparator 133 may monitor the time T MONITORING During the monitoring interval T SENSE The feedback voltage VFB is compared with the reference voltage VH. The comparator 135 can monitor the time T MONITORING During the monitoring interval T SENSE The feedback voltage VFB is compared with the reference voltage VL. The operation of the comparators 133 and 135 may be similar to the operation of the comparator 112, except that the reference voltages VH and VL are received instead of the reference voltage VREF. TRIGGER is set to the first logic value and monitors the time T MONITORING When the time has passed, the controller 131 may no longer activate the comparators 133 and 135 .

[0049] The counter 134 may count the number of times CNT that the feedback voltage VFB exceeds the reference voltage VH (or is equal to or greater than the reference voltage VH) based on the comparison result of the comparator 133. HThe counter 136 can count the number of times (hereinafter referred to as “ripple count”) that the feedback voltage VFB is less than the reference voltage VL (or equal to or less than the reference voltage VL) based on the comparison result of the comparator 135 (hereinafter referred to as “ripple count”) CNT L For example, the counters 134 and 136 may be implemented by using flip-flops.

[0050] The counting register 141 can store the ripple count CNT H . Ripple count CNT H The increase means that the event that the level of the feedback voltage VFB is higher than the level of the reference voltage VH during the monitoring time occurs relatively frequently. The counting register 141 can store the ripple count CNT L . Ripple count CNT L The increase means that the event that the level of the feedback voltage VFB is lower than the level of the reference voltage VL during the monitoring time occurs relatively frequently. The counting register 141 may store the ripple count CNT H and ripple count CNT L The sum of the violation counts CNT V The controller 131 may calculate the violation count CNT V . Violation Count CNT V Becoming larger means that the ripple of the output voltage VOUT is relatively large and the PI of the output voltage VOUT becomes relatively worse.

[0051] The count register 141 and the setting register 142 may constitute a register group. The PMIC 100 may include a register group. The register group may further include an address register that stores an address of the PMIC 100 as a slave device.

[0052] Figure 4 Show Figure 1A and Figure 1B Flowchart of an operation method of a PMIC of the present invention. In operation S110, the interface circuit 120 may receive setting information from the host 10. The setting register 142 may store the setting information. For example, the host 10 may change the monitoring condition of the output voltage VOUT by updating the setting information stored in the setting register 142 according to a user's request. The host 10 may RANGE_STEP The value of the reference voltage range V RANGE The value of V is used to adjust the reference voltage range RANGE The host 10 can adjust the monitoring time T MONITORING The value of the monitoring time T MONITORING The host 10 can adjust the monitoring interval T SENSE The value of T is used to adjust the monitoring interval SENSE .

[0053] In operation S120, the interface circuit 120 may receive a monitoring start command from the host 10. The monitoring circuit 130 may start a monitoring operation in response to the monitoring start command. For example, the host 10 may send a monitoring start command to the PMIC 100 to set the trigger bit T of the register 142. TRIGGER The monitoring circuit 130 can read the trigger bit T TRIGGER And the monitoring operation of the output voltage VOUT can be started.

[0054] In operation S130, the comparators 133 and 135 of the monitoring circuit 130 may monitor whether the feedback voltage VFB exceeds the reference voltage range V RANGE When the feedback voltage VFB exceeds the reference voltage range V RANGE When the counter 134 is in operation S140, the ripple count CNT H Increment by as much as "1", or counter 136 can count the ripple CNT H Increases by as much as "1". When the feedback voltage VFB is within the reference voltage range V RANGE When the ripple count CNT is less than 0, the process proceeds to operation S150 without increasing the ripple count CNT H and CNT L .

[0055] In operation S150, the controller 131 may determine a monitoring time T from a time point when the monitoring start command is received. MONITORING Whether it has passed. When the monitoring time T MONITORING When the monitoring interval T is not reached, in operation S160, the controller 131 of the monitoring circuit 130 may SENSE The determined sensing time point activates the comparators 133 and 135 again, and the process proceeds to operation S130. Operations S130 to S160 may be repeated until the monitoring time T elapses. MONITORING The monitoring circuit 130 can monitor the time T based on the setting information. MONITORING During the monitoring interval T SENSE Monitors whether the feedback voltage VFB based on the output voltage VOUT exceeds the reference voltage range V RANGE .

[0056] When the monitoring time T MONITORING In the past, in operation S170, the counters 134 and 136 may count the ripples CNT H and CNT L Stored in the counting register 141. The controller 131 can be used as a ripple counter CNT H and ripple count CNT L The sum of the violation counts CNTV The interface circuit 120 may receive a monitoring end command from the host 10 in operation S180. For example, the host 10 may send a monitoring end command to the PMIC 100 to set the trigger bit T of the register 142. TRIGGER The interface circuit 120 may respond to the monitoring end command by setting the ripple count CNT L , Ripple count CNT H and violation count CNT V At least one of them is sent to the host 10.

[0057] Figure 5 Show Figure 1A and Figure 1B Flowchart of the PMIC monitoring feedback voltage. Figure 5 In FIG. 1 , the horizontal axis represents time and the vertical axis represents voltage level. The interval between the sensing time points indicated by the arrows may be the monitoring interval T. SENSE At each sensing time point, the comparator 133 may compare the feedback voltage VFB with the reference voltage VH, and the comparator 135 may compare the feedback voltage VFB with the reference voltage VL. For example, at the sensing time point indicated by the dotted arrow, the feedback voltage VFB may be within the reference voltage range V RANGE and at the sensing time point indicated by the solid arrow, the feedback voltage VFB may be outside the reference voltage range V RANGE The gray area. RANGE Defined by an upper threshold voltage VH and a lower threshold voltage VL, which deviate from the target voltage by a given percentage. VH and VL may be between plus or minus 2% and plus or minus 6% of the target voltage (see Table 1 below). Figure 5 An example is shown in FIG. MONITORING During monitoring interval T SENSE is constant (ie, has the same duration), but the inventive concept is not limited thereto. For example, at the monitoring time T MONITORING During monitoring interval T SENSE The following Table 1 shows an example of monitoring conditions of the feedback voltage VFB according to the setting information stored in the setting register 142. The values ​​in Table 1 are exemplary, and the inventive concept is not limited to the values ​​in Table 1.

[0058] Table 1

[0059]

[0060]

[0061] Figure 6A block diagram of a PMIC according to another embodiment of the inventive concept is shown. PMIC 200 may include regulators 211 to 214, an input driver 215, an interface circuit 220, a monitoring circuit 230, a register group 240, and a multiplexer 250. The differences between PMIC 200 and PMIC 100 will be described in detail. Regulators 211 to 214 may generate output voltages VOUT1 to VOUT4, respectively, and may adjust the output voltages VOUT1 to VOUT4 to target levels, respectively. The operation of each of regulators 211 to 214 may be similar to the operation of regulator 110. An input voltage VIN1 may be provided to regulators 211 to 213, and output voltages VOUT1 to VOUT3 may be generated, respectively, by using the input voltage VIN1. Regulator 214 may be provided with an input voltage VIN2 having a level lower than that of input voltage VIN1, and may generate output voltage VOUT4 by using the input voltage VIN2. For example, each of the regulators 211 to 213 may be a buck regulator, and the regulator 214 may be an LDO regulator. The output voltages VOUT1 to VOUT3 may be provided to a load device that consumes relatively large power. The output voltage VOUT4 may be provided to a load device that consumes relatively small power. The input driver 215 may provide the input voltage VIN1 to the regulators 211 to 213. Figure 6 In the example shown, the input voltage V IN1 may be provided directly to the regulators 211 to 213 instead of the input driver 215 .

[0062] The configuration and operation of the interface circuit 220 may be substantially the same as the configuration and operation of the interface circuit 120. The register group 240 may include a count register 241 corresponding to the count register 141 and a setting register 242 corresponding to the setting register 142. Unlike the monitoring circuit 130, the monitoring circuit 230 may receive a feedback voltage S_VFB selected from the feedback voltages VFB1 to VFB3. The monitoring circuit 230 may monitor the selected feedback voltage S_VFB ( Figure 4 The configuration and operation of the monitoring circuit 230 may be substantially the same as those of the monitoring circuit 130.

[0063] The multiplexer 250 may select one of the feedback voltages VFB1 to VFB3, and may provide the selected feedback voltage S_VFB to the monitoring circuit 230. For example, the multiplexer 250 may select a feedback voltage corresponding to a target output voltage of a request monitoring operation according to the host 10 from among the feedback voltages VFB1 to VFB3. The monitoring start command transmitted from the host 10 may request a monitoring operation on one of the output voltages VOUT1 to VOUT3.

[0064] Figure 7 Shown in detail Figure 6 The monitoring circuit 230 may include a controller 231 , a voltage generator 232 , a comparator 233 , a counter 234 , a comparator 235 , and a counter 236 .

[0065] The setting register 242 may store setting information including monitoring conditions of the output voltage VOUT1, setting information including monitoring conditions of the output voltage VOUT2, and setting information including monitoring conditions of the output voltage VOUT3. As in the setting information stored in the setting register 142, each of the setting information of the output voltage VOUT1, the setting information of the output voltage VOUT2, and the setting information of the output voltage VOUT3 may include a reference voltage range VOUT1, VOUT2, VOUT3, VOUT2, VOUT3, VOUT3, VOUT1 ... RANGE Value, reference voltage range V RANGE Resolution V RANGE_STEP The value of the monitoring time T MONITORING The value of the monitoring interval T SENSE and the trigger bit T of each of the feedback voltages VFB1 to VFB3 TRIGGER The host 10 may transmit setting information of the output voltage VOUT1 , setting information of the output voltage VOUT2 , and setting information of the output voltage VOUT3 to the PMIC 200 .

[0066] The controller 231 may read the setting information corresponding to the target output voltage for monitoring operation according to the request of the host 10, and may control the voltage generator 232, the comparators 233 and 235, and the counters 234 and 236 as in the controller 131. For example, the host 10 may send a monitoring start command for requesting monitoring of the output voltage VOUT1 among the output voltages VOUT1 to VOUT3 to the PMIC 200 (refer to operation S120). The host 10 may set the toggle bit T of the setting information of the output voltage VOUT1 to the toggle bit T of the output voltage VOUT2. TRIGGER The multiplexer 250 may select the feedback voltage VFB1 and may provide the feedback voltage VFB1 as the selected feedback voltage S_VFB to the monitoring circuit 230 .

[0067] The controller 231 may read setting information of the output voltage VOUT1 and may control the voltage generator 232, the comparators 233 and 235, and the counters 234 and 236. The voltage generator 232 may generate a reference voltage range VOUT1 indicating a voltage VOUT2 associated with the feedback voltage VFB1. RANGEThe comparator 233 may compare the feedback voltage VFB1 with the reference voltage VH. The comparator 235 may compare the feedback voltage VFB1 with the reference voltage VL. The counter 234 may count the number of ripples CNT indicating the number of times the feedback voltage VFB1 exceeds the reference voltage VH (or is equal to or greater than the reference voltage VH) based on the comparison result of the comparator 233. H Counting can be performed, and the ripple count CNT H The counter 236 can count the number of ripples CNT indicating the number of times the feedback voltage VFB1 is less than the reference voltage VL (or equal to or less than the reference voltage VL) based on the comparison result of the comparator 235. L Counting can be performed, and the ripple count CNT L The controller 231 may store the violation count CNT of the feedback voltage VFB in the counting register 241. V , which corresponds to the ripple count CNT H and ripple count CNT L The sum.

[0068] When the host 10 requests a monitoring operation on the output voltage VOUT2 or VOUT3, the monitoring circuit 230 may monitor the output voltage VOUT2 or VOUT3 in a manner similar to the monitoring of the output voltage VOUT1. The operation of the components 231 to 236 of the monitoring circuit 230 may be similar to the operation of the components 131 to 136 of the monitoring circuit 130.

[0069] Figure 8 1 is a block diagram of a PMIC according to another embodiment of the inventive concept. The PMIC 300 may include regulators 311 to 314, an input driver 315, an interface circuit 320, a monitoring circuit 330, and a register group 340. The components 311 to 314, 315, 320, and 340 of the PMIC 300 may be substantially the same as the components 211 to 214, 215, 220, and 240 of the PMIC 200. The PMIC 300 may not include the multiplexer 250 of the PMIC 200. The monitoring circuit 230 may perform a monitoring operation on a feedback voltage S_VFB selected from the feedback voltages VFB1 to VFB3, however, the monitoring circuit 330 may perform a monitoring operation on the feedback voltages VFB1 to VFB3 in parallel or simultaneously.

[0070] Fig. 9 Shown in detail Figure 8The monitoring circuit 330 may include a controller 331. As in the controller 231, the controller 331 may read the setting information of the output voltage VOUT1, the setting information of the output voltage VOUT2, and the setting information of the output voltage VOUT3 stored in the setting register 342, and may control the components 332, 333_1 to 333_3, 334_1 to 334_3, 335_1 to 335_3, and 336_1 to 336_3 of the monitoring circuit 330.

[0071] The monitoring circuit 330 may further include a voltage generator 332. Under the control of the controller 331, the voltage generator 332 may generate a reference voltage range V indicating the feedback voltage VFB1. RANGE The reference voltage VH1 and VL1 of the feedback voltage VFB2 are indicated by the reference voltage range V RANGE The reference voltages VH2 and VL2 and the reference voltage range V indicating the feedback voltage VFB3 RANGE The monitoring circuit 330 may further include a comparator 333_1, a counter 334_1, a comparator 335_1, and a counter 336_1 for monitoring the feedback voltage VFB1. The operation of the above components 333_1 to 336_1 may be substantially the same as the operation of the components 133 to 136 of the monitoring circuit 130. The monitoring circuit 330 may further include a comparator 333_2, a counter 334_2, a comparator 335_2, and a counter 336_2 for monitoring the feedback voltage VFB2. The operation of the above components 333_2 to 336_2 may be substantially the same as the operation of the components 133 to 136 of the monitoring circuit 130. The monitoring circuit 330 may further include a comparator 333_3, a counter 334_3, a comparator 335_3, and a counter 336_3 for monitoring the feedback voltage VFB3. The operations of the above-described components 333_3 to 336_3 may be substantially the same as the operations of the components 133 to 136 of the monitoring circuit 130 .

[0072] As in the setting register 242, the setting register 342 may store setting information including monitoring conditions of the output voltage VOUT1, setting information including monitoring conditions of the output voltage VOUT2, and setting information including monitoring conditions of the output voltage VOUT3. As in the counting register 241, the counting register 341 may store a count CNT indicating that the feedback voltage VFB1 exceeds the reference voltage range. H 、CNT L and CNT V , indicating that the voltage VFB2 exceeds the reference voltage range of CNT H 、CNT L and CNT V, and a count CNT indicating that the feedback voltage VFB3 exceeds the reference voltage range H 、CNT L and CNT V .

[0073] Fig.10 A block diagram of a test system according to an embodiment of the inventive concept is shown. The test system 1000 may include a memory module 1100 and a test device 1200. The memory module 1100 may be a dual in-line memory module (DIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM), or any other memory module (e.g., a single in-line memory module (SIMM)) that complies with the Joint Electronic Device Engineering Council (JEDEC) standard.

[0074] The memory module 1100 may include a VIN1 pin terminal receiving an input voltage VIN1, a VIN2 pin terminal receiving an input voltage VIN2, and a GND pin terminal receiving a ground voltage GND. The input voltages VIN1 and VIN2 and the ground voltage GND may be power supply voltages provided to the memory module 1100. The memory module 1100 may also include an SCL pin terminal connected to SCL and receiving an SCL signal, and an SDA pin terminal connected to SDA and receiving an SDA signal or outputting an SDA signal.

[0075] The memory module 1100 may also include: a CK pin terminal for receiving a clock signal CK, a CA pin terminal for receiving a command and address signal CA, a DQ pin terminal for receiving or transmitting a data input / output signal DQ, and a DQS pin terminal for receiving or transmitting a data strobe signal DQS. The clock signal CK, the command and address CA, the data input / output signal DQ, and the data strobe signal DQS may be signals associated with the memory device 1120. The command and address signal CA may include one or more signals and may be used to provide a command or address of the memory device 1120. The data input / output signal DQ may include one or more signals and may be used to provide write data or read data. For ease of explanation, one CK pin terminal, one CA pin terminal, one DQ pin terminal, and one DQS pin terminal are shown, but the number of pin terminals for each signal may be one or more.

[0076] The memory module 1100 may include a PMIC 1110. The PMIC 1110 may be a reference Figures 1A to 9 One of the PMICs 100, 200, and 300 described. The output voltages output from the VOUT1, VOUT2, and VOUT3 pin terminals of the PMIC 1110 may be power supply voltages VDD (first power supply voltage), VDDQ (second power supply voltage), and VPP (boosted power supply voltage) of the memory device 1120, and may be provided to the memory device 1120. For example, an input voltage VIN1 of 12V and an input voltage VIN2 of 3.3V may be provided to the PMIC 1110, and a power supply voltage VDD of 1.1V, a power supply voltage VDDQ of 1.1V, and a power supply voltage VPP of 1.8V may be provided to the memory device 1120. However, the inventive concept is not limited to the above values.

[0077] The memory module 1100 may include a memory device 1120. The memory device 1120 may be referred to as a "memory chip" and may include one or more memory devices. The power supply voltage GND may be provided to the memory device 1120 through the GND pin terminal of the memory module 1100. The power supply voltages VDD, VDDQ, and VPP are not provided to the memory device 1120 directly through any pin terminal of the memory module 1100. Instead, the power supply voltages VDD, VDDQ, and VPP are provided to the memory device 1120 from the PMIC 1110 mounted on the memory module 1100. The memory device 1120 may include a VDD pin terminal, a VDDQ pin terminal, a VPP pin terminal, and a GND pin terminal that receive the power supply voltages VDD, VDDQ, VPP, and GND, respectively. The memory device 1120 may also include: a CK pin terminal that receives a clock signal CK, a CA pin terminal that receives a command and address signal CA, a DQ pin that receives or sends a data input / output signal DQ, and a DQS pin terminal that receives or sends a data strobe signal DQS. For convenience of explanation, one CK pin terminal, one CMD pin terminal, one ADD pin terminal, one DQ pin terminal, and one DQS pin terminal are shown, but the number of pin terminals for each signal may be one or more.

[0078] The memory device 1120 may be various DRAM devices, such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, LPDDR6 SDRAM, graphics double data rate synchronous graphics random access memory (GDDRSGRAM), GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, and GDDR7 SGRAM. The memory device 1120 may be a memory device having stacked semiconductor dies, such as high bandwidth memory (HBM), HBM2, or HBM3. The memory device 1120 may include a static random access memory (SRAM) device, a thyristor RAM (TRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive RAM (RRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), etc. The types of the memory device 1120 are not limited to the above types, and the memory device 1120 may include any device capable of storing data.

[0079] The test device 1200 may test the memory module 1100. The test device 1200 may include a processor 1210 and a memory 1220. For example, the test device 1200 may be an automatic test equipment (ATE). The processor 1210 may generate a test pattern and may store the test pattern in the memory 1220. The test pattern may include a memory command for the memory device 1120. For example, the memory command may include an activation command, a write command, a read command, a precharge command, a refresh command, etc. The processor 1210 may execute the test pattern for testing the memory module 1100. The memory 1220 may store the test pattern, the write data to be stored in the memory module 1100 generated when executing the test pattern, and the read data read from the memory module 1100. The test device 1200 may provide the power supply voltages VIN1, VIN2, and GND to the memory module 1100. The test device 1200 may send an SCL signal, an SDA signal, a clock signal CK, and a command and address signal CA to the memory module 1100. The test device 1200 may exchange a data input / output signal DQ and a data strobe signal DQS with the memory module 1100 .

[0080] Fig.11 A block diagram of a test system according to another embodiment of the inventive concept is shown. The test system 2000 may include a memory module 2100 and a test device 2200. The test system 2000 may be substantially the same as the test system 1000. The test device 2200 may be substantially the same as the test device 1200. The difference between the memory module 2100 and the memory module 1100 will be described in detail.

[0081] The memory module 2100 may include a PMIC 2110, a memory device 2120, a serial presence detect (SPD) module 2130, a register clock driver (RCD) 2140, and a data buffer (DB) 2150. The PMIC 2110 may be substantially the same as the PMIC 1110. The memory device 2120 may be substantially the same as the memory device 1120.

[0082] The SPD module 2130 may include an electrically erasable and programmable read only memory (EEPROM) storing information of the memory module 2100. The SPD module 2130 may receive an SCL signal and an SDA signal, and may transmit the SCL signal and the SDA signal to the PMIC 2110. The power supply voltage VOUT4 may be provided from the PMIC 2110 to the SPD module 2130. The RCD 2140 may receive a clock signal CK and a command and address signal CA, and may transmit the clock signal CK and the command and address signal CA to the memory device 2120. The RCD 2140 may buffer the clock signal CK and the command and address signal CA. The RCD 2140 may transmit a command and an address associated with the memory device 2120 to the memory device 2120. The power supply voltages VDDQ and VOUT4 may be provided from the PMIC 2110 to the RCD 2140.

[0083] The DB 2150 may receive a data input / output signal DQ and a data strobe signal DQS including write data from the test device 2200, and may transmit the data input / output signal DQ and the data strobe signal DQS including write data to the memory device 2120. The DB 2150 may receive a data input / output signal DQ and a data strobe signal DQS including read data from the memory device 2120, and may transmit the data input / output signal DQ and the data strobe signal DQS including read data to the test device 2200. The DB 2150 may buffer the data input / output signal DQ and the data strobe signal DQS. The power supply voltage VDDQ may be provided to the DB 2150 from the PMIC 2110.

[0084] Fig.12 Show Fig.112120 is a block diagram of a memory device. The memory device 2120 may include a CK buffer 2121_1, a CA buffer 2121_2, a DQ buffer 2121_3, a DQS buffer 2121_4, a command decoder 2122, a row decoder 2123, a column decoder 2124, a memory cell array 2125, an input / output circuit 2126, a data circuit 2127, and a voltage generator 2128. The CK buffer 2121_1 may receive a clock signal CK through a CK pin terminal. The CA buffer 2121_2 may receive a command and address signal CA through a CA pin terminal based on the clock signal CK. The DQ buffer 2121_3 may receive a data input / output signal DQ including write data through a DQ pin terminal, or may send a data input / output signal DQ including read data to the outside through a DQ pin terminal. The DQS buffer 2121_4 may receive a data strobe signal DQS through a DQS pin terminal, or may send a data strobe signal DQS to the outside through a DQS pin terminal. The buffers 2121_1 to 2121_4 may operate based on the power supply voltage VDDQ or the power supply voltage VDD.

[0085] The command decoder 2122 may decode a command input to the memory device 2120 based on the command and address signal CA. The command decoder 2122 may control the components 2121_1 to 2121_4 and 2123 to 2128 of the memory device 2120 based on the decoding result. The row decoder 2123 may select a word line of the memory cell array 2125 under the control of the command decoder 2122. The column decoder 2124 may select a column selection line and a bit line of the memory cell array 2125 under the control of the command decoder 2122, and the bit line may be connected to the column selection line. The memory cell array 2125 may include memory cells connected to the word line and the bit line. The input / output circuit 2126 may include a write driver WDRV and an input / output sense amplifier IOSA. The write driver WDRV may write write data into the memory cell selected by the row decoder 2123 and the column decoder 2124. The input / output sense amplifier IOSA may sense and read read data from the memory cell selected by the row decoder 2123 and the column decoder 2124.

[0086] The data circuit 2127 may receive the data input / output signal DQ and the data strobe signal DQS from the DQ buffer 2121_3 and the DQS buffer 2121_4, and may provide write data to the input / output circuit 2126. The data circuit 2127 may receive read data from the input / output circuit 2126, and may provide the data input / output signal DQ and the data strobe signal DQS to the DQ buffer 2121_3 and the DQS buffer 2121_4.

[0087] The power supply voltages VDD, VDDQ, and VPP may be provided to the voltage generator 2128, and the power supply voltages VDD, VDDQ, and VPP may be provided to other components inside the memory device 2120. For example, the voltage generator 2128 may provide the power supply voltage VDDQ to the buffers 2121_1 to 2121_4. The voltage generator 2128 may generate a word line selection voltage and a word line non-selection voltage by using the power supply voltage VPP. The voltage generator 2128 may provide the word line selection voltage and the word line non-selection voltage to the row decoder 2123 and the memory cell array 2125.

[0088] Fig.13 Show Fig.11 Flowchart of an operation method of a test system of the present invention. In operation S205, the test device 2200 may receive setting information from a user. The setting information may be one of setting information including a monitoring condition of the power supply voltage VDD, setting information including a monitoring condition of the power supply voltage VDDQ, and setting information including a monitoring condition of the power supply voltage VPP.

[0089] In operation S210, the test device 2200 may generate a test scheme for testing the memory module 2100. The test scheme may be generated according to various test conditions. For example, the test scheme may include at least one of an activation command, a write command, a read command, and a refresh command of the memory device 2120 in the memory module 2100. Based on the test scheme generated in operation S210, the test device 2200 may perform operations S215, S225, S230, S240, S250, and S255. In operation S215, the test device 2200 may provide power supply voltages VIN1, VIN2, and GND to the PMIC 2110. In operation S220, the PMIC 2110 may provide power supply voltages VDD, VDDQ, and VPP to the memory device 2120.

[0090] In operation S225, the test device 2200 may transmit the setting information and the monitoring start command received in operation S205 to the PMIC 2110 by using the SCL signal and the SDA signal. Operation S225 may be similar to operation S110 and operation S120. The setting information may be stored in the setting register 242 / 342 of the PMIC 2110. The test device 2200 may transmit the monitoring start command to the PMIC 2110 to request the PMIC 2110 to monitor one of the power supply voltages VDD, VDDQ, and VPP of the PMIC 2110. Alternatively, the test device 2200 may transmit the monitoring start command to the PMIC 2110 to request the PMIC 2110 to monitor all the power supply voltages VDD, VDDQ, and VPP of the PMIC 2110. The test device 2200 may transmit the trigger bits T of the power supply voltages VDD, VDDQ, and VPP stored in the setting register 242 / 342 of the PMIC 2110 by using the monitoring start command. TRIGGER At least one of is changed to a first logic value.

[0091] In operation S230, the test device 2200 may send a memory command to the memory device 2120 through the RCD 2140 by using the clock signal CK and the command and address signal CA. The test device 2200 may send a data input / output signal DQ and a data strobe signal DQS including write data to the memory device 2120 through the DB 2150. In operation S235, the memory device 2120 may process the memory command sent in operation S230. For example, the memory device 2120 may write write data into a memory cell, may read read data from a memory cell, or may refresh data stored in a memory cell. In operation S240, the memory device 2120 may send a data input / output signal DQ and a data strobe signal DQS including read data to the test device 2200 through the DB 2150. Operation S240 may be skipped according to the test scheme generated in operation S210.

[0092] In operation S245, the PMIC 2110 may monitor one of the power supply voltages VDD, VDDQ, and VPP in response to the monitoring start command. Alternatively, the PMIC 2110 may monitor all of the power supply voltages VDD, VDDQ, and VPP in response to the monitoring start command. In any case, the PMIC 2110 may perform operations S130 to S170. When the monitoring operation is performed by the PMIC 2110 (during the monitoring time), the memory device 2120 may process the memory command received in operation S230 (S235). In addition, the memory device 2120 may send read data to the test device 2200 (S240).

[0093] In operation S250, the test device 2200 may send a monitoring end command to the PMIC 2110. Operation S250 may be similar to operation S180. In operation S255, the PMIC 2110 may send a monitoring result to the test device 2200 in response to the monitoring end command. The PMIC 2110 may send a ripple count CNT associated with one or more of the power supply voltages VDD, VDDQ, and VPP (monitoring of which is requested by the monitoring start command in operation S215) to the test device 2200. V , Ripple count CNT L or violation count CNT V is sent to the test device 2200. In operation S260, based on the monitoring result received in operation S255, the test device 2200 may check the PI of the memory module 2100 and may screen the memory module 2100. For example, when one of the ripple count and the violation count of the power supply voltages VDD, VDDQ, and VPP is greater than a threshold value, the test device 2200 may screen the memory module 2100. The threshold value may be predetermined.

[0094] Fig.14 A block diagram of a computing system according to another embodiment of the inventive concept is shown. The computing system 3000 may include a memory module 3100, a host 3200, and a system PMIC 3300. The memory module 3100 may include a PMIC 3110, a memory device 3120, an SPD module 3130, an RCD 3140, and a DB 3150. The memory module 3100 may be substantially the same as the memory module 2100.

[0095] The power supply voltage may be provided from the system PMIC 3300 to the host 3200. The host 3200 may include a processor 3210, an on-chip memory 3220, and a memory controller 3230. The host 3200 may be an application processor (AP) or a system-on-chip (SoC).

[0096] The processor 3210 may execute various software (e.g., applications, operating systems, file systems, device drivers, etc.) loaded onto the on-chip memory 3220. The processor 3210 may include a homogeneous multi-core processor or a heterogeneous multi-core processor. For example, the processor 3210 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). Applications, operating systems, file systems, device drivers, etc. for driving the computing system 3000 may be loaded onto the on-chip memory 3220. For example, the on-chip memory 3220 may be an SRAM or register implemented in the host 3200 and having a faster data input / output speed than the memory module 3100. The on-chip memory 3220 may be referred to as a "buffer memory".

[0097] The memory controller 3230 may include an interface circuit 3231, a clock generator 3232, a command / address generator 3233, a command queue 3234, a write data queue 3235, a read data queue 3236, and a data transceiver 3237. The interface circuit 3231 may generate an SCL signal and an SDA signal based on an I2C protocol or an I3C protocol. The interface circuit 3231 may send setting information of power supply voltages VDD, VDDQ, and VPP, a monitoring start command, and a monitoring end command to the memory module 3100 in response to a request from the processor 3210.

[0098] The clock generator 3232 may generate a clock signal CK and may transmit the clock signal CK to the memory module 3100. The command / address generator 3233 may receive a command or an address from a command queue 3234 and may transmit the command or the address to the memory module 3100. The command queue 3234 may store the command and the address generated by the processor 3210. The write data queue 3235 may receive and store write data to be stored in the memory module 3100 from the on-chip memory 3220. The read data queue 3236 may store read data transmitted from the memory module 3100 as a response to a read command of the memory controller 3230. The read data queue 3236 may transmit the read data to the on-chip memory 3220. The data transceiver 3237 may transmit the write data of the write data queue 3235 to the memory module 3100. The data transceiver 3237 may receive the read data from the memory module 3100 and may store the read data in the read data queue 3236.

[0099] The system PMIC 3300 may provide a power supply voltage to the host 3200. The system PMIC 3300 may provide power supply voltages VIN1 and VIN2 to the memory module 3100. The power supply voltages VIN1 and VIN2 provided from the system PMIC 3300 are not directly provided to the memory module 3100. Instead, the PMIC 3110 may generate power supply voltages VDD, VDDQ, and VPP by using the power supply voltages VIN1 and VIN2, and may provide the power supply voltages VDD, VDDQ, and VPP to the memory device 3120.

[0100] Fig.15 4 shows a block diagram of a computing system according to another embodiment of the inventive concept. The computing system 4000 may include memory modules 4100_1 to 4100_4 and a host 4200. The computing system 4000 may also include a system PMIC ( Fig.14 3300), which provides input voltages VIN1 and VIN2 to memory modules 4100_1 to 4100_4.

[0101] The memory module 4100_1 may include a PMIC 4110, a plurality of memory devices 4120, and an RCD 4140. The memory module 4100_1 may also include an SPD module 3130 of the memory module 3100 and a plurality of DBs 3150. The PMIC 4110 may receive an SCL signal and an SDA signal from a host 4200, and may be substantially the same as the PMIC 3110. The PMIC 4110 may provide power supply voltages VDD, VDDQ, and VPP to the plurality of memory devices 4120. The RCD 4140 may transmit a CK signal and a CA signal transmitted from the host 4200 to the plurality of memory devices 4120, and may be substantially the same as the RCD 3140.

[0102] Each of the memory modules 4100_2 and 4100_4 may be substantially the same as the memory module 4100_1. The memory modules 4100_1 and 4100_2 may be assigned to the channel CH1. The memory modules 4100_3 and 4100_4 may be assigned to the channel CH2. The channel CH1 may include an input / output path for the memory modules 4100_1 and 4100_2, and the channel CH2 may include an input / output path for the memory modules 4100_3 and 4100_4. Fig.15 , the number of channels, the number of memory devices, the number of memory modules, and the number of memory modules assigned to one channel are exemplary. The processor 4210, the on-chip memory 4220, and the memory controllers 4231 and 4232 of the processor 4210 may be substantially the same as the processor 3210, the on-chip memory 3220, and the memory controller 3230, respectively. The memory controller 4231 may access the memory modules 4100_1 and 4100_2 through the channel CH1. The memory controller 4232 may access the memory modules 4100_3 and 4100_4 through the channel CH2.

[0103] Fig.16 16, the memory module 4100 may be Fig.15 One of the memory modules 4100_1 to 4100_4.

[0104] In operation S310, the PMIC 4110 may provide power supply voltages VDD, VDDQ, and VPP to the memory device 4120. In operation S320, the host 4200 may send setting information and a monitoring start command to the PMIC 4110 by using an SCL signal and an SDA signal. Operation S320 may be similar to operation S225. The setting information may be one of setting information including a monitoring condition of the power supply voltage VDD, setting information including a monitoring condition of the power supply voltage VDDQ, and setting information including a monitoring condition of the power supply voltage VPP. The setting information may be stored in a setting register 242 / 342 of the PMIC 4110. The host 4200 may send a monitoring start command to the PMIC 4110 to request the PMIC 4110 to monitor one of the power supply voltages VDD, VDDQ, and VPP. Alternatively, the host 4200 may send a monitoring start command to the PMIC 4110 to request the PMIC 4110 to monitor all power supply voltages VDD, VDDQ, and VPP of the PMIC 4110. The host 4200 may set the toggle bits T of the power supply voltages VDD, VDDQ, and VPP stored in the setting register 242 / 342 of the PMIC 4110 by using a monitoring start command. TRIGGER At least one of is changed to a first logic value.

[0105] In operation S330, the host 4200 may send a memory command to the memory device 4120 through the RCD 4140 by using a clock signal CK and a command and address signal CA. In operation S340, the memory device 4120 may perform a data input / output operation by processing the memory command sent in operation S330. In operation S350, the memory device 4120 may provide read data to the host 4200. Operations S330, S340, and S350 are similar to operations S230, S235, and S240, respectively. In operation S360, the PMIC 4110 may monitor one of the power supply voltages VDD, VDDQ, and VPP in response to the monitoring start command sent in operation S320. Alternatively, the PMIC 4110 may monitor all of the power supply voltages VDD, VDDQ, and VPP in response to the monitoring start command sent in operation S320. Operation S360 may be similar to operation S245. In any case, the PMIC 4110 may perform operations S130 to S170. When the monitoring operation is performed by the PMIC 4110 (during the monitoring time), the memory device 4120 may process the memory command received in operation S330 based on the power supply voltages VDD, VDDQ, and VPP (S340). In addition, the memory device 4120 may transmit the read data to the host 4200.

[0106] In operation S370, the host 4200 may transmit a monitoring end command to the PMIC 4110. In operation S380, the PMIC 4110 may transmit a monitoring result to the host 4200 in response to the monitoring end command. The PMIC 4110 may store a ripple count CNT associated with one or more of the power supply voltages VDD, VDDQ, and VPP (monitoring of which is requested by the monitoring start command transmitted in operation S320). H , Ripple count CNT L or violation count CNT V , and sent to the host 4200. Operations S370 and S380 are similar to operations S250 and S255, respectively. In operation S390, based on the monitoring result received in operation S380, the host 4200 may check the PI of the memory module 2100, and may adjust the workload of the memory module 4100. For example, when one of the ripple count and the violation count of the power supply voltages VDD, VDDQ, and VPP is greater than a predetermined threshold, the host 4200 may reduce the workload of the memory module 4100_1 and may increase the workload of the other memory modules 4100_2 to 4100_4 instead. The host 4200 may send the write data to be stored in the memory module 4100_1 to the other memory modules 4100_2 to 4100_4.

[0107] Fig.17 Another embodiment of the present invention is shown. Fig.15 Flow chart of the operation method of the computing system. Fig.17 Flowchart and Fig.16 Operation S410, operation S430, operation S440, operation S450, and operation S490 may be similar to operation S310, operation S330, operation S340, operation S350, and operation S390, respectively.

[0108] In operation S460, the PMIC 4110 may monitor one of the power supply voltages VDD, VDDQ, and VPP. Alternatively, the PMIC 4110 may monitor all of the power supply voltages VDD, VDDQ, and VPP. For example, the PMIC 4110 may periodically or randomly monitor all of the power supply voltages VDD, VDDQ, and VPP without the monitoring start command of operation S320.

[0109] In operation S470, the PMIC 4110 may determine a ripple count CNT associated with the power supply voltages VDD, VDDQ, and VPP. H , Ripple count CNT L or violation count CNT VWhen the ripple count CNT associated with the power supply voltages VDD, VDDQ and VPP is greater than a predetermined threshold. H , Ripple count CNT L or violation count CNT V When one of the above is greater than the threshold, in operation S480, the PMIC 4110 may send a distress signal to the host 4200. For example, the distress signal may be referred to as an "alarm signal" or an "interrupt signal". The threshold used in operation S470 may be stored in a setting register 242 / 342 of the PMIC 4110 and may be updated by the host 4200. The controller 231 / 331 of the PMIC 4110 may set the ripple count CNT associated with the power supply voltages VDD, VDDQ, and VPP to H , Ripple count CNT L or violation count CNT V In operation S490, the host 4200 may adjust the workload of the memory module 4100 based on the distress signal received in operation S480.

[0110] Fig.18 A block diagram of a computing system according to another embodiment of the inventive concept is shown. The computing system 5000 may include a storage device 5100, a host 5200, and a system PMIC 5300. The storage device 5100 may be implemented with a solid state drive (SSD), a card storage, or an embedded storage. The storage device 5100 may include a PMIC 5110, a buffer memory device 5120, a non-volatile memory device 5130, and a controller 5140.

[0111] The PMIC 5110 may be provided with a power supply voltage from the system PMIC 5300. The PMIC 5110 may include regulators 5111 to 5113, an interface circuit 5114, a monitoring circuit 5115, and a register group 5116. The operations of the PMIC 5110 and the components 5111 to 5116 may be similar to the operations of the PMIC 200 and the components 211, 212, 213, 220, 230, and 240, or the operations of the PMIC 300 and the components 311, 312, 313, 320, 330, and 340. The PMIC 5110 may further include a multiplexer 250. The regulators 5111 to 5113 may generate output voltages VOUT1 to VOUT3 based on the power supply voltage provided from the system PMIC 5300. The output voltages VOUT1 to VOUT3 may be power supply voltages of the controller 5140, the buffer memory device 5120, and the nonvolatile memory device 5130.

[0112] According to an embodiment, the interface circuit 5114 of the PMIC 5110 may communicate with the PMIC interface circuit 5142 of the controller 5140. As in the PMIC 4110 performing operations S330, S360, and S380, the PMIC 5110 may receive setting information of the output voltages VOUT1 to VOUT3, a monitoring start command, and a monitoring end command from the controller 5140, may monitor the output voltages VOUT1 to VOUT3, and may transmit the results of monitoring the output voltages VOUT1 to VOUT3 to the controller 5140. As in the PMIC 4110 performing operations S460, S470, and S480, the PMIC 5110 may monitor the output voltages VOUT1 to VOUT3, and may transmit a distress signal to the controller 5140 based on the monitoring results. According to another embodiment, the interface circuit 5114 of the PMIC 5110 may communicate with the host 5200. As in the PMIC 4110 performing operations S330, S360, and S380, the PMIC 5110 may receive setting information of the output voltages VOUT1 to VOUT3, a monitoring start command, and a monitoring end command from the host 5200, may monitor the output voltages VOUT1 to VOUT3, and may transmit the results of monitoring the output voltages VOUT1 to VOUT3 to the host 5200. As in the PMIC 4110 performing operations S460, S470, and S480, the PMIC 5110 may monitor the output voltages VOUT1 to VOUT3, and may transmit a distress signal to the host 5200 based on the monitoring results.

[0113] The data input / output speed of the buffer memory device 5120 may be faster than the data input / output speed of the nonvolatile memory device 5130. The buffer memory device 5120 may store write data to be stored in the nonvolatile memory device 5130, read data read from the nonvolatile memory device 5130, metadata associated with the operation of the controller 5140, etc. under the control of the controller 5140. For example, the buffer memory device 5120 may include a DRAM device, an SRAM device, or a tightly coupled memory (TCM). The nonvolatile memory device 5130 may write, read, and erase data under the control of the controller 5140. The nonvolatile memory device 5130 may be, for example, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, an MRAM device, etc.

[0114] The controller 5140 may include a host interface circuit 5141. The host interface circuit 5141 may communicate with the host 5200 based on a protocol such as universal serial bus (USB), small computer system interface (SCSI), advanced technology attachment (ATA), serial AT attachment (SATA), serial attached SCSI (SAS), high speed interchip (HSIC), peripheral component interconnection (PCI), PCI express (PCIe), nonvolatile memory express (NVMe), universal flash storage (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), integrated drive electronic (IDE), or enhanced IDE (EIDE).

[0115] The controller 5140 may include a PMIC interface circuit 5142. The PMIC interface circuit 5142 may communicate with the PMIC 5110 based on the SPI protocol, the I2C protocol, or the I3C protocol. Fig.18 Unlike the example shown, the interface circuit 5114 may communicate with the host 5200 and may not communicate with the controller 5140. In this case, the controller 5140 may not include the PMIC interface circuit 5142.

[0116] The controller 5140 may further include: a buffer memory interface circuit 5143 communicating with the buffer memory device 5120; an NVM interface circuit 5144 communicating with the non-volatile memory device 5130; and a processor 5145. The buffer memory interface circuit 5143 and the NVM interface circuit 5144 may operate based on a double data rate (DDR) protocol. The processor 5200 may process a request of the host 5200 and may control the components 5141 to 5144 of the controller 5140.

[0117] Fig.19A block diagram of a computing system according to another embodiment of the present invention is shown. The computing system 6000 can be implemented with an electronic device that can use or support an interface protocol proposed by the mobile industry processor interface (MIPI) alliance. The computing system 6000 may include an application processor 6100, a working memory 6200, a storage device 6300, a communication module 6400, an input / output device 6500, and a PMIC 6600. The application processor 6100 may control components 6200 to 6800 of the computing system 6000. The operation of the application processor 6100 may be similar to the operation of the above hosts 3200, 4200, and 5200. The working memory 6200 may temporarily store data processed or to be processed by the application processor 6100. The operation of the working memory 6200 may be similar to the operation of the memory device 2120. The storage device 6300 may semi-permanently store data processed or to be processed by the application processor 6100. The operation of the storage device 6300 may be similar to the operation of the storage device 5100. The communication module 6400 can communicate with external devices based on various communication protocols, such as world interoperability for microwave access (Wimax), wireless local area network (WLAN), ultra wideband (UWB), long term evolution (LTE), global system for mobile communication (GSM), code division multiple access (CDMA), Bluetooth, near field communication (NFC), wireless fidelity (Wi-Fi), radio frequency identification (RFID), transfer control protocol / Internet protocol (TCP / IP), USB, SCSI, mobile PCIe (M-PCIe) and FireWire.The input / output device 6500 may include a keyboard, a mouse, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a microphone, a gyro sensor, a vibration sensor, a liquid crystal display (LCD) device, a light-emitting diode (LED) display device, an organic LED (OLED) display device, an active matrix OLED (AMOLED) display device, a speaker, a motor, an image sensor, a depth sensor, a camera, a display, an antenna, etc. The PMIC 6600 may include a regulator 6610, an interface circuit 6620, a monitoring circuit 6630, and a register group 6640. The regulator 6610 of the PMIC 6600 may provide a power supply voltage to the components 6100 to 6500 of the computing system 6000. The operation of the PMIC 6600 may be similar to the operation of the PMICs 200, 300, 4110, and 5110. According to an embodiment, as in the PMIC 4110 performing operations S330, S360, and S380, the PMIC 6600 may receive setting information of the power supply voltage output from the regulator 6610, a monitoring start command, and a monitoring end command from the application processor 6100, may monitor the power supply voltage, and may transmit the result of monitoring the power supply voltage to the application processor 6100. As in the PMIC 4110 performing operations S460, S470, and S480, the PMIC 6600 may monitor the power supply voltage, and may transmit a distress signal to the application processor 6100 based on the monitoring result.

Claims

1. A power management integrated circuit PMIC, the PMIC comprising: a voltage regulator configured to generate an output voltage and to regulate the output voltage using a feedback voltage of the output voltage; a monitoring circuit configured to receive the feedback voltage and determine at each periodic interval whether the feedback voltage is outside a threshold voltage range; as well as a count register configured to store a count value indicating the number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range, Wherein, the voltage regulator comprises: a comparator configured to compare a reference voltage with the feedback voltage; and a voltage driver configured to generate an output voltage based on an output of the comparator, and Wherein, the PMIC further includes: A feedback voltage pin terminal is connected to the comparator and the monitoring circuit.

2. The PMIC according to claim 1, further comprising: The interface I / F circuit is configured to output monitoring data indicating the count value stored in the count register to an external device.

3. The PMIC according to claim 2, further comprising: A setup register, wherein the I / F circuit is further configured to receive an operating parameter that controls the operation of the monitoring circuit and store the operating parameter in the setup register.

4. The PMIC according to claim 3, wherein: The operating parameters include at least one of the threshold voltage range, the duration of each periodic interval, the monitoring time in which the monitoring circuit operates, a deviation from a target feedback voltage defining the threshold voltage range, a monitoring start trigger to start monitoring by the monitoring circuit, and a monitoring stop trigger to stop monitoring by the monitoring circuit.

5. The PMIC according to claim 3, further comprising: A data pin terminal is coupled to the I / F circuit, wherein the operating parameter is received at the data pin terminal.

6. The PMIC according to claim 1, wherein: The monitoring circuit includes: a first comparator configured to compare the feedback voltage with an upper threshold voltage of the threshold voltage range at each periodic interval; a first counter configured to increment a first count value at each periodic interval at which the first comparator indicates that the feedback voltage is greater than the upper threshold voltage; a second comparator configured to compare the feedback voltage with a lower threshold voltage of the threshold voltage range at each periodic interval; and The second counter is configured to increment a second count value at each periodic interval when the second comparator indicates that the feedback voltage is less than the lower threshold voltage.

7. The PMIC according to claim 6, wherein: The counting register is configured to store a first counting value of the first counter and a second counting value of the second counter.

8. The PMIC according to claim 7, wherein: The counting register is further configured to store a third counting value corresponding to a sum of the first counting value and the second counting value.

9. The PMIC according to claim 7, further comprising: The interface I / F circuit is configured to output monitoring data corresponding to at least one of the first count value and the second count value to an external device.

10. The PMIC of claim 1 , wherein the voltage regulator comprises: The voltage generator is configured to output the reference voltage.

11. The PMIC according to claim 1, wherein: The voltage regulator is a first voltage regulator, the output voltage is a first output voltage, the monitoring circuit is a first monitoring circuit, the counting register is a first counting register, the counting value is a first counting value, the threshold voltage range is a first threshold voltage range, and the feedback voltage is a first feedback voltage, wherein the PMIC further includes: a second voltage regulator configured to generate a second output voltage; a second monitoring circuit configured to receive a second feedback voltage of the second output voltage and determine at each periodic interval whether the second feedback voltage is outside a second threshold voltage range; and A second count register is configured to store a second count value indicating the number of times the second feedback voltage is determined by the second monitoring circuit to be outside the second threshold voltage range.

12. The PMIC according to claim 1, wherein: The voltage regulator is a first voltage regulator, the output voltage is a first output voltage, and the feedback voltage is a first feedback voltage, wherein the PMIC further includes: a second voltage regulator configured to generate a second output voltage; and a multiplexer circuit configured to selectively apply one of the first feedback voltage and the second feedback voltage of the second output voltage to the monitoring circuit, The monitoring circuit is configured to store a second count value indicating the number of times the second feedback voltage is determined to be outside a second voltage range in the count register.

13. The PMIC according to claim 1, wherein: The feedback voltage is obtained by dividing the output voltage.

14. A dynamic random access memory DRAM module, comprising: Module board; A DRAM device mounted on the module board, the DRAM device including a plurality of operating voltage terminals; as well as a power management integrated circuit PMIC mounted on the module board, the PMIC comprising a plurality of voltage regulators configured to generate a plurality of operating voltages applied to a corresponding plurality of operating voltage terminals of the DRAM, and the PMIC configured to receive a plurality of feedback voltages of the corresponding plurality of operating voltages, wherein the plurality of voltage regulators are further configured to adjust the corresponding plurality of operating voltages using the plurality of feedback voltages, wherein the PMIC includes a monitoring circuit configured to determine a number of times each of the plurality of feedback voltages is outside a corresponding threshold voltage range and store the number of times in a counting register, Wherein, one of the plurality of voltage regulators comprises: a comparator configured to compare a reference voltage with one of the plurality of feedback voltages; and a voltage driver configured to generate an output voltage based on an output of the comparator, and Wherein, the PMIC further includes: A feedback voltage pin terminal is connected to the comparator and the monitoring circuit.

15. The DRAM module according to claim 14, further comprising: at least one first pin terminal; as well as A serial presence detection (SPD) circuit is mounted on the module board and is configured to exchange PMIC control and data signals between the at least one first pin terminal and the PMIC.

16. The DRAM module according to claim 15, further comprising: at least one second pin terminal; as well as A data buffer circuit is mounted on the module board and is configured to exchange memory data signals between the at least one second terminal and the DRAM device.

17. The DRAM module according to claim 16, further comprising: at least one third pin terminal; as well as A register clock driver circuit is mounted on the module board and is configured to exchange command and address signals between the at least one third pin terminal and the DRAM device.

18. The DRAM module according to claim 17, further comprising: At least one fourth pin terminal is used to provide an input voltage to the PMIC.

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