Equipment process scheduling

Abstract

A device for contactless communication with a terminal, comprising: an antenna for communicating with the terminal; an embedded chip configured to communicate with the terminal according to a contactless transmission protocol, wherein, according to the contact transmission protocol, a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response; and a module configured to perform a process formed by a plurality of discrete operations, and the module is configured to: in response to completing a subset of one or more discrete operations within a waiting time interval set by the terminal, send a first type of command to the embedded chip if the process is not completed; wherein the embedded chip is further configured to: in response to receiving the first type of command, transmit a request to the terminal to extend the waiting time for the response.

Description

Technical Field

[0001] The present invention relates to the scheduling of processes within a device when the device communicates with a terminal. Background Art

[0002] A smart card may refer to a device that includes an embedded integrated circuit chip and internal memory. The internal memory may be located on the integrated circuit chip, or may be a separate chip embedded in the card. A smart card may be a contact card; a contactless card, or may be capable of operating as both a contact card and a contactless card. Smart cards exist in a variety of form factors, including plastic cards, key fobs, watches, wearable devices, electronic passports, and USB-based tokens, as well as subscriber identity modules (SIMs) used in mobile phones.

[0003] A contact card communicates with a terminal (e.g., a card reader) by being physically connected to the terminal. For example, a contact card may include one or more contact points that provide an electrical connection to the terminal when the card and the terminal are brought into appropriate physical contact (e.g., by inserting the card into a slot in the terminal).

[0004] Contactless cards communicate with a terminal without direct physical contact. Typically, contactless cards communicate with a terminal via radio waves. A contactless card may include an antenna for receiving electromagnetic signals (e.g., RF signals) emitted from a terminal. Similarly, the antenna of the card may be used to transmit data from the card back to the terminal.

[0005] Some contactless cards are "passive". Passive cards harvest energy from the signal transmitted by the free terminal to power the embedded chip. One way to harvest energy from the transmitted signal is to arrange the antenna as a coil that, when it receives the transmitted signal, induces a voltage across its terminals by induction.

[0006] Smart card technology is being implemented in a variety of devices for performing an increasingly diverse range of functions, such as for performing payments, granting a user physical access to an area of ​​an environment, for storing a user's personal identification information, identifying or authenticating a user, etc. In some cases, it may be desirable for a device to be able to perform multiple different functions.

[0007] When trying to use smart card technology to implement multiple functionalities into a device (especially when a device designed to perform a "basic" or primary function is adapted to perform additional functions), several difficulties are faced. One problem is that the industry standards governing smart card technology were originally designed for payment / authentication cards. Therefore, the existing infrastructure has been designed in accordance with these standards to be suitable for powering this primary function of facilitating payments or transactions, which may constrain the power that can be consumed by any additional functionality placed on the card. This problem difficulty is exacerbated by the fact that the additional functions may consume more power and / or require power for a longer period of time than the primary function of the card. Another problem is that for cards operating in contactless mode, the power drawn by the additional functionality may affect the load modulation of the signal transmitted by the terminal, which may appear as additional noise to the terminal.

[0008] It would therefore be desirable to implement a device that supports smart card technology that provides the flexibility to conserve power consumption where possible and share available power with the primary functions of the device. Summary of the invention

[0009] According to the present invention, there is provided a device for contactless communication with a terminal, comprising:

[0010] An antenna, used for communicating with a terminal;

[0011] an embedded chip configured to communicate with the terminal according to a contactless transmission protocol, wherein, according to the contactless transmission protocol, a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response; and

[0012] A module executes a process formed by multiple discrete operations, and the module is configured to: in response to completing a subset of one or more discrete operations within a waiting time interval set by a terminal, send a first type of command to an embedded chip if the process is not completed; wherein the embedded chip is further configured to: in response to receiving the first type of command, transmit a request to the terminal to extend the waiting time for the response.

[0013] The waiting time interval may be a time period during which a communication is to be sent from the embedded chip to the terminal to maintain a connection between the embedded chip and the terminal. The waiting time interval may be a time period during which a response to a message or a waiting time extension request is to be transmitted from the embedded chip to the terminal to maintain the connection. The waiting time interval may be the interval between the time when a message from the terminal is received and the initially specified waiting time, or the interval between the time when a waiting time extension request is sent to the terminal and the extended waiting time resulting from the request.

[0014] The embedded chip may be configured to, in response to receiving the command before the waiting time interval expires, initiate transmission of the request to the terminal before the waiting time interval expires.

[0015] The module may be configured to respond to, but not limited to, messages sent from the terminal.

[0016] The module may be further configured to enter a low power mode once it has sent the command to the embedded chip.

[0017] The embedded chip may also be configured to enter a low power mode when it is not communicating with a terminal or module or participating in a process performed by a module.

[0018] The embedded chip may be configured to indicate to the module that a wait time extension request has been sent to the terminal. The module may be configured to exit the low power mode in response to the indication.

[0019] The module may include a controller unit configured to select a subset of the one or more discrete operations to be performed according to the waiting time interval. The controller unit may be configured to select, in response to an indication that a waiting time extension request has been sent to the terminal, a subset of the one or more discrete operations to be performed within the waiting time interval resulting from the request.

[0020] The module may also be configured to determine whether processing is complete in response to a subset of the one or more discrete operations being completed within the wait time interval.

[0021] The module may also be configured to send a second type of command to the embedded chip if it determines that the processing is complete.

[0022] The embedded chip may be configured to: in response to receiving the second type of command, determine whether the action requested by the terminal is completed, and:

[0023] In response to determining that the action is completed, transmitting an indication of the completion of the action to the terminal; and

[0024] In response to determining that the action is not completed, a wait time extension request is transmitted to the terminal.

[0025] The action requested by the terminal may be identity authentication or identity registration. The module may be a biometric sensor module. The module may be configured to: perform processing as part of performing a biometric authentication process. The module may be configured to: perform processing as part of performing a biometric registration process.

[0026] The biometric sensor module may include a biometric sensor and an ASIC for controlling the operation of the biometric sensor.

[0027] The subset of one or more discrete operations may be to start the ASIC. The subset of one or more discrete operations may be to collect at least a portion of the biometric parameters using the biometric sensor. The subset of one or more discrete operations may be to perform parameter matching on at least a portion of the biometric parameters captured by the biometric sensor.

[0028] The device may be a proximity integrated circuit card (PICC) and the terminal may be a proximity coupling device (PCD). The transmission protocol may be ISO14443, ISO1443 or Standard designation.

[0029] A method for contactless communication between a device and a terminal may be provided, the device comprising an embedded chip, the embedded chip being configured to communicate with the terminal according to a contactless transmission protocol, wherein according to the contactless transmission protocol, a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response, the method comprising:

[0030] At a module within the device, a process formed of a plurality of discrete operations is executed during a waiting time interval set by the terminal;

[0031] In response to completing a subset of the one or more discrete operations within a waiting time interval set by the terminal, sending a command of a first type from the module to the embedded chip if the processing is not completed;

[0032] In response to receiving the first type of command, a request is transmitted from the embedded chip to the terminal to extend a waiting time for a response.

[0033] According to another aspect of the present disclosure, there is provided a device for contactless communication with a terminal, comprising:

[0034] An antenna, used for communicating with a terminal;

[0035] an embedded chip configured to communicate with the terminal according to a contactless transmission protocol, wherein, according to the contactless transmission protocol, a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response; and

[0036] A module configured to perform a process formed by a plurality of discrete operations;

[0037] The embedded chip is configured to, for each waiting time extension request sent to the terminal: transmit a first signal to the module to indicate that the waiting time extension request has been sent to the terminal; and before the extended waiting time generated by the extension request, transmit a second signal to the module to indicate that another waiting time extension request is scheduled to be transmitted to the terminal; and

[0038] Wherein the module is configured to: start processing a subset of one or more discrete operations in response to a first signal; and stop processing the subset of discrete operations in response to a second signal.

[0039] The module may also be configured to transition to a low power state in response to a second signal.

[0040] The first signal may cause the module to transition from a low power state to an active state, in which the module is able to process discrete operations.

[0041] The module may be configured to: in response to the second signal, determine whether the process is complete, and if the process is complete, send an indication of the completion of the process to the embedded chip.

[0042] The embedded chip may be configured to: in response to receiving an indication of processing completion, determine whether the action requested by the terminal is completed, and:

[0043] In response to determining that the action is completed, transmitting an indication of the completion of the action to the terminal; and

[0044] In response to determining that the action is not completed, a wait time extension request is transmitted to the terminal.

[0045] The action requested by the terminal may be identity authentication or identity registration.

[0046] The embedded chip may be configured to transmit the second signal a specified period of time before transmitting a further wait time extension request to the terminal.

[0047] The module may be configured to transition to the low power state within a specified period of time from receipt of the second signal.

[0048] The embedded chip may also be configured to enter a low power mode when it is not communicating with a terminal or module and is not participating in processing performed by the module.

[0049] The device may include a communication link between the chip and the module, and the chip is configured to transmit the first signal by driving a state of the communication link from a first state to a second state.

[0050] The chip may be configured to transmit the second signal by driving the state of the communication link from the second state back to the first state.

[0051] The communication link can be I 2 C bus or Serial Peripheral Interface (SPI) bus.

[0052] The module may also be configured to transmit a third signal to the embedded chip to indicate that the first signal is received.

[0053] The device may include a first communication link and a second communication link between the chip and the module, the chip being configured to transmit the first signal and the second signal through the first communication link, and the module being configured to transmit the third signal through the second communication link.

[0054] The module may also be configured to: transmit a fourth signal to the embedded chip to indicate that the second signal is received.

[0055] The module may be configured to transmit a fourth signal via the second communication link.

[0056] The module may be configured to: transmit a third signal by driving the state of the second communication link from the first state to the second state; and transmit a fourth signal by driving the state of the communication link from the second state back to the first state.

[0057] The embedded chip may also be configured to retransmit the first signal to the module if it does not receive the third signal from the module within a specified waiting time.

[0058] The embedded chip may be configured to wait for a specified period of time before retransmitting the first signal after expiration of the specified waiting time.

[0059] The module may be a biometric sensor module.

[0060] The modules may be configured to perform processing as part of performing a biometric authentication process. The modules may be configured to perform processing as part of performing a biometric enrollment process.

[0061] The biometric sensor module may include a controller unit, a biometric sensor, and an ASIC for controlling the operation of the biometric sensor.

[0062] The embedded chip may be configured to send the first signal and the second signal to the ASIC after the ASIC is started.

[0063] The controller unit may be configured to, in response to receiving an activation signal from the embedded chip after the wait time extension request is transmitted to the terminal, activate the ASIC.

[0064] The device may be a proximity integrated circuit card (PICC) and the terminal may be a proximity coupling device (PCD). The transmission protocol may be ISO14443, ISO1443 or Standard designation.

[0065] A method for contactless communication between a device and a terminal may be provided, the device comprising a module and an embedded chip, the module being configured to perform a process formed of a plurality of discrete operations, the embedded chip being configured to communicate with the terminal according to a contactless transmission protocol, according to which a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip being configured to transmit a request to the terminal to extend the waiting time for the response, the method comprising, for each waiting time extension request sent to the terminal:

[0066] transmitting a first signal from the chip to the module to indicate that a wait time extension request has been sent to the terminal;

[0067] At the module, initiating processing of a subset of the one or more discrete operations in response to a first signal;

[0068] Before the extended wait time is generated due to the extension request, transmitting a second signal from the chip to the module to indicate that another wait time extension request is scheduled for transmission to the terminal;

[0069] At the module, processing of a subset of the discrete operations is stopped in response to the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The present invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

[0071] Figure 1 An example architecture of a device capable of contactless and contact communication with a terminal is shown.

[0072] Figure 2 Shows Figure 1 An example module for the device shown in .

[0073] Figure 3 An example implementation is shown. Figure 1 and Figure 2A timing diagram of the operation of the chips and modules of the device shown in FIG.

[0074] Figure 4 A timing diagram illustrating a first synchronization technique during startup of a module is shown.

[0075] Figure 5 A timing diagram illustrating a first synchronization technique at a subsequent stage of startup is shown.

[0076] Figure 6 A flow chart illustrating the steps of a first synchronization technique is shown.

[0077] Figure 7 A timing diagram illustrating a second synchronization technique during startup of a module is shown.

[0078] Figure 8 A timing diagram illustrating a second synchronization technique at a subsequent stage of startup is shown.

[0079] Fig. 9 A flow chart illustrating the steps of a second synchronization technique is shown.

[0080] Fig.10 A timing diagram illustrating a third synchronization technique during startup of a module is shown. Fig.11 A timing diagram illustrating a third synchronization technique at a subsequent stage of startup is shown.

[0081] Fig.12 A flow chart illustrating the steps of a third synchronization technique is shown.

[0082] Fig.13 A timing diagram illustrating communication between chips and modules according to a third synchronization technique is shown.

[0083] Fig.14 A timing diagram illustrating communications between a chip and a module according to a third synchronization technique when the module fails to acknowledge communications from the chip is shown.

[0084] Fig.15 A timing diagram illustrating communications between a chip and a module according to a third synchronization technique when the module fails to acknowledge receipt of communications from the chip within a specified period of time is shown. DETAILED DESCRIPTION

[0085] The present disclosure relates to a device for communicating with a terminal. The device includes: an antenna for receiving a wireless signal transmitted by the terminal; an embedded chip (e.g., an integrated circuit chip) and an additional embedded module. The device may be capable of operating in a contact operation mode and a contactless operation mode. The device may be, for example, a smart card, an ID card, a passport, etc. The terminal may be a card reader, for example, a point of sale (POS) terminal, a cash register, an ATM machine, a computer, a smart phone, etc.

[0086] The chip generates data for communicating with the terminal to perform a first function associated with the device. This first function may be the basis or primary function of the device. The chip may be, for example, a security element. The module is configured to perform one or more processes or steps as part of a second function associated with the device. Therefore, the device is a multifunctional device. The second function can be implemented by both the chip and the module; that is, the process required to perform the second function can be distributed across both the chip and the module; that is, both the module and the chip can each perform one or more processing steps that form part of the second function. Alternatively, the processing steps required to perform the second function can all be performed by the module; that is, the module can perform the second function. In addition, although the device has been described as performing two functions, it will be recognized that the device can perform additional functions (for example, it performs three, four, five, etc. functions). Generally, the device can perform multiple functions including a first function performed by the chip and a second function performed at least in part by the module.

[0087] In one particular implementation, the device is a smart card (e.g., a bank or credit card), and the primary function is a type of banking functionality such as performing a financial transaction, e.g., making a purchase. Alternatively, the first function may be some other function that requires communication with a terminal, such as: providing the card user with physical access to an environmental area (e.g., building access); identifying or authenticating the user; retrieving personal user information (e.g., medical information and records), etc. The second function may consist of processing steps that do not require communication with the terminal. However, the terminal may request that the second function be performed. The second function may, for example, be a type of biometric authentication. Biometric authentication may authenticate the user of the device to enable the first function (e.g., performing a financial transaction) to be completed. In other examples, the second function may be capturing an image of a portion of the user (e.g., for the purpose of biometric authentication); or may be a type of biometric enrollment. Other example implementations will be described in more detail below.

[0088] The chip is configured to communicate with the terminal according to a contactless transmission protocol, according to which a message or command sent by the terminal sets a specified waiting time for a response from the chip for maintaining a connection with the terminal. For example, the contactless transmission protocol may be provided by ISO14443 and / or The chip may transmit requests to the terminal to extend the waiting time for a response, but each request must be sent before the existing waiting time expires, otherwise the terminal considers the connection to the chip to have failed. Therefore, the transmission protocol governing the communications between the chip and the terminal may set time limits on those communications. In particular, the contactless transmission protocol may cause the failure of the chip to respond to the terminal before the expiration of a specified waiting time (by transmitting a waiting time extension request or some other message) to cause the connection between the chip and the terminal to fail (e.g., time out).

[0089] The module is configured to perform a process as part of a second function of the execution device. The process may be formed by a number of process steps. It may take longer to complete the process steps than the waiting time interval set by the terminal (e.g., the time window between consecutive waiting time extension requests). Described herein is a method for scheduling the process performed by the module and the embedded chip so that the process is synchronized with the waiting time extension request sent to the terminal by the embedded chip. By appropriately scheduling this process, the power consumption of the device can be effectively managed, and the potential interference to the required communication between the terminal and the embedded chip caused by the process performed by the module can be reduced.

[0090] Figure 1 An example device 100 is shown. The device 100 can communicate with a terminal 102 via a contact or contactless interface. The device includes an antenna 104, a chip 106, a module 108, and a contact element 118. The chip 106 is embedded in the device and may be, for example, a security element. The module 108 may also be embedded in the device. In this example, the module is a component that is physically different from the chip 106; each of the chip 106 and the module 108 may be implemented, for example, on a corresponding integrated circuit chip embedded in the device. In other examples, the module 108 and the chip 106 may be physically connected but logically separated entities. The module 108 and the chip 106 are connected to each other by one or more links (generally as shown at 110). Each of these links may be a bus.

[0091] The device 100 communicates with the terminal 102 (e.g., sends messages to and / or receives messages from the terminal) via the antenna 104 when operating in the contactless mode, and communicates with the terminal 102 via the contact element 118 when operating in the contact mode. In general, the device 100 may include one or more contact elements; for clarity, one contact element is shown here.

[0092] The contact element 118 is connected to the chip 106. The chip can be connected to the contact element by a conductive link. When the device is operating in the contact operation mode, the contact element enables the device to communicate with the terminal by direct physical contact. When the device and the terminal are brought into suitable physical contact, the contact element also provides an electrical connection to the terminal. Therefore, when the device is operating in the contact mode, the chip receives electrical energy from the terminal through the contact element. The device can communicate with the terminal according to the ISO7816 standard when operating in the contact mode.

[0093] In some arrangements, the contact element may be connected only to the chip. In these arrangements, the chip receives power from the terminal through the contact element. The chip may then manage the received power to power its internal components and supply power to the module to power its internal components. Figure 1 In the arrangement shown in , the contact elements are connected to both the chip 106 and the module 108. Thus, when the device is in contact mode, both the chip and the module can receive power from the terminals via the contact elements.

[0094] The antenna 104 is connected to both the chip 106 and the module 108, for example by a physical link such as a conductive element. In other arrangements, the chip may be connected only to the antenna.

[0095] When the device 100 is operating in contactless mode, data is exchanged between the chip 106 and the terminal 102 via the antenna 104. When operating in contactless mode, the chip communicates with the terminal 102 according to a transmission protocol, whereby a message or command sent by the terminal to the chip 106 sets an initial specified waiting time for a response. It may be necessary to communicate with the terminal 102 within the waiting time to maintain the connection between the device 100 and the terminal 102. Failure to respond to the terminal 102 within the specified waiting time may cause the connection between the device and the terminal to be lost or reset. The waiting time may not be explicitly set by the protocol, but may be negotiated between the device 100 and the terminal 102 according to a formula specified by the protocol. The transmission protocol may be, for example, ISO14443 and / or Standard control.

[0096] The chip 106 includes a power harvesting unit 112, a transceiver modem 114, a power management unit 118, and a contact modem 120. These components may be interconnected by a bus.

[0097] When the card is operating in contactless mode, the power harvesting unit 112 harvests power from the wireless signal transmitted from the terminal and received by the antenna 104. The power harvesting unit 112 can, for example, induce a voltage from the received signal transmitted by the terminal 102. The induced voltage can be supplied to the chip 106 and other components of the module 108. The wireless signal transmitted from the terminal can be a radio frequency signal regulated by a radio communication standard. In one example, the wireless signal is an NFC signal.

[0098] When in contactless mode, transceiver modem 114 manages the transmission of messages to and reception of messages from terminal 102. Transceiver modem 114 can operate to manage the reception and transmission of these messages to comply with standards governing communications with the terminal. Modem 114 can also operate to extract data from received wireless signals. Terminal 102 transmits data to device 100 by modulating the signal it generates. The terminal can modulate the generated signal using amplitude modulation. Modem 114 can then extract data from received wireless signals by demodulating the amplitude variation of the voltage induced in the antenna caused by the amplitude modulation at terminal 102.

[0099] The modem can transmit the message to the terminal by modulating the data generated within the chip 106 onto the wireless signal transmitted from the terminal 102. To do this, the modem 114 will apply a modulation load to the antenna 104. Modulating the antenna load at the device 100 changes the power drawn from the received signal according to the modulation. The change in the power drawn can be detected by the terminal 102 and interpreted as data.

[0100] A power management unit (PMU) 118 operates to manage or control the use of power (harvested by power harvesting unit 112 in contactless mode or supplied by contact elements in contact mode) by the components of the chip. PMU 118 can control the power consumed by other components of the chip to perform their tasks. In arrangements where the module is not connected to antenna 104 or contact elements 120, the PMU can also control the supply of harvested power from chip 106 to module 108.

[0101] The chip also includes a contact modem 120, which manages the transmission and reception of messages to and from the terminal when operating in contact mode. When the device is operating in contact mode, the contact modem 120 can also ensure that the communication between the chip and the terminal meets any relevant standards (e.g., ISO7816 standard).

[0102] The module 108 includes its own power harvesting unit 116. The power harvesting unit 116 is operable to harvest power from signals received by the antenna 104 in the contactless mode. The power harvested by the unit 116 may be supplied to other components of the module 108 to power those components. By implementing this architecture, the module 108 may harvest power from the received signals independently of the chip 106 (e.g., independent of the operation of the chip). The module 108 may also include its own power management unit (PMU) 122 for managing or controlling the consumption of power (harvested by the power harvesting unit 116 in the contactless mode, or supplied by the contact elements in the contact mode) by the components of the module. The module's PMU 122 may control the power consumed by other components of the module 108 during their operation to perform their tasks. In an implementation where only the chip is connected to the antenna, the module may not include a power harvesting unit and / or a power management unit.

[0103] Module 108 is configured to perform one or more processes as part of implementing a second function associated with device 100, and is not limited to responding to terminal 102 within any specified waiting time. The second function may not require communication with terminal 102; therefore, in some examples, module 108 may not communicate directly with the terminal at all—that is, only the chip communicates with the terminal. The module may be a biometric sensor module including one or more biometric sensors. The biometric sensor module may operate to perform biometric identification or authentication of one or more biometric parameters, including, for example: fingerprint recognition; iris recognition; vein recognition; retinal recognition; voice recognition; behavior recognition; facial recognition, etc. Alternatively, the module may be a PIN or password generator, a movement or position sensor, a display screen, a status indicator, or a data input mechanism such as a keyboard.

[0104] The device 100 and the terminal 102 may take one of many different form factors. The device 100 may be, for example, a smart card, an ID card, a passport, a key fob, a dongle, a security token (e.g., a USB token), etc. Alternatively, the device 100 may be integrated into the following devices: a communication device, such as a mobile phone or a smart phone; a wearable device, such as a bracelet, a watch, a glove / a pair of gloves, a pin (e.g., a brooch), a badge, or some other contactless wearable device. The terminal 102 may be a card reader, such as a point of sale (POS) terminal, a cash register, an ATM machine, a computer, a smart phone, etc.

[0105] In the following examples, device 100 is considered to be a smart card, terminal 102 is a card reader and they are communicating in contactless mode. In particular, device 100 can be a proximity integrated circuit card (PICC) and the terminal can be a proximity coupling device (PCD). Module 108 takes the form of a biometric sensor module, which operates to perform biometric identification or authentication of one or more biometric parameters. It can also perform biometric registration. Examples of types of biometrics include, for example, fingerprint recognition; iris recognition; vein recognition; retinal recognition; voice recognition; behavioral recognition; facial recognition, etc. It will be appreciated that these implementations have been selected for illustration purposes only, and the following examples are equally applicable to any alternative implementations mentioned above.

[0106] exist Figure 2 An example implementation of module 108 as a biometric sensor module is shown in . The biometric sensor module operates to perform a second function of the card 100, which in this example is to biometrically identify or authenticate a user of the card 100. The sensor module 108 includes a power management unit 210, a microcontroller unit (MCU) 212, an application specific integrated circuit (ASIC) 214, and a biometric sensor 218. The sensor module 108 may also optionally include a power harvesting unit 216 (for example, if the card 100 adopts an architecture in which both the chip and the module are connected to the antenna). The components of the sensor module 108 may be interconnected by a bus. In addition, in Figure 2 1 and 2. Two communication links 220 and 222 are shown to interconnect module 108 and chip 106. Links 220 and 222 may be physically and / or logically separate links. Link 220 and / or link 222 may be physical links. Link 220 and / or link 222 may be I 2 C bus or Serial Peripheral Interface (SPI) bus.

[0107] The power management unit 210 manages or controls the power supplied to the components of the biometric sensor module 108. In this way, the power management unit 210 can control the power consumed by other components of the sensor module. The power management unit 210 can be physically interconnected to each of the MCU 212, the sensor 218, and the ASIC 214. This allows the power management unit to individually control the power supplied to each of these components. Including the power management unit 210 within the sensor module 108 also enables the sensor module to control the power consumption of each of its internal components independently of the chip 106.

[0108] Sensor 218 is a biometric sensor for capturing one or more biometric parameters of a user. In some examples, the sensor may capture the biometric parameters by capturing an image of a biometric source. Sensor 218 may be, for example, a fingerprint sensor (single-sided or dual-sided sensor), a retinal sensor, an iris sensor, a facial sensor, etc.

[0109] ASIC 214 controls the operation of sensor 218. The ASIC may, for example, instruct the sensor to enter an acquisition mode in which the sensor captures data of a biometric parameter (e.g., a fingerprint pattern, a retinal pattern, an iris pattern, etc.). The ASIC may also receive data (e.g., image data) captured by sensor 218 (e.g., during acquisition mode). The ASIC may transmit the captured biometric data to MCU 212. The ASIC may also control the operating state of the sensor, for example, by controlling when the sensor transitions between a low-power standby mode and a higher-power acquisition mode.

[0110] MCU 212 can perform biometric matching to compare the data of the biometric parameters captured by sensor 218 with stored template data. For example, if the data captured by the sensor is an image, the MCU can perform image matching to compare the image captured by sensor 218 with a stored template image or with a stored template image. The template image is a credible image. In the sense that the image is regarded as a biometric source belonging to the user of card 100, the image can be trusted. In order to perform image matching, the MCU can perform feature extraction on the captured image to identify a set of one or more extracted features. The extracted features are then compared with the features of the template image to determine whether the captured image matches the template image. The MCU can, for example, compare the features of the image to determine the matcher score for the captured image. If the matcher score is higher than a predetermined threshold, the captured image can be considered to match the template image.

[0111] The MCU may transmit an indication that the captured biometric parameter data matches the template data to the chip 106. The chip 106 may then transmit an indication back to the reader 102 that the user of the card has been authenticated. Authentication of the card user may enable completion of the primary function associated with the card 100. Alternatively, the MCU may transmit to the secure element 106 that the captured biometric parameter data does not match the template data, in which case the user of the card has not been authenticated and may not proceed with the primary function associated with the card 100 (or may proceed in a modified manner as a result of the absence of a match). This is an example of an implementation of each stage or process of biometric authentication performed by the module 108.

[0112] In an alternative implementation, the process of performing image matching may be performed by chip 106 rather than module 108. This is an example of an implementation in which the process of biometric authentication is performed by both chip 106 and module 108;

[0113] MCU 212 may also be configured to control the operating state of ASIC 214. For example, the MCU may control the transition of the ASIC between a low-power standby mode and a high-power active mode.

[0114] Figure 3 is a schematic timing diagram illustrating the operation of module 108 and chip 106 .

[0115] When the device 100 is operating in the contactless operation mode, the chip 106 is in accordance with ISO14443 and The standards communicate with the terminal 102. These standards specify that the terminal that has sent a command to the chip 106 sets an initial waiting time (referred to as the frame waiting time (FWT)) for a response from the chip. The FWT is the maximum amount of time allowed for the chip to initiate sending a response back to the terminal. Failure of the chip to send a response to the terminal within the FWT may result in a loss of the communication connection between the chip and the terminal (e.g., a timeout). The value of the FWT may be negotiated between the device 100 and the terminal 102. The chip 106 may transmit a waiting time extension request to the terminal 102. The waiting time extension request may be represented as S(WTX). In response to receiving the waiting time extension request, the terminal extends the waiting time for the response from the chip. The device may extend the waiting time by the frame waiting time FWT (i.e., it may extend the waiting time by an amount equal to the initial waiting time). The waiting time extension request may be made at any time before the current waiting time expires.

[0116] exist Figure 3 The diagram schematically illustrates the The standard specifies the time limit. Block 302 represents starting chip 106 and module 108 and A series of waiting time extension requests transmitted from the chip to the terminal 102 are represented as 304 1-6. The time period during which the terminal expects a response from the chip 106 can be referred to as a waiting time interval. The waiting time interval is a time period between successive communications between the device 100 and the terminal 102 as specified by the time limits of the standards governing those communications. The waiting time interval is a time period during which a communication (e.g., a response to a command issued by the terminal 102 or a request for a waiting time extension) is to be sent from the chip to the terminal 102 to maintain a communication connection. Therefore, the waiting time interval can be a time period between the time when the command is received from the terminal and the initial specified waiting time, or a time period between making a waiting time extension request and the new extended waiting time caused by the request. That is, the waiting time interval can be regarded as a time period between two scheduled communications between the chip and the terminal. In this example, the waiting time interval is equal to the frame waiting time FWT. An example waiting time interval is shown at 308.

[0117] The module 108 operates to perform at least a portion of the second device function of biometric authentication. The execution of this function may be requested by the terminal. The function (and the processing performed by the module as a result) may be divided into a number of processing steps, such as: image acquisition using a biometric sensor; transferring the image to the MCU 212; image preprocessing and biometric feature extraction at the MCU; feature matching against one or more templates at the MCU; and transmitting the results of the feature matching to the chip.

[0118] exist Figure 3 306 illustrates a set of processing steps to be performed by the module 108. As shown, the time required for the module to perform the processing step may exceed the waiting time interval. In some cases, the duration of the processing step may span several waiting time intervals.

[0119] It should be appreciated that it is desirable that module 108 does not perform its processing during the time period when the chip is communicating with terminal 102. This is for two main reasons. First, when the device is operating in a contactless operating mode, the power that can be harvested from the received signal transmitted from the terminal may be limited. The harvestable power is prioritized to support the scheduled communications with terminal 102 required by the standard that the device 100 is complying with to operate. Secondly, during the time period when the chip is communicating with the terminal, the power drawn by module 108 affects the load modulation of the signal transmitted by the terminal, which may appear as additional noise to the terminal. In other words, the power drawn by the module can cause interference in the communication between the chip and the terminal.

[0120] To avoid these problems, the processing steps 306 performed by the module 108 are further divided into a plurality of discrete operations or tasks. Each task forms a part of the processing step, and the amount of time spent on completing each task can be less than that of the processing step. The processing performed by the module 108 can be started or paused at the boundary between the discrete operations. In other words, the processing performed by the module can be paused when the discrete task is completed, and can be resumed by processing the subsequent discrete tasks. The process 306 performed by the module can be divided into discrete tasks with different granularities. For example, a discrete operation can refer to one of the above-mentioned authentication steps (e.g., image acquisition). Alternatively, the discrete operation can be a combination of authentication steps, or a part of an authentication step (e.g., each authentication step can be formed by a plurality of discrete operations).

[0121] Then, the device 100 operates to synchronize the processing of these separate operations with the scheduled communication (in this example, the wait time extension request S(WTX)) between the device 100 and the terminal 102. The device performs this synchronization so that the separate operations are performed during the waiting time interval rather than during the period when the device 100 is communicating with the terminal 102. That is, the separate operations are performed during the time interval between the scheduled communications between the device 100 and the terminal 102.

[0122] Three methods for performing this synchronization will now be described. Each synchronization process will be described for the initial startup process when the device 100 is close to the terminal 102 and for the subsequent time after startup. For each of these synchronization methods, reference is made to the transition between the low-power state and the active state of the chip and module. The low-power state refers to the state in which the components (e.g., chips, modules, module components, etc.) of the device consume minimal power. The component may not be able to perform its full functionality when it is in a low-power state but not completely inactive (such as before startup, for example). The low-power state may be referred to as a standby state. The active state may refer to the state of such a component: the component consumes more electrical energy than when it is in a low-power state. The component may be able to perform its full functionality when it is in an active state.

[0123] In each of the synchronization methods discussed, the general principle illustrated in the accompanying figures is that once a device component can be placed in a low-power state (e.g., because it is not required for subsequent operations), the component should be placed in a low-power state, or should become completely inactive. Taking this action increases the power budget available to the remaining components that need to operate. When the component is needed again, it should be returned from the low-power or inactive state to the active state in time to perform its required operations.

[0124] While this is the illustrated approach, alternative approaches are contemplated where components can remain active while not participating in current operations. The choice of approach may depend on the architecture of the smart card, for example, whether the chip and module can operate independently, the availability of lines to signal status between the chip and module and its various internal components, and the availability of harvested power compared to the power budget required at any time by the various components that may be operating.

[0125] Figure 4 A timing diagram illustrating a first synchronization method during the startup process is shown. Time is represented along the x-axis. Line 402 shows the field strength of the signal transmitted from the terminal received by the device 100 when the device 100 is brought into the vicinity of the terminal and kept within a certain distance from the terminal. Line 404 represents the state of the chip 106; line 406 illustrates the communication along the communication line 220 between the chip 106 and the module 108. Line 408 represents the state of the MCU 212 of the module; line 410 represents the state of the ASIC 214 of the module, and line 411 represents the overall state of the module 108. When at least one of the components of the module 108 is in an active state, the module 108 is considered to be in an active state, and when all of its components are in a low-power state, it is considered to be in a low-power state. For example, when the MCU is in an active state (block 422), the module is said to be in an active state (represented by block 438 on line 411). When both the MCU and the ASIC have powered down to a low power state, the module is also in a low power state (represented by block 440 on line 411).

[0126] The power management unit of the chip 106 and the module 108 measures the voltage induced in the signal transmitted from the terminal 102. When the measured voltage increases above a specified voltage, the chip 106 and the MCU 212 of the module start up, as illustrated by blocks 412 and 414, respectively. When the device 100 is brought within a certain distance from the terminal, the chip 106 and the MCU 212 start up simultaneously but independently of each other. This conveniently eliminates the need for the chip 106 to control the startup of the MCU 212, which can eliminate the need for dedicated control signals and simplify the design of the power management unit of the chip and the module.

[0127] After startup, MCU 212 enters a low power state (illustrated at block 416). Chip 106 receives a communication from terminal 102, illustrated by block 418. This communication is based on and ISO14443 standards. During this communication, the MCU is in a low power state and the ASIC is not powered on, so the power drawn by the module is kept to a minimum, thereby reducing interference in the communication between the chip and the terminal. The communication from the terminal 102 may be a command. The command may be a request for a certain function or process to be performed, for example, authentication and / or registration of a device user. In the context of this example, the requested function is biometric authentication or registration.

[0128] The communication 418 from the terminal 102 sets an initial waiting time for a response to the terminal. This initial waiting time is denoted as TW1. The time period between the completion of the communication 418 and the initial waiting time defines a waiting time interval WTI. During this waiting time interval, a request for a waiting time extension or a response to the terminal will be sent from the chip 106 to the terminal 102 to avoid losing the connection to the terminal.

[0129] In response to completing the communication 418 with the terminal, the chip 106 indicates to the module 108 that it should transition out of its low power state and perform processing as part of the function requested by the terminal. The chip can do this by sending a "command" signal to the module along the communication line 220 (shown by block 420). The command 420 can be a request for the module to perform a biometric authentication process, or more generally, a request to perform at least a portion of a biometric authentication process. The command 420 also indicates the start of a wait time interval. The module can start an internal timer in response to receiving the command 420.

[0130] If the module does not require the chip to perform subsequent operations within the waiting time interval, the chip can transition to a low power state (shown by block 426) after the issuance of command 420. For example, if the chip Figure 1 If the device architecture discussed in , the module is able to harvest and manage its own power and therefore operate independently of the chip, the chip can enter a low power state because the module does not require the chip to be active during the wait time interval. Alternatively, if the device architecture is such that the module requires the chip to manage its power, or if the module requires the chip to participate in its processing during the wait time interval, the chip remains in the active state. In another alternative, the chip can remain in the active state if the available power is greater than or equal to the power budget required by the chip and the module.

[0131] The command signal 420 is received at the module's MCU 212. In response to receiving the signal 420, the MCU 212 transitions out of its low power state (shown by block 422).

[0132] The MCU 212 may start a timer in response to receiving a command 420 indicating the start of a waiting time interval WTI. The MCU may also be programmed to be aware of the waiting time interval and may select a subset of one or more discrete operations to be performed within the waiting time interval (subject to sufficient harvested electrical energy (402) continuing to be available). In other words, the MCU 212 may identify a subset of one or more discrete operations to be performed according to the waiting time interval. The subset of one or more discrete operations may be performed by an MCU, an ASIC (assigned by the MCU), a combination of both the MCU and the ASIC, or some other component of the module. The discrete operations may form part of one of the above-mentioned biometric authentication steps. For purposes of illustration, in this example, the discrete operations form part of the processing steps involved in starting the ASIC 214, such as bootloading, firmware initialization, calibration, and tuning. Therefore, the MCU 212, after transitioning to the active state, schedules the subset of discrete operations at block 424 to start the ASIC 214 of the module. That is, the command 420 triggers the startup of the ASIC of the module.

[0133] It is convenient if the booting of the module's ASIC can be fully completed within the agreed waiting time interval WTI, but in some cases the processing steps of booting the ASIC may span multiple waiting time intervals. Figure 4 In the example illustrated in , it is assumed that the module completes the startup of the ASIC within the illustrated waiting time interval. In order to increase the possibility that the startup of the ASIC 214 can be completed within the waiting time interval WTI, the chip 100 can be configured to send the command 420 immediately after completing the communication with the terminal 418.

[0134] Upon completion of the ASIC's assigned subset of discrete operations, the ASIC transitions to a low power state (shown at block 428). In response to the ASIC completing its operations and transitioning to a low power state, the module's MCU 212 signals a command 430 to the chip 106 and itself transitions to a low power state 432. Since both the MCU and the ASIC have been powered down to a low power state, the module 108 is in a low power state (represented by block 440 on line 412), so the power drawn by the module that could interfere with communications between the chip and the terminal is kept to a minimum.

[0135] Command 430 may indicate to chip 106 that module 108 has completed its assigned subset of discrete operations. Thus, command 430 may indicate to chip 106 that a transmission to terminal 102 may proceed. Thus, in response to receiving command 430, chip 106 sends a latency extension request 434 to terminal 102. Note that if the chip has previously transitioned to a low power state (as shown at block 426), receipt of command 430 may also cause the chip to transition out of the low power state to enable it to transmit latency extension request 434.

[0136] The chip 106 indicates to the module 108 that the transmission of the latency extension request to the terminal is in progress. In one example, the chip does this by clock stretching on the communication line 220. The rising edge of the clock stretching indicates the start of the transmission of the latency extension request. This is shown at block 436.

[0137] Because the chip sends the wait time extension request to the terminal 102 in response to receiving the command 430, the command 430 synchronizes the operation of the module 108 with the operation of the chip 106. The chip 106 does not have to send the request for the wait time extension until the wait time interval expires (i.e., until the initial wait time TW1). However, because the ASIC completes its assigned set of discrete operations before the wait time interval expires, the command 430 enables the module to signal the chip to optionally send the request for the wait time extension before the initial wait time TW1. This reduces the overhead of the system to a minimum. In the illustrated example, the transmission of the wait time extension request is completed before the time T before the time TW1.

[0138] Figure 5 The diagram shows an example of a process during operation of the device 100. Figure 4 1 is a timing diagram of a first synchronization method after initialization of the startup process of module 108 shown in FIG.

[0139] In response to completing the latency extension request, the chip 106 indicates to the module 108 that the transmission of the latency extension request 434 is complete. The chip may do this by lifting the clock extension on the communication line to the module (block 436). The falling edge of the clock extension indicates the end of the transmission of the latency extension request.

[0140] The completion of the wait time extension request 434 sets the wait time TW2, which is used for the additional communication to the terminal 102. Therefore, the completion of the wait time extension request 434 sets the wait time interval WTI, which defines the time period during which the chip 106 is to send additional communications to the terminal. If the module does not require the chip to perform subsequent operations during the new wait time interval, the chip 106 can transition to a low power state after the wait time extension request 434 is completed (block 516), otherwise the chip can remain in the active state.

[0141] In response to the chip indicating that the transmission of the wait time request is complete, the module's MCU 212 transitions from the low power state to the active state (block 510).

[0142] After transitioning to the active state, the MCU 212 may start a timer at the beginning of the waiting time interval and may be programmed to be aware of the waiting time interval. The MCU may then select a subset of one or more discrete operations to be performed during the waiting time interval (subject to sufficient harvested electrical energy (402) continuing to be available). In other words, the MCU 212 may identify a subset of one or more discrete operations to be performed according to the waiting time interval. The subset of one or more discrete operations may be performed by an MCU, an ASIC (assigned by the MCU), a combination of both the MCU and the ASIC, or some other component of the module. The discrete operations may form part of one of the above-described biometric authentication steps. For purposes of illustration, in this example, the subset of discrete operations is using the sensor 218 to capture a portion of an image under the control of the ASIC 214. Therefore, the MCU 212, after transitioning to the active state, signals the ASIC 214 to transition from its low power state to the active state (block 512). After transitioning to the active state, the ASIC executes its assigned set of one or more discrete operations in block 512.

[0143] After completing its assigned subset of discrete operations, the ASIC transitions to a low power state (block 514). The MCU detects that the ASIC has transitioned to a low power state and in response determines whether its processing (i.e., all of its discrete operations) is complete. In this example, it is assumed that the processing is not complete, so the MCU sends a command 518 to the chip 106, and after sending the command, it itself transitions to a low power state (block 520).

[0144] Command 518 may indicate to chip 106 that module 108 has completed its assigned subset of discrete operations and / or that the module is in a low power state. Thus, command 518 may indicate to chip 106 that a transmission to terminal 102 may be made. Thus, in response to receiving command 518, chip 106 may send a latency extension request 522 to terminal 102.

[0145] Thus, command 518 synchronizes the operation of module 108 (particularly, the execution of the discrete operations) with the communication from chip 106 to terminal 102. Note that chip 106 does not have to send a request for a wait time extension until the wait time interval expires (i.e., until the wait time TW2 is extended). However, because the module completes a subset of one of its discrete operations within the wait time interval (i.e., before the wait time interval expires), command 518 sent from the module to the chip enables the chip to send a wait time extension request before extending the wait time TW2.

[0146] In other examples, a subset of the discrete operations to be performed during the wait time interval may be performed by the MCU. In this case, the MCU may not activate the ASIC during the wait time interval. Alternatively, the MCU may process a subset of its discrete operations and, after completing the subset during the wait time interval, send command 518 to chip 106 before transitioning to a low power state.

[0147] Block 524 indicates that the module is in an active state during a period of time when at least one component of the module is in an active state. Block 526 indicates that the module is in a low power state when all of its components are in a low power state.

[0148] As above, the chip 106 indicates to the module 108 that the transmission of the latency extension request 522 is in progress by raising the clock stretch on the communication line to the module (block 528). In response to completing the latency extension request, the chip 106 indicates to the module 108 that the communication is complete by stopping the clock stretch 528 on the communication line 220. The falling edge of the clock stretch indicates the end of the latency extended transmission, thereby indicating to the module that it can resume operation to complete the process 306 (represented by blocks 532, 534 and 536). If the module does not need the chip to perform subsequent operations during the latency time interval generated by transmitting the extension request 522, the chip 106 can be transitioned to a low power state (block 530), otherwise the chip can remain in the active state.

[0149] Can be Figure 6 The first synchronization process implemented by the device 100 is summarized by the flowchart in FIG.

[0150] At step 602, the device is brought within a certain distance from the terminal so that the field strength rises above a specified threshold, thereby triggering the startup of the chip 106 and the MCU 212. The MCU may remain in a low power state after startup.

[0151] At step 604, the chip 106 enters an active state and communicates with the terminal 102. Figure 6 , the communication involves the chip receiving a command from the terminal, setting an initial waiting time for a response. The command from the terminal may be a request for a function to be performed (e.g., biometric authentication or enrollment). For subsequent passes through the loop, at step 604, the chip sends a request to the terminal to extend the waiting time for a response. The transmission of the waiting time extension request to the terminal may be initiated before the expiration of the previous waiting time interval.

[0152] During step 604 , the chip may indicate to the module that communication with the terminal is in progress (eg, by clock stretching on the communication line 220 ).

[0153] At step 606, the chip 106 notifies the module with a signal to indicate that the communication with the terminal is complete. Figure 6 In the first pass of the steps shown in , the chip can do this by sending a command on the communication line 220 to request the module to perform processing as part of the process requested by the execution terminal. Figure 6 In a subsequent pass of the steps shown in , the chip can do this by raising the clock extension on the communication line 220. The completion of this communication sets a new waiting time interval in which subsequent communications are to be sent to the terminal. In response to completing the communication with the terminal, the module transitions to an active state and optionally starts an internal timer for the start of the waiting time interval. Optionally, the chip can enter a low power state after signaling the module.

[0154] At step 608, the module performs a subset of one or more discrete operations forming part of the process during the waiting time interval set by the terminal. The module may determine the subset of discrete operations to be performed based on the length of the waiting time interval and / or the level of available power harvested from the signal transmitted by the terminal 102. In the above example, the subset of discrete operations is determined by the MCU and assigned to the ASIC.

[0155] At step 610, the module determines whether its processing is complete. That is, the module determines whether all discrete operations that form the processing steps 306 to be performed by it have been completed. This determination can be performed by the MCU. When the module has performed all of its assigned processing steps required to implement the second function of the device, the processing can be completed. The module then sends a command to the chip based on the determination. The module sends a first type of command in response to determining that the processing is not complete, and sends a second type of command in response to determining that the processing is complete. The first type of command indicates that the processing is not complete, while the second type of command indicates that the processing is complete. Figure 5 The command 518 in is an example of a first type of command. The second type of command may indicate the consequence or result of the processing performed by the module. For example, if the module performs each step of biometric authentication, the second type of command may contain the result of the authentication (i.e., whether the device user is authenticated). For implementations in which image matching is performed by the chip, the second type of command may contain data about the captured image that enables the chip to perform image matching, for example, data representing the captured image or data representing features extracted from the captured image. Both the first type of command and the second type of command may be transmitted over the communication line 220.

[0156] After transmitting the command to the chip, the module transitions to the low power state. The command may indicate to the chip that the module is in the low power state.

[0157] At step 612, the chip determines whether its action is completed. The chip can, for example, determine whether the function requested by the terminal at step 604 is completed. When the function requested by the terminal is completed, the chip can determine that its action is completed. In other words, the chip determines whether another wait time extension request is required.

[0158] The chip may determine that the function requested by the terminal is not completed (and therefore requires an additional wait time extension request) in response to receiving a first type of command from the module at step 610. Receiving a second type of command from the module at step 610 does not necessarily mean that an additional wait time extension request is not required. For example, if both the chip and the module perform processing steps to perform the function requested by the terminal, receiving a second type of command indicates that the module has completed its assigned processing steps, but does not mean that the chip has completed its assigned processing steps. In some implementations, the processing steps are assigned to the chip and the module in such a way that the chip cannot perform its processing steps until the module has completed its processing steps. An example of this is that the step of biometric image capture is performed by the module, while the steps of image feature extraction and / or image matching are performed by the chip. Therefore, the second type of command may indicate that the chip is to perform its processing steps to perform the requested function.

[0159] If the chip determines that its action is not completed, the method returns to step 604, where the chip transmits a wait time extension request to the terminal. If the module has not completed its processing, steps 606, 608, 610 and 612 are repeated until the processing of the module is completed. If the processing of the module is completed but the action of the chip is still not completed, the chip can continue to perform its processing in the waiting time interval between consecutive wait time extension requests sent to the terminal until its action is completed.

[0160] If the chip determines at step 612 that its action is complete, the method proceeds to step 614, where the chip transmits a message to the terminal indicating the end of its action. The message may indicate that the function requested by the terminal has been completed. The message may additionally indicate the result of the function (e.g., whether the user of the device has been authenticated). After transmitting the message to the terminal, the chip may enter a low power state. When the chip determines that its action is complete, no additional wait time extension request may be sent.

[0161] Thus, in summary, for each waiting time interval set by the communication from the chip to the terminal, the chip notifies the module to indicate that the communication to the terminal is complete. In response, the module identifies and begins processing a subset of discrete operations. In response to completing the subset of operations within the waiting time interval, the module sends a command to the chip before the waiting time interval expires, which causes the chip to send a waiting time extension request to the terminal if it is determined that the module has not completed its processing. The waiting time extension request then sets an additional waiting time interval.

[0162] The second synchronization method will now be described.

[0163] Figure 7 7 is a timing diagram illustrating a second synchronization method during the startup process. Again, time is represented along the x-axis. Line 702 shows the field strength of the signal transmitted from the terminal received by the device 100 when the device is brought near the terminal and kept within a certain distance from the terminal. Line 704 represents the state of the chip 106; line 706 illustrates the communication along the communication line 220 between the chip 106 and the module 108. Line 708 represents the state of the communication line 222 between the chip 106 and the module 108. The communication line 222 can be a physical link. It can be a line separated from the first communication line (physically and / or logically). Line 710 represents the state of the MCU 212 of the module; line 712 represents the state of the ASIC 214 of the module, and line 713 represents the overall state of the module. The module 108 is considered to be in an active state on line 713 when at least one of its components is in an active state, and is considered to be in a low power state on line 713 when all of its components are in a low power state.

[0164] As previously described, the chip 106 and the power management unit of the module measure the voltage induced in the signal transmitted from the terminal 102. When the measured voltage increases to exceed a specified voltage, the chip 106 and the MCU 212 of the module are activated (illustrated by blocks 714 and 716, respectively). When the device 100 is brought to a certain distance from the terminal, the chip 106 and the MCU 212 are activated simultaneously but independently of each other.

[0165] After startup, MCU 212 enters a low power state (illustrated at block 718). Then, chip 106 communicates with terminal 102 (illustrated by block 720). This communication is based on and ISO14443 standards. During this communication, the MCU is in a low power state and the ASIC is not powered on, so the power drawn by the module is kept to a minimum, thereby reducing interference in the communication between the chip and the terminal. Communication 720 is similar to Figure 4 Communication 418 shown in and described above.

[0166] The communication 720 from the terminal 102 sets an initial waiting time for the response to the terminal. This initial waiting time is denoted as TW1. The time period between the communication 720 and the initial waiting time defines a waiting time interval WTI. A request for an extension of the waiting time or a response to the terminal is to be sent from the chip 106 to the terminal 102 during this waiting time interval to avoid losing the connection to the terminal.

[0167] In response to completing the communication with the terminal 720, the chip 106 indicates to the module that it should transition out of its low power state and perform processing as part of performing the function requested by the terminal. The chip can do this by sending a "command" signal to the module (shown by block 722). The command 722 can be a request for the module to perform a biometric authentication process, or more generally a request to perform at least a portion of a biometric authentication process. The indication is sent from the chip to the module via the communication line 220. The command also indicates the start of a wait time interval.

[0168] If the module does not require the chip to perform subsequent operations within the waiting time interval, the chip can transition to a low power state (shown by block 724) after the issuance of command 722. For example, if the chip Figure 1If the device architecture discussed in , the module is able to harvest and manage its own power and therefore operate independently of the chip, the chip can enter a low power state because the module does not require the chip to be active during the wait time interval. Alternatively, if the device architecture is such that the module requires the chip to manage its power, or if the module requires the chip to participate in its processing during the wait time interval, the chip remains in the active state during the wait time interval. In another alternative, the chip can remain in the active state if the available power is greater than or equal to the power budget required by the chip and the module.

[0169] The command signal 722 is received at the module's MCU 212. In response to receiving the signal 722, the MCU 212 transitions out of its low power state (shown by block 726).

[0170] The MCU 212 may start a timer in response to receiving a command 722 indicating the start of a waiting time interval WTI. The MCU may also be programmed to be aware of the waiting time interval and may select a subset of one or more discrete operations to be performed within the waiting time interval (subject to sufficient harvested electrical energy (702) continuing to be available). In other words, the MCU 212 may identify a subset of one or more discrete operations to be performed based on the waiting time interval. The subset of one or more discrete operations may be performed by an MCU, an ASIC (assigned by the MCU), a combination of both the MCU and the ASIC, or some other component of the module. The discrete operations may form part of one of the above-mentioned biometric authentication steps. For purposes of illustration, in this example, the discrete operations form part of the processing steps involved in starting the ASIC 214, such as boot loading, firmware initialization, calibration, and tuning. Therefore, the MCU 212, after transitioning to the active state, schedules the subset of discrete operations at block 728 to start starting the ASIC 214 of the module. That is, the signal 722 triggers the ASIC of the module to start.

[0171] It is convenient if the startup of the ASIC can be completed completely within the agreed waiting time interval WTI, but in some cases the processing steps of starting the ASIC may span multiple waiting time intervals separated by the extension request. Figure 7 In the example illustrated in , it is assumed that the module completes the booting of the ASIC within the illustrated waiting time interval. In order to increase the possibility that the booting of the ASIC 214 can be completed within the waiting time interval WTI, the chip 100 can be configured to send the command 722 immediately after the communication with the terminal 720 is completed.

[0172] Upon completion of its assigned subset of discrete operations, the ASIC transitions to a low power state (shown at block 730). In response to the ASIC completing its operations and transitioning to a low power state, the module's MCU itself transitions to a low power state 732. Since both the MCU and the ASIC have been powered down to a low power state, the module 108 is in a low power state (represented by block 742 on line 713), so the power drawn by the module can cause interference in communications between the chip and the terminal to be kept to a minimum.

[0173] Before the chip sends the wait time extension request 734 to the terminal, the chip signals the module that the wait time extension request is to be sent. This signal is transmitted through the communication line 222. In this example, the chip signals the wait time extension request to be sent by changing the state of the communication line 222 from a first state to a second state. This is illustrated at 736. The module 108 can be configured to interpret the change of state (in this example, the rising edge of the state) as a signal that the wait time extension request will be sent. The state of the communication line 222 can be the voltage level of the line. The first state can be associated with a first voltage level, and the second state can be associated with a second voltage level.

[0174] The chip may signal the module that a wait time extension request is to be sent a specified amount of time before the wait time extension request is sent. In other words, the chip may change the state of the communication line 222 a specified amount of time before the request is sent. This is to provide the module with a time window in which the module will complete or stop the discrete operation it is processing and transition to a low power state before the wait time extension request is sent.

[0175] If the chip has transitioned to the low power state after a previous communication with terminal 720, it transitions to the active state before transmitting signal 736 to the module. The chip may include an internal timer for setting the transition from the low power state to the active state before a predetermined amount of time before the wait time interval expires.

[0176] When the sending of the wait time extension request 734 has been completed, the chip 106 signals the module 108 that the wait time extension request has been sent. In this example, the chip does this by changing the state of the communication line 222 from the second state back to the first state. The module 108 is configured to interpret the change in state (in this example, the falling edge of the state) as a signal that the wait time extension request has been sent. This indicates to the module that it can resume operation. Therefore, the second synchronization method uses a signal from the chip 106 to the module 108 to synchronize the operation of the module with the chip.

[0177] If the module does not require the chip for subsequent operation, the chip 106 may transition to a low power state after the communication with the terminal is completed (shown by block 806 ).

[0178] Subsequent operations (shown by blocks 812, 814, and 826) may be performed according to the process (block 722) commanded by the chip. For example, after activation of the biometric module and chip, the process 306 that may have been requested to be performed is to authenticate the card user for payment, thereby requiring the capture of a biometric image.

[0179] Figure 8 The diagram shows a diagram of the operation of the device 100 during operation. Figure 7 1 is a timing diagram of a second synchronization method after initialization of the startup process of module 108 shown in FIG.

[0180] The completion of the wait time extension request transmission 734 extends the wait time to TW2 and sets a new wait time interval WTI, in which the terminal 102 expects additional communication from the chip 106. After the transmission of the wait time extension request 734, if the module does not need the chip for subsequent operations in the new wait time interval, the chip can transition to a low power state (indicated by block 806), otherwise the chip can remain in the active state.

[0181] The state of the communication line 222 changes from its second state back to its first state (indicated by the falling edge of line 736) to signal the module's MCU and ASIC that the wait time extension request 734 has been sent to the terminal (i.e., the transmission of the wait time extension request has been completed). The falling edge indicates the start of a new wait time interval. This signal causes one or both of the MCU and ASIC to change from their low power state to an active state (indicated by blocks 812 and 814, respectively). Because at least one of the components of the module is in the active state, the module itself is considered to be in the active state (shown by block 826).

[0182] In this example, the MCU 212 may be programmed to be aware of the wait time interval and may select a subset of one or more discrete operations to be performed during the wait time interval (subject to sufficient harvested electrical energy (702) continuing to be available). In other words, the MCU 212 may identify a subset of one or more discrete operations to be performed based on the wait time interval. The subset of one or more discrete operations may be performed by the MCU, the ASIC, or a combination of the MCU and the ASIC. The discrete operations may form part of one of the biometric authentication steps described above, such as using the sensor 218 to capture a portion of an image under the control of the ASIC. The MCU and / or ASIC performs its subset of discrete operations when in an active state.

[0183] Whether the MCU, the ASIC, or both the MCU and the ASIC transition to the active state may depend on the one or more discrete operations to be performed during the waiting time interval. For example, the process of image acquisition using the sensor 218 may be controlled only by the ASIC 214, in which case only the ASIC may transition to the active state during the waiting time interval. As another example, the process of image matching may be performed only by the MCU, so if the discrete operation to be performed during the waiting time interval is an operation that forms part of the image matching, only the MCU (and not the ASIC) may transition to the active state. Therefore, the components of the module 108 that transition to the active state may be limited to the components required to perform the one or more discrete operations to be performed during the waiting time interval.

[0184] Before the waiting time interval expires (and therefore before the next scheduled communication to the terminal 102 at time TW2), the chip 106 causes the state of the communication line 222 to transition from its first state to its second state. This transition (indicated by the rising edge of line 816) signals the MCU and ASIC that the waiting time extension request 822 is to be sent to the terminal. In response to this signal, the MCU and ASIC complete or interrupt the discrete operations being performed. Then, the module (e.g., MCU) determines whether its processing is all completed. If the module determines that its processing is not completed, the module transitions to a low power state and takes no further action. If the module determines that its processing is complete, it signals the chip to indicate that its processing is complete (discussed in more detail below).

[0185] In this example, it is assumed that the processing of the module is not completed, so the MCU and ASIC transition to a low power state in response to a signal from the chip (shown at blocks 818 and 820, respectively). When both the ASIC and the MCU are in a low power state, the module is in a low power state (shown at block 828). The chip 106 may signal the module that a wait time extension request 822 is to be sent before a specified time interval ΔT before the wait time extension request 822 is sent. This enables the MCU and ASIC to transition to their low power states before the transmission of the wait time extension request 822. The MCU and ASIC may be configured to transition to their low power states within a time period (equal to the specified time interval ΔT) in which a signal is received from the chip. The value of ΔT may vary depending on the implementation, but in one example, ΔT=1ms.

[0186] The module may decide whether to interrupt or complete processing of the discrete operations in response to receiving the signal from the chip based on: (i) the amount of processing remaining to complete the subset of discrete operations when the second signal is received, and (ii) the amount of time (e.g., the value of ΔT) before the wait time interval expires. If the module determines that there is enough time to complete the subset of discrete operations, it may do so before transitioning to a low-power state. In contrast, if the module determines that there is not enough time to complete the subset of discrete operations, it may interrupt the active operation being executed and then transition to a low-power state.

[0187] If the module has not completed its processing before the waiting time interval expires, the chip 106 sends an additional waiting time extension request 822 to the terminal. The MCU and ASIC of the module have already transitioned to a low power state before the chip starts sending the waiting time extension request 822. If, on the other hand, the module has completed its processing, no additional waiting time extension is needed.

[0188] Figure 7 and Figure 8 The diagram illustrates how the state of the communication line 222 between the chip 106 and the module 108 synchronizes the operation of the module with the scheduled communication from the chip to the terminal 102 in the second synchronization method. The state of the communication line is controlled by the chip 106. By synchronizing the state changes of the communication line 222 with the scheduled communication to the terminal, the operation of the module components can be controlled so that they are in a low power state during the transmission of the wait time extension request, and in an active state to perform one or more discrete operations during the wait interval between the scheduled communications to the terminal.

[0189] Available through Fig. 9 The second synchronization process implemented by the device 100 is summarized by the flowchart in FIG.

[0190] At step 902, the device is brought within a certain distance from the terminal, causing the field strength to rise above a specified threshold, thereby triggering the chip and MCU to start. The MCU can remain in a low power state.

[0191] At step 904, the chip 106 enters an active state and communicates with the terminal. Fig. 9 , the communication involves the chip receiving a command from the terminal, setting an initial waiting time for a response. The command from the terminal may be a request for a function to be performed (e.g., biometric authentication or enrollment). For subsequent passes through the loop, at step 904, upon expiration of the previous waiting time interval, the chip sends a request to the terminal to extend the waiting time for a response.

[0192] At step 906, the chip 106 transmits a first signal to the module indicating that the communication with the terminal is completed. Fig. 9 In the first pass of the steps shown in , the chip can do this by sending a command 722 on the communication line 220 to request the module to perform a process that is part of the process requested by the execution terminal. Fig. 9 In the subsequent pass of the steps shown in , the chip can do this by causing the state of the communication line 222 to transition from the first state to the second state. The completion of this communication with the terminal sets a new waiting time interval in which subsequent communications are to be sent to the terminal. In response to the completion of the communication with the terminal, the module transitions to the active state and optionally starts an internal timer to start the waiting time interval. Optionally, the chip can enter a low power state after notifying the module with a signal.

[0193] At step 908, the module performs a subset of one or more discrete operations. The module may determine the subset of discrete operations to be performed based on the length of the waiting time interval and / or the level of available power harvested from the signal transmitted by the terminal 102. These discrete operations are performed within the waiting time interval set by the transmission protocol, wherein the message is transmitted between the device 100 and the terminal 102 according to the transmission protocol. The waiting time interval is the time interval for sending communications from the chip to the terminal. The waiting time interval can be the time interval between consecutive scheduled transmissions between the device 100 and the terminal 102. The waiting time interval can be the time interval between a command sent by the terminal and the initial waiting time for the response to the command. Alternatively, the waiting time interval can be the time interval between a waiting time extension request sent to the terminal and the extended waiting time generated by the request.

[0194] At step 910, the chip 106 transmits a second signal to the module 108 indicating that the module is to stop processing its discrete operations. This second signal indicates that a wait time extension request is to be sent to the terminal; that is, it indicates that the next wait time extension request is scheduled for transmission. The chip can send the second signal by causing the state of the communication line 222 to transition from the second state back to the first state. The second signal is transmitted to the module before the waiting time interval expires. The second signal can be transmitted before a specified time period ΔT before the waiting time interval expires (that is, before the time ΔT before the waiting time extension request is transmitted). The module 108 completes or stops processing one or more discrete operations in response to receiving the first signal. The module completes or stops processing before the waiting time interval expires (that is, before the waiting time extension request is transmitted to the terminal). The module can be configured to complete or stop processing one or more discrete operations within a time period ΔT of receiving the first signal.

[0195] After stopping the processing of its discrete operations, at step 912, the module determines whether its processing is complete. That is, the module determines whether all discrete operations forming the processing steps 306 to be performed by it have been completed. This determination can be performed by the MCU. When the module has performed all the processing steps required for the second function of the device to be assigned, the processing can be completed. If the module determines that its processing is not completed, it is transferred to a low power state and no further action is taken. Then, the method returns to step 904, wherein the chip transmits a waiting time extension request to the terminal.

[0196] If the module determines at step 912 that its processing is complete, it sends a message to the chip indicating that its processing is complete (step 914). The message may indicate the consequence or result of the processing performed by the module. For example, if the module performs each step of biometric authentication, the message may contain the result of the authentication (i.e., whether the device user is authenticated). For implementations in which image matching is performed by the chip, the message may contain data about the captured image that enables the chip to perform image matching, such as data representing the captured image or data representing features extracted from the captured image. The message may be sent over communication line 220. After sending the message, the module may enter a low power state.

[0197] At step 916, in response to receiving the message from the module, the chip determines whether its action is completed. The chip can, for example, determine whether the function requested by the terminal at step 904 is completed. When the function requested by the terminal has been completed, the chip can determine that its action is completed. In other words, the chip determines whether an additional wait time extension request is required.

[0198] If both the chip and the module perform processing steps to complete the function requested by the terminal, the message received from the module at step 914 may instruct the chip to perform its processing steps to perform the requested function.

[0199] If the chip determines that its action is not completed, the method returns to step 904, where the chip transmits a wait time extension request to the terminal. If the module has completed its processing, the chip can continue to perform its processing in the waiting time interval between sending consecutive wait time extension requests to the terminal.

[0200] If the chip determines at step 916 that its action is complete, the method proceeds to step 918, where the chip transmits a message to the terminal indicating the end of its action. The message may indicate that the function requested by the terminal has been completed. It may additionally indicate the result of the function (e.g., whether the user of the device has been authenticated). After transmitting the message to the terminal, the chip may enter a low power state. When the chip determines that its action is complete, no additional wait time extension request may be sent.

[0201] The third synchronization method will now be described.

[0202] Fig.10 1 is a timing diagram illustrating a third synchronization method during the startup process. Again, time is represented along the x-axis. Line 1002 shows the field strength of the signal transmitted from the terminal received by the device 100 when the device is brought near the terminal and kept within a certain distance from the terminal. Line 1004 represents the state of the chip 106; line 1006 illustrates the communication along the communication line 220 between the chip 106 and the module 108. Line 1008 represents the state of the communication line 222 between the chip 106 and the module 108. Communication lines 220 and 222 can be physical links. Communication line 222 can be a line that is (physically and / or logically) separated from communication line 220. Line 1010 represents the state of the module's MCU 212; line 1012 represents the state of the module ASIC 214, and line 1013 represents the overall state of the module. Module 108 is considered to be in an active state on line 713 when at least one of its components is in an active state, and is considered to be in a low power state on line 713 when all of its components are in a low power state.

[0203] As previously described, the chip 106 and the power management unit of the module measure the voltage induced in the signal transmitted from the terminal 102. When the measured voltage increases to exceed a specified voltage, the chip 106 and the MCU 212 of the module are activated (illustrated by blocks 1014 and 1016, respectively). When the device 100 is brought to a certain distance from the terminal, the chip 106 and the MCU 212 are activated simultaneously but independently of each other.

[0204] After startup, MCU 212 enters a low power state (illustrated at block 1018). Chip 106 then communicates with terminal 102 (illustrated by block 1020). This communication is based on and ISO14443 standards. During this communication, the MCU is in a low power state and the ASIC is not powered on, so the power drawn by the module is kept to a minimum, thereby reducing interference in the communication between the chip and the terminal. Communication 1020 is similar to that shown in Figure 4 and Figure 7 Communications 418 and 720 described in and above.

[0205] The communication 1020 from the terminal 102 sets an initial waiting time for a response to the terminal. This initial waiting time is denoted as TW1. The time period between the communication 1020 and the initial waiting time defines a waiting time interval WTI. A request for a waiting time extension or a response to the terminal is to be sent from the chip 106 to the terminal 102 within this waiting time interval to avoid losing the connection to the terminal.

[0206] In response to completing the communication 1020 with the terminal, the chip 106 indicates to the module that it should be transformed from its low power state and perform a process as a part of the function requested by the execution terminal. In this example, the chip signals this command by changing the state of the communication line 220 from the first state to the second state. This is illustrated at 1044A. The module 108 can be configured to interpret the change of state (in this example, the rising edge of the state) as a signal for transitioning out of the low power state. Therefore, the signal 1044A can indicate that the communication of the chip with the terminal has been completed. The state of the communication line 220 can be the voltage level of the line. The first state can be associated with the first voltage level, and the second state can be associated with the second voltage level. The change of state also indicates the start of the waiting time interval. The second voltage level can be lower than the first voltage level. Alternatively, the first voltage level can be lower than the second voltage level.

[0207] The command signal 1044A is received at the module's MCU 212. In response to receiving the signal 1044A, the MCU 212 transitions from its low power state (shown by block 1026) to an active state. The MCU may start a timer at the beginning of a wait time interval due to the chip's communication 1020 with the terminal, and may be programmed to be aware of the wait time interval.

[0208] Once the MCU has been transformed from its low power state, the MCU 212 sends a confirmation to the chip that it has received the signal in response to receiving signal 1044A. In this example, the module signals this command by changing the state of the communication line 222 from a first state to a second state. This is illustrated at 1046B. The chip can be configured to interpret the change of state (in this example, the rising edge of the state) as a signal that the module is active, and the confirmation that signal 1044A has been received. The state of the communication line 222 can be the voltage level of the line. The first state can be associated with the first voltage level, and the second state can be associated with the second voltage level. The first voltage level of the communication line 222 can be lower than the second voltage level.

[0209] If the module does not require the chip to perform subsequent operations during the waiting time interval, the chip 106 may transition to a low power state (shown by block 1024) after sending signal 1044A. Figure 1If the module is capable of managing its own power and thus operates independently of the chip, the chip can enter a low power state during the wait time interval because the module does not require the chip to be active during the wait time interval. Alternatively, if the module requires the chip to manage its power, or if the module requires the chip to participate in its processing during the wait time interval, the chip remains in the active state. In another alternative, the chip can remain in the active state if the available power is greater than or equal to the power budget required by the chip and the module.

[0210] Returning to block 1026, the MCU, after transitioning to the active state, may select a subset of one or more discrete operations to be performed during the waiting time interval (subject to sufficient harvested electrical energy (1002) continuing to be available). In other words, the MCU212 may identify a subset of one or more discrete operations to be performed based on the waiting time interval. The subset of one or more discrete operations may be performed by the MCU, the ASIC (assigned by the MCU), a combination of both the MCU and the ASIC, or some other component of the module. The discrete operations may form part of one of the biometric authentication steps described above. For purposes of illustration, in this example, the discrete operations form part of the processing steps involved in starting the ASIC 214, such as boot loading, firmware initialization, calibration, and tuning. Therefore, the MCU 212, after transitioning to the active state, schedules the subset of discrete operations at block 1028 to begin starting the ASIC 214 of the module. That is, the signal 1044 triggers the ASIC of the module to start.

[0211] It is convenient if the startup of the ASIC can be completed completely within the agreed waiting time interval WTI, but in some cases the processing steps of starting the ASIC may span multiple waiting time intervals separated by the extension request. Fig.10 In the example illustrated in , it is assumed that the module completes the startup of the ASIC within the illustrated waiting time interval. In order to increase the possibility that the startup of the ASIC 214 can be completed within the waiting time interval WTI, the chip 100 can be configured to send a signal 1044A immediately after the communication with the terminal 1020 is completed.

[0212] After completing its assigned subset of discrete operations within the WTI, the ASIC transitions to a low-power state (shown at block 1030). In response to the ASIC completing its operations within the WTI and transitioning to a low-power state, the module sends a signal to the chip. In this example, the module sends this signal by changing the state of the communication line 222 from the second state back to the first state. This is shown at 1046D. The chip can be configured to interpret the change of state (in this example, the falling edge of the state) as a signal that the module is ready. That is, signal 1046D can indicate to the chip that the module has successfully started its ASIC. More generally, signal 1046D can indicate to the chip that the module has successfully started its components. Therefore, signal 1046D can be called a heartbeat signal.

[0213] After the module transmits signal 1046D, the MCU transitions to a low power state 1032. Since both the MCU and the ASIC are powered down to a low power state, the module 108 is in a low power state (represented by block 1042 on line 1013), so the power drawn by the module, which could interfere with communications between the chip and the terminal, is kept to a minimum.

[0214] Before the waiting time interval expires (i.e., before the initial waiting time TW1), the chip transitions from its low power state and transmits a waiting time extension request 1034 to the terminal. The device may include an internal timer or clock that signals the chip to transition from the low power state before the waiting time TW1. The timer may be located locally relative to the chip. In some implementations, it may be included in the chip. In other implementations, the chip may be configured to transition from its low power state 1024 in response to receiving a signal 1046D from the module. That is, the signal 1046D may indicate that the module is ready and causes the chip to transition to an active state in order to transmit a waiting time extension request 1034.

[0215] After transitioning out of its low power state, the chip changes the state of its communication line 220 from the second state back to the first state (illustrated at 1044C). Thus, during the period of time that the chip is transmitting the latency extension request 1034 to the terminal, the communication line 220 is in the first state.

[0216] After initialization of the boot process of the module and chip, subsequent operations (shown by blocks 1106, 1108, 1112, 1114 and 1116) may be performed. These are shown in more detail in Fig.11 in the timing diagram.

[0217] Completion of the transmission of the wait time extension request 1034 extends the wait time to TW2 and sets a new wait time interval WTI during which the terminal 102 expects further communications from the chip 106 .

[0218] The chip signals the module's MCU and ASIC that the wait time extension request 1034 has been sent to the terminal (i.e., the transmission of the wait time extension request has been completed). The chip signals this by causing the state of the communication line 220 to transition from its first state back to its second state (indicated by a rising edge 1108A). The rising edge indicates the start of a new wait time interval WTI. This signal 1108A may be referred to as a "communication complete" signal, and causes one or both of the MCU and ASIC to transition from their low power state to an active state (indicated by blocks 1112 and 1114, respectively). Because at least one of the components of the module is in an active state, the module itself is considered to be in an active state (shown by block 1116).

[0219] After transitioning to the active state, the module sends a signal to the chip in response to receiving the "communication complete" signal 1108A. In this example, the module signals its response by changing the state of the communication line 222 from the first state back to the second state. This is illustrated by the rising edge 1110B. The chip can be configured to interpret the change of state (in this example, the rising edge of the state) as a signal that the module is active. This signal can be called a confirmation signal. In other words, the signal 1110B can indicate that the signal 1108A has been received and / or the module has transitioned to the active state.

[0220] If the module does not require the chip for subsequent operation during the waiting time interval, the chip can transition to a low power state (shown by block 1106). The chip can transition to a low power state in response to sending a "communication complete" signal 1108. Alternatively, the chip can transition to a low power state only in response to receiving an acknowledgement signal 1110.

[0221] Returning to block 1112, the MCU 212, after transitioning to the active state, may select a subset of one or more discrete operations to be performed during the waiting time interval (subject to sufficient harvested electrical energy (1002) continuing to be available). In other words, the MCU 212 may identify a subset of one or more discrete operations to be performed based on the waiting time interval. The subset of one or more discrete operations may be performed by the MCU, the ASIC, or a combination of the MCU and the ASIC. The discrete operations may form part of one of the above-mentioned biometric authentication steps, for example, using the sensor 218 to capture a portion of an image under the control of the ASIC. The MCU and / or ASIC performs its subset of discrete operations when in the active state.

[0222] Whether the MCU, the ASIC, or both the MCU and the ASIC transition to the active state may depend on one or more discrete operations to be performed during the waiting time interval. For example, the process of image acquisition using the sensor 218 may be controlled only by the ASIC 214, in which case only the ASIC may transition to the active state during the waiting time interval. As another example, the process of image matching may be performed only by the MCU, so if the discrete operation to be performed during the waiting time interval is an operation that forms part of the image matching, only the MCU (and not the ASIC) may transition to the active state. Therefore, the components of the module 108 that transition to the active state may be limited to the components required to perform the one or more discrete operations to be performed during the waiting time interval.

[0223] Before the waiting time interval expires (and therefore before the next scheduled communication to the terminal 102 at time TW2), the chip 106 transitions the state of the communication line 222 from its second state back to its first state. This transition (indicated by falling edge 1108C) signals the MCU and ASIC that the waiting time extension request 1122 is scheduled to be transmitted to the terminal. In response to this signal 1108C, the MCU and ASIC complete or interrupt the discrete operation being performed. Then, the module (e.g., MCU) determines whether its processing is all completed. If the module determines that its processing is not completed, the module signals the chip that it has received the signal 1108C and transitions to a low-power state. The module can signal the receipt of the signal 1108C (indicated by falling edge 1110D) by transitioning the state of the communication line 222 from its second state back to its first state. Therefore, the signal 1110D can be regarded as a confirmation signal that the signal 1108C from the chip has been received. The signal 1110D can indicate to the chip that the module is pausing its processing and transitioning to a low-power state. If the module determines that its processing is complete, it signals the chip to indicate that its processing is complete (discussed in more detail below).

[0224] In this example, it is assumed that the processing of the module is not completed. The MCU and ASIC transition to a low power state (shown at blocks 1118 and 1120, respectively). When both the ASIC and the MCU are in a low power state, the module is in a low power state (shown at block 1128). The chip 106 can signal the module to wait for the time extension request 1122 to be sent before the specified time interval ΔT before the wait time extension request 1122 is sent. This enables the MCU and ASIC to transition to their low power states before the waiting time extension request 1122 is sent, thereby minimizing interference in the communication between the chip and the terminal that may be caused by the module drawing power. The MCU and ASIC can be configured to transition to their low power states within a time period (equal to the specified time interval ΔT) in which a signal is received from the chip. The value of ΔT may vary depending on the implementation, but in one example ΔT=1ms.

[0225] Since it is assumed that the module has not completed its processing before the wait time interval expires, the chip 106 sends an additional wait time extension request 1122. If, on the other hand, the module completes its processing during the wait time interval, no additional wait time extension may be required.

[0226] Fig.10 and Fig.11 The diagram illustrates how the states of the communication lines 220 and 222 between the chip 106 and the module 108 synchronize the operation of the module with the scheduled communications from the chip to the terminal 102 in the third synchronization method. The state of the communication line 220 is controlled by the chip 106, while the state of the communication line 222 is controlled by the module. By synchronizing the state changes of the communication line 222 with the scheduled communications to the terminal, the operation of the module components can be controlled so that they are in a low-power state during the transmission of the wait time extension request, and in an active state during the wait interval between the scheduled communications to the terminal to perform one or more discrete operations.

[0227] Using the state of the communication line to transmit signals between the module and the chip is a convenient implementation because it enables two types of signals to be transmitted over a single communication line, thereby reducing the number of communication lines between the chip and the module required in the device. For example, both a signal 1108A indicating that a wait time extension request has been transmitted to the terminal and a signal 1108C indicating that another wait time extension request is scheduled for transmission can be transmitted over a single communication line 220 by reversing the state transition of the single communication line 220. Similarly, two types of confirmation signals can be transmitted from the module to the chip over line 222: a first type of confirmation signal in response to receiving signal 1108A can be transmitted over a first state transition of line 222, and a second type of confirmation signal in response to receiving signal 1108C can be transmitted over a second opposite state transition of line 222.

[0228] Another advantage of the third approach is that the module is able to signal the chip back in response, providing a so-called "handshake". This handshake provides an opportunity to recover from error conditions, for example, if the chip does not receive a response from the module within a certain time, it can take mitigating actions, such as retrying until a response is received. Examples of how errors may occur can be situations where the harvested power level drops if the device is temporarily moved out of range from the terminal, or where noise on the signal causes the signal from any one component to be misinterpreted.

[0229] exist Figures 13 to 15 Some examples of how handshaking can provide recovery opportunities are shown in Figure 2. Fig.10 and Fig.11 As previously described, Fig.13 A normal handshake between the chip and the module using communication lines 220 and 222 is shown. At state transition A (indicated at 1301), the chip signals the module and the module sends a response signal due to state transition B 1303 within a time period Tds, where Tds is the maximum delay allowed between the chip sending a signal to the module and detecting a response from the module. The chip can now enter a low power state in response to receiving a reply signal from the module. The signal indicated by state transition 1301 can be, for example, a communication completion signal indicating that a wait time extension request has been sent to the terminal, and the response signal indicated by state transition 1303 can be an acknowledgement signal.

[0230] At a later time less than Tdm, the chip becomes active and signals the module again by converting its communication line 220 back to its original state (represented by state transition C, marked as 1305). Tdm is the maximum delay allowed between the module sending a signal to the chip and detecting a response from the chip. The module responds to this signal by converting its communication line back to its original state within a time period Tds (shown by state transition D, marked as 1307). The signal indicated by state transition C may be, for example, a pause signal indicating that a wait time extension request is to be sent to the terminal. The signal indicated by state transition D may be a confirmation signal indicating that the module has stopped processing and converted to a low power state. At a later time less than Tdm, the process may be repeated again (e.g., in a subsequent wait time interval).

[0231] Fig.14It shows what may happen if the module does not respond to the chip (for example, if the module is not ready or does not have enough power). At state transition A (marked as 1401), the chip notifies the module with a signal but the module does not send a response signal through state transition B within a specified time period Tds. After the time period Tds, the chip transitions back to its previous state (that is, its state before state transition A), which is illustrated at 1403. After the expiration of the time period Tds, the chip waits for a specified time period Tretry before resending a signal to the module due to another state transition A (marked as 1405). Tretry can be the minimum delay allowed between the expiration of the time period Tds and the resending of another signal. At this time, the module returns a signal response through state transition B (marked as 1407) within the time period Tds. At a time less than Tdm later, the chip once again signals the module by transitioning its communication line back to its original state due to state transition C (marked as 1409). At a time less than Tds later, the process can be repeated again.

[0232] Fig.14 An illustration of the advantages of the third synchronization method is provided. For example, assume that the signal indicated by transition 1401 is a signal indicating that a wait time extension request has been sent to the terminal. If the module does not receive this signal, then in the absence of Fig.14 In the case of the error recovery mechanism shown in , the module may remain in its low power state and not transition to the active state for the duration of the resulting WTI. However, the use of the confirmation signal enables the chip to determine that the module has not received the previous signal (so it may be in a low power state) so that the signal should be resent. By resending the signal, the chip provides the module with an additional opportunity to transition to the active state within the WTI.

[0233] Fig.15 1501, the module sends its response signal (via state transition B, labeled 1503) after the time period Tds has passed (i.e., after the time window in which it should have responded). After the time period Tds, the chip transitions the state of line 220 back to its previous state via transition C, labeled 1505. As a result, the module does not get a response signal from the chip within the specified time period Tdm of transition 1503. After the time period Tdm has expired, the module transitions line 222 back to its original state (i.e., the state before transition B) via transition D. The module can then transition to a low power state and wait for the chip once again.

[0234] After the time period Tretry has passed (after the time period Tds has expired), the chip resends the signal to the module via state transition A (labeled 1507) of its communication line 220. At this point, the module sends a response signal via state transition B within the time period Tds. At some time later, less than Tdm, the chip once again signals the module by transitioning its communication line back to its original state via transition C. The process can then be repeated once more.

[0235] Thus, in summary, the chip and the module can communicate with each other according to a protocol in which the signal from the chip to the module sets a time period Tds for the module to send a response signal to the chip. The module's failure to do so causes the chip to wait for a time period Tretry after the time period Tds expires and then resend the signal to the module.

[0236] Can be Fig.12 The third synchronization process implemented by the device 100 is summarized by the flowchart in FIG.

[0237] At step 1202, the device is brought within a certain distance from the terminal so that the field strength rises to exceed a specified threshold, thereby triggering the chip and MCU to start. The MCU can remain in a low power state.

[0238] At step 1204, the chip 106 enters an active state and communicates with the terminal. Fig.12 , the communication involves the chip receiving a command from the terminal, setting an initial waiting time for a response. The command from the terminal may be a request for a process to be performed (e.g., biometric authentication or enrollment). For subsequent passes through the loop, at step 904, upon expiration of the previous waiting time interval, the chip sends a request to the terminal to extend the waiting time for a response.

[0239] At step 1206, the chip 106 transmits a first signal to the module to indicate that the communication with the terminal is completed. The chip can do this by changing the state of the communication line 222 from the first state to the second state. The completion of this communication with the terminal sets a new waiting time interval in which subsequent communications will be sent to the terminal. In response to the completion of the communication with the terminal, the module transitions to an active state and optionally starts an internal timer for the start of the waiting time interval. Optionally, the chip can enter a low power state after notifying the module with a signal.

[0240] At step 1208, the module acknowledges receipt of the first signal from the chip and begins activity. The module may acknowledge receipt of the first signal by sending an acknowledgement signal in reply to the chip. The module may do this by causing the state of the communication line 220 to transition from a first state to a second state. The acknowledgement signal may indicate that the module has transitioned to an active state. Fig.12 Not shown, but if the chip does not receive the confirmation signal within the specified time period Tds, the chip can resend the first signal to the module (eg, by re-transitioning the state of line 222 from the first state to the second state).

[0241] At step 1210, the module performs a subset of one or more discrete operations. The module may determine the subset of discrete operations to be performed based on the length of the waiting time interval and / or the level of available power harvested from the signal transmitted by the terminal 102. The discrete operations are performed within the waiting time interval set according to the transmission protocol, wherein messages are transmitted between the device 100 and the terminal 102 according to the transmission protocol.

[0242] At step 1212, the chip 106 transmits a second signal to the module 108 to indicate that the wait time extension request will be sent to the terminal. The second signal indicates that the module will stop processing its separate operations. The second signal is transmitted to the module before the waiting time interval expires. The second signal can be transmitted before the specified time period ΔT before the waiting time interval expires (i.e., the time ΔT before the waiting time extension request is transmitted). In response to receiving the first signal, the module 108 completes or stops processing one or more of its separate operations. The module completes or stops processing before the waiting time interval expires (i.e., before the waiting time extension request is transmitted to the terminal). The module can be configured to complete or stop processing one or more of its separate operations within the time period ΔT of receiving the first signal. The chip can send the second signal by transitioning the state of the communication line 222 from the second state back to the first state.

[0243] At step 1214, the module sends an acknowledgement signal to the chip to acknowledge receipt of the second signal. The acknowledgement signal indicates to the chip that the module's activity has been suspended and that it has entered a low power state. The module may send the acknowledgement signal by transitioning the state of the communication line 220 from the second state back to the first state. Fig.12 Not shown, but if the chip does not receive the confirmation signal within the specified time period Tds, the chip can resend the second signal to the module (eg, by causing the state of line 222 to transition from the second state to the first state again).

[0244] After stopping processing its discrete operations, at step 1216, the module determines whether its processing is complete. That is, the module determines whether all discrete operations forming the processing steps 306 to be performed by it have been completed. This determination can be performed by the MCU. When the module has performed all of its assigned processing steps required to implement the second function of the device, the processing can be completed. If the module determines that its processing is not completed, it switches to a low-power state and does not take additional action. Then, the method returns to step 1204, wherein the chip transmits a wait time extension request to the terminal.

[0245] If the module determines at step 1216 that its processing is complete, it sends a message to the chip indicating that its processing is complete (step 1218). The message may indicate the consequence or result of the processing performed by the module. For example, if the module performs each step of biometric authentication, the message may contain the result of the authentication (i.e., whether the device user is authenticated). For implementations in which image matching is performed by the chip, the message may contain data about the captured image that enables the chip to perform image matching, such as data representing the captured image or data representing features extracted from the captured image. The message may be sent over communication line 220. After sending the message, the module may enter a low power state.

[0246] exist Fig.12 In a variation of the method shown in , step 1216 follows immediately after step 1212, wherein step 1214 is performed only in response to a module determining that its processing is not complete.

[0247] At step 1220, the chip determines whether its own action is completed in response to receiving a message from the module that its processing is completed. The chip can, for example, determine whether the function requested by the terminal at step 1204 is completed. When the function requested by the terminal has been completed, the chip can determine that its action is completed. In other words, the chip determines whether an additional wait time extension request is required.

[0248] If both the chip and the module perform processing steps to complete the function requested by the terminal, then at step 1218, the message received from the module may instruct the chip to perform its processing steps to perform the requested function.

[0249] If the chip determines that its action is not completed, the method returns to step 1204, where the chip transmits a wait time extension request to the terminal. If the module has completed its processing, the chip can continue to perform its processing in the waiting time interval between sending consecutive wait time extension requests to the terminal.

[0250] If the chip determines at step 1220 that its action is complete, the method proceeds to step 1222, where the chip transmits a message to the terminal indicating the end of its action. The message may indicate that the function requested by the terminal has been completed. The message may additionally indicate the consequence of the function (e.g., whether the user of the device has been authenticated). After transmitting the message to the terminal, the chip may enter a low power state. When the chip determines that its action is complete, no additional wait time extension request may be sent.

[0251] A method for synchronizing the processing of discrete operations performed at a device module with scheduled contactless communications between a chip of the device and a terminal has been described herein. This synchronization enables discrete operations to be performed in time intervals between scheduled communications between the device and the terminal, and enables the module of the device to enter a low-power mode during a time period when the chip is communicating with the terminal. This synchronization enables the power harvested from the signal transmitted by the terminal to be shared between the chip and the module. In addition, power consumption can be reduced by causing the module to enter a low-power or inactive state during the communication period between the chip and the terminal, while also reducing interference at the terminal from operating the module during communication with the chip. The synchronization method also makes it feasible to cause the chip of the device to enter a low-power or inactive state during a time period when the module can operate independently of the chip, thereby further reducing total power consumption.

[0252] An example where the device is a smart card has been described herein. It should be understood that the term "card" does not imply any constraints on its size, shape, thickness or function. The card described herein may be, for example, a plastic card such as a bank card, an ID card, a passport, etc. It should also be understood that each example described herein can be implemented in a device that adopts a different form factor that is not a card, such as a key card, a dongle, or a security token (e.g., a USB token). Alternatively, the device described herein can be integrated into the following devices: a communication device such as a mobile phone or a smart phone; a wearable device, such as a bracelet, a watch, a glove / a pair of gloves, a pin (e.g., a brooch), a badge, or some other contactless wearable device. Reference has also been made to a terminal in this article. The terminal of any of the described examples can take any suitable form according to the implementation, such as a card reader such as a point of sale (POS) terminal, a cash register, an ATM machine, a computer, a smart phone, etc.

[0253] Some cards described herein are referred to as contactless cards. It should be understood that a contactless card as described herein refers to a card that can communicate with a reader via a contactless interface. However, each card described as a contactless card may also be able to communicate with a reader via direct physical contact. Therefore, the term "contactless" is not used herein to exclude the possibility of contact functionality.

[0254] In the examples given above, the term "electrical energy" may be understood to refer to any relevant characteristic of energy availability. Examples include available energy, voltage, current and power, or any combination thereof.

[0255] The applicant hereby discloses separately each individual feature described herein and any combination of two or more such features, to the extent that such feature or combination can be performed based on this specification in view of the common general knowledge of a person skilled in the art as a whole, regardless of whether such feature or combination of features solves any problem disclosed herein, and without limitation to the scope of the claims. The applicant indicates that various aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description, it will be apparent to a person skilled in the art that various modifications may be made within the scope of the present invention.

Claims

1. A device for contactless communication with a terminal, include: an antenna, wherein the antenna is used to communicate with the terminal; an embedded chip configured to communicate with the terminal according to a contactless transmission protocol, wherein, according to the contactless transmission protocol, a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response; and A module, the module is configured to execute a process formed by a plurality of discrete operations, the module is configured to: in response to completing a subset of one or more discrete operations within a waiting time interval set by the terminal, if the process is not completed, send a command of a first type to the embedded chip; The embedded chip is further configured to: in response to receiving the first type of command, transmit a request to the terminal to extend a waiting time for a response.

2. The device according to claim 1, in, The waiting time interval is a time period during which communications are to be sent from the embedded chip to the terminal to maintain a connection between the embedded chip and the terminal.

3. The device according to claim 2, in, The waiting time interval is a time period during which a response to the message or a waiting time extension request is to be transmitted from the embedded chip to the terminal to maintain the connection.

4. The device according to any one of claims 1 to 3, in, The waiting time interval is between the time when the message from the terminal is received and the specified initial waiting time, or is the interval between the time when a waiting time extension request is sent to the terminal and the extended waiting time resulting from the request.

5. The device according to any one of claims 1 to 3, in, The embedded chip is configured to, in response to receiving the command before the waiting time interval expires, initiate transmission of the request to the terminal before the waiting time interval expires.

6. The device according to any one of claims 1 to 3, in, The module is configured to: not limited to responding to a message sent from the terminal.

7. The device according to any one of claims 1 to 3, in, The module is also configured to enter a low power mode once it has sent the command to the embedded chip.

8. The device according to any one of claims 1 to 3, in, The embedded chip is also configured to enter a low power mode when it is not communicating with the terminal or the module or is not participating in the process performed by the module.

9. The device according to any one of claims 1 to 3, in, The embedded chip is configured to indicate to the module that a request for extending the waiting time has been sent to the terminal.

10. The device according to claim 9, in, The module is configured to enter a low power mode once it has sent the command to the embedded chip, and to exit the low power mode in response to the indication.

11. The device according to any one of claims 1 to 3, in, The module includes a controller unit configured to select a subset of one or more discrete operations to be performed based on the wait time interval.

12. The device according to claim 11, in, The embedded chip is configured to indicate to the module that a request for extending the waiting time has been sent to the terminal, and the controller unit is configured to, in response to an indication that the waiting time extension request has been sent to the terminal, select a subset of the one or more discrete operations to be performed within the waiting time interval generated by the request.

13. The device according to any one of claims 1 to 3, in, The module is further configured to determine whether the processing is complete in response to a subset of the one or more discrete operations being completed within the wait time interval.

14. The device according to claim 13, in, The module is further configured to send a second type of command to the embedded chip if it determines that the process is complete.

15. The device according to claim 14, in, The embedded chip is configured to: in response to receiving the second type of command, determine whether the action requested by the terminal is completed, and: In response to determining that the action is completed, transmitting an indication of the completion of the action to the terminal; and In response to determining that the action is not completed, a wait time extension request is transmitted to the terminal.

16. The device according to claim 15, in, The action requested by the terminal is identity authentication or identity registration.

17. The apparatus according to any one of claims 1 to 3, in, The module is a biometric sensor module.

18. The device according to claim 17, in, The modules are configured to perform processing as part of performing a biometric authentication process.

19. The device according to claim 17, in, The modules are configured to perform processing as part of performing a biometric enrollment process.

20. The apparatus according to claim 17, in, The biometric sensor module includes a biometric sensor and an ASIC for controlling the operation of the biometric sensor.

21. The device according to claim 20, in, A subset of the one or more discrete operations is enabling the ASIC.

22. The device according to claim 20, in, A subset of the one or more discrete operations is collecting at least a portion of a biometric parameter using the biometric sensor.

23. The device according to claim 20, in, A subset of the one or more discrete operations is performing parameter matching on at least a portion of the biometric parameters captured by the biometric sensor.

24. The apparatus according to any one of claims 1 to 3, in, The device is a proximity integrated circuit card (PICC) and the terminal is a proximity coupling device (PCD).

25. The apparatus according to any one of claims 1 to 3, in, The transmission protocol is specified by ISO14443, ISO1443 or EMVCo® standards.

26. A method for contactless communication between a device and a terminal, the device comprising an embedded chip, the embedded chip being configured to communicate with the terminal according to a contactless transmission protocol, in, According to the contactless transmission protocol, the message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response, the method comprising: At a module within the device, a process formed of a plurality of discrete operations is executed during a waiting time interval set by the terminal; In response to completing a subset of one or more discrete operations within the waiting time interval set by the terminal, sending a command of a first type from the module to the embedded chip if the processing is not completed; In response to receiving the first type of command, a request is transmitted from the embedded chip to the terminal to extend a waiting time for a response.

27. A device for contactless communication with a terminal, include: an antenna, wherein the antenna is used to communicate with the terminal; an embedded chip configured to communicate with the terminal according to a contactless transmission protocol, wherein, according to the contactless transmission protocol, a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip is configured to transmit a request to the terminal to extend the waiting time for the response; and a module configured to perform a process formed by a plurality of discrete operations; The embedded chip is configured to, for each waiting time extension request sent to the terminal: transmit a first signal to the module to indicate that the waiting time extension request has been sent to the terminal; and before the extended waiting time generated by the extension request, transmit a second signal to the module to indicate that another waiting time extension request is scheduled to be transmitted to the terminal; and The module is configured to: start processing a subset of one or more discrete operations in response to the first signal; and stop processing the subset of discrete operations in response to the second signal.

28. The device according to claim 27, in, The module is also configured to transition to a low power state in response to the second signal.

29. The device according to claim 28, in, The first signal causes the module to transition from the low-power state to an active state in which the module can process discrete operations.

30. The apparatus according to claim 29, in, The module is configured to: determine whether the process is completed in response to the second signal, and if the process is completed, send an indication of the completion of the process to the embedded chip.

31. The apparatus according to claim 30, in, The embedded chip is configured to: in response to receiving the indication of completion of the processing, determine whether the action requested by the terminal is completed, and: In response to determining that the action is completed, transmitting an indication of the completion of the action to the terminal; and In response to determining that the action is not completed, a wait time extension request is transmitted to the terminal.

32. The device according to claim 31, in, The action requested by the terminal is identity authentication or identity registration.

33. Apparatus according to any one of claims 27 to 32, in, The embedded chip is configured to transmit the second signal a specified period of time before transmitting the further wait time extension request to the terminal.

34. The apparatus according to claim 33, in, The module is configured to transition to a low power state within the specified time period starting from receipt of the second signal.

35. Apparatus according to any one of claims 27 to 32, in, The embedded chip is also configured to enter a low power mode when it is not communicating with the terminal or the module and is not participating in the process performed by the module.

36. Apparatus according to any one of claims 27 to 32, in, The device includes a communication link between the chip and the module, and the chip is configured to transmit the first signal by driving a state of the communication link from a first state to a second state.

37. The apparatus according to claim 36, in, The chip is configured to transmit the second signal by driving the state of the communication link from the second state back to the first state.

38. The apparatus according to claim 36, in, The communication link is I 2 C bus or Serial Peripheral Interface (SPI) bus.

39. Apparatus according to any one of claims 27 to 32, in, The module is further configured to transmit a third signal to the embedded chip to indicate receipt of the first signal.

40. The apparatus according to claim 39, in, The device includes a first communication link and a second communication link between the chip and the module, the chip is configured to transmit the first signal and the second signal through the first communication link, and the module is configured to transmit the third signal through the second communication link.

41. The apparatus according to claim 40, in, The module is further configured to transmit a fourth signal to the embedded chip to indicate receipt of the second signal.

42. The apparatus according to claim 41, in, The module is configured to transmit the fourth signal via the second communication link.

43. The apparatus according to claim 42, in, The module is configured to: transmit the third signal by driving the state of the second communication link from a first state to a second state; and transmit the fourth signal by driving the state of the communication link from the second state back to the first state.

44. The apparatus according to claim 39, in, The embedded chip is further configured to retransmit the first signal to the module if it does not receive the third signal from the module within a specified waiting time.

45. The apparatus according to claim 44, in, The embedded chip is configured to wait for a specified period of time before retransmitting the first signal after the specified waiting time expires.

46. ​​Apparatus according to any one of claims 27 to 32, in, The module is a biometric sensor module.

47. Apparatus according to any one of claims 27 to 32, in, The modules are configured to perform processing as part of performing a biometric authentication process.

48. Apparatus according to any one of claims 27 to 32, in, The modules are configured to perform processing as part of performing a biometric enrollment process.

49. The apparatus according to claim 46, in, The biometric sensor module includes a controller unit, a biometric sensor, and an ASIC for controlling the operation of the biometric sensor.

50. The apparatus according to claim 49, in, The embedded chip is configured to send the first signal and the second signal to the ASIC after the ASIC is started.

51. The apparatus according to claim 49, in, The controller unit is configured to activate the ASIC in response to receiving an activation signal from the embedded chip after a wait time extension request is transmitted to the terminal.

52. Apparatus according to any one of claims 27 to 32, in, The device is a proximity integrated circuit card (PICC) and the terminal is a proximity coupling device (PCD).

53. Apparatus according to any one of claims 27 to 32, in, The transmission protocol is specified by ISO14443, ISO1443 or EMVCo® standards.

54. A method for contactless communication between a device and a terminal, the device comprising a module and an embedded chip, the module being configured to perform a process formed by a plurality of discrete operations, the embedded chip being configured to communicate with the terminal according to a contactless transmission protocol, according to which a message sent by the terminal sets a specified initial waiting time for a response from the embedded chip for maintaining a connection with the terminal, and the embedded chip being configured to transmit a request to the terminal to extend the waiting time for the response, the method comprising, for each waiting time extension request sent to the terminal: transmitting a first signal from the chip to the module to indicate that a wait time extension request has been sent to the terminal; at the module, initiating processing of a subset of one or more discrete operations in response to the first signal; before the extended latency is generated due to the extension request, transmitting a second signal from the chip to the module to indicate that another latency extension request is scheduled for transmission to the terminal; At the module, processing of the subset of discrete operations is stopped in response to the second signal.

Images