Pulse Detection Priority Mode Selection Device
Through the mode selection device that prioritizes pulse detection, combined with the voltage and pulse detection module, the flexibility and reliability of functional mode selection under the limited resources of the main control chip are solved, and the resistance to voltage jitter and glitches is improved, reducing system resource occupation.
Patent Information
- Application Number
- CN202010602237.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-06-29
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2040-06-29
AI Technical Summary
With limited main control chip pins and computing resources, it is difficult for the prior art to achieve flexible and reliable chip function mode selection, especially the lack of resistance to voltage jitter and glitches, and it requires occupancy of system computing resources.
The pulse detection priority mode selection device is adopted, and the voltage detection module and the pulse detection module are combined with the timing module to flexibly select the functional mode to ensure the priority of the pulse detection mode. The pulse state is judged by the NAND gate and the trigger unit, and the delay module controls the output synchronization.
It realizes flexible selection of modes in different application environments, improves application flexibility and reliability, reduces the use of system computing resources, and enhances the resistance to voltage jitter and glitches.
Smart Images
Figure CN111856995B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of wireless communication technology, and in particular to a 1T2R radio frequency circuit and a radio frequency signal transmitting and receiving method. Background Art
[0002] In electronic products, the main control chip can control the chip through various methods, such as I2C and SPI. These control methods require multiple pins and have timing requirements. In some applications, the main control chip has limited control pins and computing resources, and it is desirable to use simple control methods, such as multiplexing the voltage of the enable pin or sending a pulse sequence to select the chip's functional mode. Summary of the Invention
[0003] The purpose of the present invention is to provide a mode selection device with pulse detection priority and a flexible function mode selection method.
[0004] In one embodiment of the present application, a pulse detection priority mode selection device is provided, comprising:
[0005] A voltage detection module and a pulse detection module, wherein the voltage detection module and the pulse detection module are respectively connected to an enable signal, multiple outputs of the pulse detection module are respectively connected to a pulse state detection module and a selection module, multiple outputs of the voltage detection module are respectively connected to the selection module, and an output end of the pulse state detection module is connected to the selection module;
[0006] a timing module, wherein an input end of the timing module is connected to the pulse detection module and a clock signal, and an output end of the timing module is connected to the pulse detection module and the voltage detection module, and is configured to control clock synchronization between the pulse detection module and the voltage detection module;
[0007] If the pulse state detection module detects a pulse signal, the selection module performs output according to the state bit of the pulse state detection module; if the pulse state detection module does not detect a pulse signal, the selection module performs output according to the voltage detection module.
[0008] In a preferred example, the voltage detection module includes multiple resistors, multiple comparators and multiple first trigger units, wherein:
[0009] The multiple resistors are connected in series between the enable signal and the ground terminal, the nodes between adjacent resistors are connected to the positive input terminal of one of the multiple comparators, the negative input terminal of each of the comparators is connected, the output terminal of each of the comparators is connected to the data input terminal of one of the multiple first trigger units, and the latch output terminal of each of the first trigger units is connected to the selection module.
[0010] In a preferred example, the resistance values of the multiple resistors are from 1 kΩ to 25 kΩ.
[0011] In a preferred example, the pulse detection module includes: a high-level duration detection unit, a low-level duration detection unit, a NOR gate, and multiple second trigger units, where
[0012] The enable signal is respectively connected to the high-level duration detection unit, the low-level duration detection unit, and the NOR gate. The output end of the NOR gate is connected to the clock input end of the first-stage second trigger unit. The data input ends of the second trigger units at the same stage are connected to the inverted latch output end and are connected to the clock input end of the next-stage second trigger unit. The reset ends of each second trigger unit are connected together and are connected to the output end of the low-level duration detection unit and the input end of the timing module.
[0013] In a preferred example, the pulse status detection module includes a NOR gate, and the NOR gate is used to determine whether the pulse status detection module receives a pulse signal.
[0014] In a preferred example, when the outputs of the multiple second trigger units of the pulse detection module are all low, the NOR gate determines that the pulse status detection module does not receive a pulse signal. When at least one of the outputs of the multiple second trigger units of the pulse detection module is high, the NOR gate determines that the pulse status detection module receives a pulse signal.
[0015] In a preferred example, it further includes: a delay module, which is respectively connected to the inverted clock signal and the timing module, and is configured to control the chip to delay receiving the output of the selection module.
[0016] In a preferred example, the delay module includes a third trigger unit. The clock signal is connected to the clock input end of the third trigger unit through an inverter. The data input end of the third trigger unit is connected to the power supply end. The reset end is connected to the output end of the timing module. The latch output end is connected to the chip to be controlled.
[0017] Compared with the prior art, the method of the present application has the following beneficial effects:
[0018] In the present application, voltage detection mode and pulse detection mode control signals can be received simultaneously, and different application environments can adopt different mode selection methods, which improves the flexibility and reliability of the application.
[0019] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are listed, the specification will become overly lengthy. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of this application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (all these technical solutions should be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed, and features C and D are equivalent technical means that play the same role and only one of them can be used technically and it is impossible to use both at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The non-limiting and non-exhaustive embodiments of this application are described with reference to the following drawings, in which the same reference numerals refer to the same parts in each view unless otherwise specified.
[0021] Figure 1 It is a schematic diagram of the voltage detection mode in an embodiment of the present invention.
[0022] Figure 2 It is a circuit schematic diagram of the voltage detection mode in an embodiment of the present invention.
[0023] Figure 3 It is a schematic diagram of the pulse detection mode in an embodiment of the present invention.
[0024] Figure 4 It is a circuit schematic diagram of the pulse detection mode in an embodiment of the present invention.
[0025] Figure 5 It is a schematic diagram of implementing voltage detection using multiple GPIO control ports in the voltage detection mode in an embodiment of the present invention.
[0026] Figure 6 It is a circuit diagram of the mode selection device with pulse detection priority in an embodiment of the present invention.
[0027] Figure 7 It is a schematic diagram of selecting the working state according to different conditions in an embodiment of the present invention.
[0028] Figure 8 It is a timing control diagram of the pulse detection priority in an embodiment of the present invention. EMBODIMENTS
[0029] In the following description, many technical details are presented to help readers better understand this application. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the claims of this application can still be implemented.
[0030] In traditional solutions, voltage detection mode and pulse detection mode are usually adopted. Among them, for the voltage detection mode as Figure 1 shown, the circuit is as Figure 2 shown. The main control chip sends different voltages to the chip to be controlled, and the chip to be controlled judges the voltage values. Different voltage values correspond to different working modes.
[0031] For the pulse sequence detection mode as Figure 3 shown, the circuit is as Figure 4 shown. The main control chip sends different pulse sequences to the chip to be controlled, and the chip detects the number of pulses. Different pulse numbers correspond to different working modes.
[0032] The advantages of the pulse detection mode are simple control, insensitive to voltage, and strong anti-voltage jitter ability. The disadvantages are weak anti-glitch ability and the need to occupy system computing resources (counting and masking interrupts, etc. during the pulse sending period).
[0033] The advantages of the voltage detection mode are strong anti-glitch ability (the glitch signal can be removed by setting a longer detection time or adding resistor-capacitor filtering), and it does not occupy system computing resources. The disadvantages are sensitive to voltage (if the output voltage of the main control chip is lower than the mode voltage, some working modes cannot be selected), weak anti-voltage jitter ability. If the voltage jitters just during the voltage detection period, it may enter the wrong working mode, complex control, and the need for multiple GPIO control ports (if the main control chip cannot send out the required various voltage values, an external resistor network needs to be built, and the required voltage values are obtained through the cooperation of multiple GPIO control ports. As Figure 5 shown, through the cooperation of two GPIO ports, three-mode voltages can be generated. If more voltages need to be generated, more GPIO ports are required).
[0034] Therefore, the inventors of this application have proposed a new mode selection device that can flexibly adopt different detection modes. To make the purpose, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be further described in detail below with reference to the accompanying drawings.
[0035] In one embodiment of this application, a mode selection device with pulse detection priority is disclosed. Figure 6The schematic diagram of the mode selection device is shown. The device includes: a voltage detection module 10, a pulse detection module 20, a timing module 30, a pulse state detection module 50, and a selection module 60.
[0036] The voltage detection module 10 and the pulse detection module 20 are respectively connected to an enable signal, and multiple outputs PDC of the pulse detection module 20 <n:1>Each is connected to the pulse state detection module 50 and the selection module 60, and multiple outputs VDC of the voltage detection module 10 <n:1>Each is connected to the selection module 60 respectively, and the output ends of the pulse state detection module 50 are connected to the selection module 60 through an OR logic gate 80 respectively;
[0037] The input end of the timing module 30 is connected to the pulse detection module 20 and the clock signal CLK1, and the output end is connected to the pulse detection module 20 and the voltage detection module 10, and it is configured to control the clock synchronization of the pulse detection module 20 and the voltage detection module 10;
[0038] Wherein, if the pulse state detection module 50 detects a pulse signal, the selection module 60 outputs according to the status bit of the pulse state detection module 50. If the pulse state detection module 50 does not detect a pulse signal, the selection module 60 outputs according to the voltage detection module 10.
[0039] In one embodiment, the voltage detection module 10 includes a plurality of resistors 11, a plurality of comparators 12 and a plurality of first trigger units 13, wherein,
[0040] The plurality of resistors 11 are sequentially connected in series between the enable signal and the ground terminal, the node between adjacent resistors 11 is connected to the positive input terminal of one of the plurality of comparators 12, the negative input terminals of each comparator 12 are connected together, the output terminal of each comparator 12 is connected to the data input terminal of one of the plurality of first trigger units 13, and the latch output terminal of each first trigger unit 13 is connected to the selection module 60.
[0041] In one embodiment, the resistance values of the plurality of resistors 11 are from 1 kΩ to 25 kΩ, for example, 5 kΩ, 10 kΩ, 15 kΩ, 20 kΩ, etc. Those skilled in the art should understand that the above specific values are only examples and do not constitute a limitation on the scope of the application. In one embodiment of the present application, the resistance values of the plurality of resistors 11 can be the same. In other embodiments of the present application, the resistance values of the plurality of resistors 11 can be different.
[0042] In one embodiment, the pulse detection module 20 includes: a high-level duration detection unit 21, a low-level duration detection unit 22, a NOR gate 23 and a plurality of second trigger units 24, wherein,
[0043] The enable signal is respectively connected to the high-level duration detection unit 21, the low-level duration detection unit 22, and the NOR gate 23. The output end of the NOR gate 23 is connected to the clock input end of the first-stage second trigger unit 24. The data input ends of the second trigger units 24 at the same level are connected to the inverted latch output end and are connected to the clock input end of the next-stage second trigger unit 24. The reset ends of each second trigger unit 24 are connected together and are connected to the output end of the low-level duration detection unit 22 and the input end of the timing module 30.
[0044] In an embodiment, the pulse state detection module 50 includes a NOR gate, and the NOR gate is used to determine whether the pulse state detection module 50 receives a pulse signal. In an embodiment, when the outputs of the multiple second trigger units 24 of the pulse detection module 20 are all low, the NOR gate determines that the pulse state detection module 50 does not receive a pulse signal. When at least one of the outputs of the multiple second trigger units 24 of the pulse detection module 20 is high, the NOR gate determines that the pulse state detection module 50 receives a pulse signal.
[0045] In an embodiment, it further includes: a delay module 70, the delay module 70 is respectively connected to the inverted clock signal CLK1 and the timing module 30, and is configured to control the chip to delay receiving the output of the selection module 60.
[0046] In an embodiment, the delay module 70 includes a third trigger unit. The clock signal CLK1 is connected to the clock input end of the third trigger unit through an inverter. The data input end of the third trigger unit is connected to the power supply end, the reset end is connected to the output end of the timing module, and the latch output end is connected to the chip to be controlled.
[0047] In an embodiment, the preset range is less than or equal to 3V.
[0048] After the enable signal is sent, both the pulse detection module 20 and the voltage detection module 10 start to collect the state of the enable signal. It is necessary to determine which detection module's state the chip finally adopts, and priorities need to be set for the two detection methods. In this embodiment, the priority of the pulse detection mode is higher. Detection is performed through the pulse state detection module 50. When the enable signal is input by a pulse, the output PDC of the pulse detection module 20 <n:1>is in a non - all - 0 state. An OR logic judgment is performed on these signals. As long as one of the signals is 1, it indicates that the enable signal is input by a pulse. In the selection module MUX2 - 1, the state bit of the final mode state is selected as the pulse detection mode. If the enable signal has no pulse input, the output PDN of the pulse detection module 20 <n:0>Is all 0. In the selection module MUX2-1, the state bit that selects the final mode state as the voltage detection mode. Figure 7 Shows a schematic diagram of selecting the working state according to different conditions.
[0049] The time for the pulse detection module 20 and the voltage detection module 10 to complete state acquisition is different. The pulse detection module 20 has its own timing sequence. When the pulse reception is completed and the high-level duration detection is over, the pulse state acquisition is completed. The voltage detection module 10 needs to wait for the enable signal to be stable for a certain time before completing state acquisition. When the two detection modes coexist, it is necessary to ensure that the states of both detection modules 10 and 20 are acquired before sending out the final state signal. It is synchronized through a timing module 30, as Figure 6 shown. After the enable signal becomes valid, the timing module 30 starts timing. An appropriate timing time needs to be set. After both pulse detection and voltage detection are completed and the timing ends, the input signal of the pulse detection is shielded and no longer accepts the enable pulse signal; at the same time, the state bit of the voltage detection is locked in the register. Since the state bit output by MUX2-1 will change at this time, an additional delay module is added. Wait for MD <n:1>After stabilization, send out the START signal to make the chip start working. In this embodiment, the working timing diagram is as Figure 8 shown. CLK1 is the timing clock signal. When the timing ends, send out the CNT_OK signal to lock the status bit MD at this time <n:1>, after a delay of one falling edge, the START signal is sent to make the chip start working and receive the status bit MD <n:1>.
[0050] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising said element. In the application documents of this patent, if it is mentioned that an act is performed according to a certain element, it means that the act is performed at least according to that element, including two cases: performing the act only according to that element and performing the act according to that element and other elements. Expressions such as multiple, many times, and various include 2, 2 times, 2 kinds, as well as more than 2, more than 2 times, and more than 2 kinds.
[0051] All documents mentioned in this specification are considered to be integrally included in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not used to limit the protection scope of this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the protection scope of one or more embodiments of this specification.
[0052] In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims
1. A pulse detection priority mode selection device, characterized in that: include: A voltage detection module and a pulse detection module, wherein the voltage detection module and the pulse detection module are respectively connected to an enable signal, multiple outputs of the pulse detection module are respectively connected to a pulse state detection module and a selection module, multiple outputs of the voltage detection module are respectively connected to the selection module, and an output end of the pulse state detection module is connected to the selection module; a timing module, wherein the input end of the timing module is connected to the pulse detection module and the clock signal, and the output end is connected to the pulse detection module and the voltage detection module, and is configured to control the clock synchronization of the pulse detection module and the voltage detection module; wherein, if the pulse state detection module detects a pulse signal, the selection module outputs according to the state bit of the pulse state detection module; if the pulse state detection module does not detect a pulse signal, the selection module outputs according to the voltage detection module; The voltage detection module includes a plurality of resistors, a plurality of comparators and a plurality of first trigger units.
2. The pulse detection priority mode selection device according to claim 1, wherein: The resistance of the plurality of resistors ranges from 1 kΩ to 25 kΩ.
3. The pulse detection priority mode selection device according to claim 1, wherein: The pulse detection module includes: a high-level duration detection unit, a low-level duration detection unit, an NOR gate, and multiple second trigger units, wherein the enable signal is respectively connected to the high-level duration detection unit, the low-level duration detection unit and the NOR gate, the output end of the NOR gate is connected to the clock input end of the second trigger unit of the first stage, the data input end of the second trigger unit of the same stage is connected to the inverted latch output end and connected to the clock input end of the second trigger unit of the next stage, and the reset end of each second trigger unit is connected and connected to the output end of the low-level duration detection unit and the input end of the timing module.
4. The pulse detection priority mode selection device according to claim 3, wherein: The pulse state detection module includes a NOR gate, and the NOR gate is used to determine whether the pulse state detection module receives a pulse signal.
5. The pulse detection priority mode selection device according to claim 4, characterized in that: When the outputs of the multiple second trigger units of the pulse detection module are all low levels, the NOR gate determines that the pulse state detection module has not received a pulse signal; when the outputs of the multiple second trigger units of the pulse detection module are at least one high level, the NOR gate determines that the pulse state detection module has received a pulse signal.
6. The pulse detection priority mode selection device according to claim 1, wherein: Also includes: A delay module is connected to the inverted clock signal and the timing module respectively, and is configured to control the chip to delay receiving the output of the selection module.
7. The pulse detection priority mode selection device according to claim 6, characterized in that: The delay module includes a third trigger unit, the clock signal is connected to the clock input end of the third trigger unit through an inverter, the data input end of the third trigger unit is connected to the power supply end, the reset end is connected to the output end of the timing module, and the latch output end is connected to the chip to be controlled.