Centralized power outage management system for data storage devices

Abstract

The present application discloses a centralized power failure management system for data storage devices. The power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to provide temporary power from the at least one energy storage device to multiple data storage devices in the event of a system power failure. The power controller is further configured to receive a power failure indication signal associated with any single one of the multiple data storage devices, and responsively enable power failure protection for the data storage device.

Description

Summary of the invention

[0001] In one embodiment, a power management circuit is provided. The power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to provide temporary power from the at least one energy storage device to multiple data storage devices in the event of a system power failure. The power controller is further configured to receive a power failure indication signal associated with any single one of the multiple data storage devices, and responsively enable power failure protection for the data storage device.

[0002] In another embodiment, a method is provided. The method includes detecting a system power failure event and responsively enabling temporary power supply from at least one energy storage device to at least one of a plurality of data storage devices. The method also includes receiving a power failure indication signal associated with any single one of the plurality of data storage devices, and responsively enabling power failure protection for the data storage device.

[0003] In yet another embodiment, a system is provided. The system includes a plurality of data storage devices, each of which has a main memory and a cache memory. The system also includes a power management circuit coupled to each of the plurality of data storage devices. The power management circuit is configured to detect a system power failure event that results in a reduction in power to the plurality of data storage devices, and responsively provides temporary power to the plurality of data storage devices. The temporary power enables the plurality of data storage devices to dump and clear volatile data from each of the plurality of cache memories to each of the plurality of main memories. The power management circuit is further configured to receive a power failure indication signal associated with any single one of the plurality of data storage devices, and responsively enable power failure protection for the data storage device.

[0004] The present disclosure is not intended to describe every disclosed embodiment or every implementation of a centralized power failure management system for data storage devices. Numerous other novel advantages, features, and relationships will become apparent as this detailed description proceeds. The following drawings and detailed description more particularly illustrate illustrative embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a block diagram of a data storage system including a power management circuit according to one embodiment.

[0006] Figure 1B is a schematic diagram of a data storage device mounted in a carrier according to one embodiment.

[0007] Figure 2is a diagram illustrating charging and discharging of a capacitor and a rechargeable battery employed in a power backup unit according to one embodiment.

[0008] Figures 3A-3D is a flow chart of a method embodiment. DETAILED DESCRIPTION

[0009] The embodiments described below relate to a centralized power outage management system for a data storage device (DSD).

[0010] DSDs are typically included in systems with one or more host computers. Examples of DSDs include hard disk drives (HDDs), which are electromechanical devices containing spinning platters and movable read / write heads; solid-state drives (SSDs), which use memory chips and contain no moving parts; hybrid drives, which combine features of HDDs and SSDs in a single unit; and NVDIMMs, which are similar to SSDs but sit on the main memory bus of a computer's CPU.

[0011] The DSD may include non-volatile main memory, volatile cache memory, and control circuitry (e.g., data storage management circuitry). Additionally, current DSDs may include circuitry that detects a power outage in the DSD and responsively performs operations to prevent any loss of volatile data that may be present in the volatile cache memory. The operations may include providing temporary power from within the DSD to enable flushing of the cache memory.

[0012] HDDs can use the back EMF generated when the disk spins down to provide temporary power for volatile cache flushing during power outages. Hybrid drives can perform data protection during power outages in a similar manner to HDDs.

[0013] SSDs can use high-speed volatile memory (such as SDRAM) as a cache. To help ensure that volatile data is not corrupted and / or lost when power is suddenly lost, SDRAM and other SSD circuits are usually temporarily powered by on-board capacitors when power is lost. These on-board capacitors are expensive and take up space within the SSD.

[0014] For a system (such as a storage enclosure, storage array, storage server, data center, etc.) including multiple DSDs (e.g., SSDs), embodiments of the present invention provide a system-level power-off management circuit that eliminates the need for a drive-level power-off management circuit (e.g., on-board capacitor) within each individual DSD (e.g., SSD) of the multiple DSDs (e.g., multiple SSDs). Figure 1A System level power outage management according to one embodiment is described.

[0015] It should be noted that the same or similar elements use the same reference numerals in different drawings. It should be understood that the terms used herein are only for the purpose of describing a particular embodiment, and the term is not intended to be limited. Unless otherwise indicated, the sequence number (e.g., first, second, third, etc.) is used to distinguish or identify different elements or steps in a group of elements or steps, and does not provide sequence or numerical restrictions for the elements or steps of its embodiments. For example, "first", "second" and "third" elements or steps do not have to appear in this order, and its embodiments do not have to be limited to three elements or steps. It should also be understood that, unless otherwise indicated, any label, such as "left", "right", "front", "back", "top", "bottom", "forward", "opposite", "clockwise", "counterclockwise", "up", "down", or other similar terms, such as "above", "below", "after", "before", "vertical", "horizontal", "proximal end", "distal end", "between", etc., is used for convenience and does not mean, for example, any specific fixed position, orientation or direction. On the contrary, such labels are used to reflect, for example, relative position, orientation or direction. It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0016] FIG. 1 is a block diagram of a data storage system 100 including a power management circuit according to one embodiment. The system 100 includes a host 102, a plurality of DSDs 104A-104N, and a power management circuit 106. In an embodiment where the system 100 is part of a data center, by way of example only and not limitation, the host 102 may be a host central processing unit (CPU), a host bus adapter (HBA) CPU, an input / output controller (IOC) CPU, an input / output module (IOM) CPU, an expansion circuit controller having a topology such as a serially connected small computer system interface (SCSI / SAS / SATA / Ethernet, etc.), a switch controller having a topology such as a peripheral component interconnect (PCIe), a system enclosure processor (SEP) controller, a universal enclosure management controller, or a combination thereof. The DSDs 104A-104N may include SSDs, HDDs, hybrid drives, non-volatile dual in-line modules (NVDIMMs), etc. In one embodiment, each of DSDs 104A-104N may include non-volatile main memory 108, volatile cache memory 110, and DSD control circuitry 112 that performs data storage management.

[0017] The power management circuit 106 includes a power controller 114, a power fault detection circuit 116, an energy storage and discharge management (ESPRM) circuit 118, a power backup unit 120, a direct current (DC)-DC converter (e.g., a buck-boost converter) 122, a switch (e.g., a set of solid-state switches) 124, a power fault instruction processing module (PFIHM) 126, and an interrupt control circuit 128.

[0018] The power management circuit 106 further includes a single connector and / or bus connections (e.g., each bus connection has multiple single connectors) that provide coupling for power and / or signal transmission between different elements of the power management circuit 106. An external power source at a first voltage level (V1) is coupled to the ESPRM circuit 118. The ESPRM circuit 118 is also coupled to a power backup unit 120. The power backup unit 120 may include any suitable number and type(s) of energy storage devices. In one embodiment, the power backup unit 120 includes at least one capacitor (e.g., a supercapacitor or other suitable type of capacitor) and at least one battery (e.g., a lithium-ion battery) that outputs a backup voltage to the ESPRM circuit 118. A first output of the ESPRM circuit 118 is coupled to a power failure detection circuit 116, which provides a power failure indication signal to the power controller 114 when a power failure at the output of the ESPRM circuit 118 is detected. A second output of the ESPRM circuit 118 is coupled to an input of a DC-DC converter 122, which provides a second voltage level (V2) as an output. The output of the DC-DC converter 122 is coupled to a switch 124 and a power controller 114. The power controller 114 is coupled to the switch 124 via a power switch bus 130, and is configured to control the power provided to a corresponding one of the DSDs 104A-104N by sending a switch control signal via the power switch bus 130. Power connection lines 132A-132N couple different switches 124 to connectors A of corresponding switches of the DSDs 104A-104N. As described above, in one embodiment, the switch 124 may be a solid-state switch. In such an embodiment, the switch 124 may be controlled from the power controller 114 by employing, for example, a bit mask of N-bit data (where N is equal to the number of DSDs). Different individual bits of the N bits may be set to on (e.g., "1"), off (e.g., "0"), or inverted from on to off (or from off to on) in a single bitwise operation. In some such embodiments, the bit mask value may be sent by the host 102 to the power controller 114, which may control the switch 124 using the bit mask value of the host communication. Communication between the host 102 and the power controller 114 may be via a communication bus 115. In one embodiment, the communication bus 115 may be a bidirectional serial bus (e.g., a universal asynchronous receiver-transmitter (UART) bus, a serial peripheral interface (SPI) bus, an inter-integrated circuit (I2C) bus, etc.). In some embodiments, the power controller 114 may communicate DSD 104A-104N status information (e.g., active / inactive status information) to the host 102 via the bus 115.

[0019] In some embodiments, the power controller 114 is also configured to provide instructions to external devices (e.g., DSDs 104A-104N) when a power outage occurs. The instructions may be for the external device (e.g., DSDs 104A-104N) to perform a cache flush operation, for the external device to enter a low power mode (e.g., a self-refresh mode that significantly reduces the power utilization of the DSDs 104A-104N while keeping the volatile content intact), etc. The power controller 114 sends instructions such as cache flush, low power mode, etc. to the downstream DSDs 104A-104N via the communication channel 125. The PFIHM 126 appropriately routes the instructions on a set of communication channels (e.g., power failure instruction buses) 134A-134N by identifying the destination DSD field in the (multiple) instructions. In one embodiment, each of the power failure instruction buses 134A-134N may include at least one connection line. In one example, two connection lines are used. The first of these connection lines may be used to communicate a cache dump flush instruction to the corresponding DSD 104A-104N, and the second connection line may be used to communicate a low power mode instruction. The communication may involve setting the instruction bit to "0" or "1". For example, when there is no power outage in the system 100, both the cache dump flush instruction bit and the low power mode instruction bit may be set to "0", thereby indicating to the DSD 104A-104N that normal operation may continue. When there is a power outage in the system 100, at least some of the cache dump flush bits and / or at least some of the low power mode instruction bits may be set to "1".

[0020] In response to a single one of the DSDs 104A-104N sensing that the cache flush instruction bit is set to "1", the DSD flushes its volatile cache memory 110. Similarly, in response to a single one of the DSDs 104A-104N sensing that the low power mode instruction bit is set to "1", the DSD enters a low power mode (e.g., a self-refresh mode). It should be noted that, depending on the capacity of the power backup unit 120, different embodiments may provide backup power to all of the DSDs 104A-104N (referred to herein as full backup), or provide backup power to a subset (e.g., less than all) of the DSDs 104A-104N (referred to herein as partial backup). In some embodiments, the power controller 114 may determine that a subset of the DSDs 104A-104N has been inactive for at least a predetermined period of time and may therefore be shut down without backup when the system 100 loses power. When the system 100 is powered off, the individual switches of the switches 124 corresponding to the DSDs determined to be inactive may be turned off using, for example, the bit masking techniques discussed above. When an individual one of the DSDs 104A-104N is turned off, the value of any instruction bit (e.g., "0" or "1") of that DSD is irrelevant.

[0021] The DSDs 104A-104N and / or the drive carriers holding the DSDs 104A-104N in the data center cabinets may also be connected to the DSDs 104A-104N via appropriate connectors (eg, Figure 1A The power management circuit 106 is connected to the connecting lines 136A-136N to send communication signals (e.g., interrupt signals) to the power management circuit 106. In the system 100, the connecting lines 136A-136N are coupled to the interrupt control circuit 128, which can combine interrupts from different DSDs in the DSDs 104A-104N and send the signal to the power controller 114 via the interrupt communication bus 138. Figure 1B Details regarding the sending of interrupt signals from the carriers of the DSDs 104A-104N to the power management circuit 106 and the responsive actions taken by the power management circuit 106 are described.

[0022] Figure 1B 1 is a schematic diagram of a DSD 104 installed in a carrier 140 according to one embodiment. In one embodiment, the carrier 140 may be in a data center cabinet (not shown) including multiple DSDs and carriers for each DSD. The DSD 104 of the system 100 may be hot-swapped / unswapped by opening / closing the carrier 140 and installing / removing the DSD 104. Figure 1BIn an embodiment of the present invention, the DSD 104 may be removed from the carrier 140 by pressing a button 142 of the carrier 140 and then manually detaching the DSD 104. The button 142 is coupled to a plunger / switch 144, which contacts a switch debouncer 146 when the button 142 is pressed. When the switch 144 contacts the debouncer 146, an interrupt for drive detachment is sent to the interrupt control circuit 128 via the communication line 136. The interrupt control circuit 128 responsively forwards an appropriate signal to the power supply controller 114. Upon receiving the signal, the power supply controller 114 sends a cache flush instruction to the DSD 104 (e.g., sets a cache flush instruction bit to "1"). In response to receiving the cache flush instruction, the control circuit 112 of the DSD 104 flushes the volatile cache memory 110. It should be noted that the inherent delay (e.g., about 1-2 seconds) between pressing the button 142 and mechanically separating the DSD 104 helps ensure that the DSD 104 is powered on for at least about 20 milliseconds after receiving the cache flush signal, thereby allowing the cache flush operation to be completed. It should be noted that the plunger switch 144 is merely an example, and any other suitable switch arrangement that is activated just prior to mechanical separation of the DSD 104 may be employed.

[0023] Figure 2 2 is a diagram 200 illustrating the charging and discharging of a capacitor and a rechargeable battery employed in the power backup unit 120 according to one embodiment. In the diagram 200, the vertical axis 202 represents voltage and the horizontal axis 204 represents time. In a particular embodiment, the power backup unit 120 is configured so that the capacitor is used as an initial backup power source and the capacitor voltage drops to or below a threshold backup voltage level (e.g., a minimum voltage level that enables the power controller 114 and other components of the power management circuit 106 to operate). Figure 2 In FIG. 206 , graph 206 represents a capacitor charge / discharge cycle, and graph 208 represents a battery charge / discharge cycle. In FIG. 206 , point 210 is the “switch” point at which the battery takes over the function of providing backup power from the capacitor.

[0024] As shown herein, full power backup or partial power backup may be provided, depending on the capacity of the power backup unit 120. Examples of different power backup method embodiments for multiple (N) DSDs are provided below.

[0025] ■For N DSDs, let B be the number of DSDs that are budgeted to have backup.

[0026] ■Therefore there is (NB) DSD that has not been budgeted for backup.

[0027] • For full backup, B=N and therefore (NB)=0.

[0028] The combination of B DSDs and (NB) DSDs can be handled in a variety of ways:

[0029] ●Method Example 1: Power B DSDs, power off (NB) DSDs, and wait for B DSDs to be dumped and cleared (hereinafter combined with Figure 3A illustrate).

[0030] ●Method Example 2: According to the host defined policy and / or as long as the power supply lasts, power B DSDs, power (NB) DSDs with low power, wait for B DSDs to be dumped and cleared, power off B DSDs, power each of (NB) DSDs one by one (or in pairs, triplets, etc.) to allow (multiple) DSDs to be dumped and cleared (hereinafter combined with Figure 3B describe).

[0031] ●Method Example 3: According to the host defined policy and / or as long as the power supply lasts, all DSDs are powered on with low power, first B and then (NB) DSDs are powered on one by one (or in pairs, triplets, etc.), so that each DSD is dumped and cleared (hereinafter combined with Figure 3C describe).

[0032] Host-defined policies can combine any / all of the following scenarios:

[0033] 1. The host 102 periodically proposes bit mask values ​​to the power controller 114 to turn on / off different combinations of switches 124 (depending on the DSD activity).

[0034] 2. The host 102 predefines the priority of DSD power backup.

[0035] o For example, booting a DSD with a high power backup priority, backing up a redundant array of independent disks (RAID) DSD with a low power backup priority, and so on.

[0036] 3. Figure 3B and 3C The queue in (described further below) may have sub-queue(s) for B DSDs and / or sub-queue(s) for (NB) DSDs.

[0037] Figure 3A 300 (method embodiment 1 above). Method 300 starts from a power good state at 302, where all DSDs are powered on. Figure 1AAs described above, for example, all N data bits of the bit mask for controlling switch 124 may be set to "1" by power controller 114 to power on all N DSDs. In addition, in a power good state where there is no power outage in system 100, for example, both the cache flush instruction bit and the low power mode instruction bit may be set to "0" to indicate to DSDs 104A-104N that normal operation may continue. At 304, for example, the power controller 114 may power on all N DSDs by setting all N data bits of the bit mask for controlling switch 124 to "1". In addition, in a power good state where there is no power outage in system 100, for example, both the cache flush instruction bit and the low power mode instruction bit may be set to "0", thereby indicating to DSDs 104A-104N that normal operation may continue. Figure 1A The power failure detection circuit 116 of the embodiment of the present invention performs system power failure detection. If no power failure is detected, control returns to 302. If a power failure is detected at 304, a cache flush instruction is communicated to the DSDs at 306 by, for example, the power controller 114 setting the cache flush instruction bit to "1". At 308, the (NB) DSDs are powered off by, for example, the power controller 114 setting NB data bits of the bit mask for controlling the switch 124 to "0". At 310, the system waits a predetermined time for the cache flush operation in the B DSDs to complete. The method ends at the end of the predetermined waiting time.

[0038] Figure 3B is a flow chart of the second method 320 (method embodiment 2 above). Figure 3AAs described in method 300 of , method 320 starts from a power good state at 322, where all DSDs are powered on. At 324, a system power failure detection is performed. If no power failure is detected, control returns to 322. If a power failure is detected at 324, the (NB) DSDs are instructed to enter a low power mode at 326 by, for example, the power controller 114 setting NB low power mode instruction bits to "1". At 328, a cache dump flush instruction is communicated to the B DSDs. At 330, the system waits for a predetermined time for the cache dump flush operation in the B DSDs to complete. At 332, the B DSDs are powered off by, for example, the power controller 114 setting B data bits of the bit mask for controlling the switch 124 to "0". Then, according to the host defined policy and / or during the power-on duration, the remaining NB DSDs are placed in a queue and powered on in queue order, and dump flushing is allowed (at 334-344). Specifically, at 334, the next DSD at position "m" in the queue from the NB queue is dequeued. At 336, DSD m is taken out of low power mode, for example, by the power controller 114 setting the DSD m low power mode instruction bit to "0". At 338, the system waits for a predetermined time for the cache flush operation in DSD m to complete. At 340, DSD m is powered off by, for example, the power controller 114 setting the DSD m data bit of the bit mask for controlling the DSD m switch 124 to "0". At 342, DSD m is deleted from the queue. At 344, it is determined whether DSD m is the last DSD in the queue. If DSD m is not the last DSD in the queue, control returns to 334. If DSD m is the last DSD in the queue, the process ends. When discussing powering on a single DSD m, it should be understood that the DSDs of the (NB) DSDs may be powered on and flushed in groups (such as pairs, triplets, etc.) without departing from the scope of the present invention.

[0039] Figure 3C350 (method embodiment 3 above). Method 350 starts from a power good state at 352, where all DSDs are powered on. At 354, a system power failure detection is performed. If no power failure is detected, control returns to 352. If a power failure is detected at 354, all N DSDs are instructed to enter a low power mode at 356. Then, B DSDs, followed by (NB) DSDs, are powered on one by one, allowing each DSD to flush its respective cache (at 358-370). Specifically, at 358, the next DSD at position "m" in the queue from the B queue and then the NB queue is dequeued. At 360, DSD m will exit the low power mode. At 362, a cache flush instruction is communicated to DSD m. At 364, the system waits for a predetermined time for the cache flush operation in DSD m to complete. At 366, the DSD is powered off. At 368, DSD m is deleted from the queue. At 370, it is determined whether DSD m is the last DSD in the queue. If DSD m is not the last DSD in the queue, control returns to 360. If DSD m is the last DSD in the queue, the process ends. While discussing powering up a single DSD m, it should be understood that the DSDs of the N DSDs may be powered up and flushed in groups (such as pairs, triplets, etc.) without departing from the scope of the present invention.

[0040] Figure 3D 380 is a flow chart of a fourth method embodiment 380. The method 380 begins at 382 with a DSD attached or in a connected state. At 384, a DSD detachment detection is performed. In one embodiment, Figure 1A The power controller 114 of the power supply 114 performs DSD detach detection. The power controller 114 can actively or passively monitor the connection status of the DSD. The power controller 114 can detect that the DSD is not detached (indicated by the control return 382), or can determine that the DSD is detached based on information about the change in the connection status of the DSD from attached to detached. For example, when the power controller 114 performs active or passive monitoring, the DSD detach switch can be triggered at 386 (e.g., when pressed Figure 1B142 and the plunger / switch 144 attached to the button 142 makes contact with the switch debouncer 146). For example, this results in a signal being sent from the carrier 140 to the interrupt control circuit 128, which generates an interrupt at 388 and identifies the detached DSD as "n" at 390. The interrupt with DSD identifier n is sent to the power controller 114, which determines that DSD n is detached based on the received information. At 392, the cache dump clear instruction is communicated to DSD n by, for example, the power controller 114 setting the cache dump clear instruction bit of DSD n to "1". At 394, the system waits a predetermined time for the cache dump clear operation in DSD n to be completed. Figure 3D In the example, “Q”, “R” and “S” are the Figure 3A , Figure 3B and Figure 3C Thus, these connections between all of the above flowcharts include both system-triggered and DSD-triggered data enhancement methods. Although a single separated DSD is discussed, it should be understood that the DSDs may be separated in groups (such as pairs, triplets, etc.) without departing from the central concepts of the present invention.

[0041] The subject matter disclosed above is intended to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the present disclosure. For example, an embodiment may also include handling the mechanical disengagement of a DSD after a power failure event, in which case the system may preferentially include that particular DSD in any of the flowcharts (3A to 3D) for cache dump clearing. In addition, the above-mentioned different communication lines, buses, communication channels, etc. may be wired or wireless communication channels. Therefore, in order to obtain the maximum scope allowed by law, the scope of the present disclosure will be determined by the broadest interpretation permitted by the appended claims and their equivalents, and shall not be restricted or limited by the above detailed description.

[0042] Further examples

[0043] Example 1 is a power management circuit, comprising: at least one energy storage device; and a power controller coupled to the at least one energy storage device, the power controller being configured to: provide temporary power from the at least one energy storage device to a plurality of data storage devices in the event of a system power outage; and receive a power-off indication signal associated with any individual one of the plurality of data storage devices, and responsively enable power-off protection for the data storage device.

[0044] Example 2 is the power management circuit described in Example 1, wherein the at least one energy storage device includes at least one capacitor.

[0045] Example 3 is the power management circuit described in Example 2, wherein the at least one energy storage device further comprises at least one battery, and the at least one battery is used as a backup energy storage device for delivering the temporary power when the capacitor is in a basically discharged state.

[0046] Example 4 is the power management circuit described in Example 1, further comprising a power failure detection circuit, wherein the power failure detection circuit is configured to detect the system power failure event and responsively notify the power controller of the system power failure event.

[0047] Example 5 is the power management circuit described in Example 1, further comprising an interrupt control circuit configured to receive a power-off indication signal and responsively notify the power controller.

[0048] Example 6 is the power management circuit described in Example 1, wherein the power-off indication signal includes a device separation indication signal, and the device separation indication signal warns the power-off management circuit that the electrical connection of the data storage device is about to be disconnected.

[0049] Example 7 is the power management circuit described in Example 1, further comprising a set of switches controlled by a power controller to selectively provide the temporary power to different devices among the multiple data storage devices.

[0050] Example 8 is the power management circuit described in Example 1, further comprising a plurality of power failure command buses coupled to the power controller, wherein the plurality of power failure command buses are configured to transmit command signals from the power controller to the plurality of data storage devices.

[0051] Example 9 is the power management circuit described in Example 8, characterized in that the instruction signal includes a low power mode instruction signal and a cache dump clear instruction signal.

[0052] Example 10 is a method comprising: detecting a system power failure event and responsively providing temporary power from at least one energy storage device to at least one of a plurality of data storage devices; and receiving a power failure indication signal associated with any individual one of the plurality of data storage devices and responsively enabling power failure protection for the data storage device.

[0053] Example 11 is the method of Example 10, further comprising sending a cache flush instruction to the at least one of the plurality of data storage devices.

[0054] Example 12 is the method of Example 10, further comprising sending a low power mode instruction to the at least one of the plurality of data storage devices.

[0055] Example 13 is the method described in Example 10, further comprising: designating a first subset of the plurality of data storage devices as high priority data storage devices; and designating at least a second subset of the plurality of data storage devices as low priority data storage devices.

[0056] Example 14 is the method of Example 13, wherein causing temporary power to be provided from at least one energy storage device to at least one of a plurality of data storage devices includes causing the temporary power to be provided to the first subset of the data storage devices.

[0057] Example 15 is the method of Example 13, further comprising causing the temporary power source not to be provided to the second subset of the plurality of data storage devices.

[0058] Example 16 is a system comprising: a plurality of data storage devices, each data storage device having a main memory and a cache memory; and a power management circuit coupled to the plurality of data storage devices, the power management circuit being configured to: detect a system power failure event resulting in a reduction in power supplied to the plurality of data storage devices, and responsively provide temporary power to the plurality of data storage devices, the temporary power enabling the plurality of data storage devices to dump and clear volatile data from each of the plurality of cache memories to a corresponding each of the plurality of main memories; and receive a power failure indication signal associated with any individual one of the plurality of data storage devices, and responsively enable power failure protection for the data storage device.

[0059] Example 17 is the system of Example 16, further comprising a plurality of carriers for the plurality of data storage devices.

[0060] Example 18 is the system of Example 17, wherein each of the plurality of carriers includes a driver separation enable feature, the driver separation enable feature being configured to move between a first position and a second position, in which a switch is activated to send a power-off indication signal to the power management circuit.

[0061] Example 19 is the system described in Example 16, wherein the power management circuit further includes a primary energy storage device and a backup energy storage device.

[0062] Example 20 is the system described in Example 19, wherein the primary energy storage device includes a capacitor and the backup energy storage device includes a battery.

Claims

1. A power management circuit, comprising: at least one energy storage device; as well as a power controller coupled to the at least one energy storage device, the power controller being configured to: causing temporary power to be provided from the at least one energy storage device to the plurality of data storage devices in the event of a system power outage; as well as Receive a power-off indication signal associated with any individual one of the plurality of data storage devices and responsively enable power-off protection for the data storage device, wherein the temporary power supply enables the plurality of data storage devices to clear volatile data dumps from respective cache memories in the plurality of cache memories to respective memories in the plurality of main memories.

2. The power management circuit according to claim 1, characterized in that: The at least one energy storage device includes at least one capacitor.

3. The power management circuit according to claim 2, characterized in that: The at least one energy storage device further comprises at least one battery, the at least one battery being used as a backup energy storage device for delivering the temporary power supply when the capacitor is in a substantially discharged state. 4 . The power management circuit of claim 1 , further comprising a power failure detection circuit configured to detect the system power off event and responsively notify the power controller of the system power off event. 5 . The power management circuit of claim 1 , further comprising an interrupt control circuit configured to receive a power-off indication signal and responsively notify the power controller.

6. The power management circuit according to claim 1, wherein: The power-off indication signal includes a device detach indication signal, which warns the power-off management circuit that the electrical connection of the data storage device is about to be disconnected.

7. The power management circuit of claim 1, further comprising a set of switches controlled by a power controller to selectively provide the temporary power to different devices among the plurality of data storage devices.

8. The power management circuit of claim 1, further comprising a plurality of power failure command buses coupled to the power controller, the plurality of power failure command buses being configured to transmit command signals from the power controller to the plurality of data storage devices.

9. The power management circuit according to claim 8, characterized in that: The instruction signal includes a low power mode instruction signal and a cache flush instruction signal.

10. A method for power management, comprising: detecting a system power outage event and responsively causing temporary power to be provided from at least one energy storage device to at least one of a plurality of data storage devices, wherein the temporary power enables the plurality of data storage devices to flush volatile data from respective ones of a plurality of cache memories to respective ones of a plurality of main memories; as well as A power failure indication signal associated with any individual one of the plurality of data storage devices is received, and power failure protection is responsively enabled for the data storage device.

11. The method of claim 10, further comprising sending a cache flush instruction to the at least one of the plurality of data storage devices.

12. The method of claim 10, further comprising sending a low power mode command to the at least one of the plurality of data storage devices.

13. The method of claim 10, further comprising: designating a first subset of the plurality of data storage devices as high priority data storage devices; as well as At least a second subset of the plurality of data storage devices is designated as low priority data storage devices.

14. The method according to claim 13, characterized in that Causing temporary power to be provided from at least one energy storage device to at least one of a plurality of data storage devices includes causing the temporary power to be provided to the first subset of the data storage devices.

15. The method of claim 13, further comprising causing the temporary power source not to be provided to the second subset of the plurality of data storage devices.

16. A system for power management, comprising: a plurality of data storage devices, each data storage device having a main memory and a cache memory; as well as A power management circuit is coupled to the plurality of data storage devices, the power management circuit being configured to: detecting a system power outage event resulting in a reduction in power to the plurality of data storage devices and responsively providing temporary power to the plurality of data storage devices, the temporary power enabling the plurality of data storage devices to flush volatile data from respective ones of the plurality of cache memories to respective ones of the plurality of main memories; as well as A power failure indication signal associated with any individual one of the plurality of data storage devices is received, and power failure protection is responsively enabled for the data storage device.

17. The system of claim 16, further comprising a plurality of carriers for the plurality of data storage devices.

18. The system of claim 17, wherein: Each of the plurality of carriers includes a driver disconnect enable feature configured to move between a first position and a second position in which a switch is activated to send a power-off indication signal to the power management circuit.

19. The system of claim 16, wherein: The power management circuit further includes a main energy storage device and a backup energy storage device.

20. The system of claim 19, wherein: The main energy storage device includes a capacitor, and the backup energy storage device includes a battery.

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