Instruction Execution Method and Instruction Execution Device

By decoding macro instructions into multiple micro instructions and identifying atomic operation flags, the problem of processors extending large bit-width data instructions is solved, achieving more efficient instruction execution and reducing energy consumption.

CN111857826BActive Publication Date: 2025-07-25VIA ALLIANCE SEMICON CO LTD
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Patent Information

Application Number
CN202010721141.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-07-24
Publication Date
2025-07-25
Estimated Expiration
2041-03-14

AI Technical Summary

Technical Problem

Existing processors have difficulty effectively extending instructions that process large bit-width data, especially floating point and vector instructions, resulting in waste of processor resources and increased execution time.

Method used

Decode the macro instructions into multiple micro-instructions and identify atomic operation flags for these micro-instructions to ensure that they are executed adjacently in the micro-instruction storage space, and implement atomic operations of instructions through the instruction translator and rearrangement buffer to avoid uncertain intermediate states.

Benefits of technology

Reduces the execution time of macros, reduces power consumption, and ensures the correctness and efficiency of the processor when processing large bit-width data.

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Abstract

The present invention discloses an instruction execution method and an instruction execution device. The instruction execution method includes: translating a macro instruction into at least a first micro-instruction and a second micro-instruction, and identifying first binding information for the first micro-instruction and second binding information for the second micro-instruction; and simultaneously performing an exit operation of the first micro-instruction and the second micro-instruction according to the first binding information and the second binding information; wherein the first micro-instruction and the second micro-instruction are adjacent in a micro-instruction storage space.
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Citation Information

Patent Citations

  • Instruction execution method and instruction execution device

    CN111221576A