A transmitter circuit based on JESD204B protocol

Abstract

The present invention discloses a transmitting end circuit based on the JESD204B protocol, belonging to the technical field of high-speed data transmission, and includes a transport layer, a scrambling module and a data link layer. The transport layer includes a data combination module and a mapping unit to realize mapping from original sampled data to channel data; the scrambling module scrambles the data output by the transport layer; the data link layer includes a synchronization module, a control character insertion module and an encoding module, the synchronization module realizes the synchronization process of the protocol, the control character insertion module inserts control characters into the data stream according to the rules of the protocol, and the encoding module realizes 8B / 10B encoding.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed data transmission, and particularly to a transmitting-end circuit based on the JESD204B protocol. Background Art

[0002] The rapid development of 5G and Internet of Things technologies has brought about a huge amount of data exchange, making high-speed and high-precision data transmission particularly important. Most existing high-speed chips use LVDS interfaces, but chips with LVDS interfaces have many pins, complex application board wiring, and great difficulty in multi-chip synchronization. As a new transmission protocol, JESD204B has many advantages such as deterministic delay, high throughput rate, and few pin numbers, so it is widely used in high-speed AD / DA systems. Summary of the Invention

[0003] The purpose of the present invention is to provide a transmitting-end circuit based on the JESD204B protocol to solve the problems of many interfaces, complex wiring, and great difficulty in multi-chip synchronization of existing high-speed circuits.

[0004] To solve the above technical problems, the present invention provides a transmitting-end circuit based on the JESD204B protocol, including:

[0005] A transmission layer, including a data combination module and a mapping unit. The data combination module combines sample data according to the relationship of link configuration parameters N’, N, CS, and the mapping unit maps the data output by the data combination module to corresponding output channels according to the link configuration.

[0006] A scrambling module, which scrambles the data output by the transmission layer or bypasses and directly outputs it to the next stage.

[0007] A data link layer, including a synchronization module, a control character insertion module, and an encoding module. The synchronization module realizes the synchronization process of the protocol, the control character insertion module inserts control characters into the data stream according to the rules of the protocol, and the encoding module realizes 8B / 10B encoding.

[0008] Optionally, the data combination module supports N’ = 16 or 8, and completes the combination of sampled data, control bits, and end bits:

[0009] When the sampling data accuracy is 8 < N ≤ 16, configure N’ = 16, and 16-bit data fills the bit sampling data bits, control bits, and end bits in sequence.

[0010] When N ≤ 8, configure N’ = 8. At this time, the high 8 bits are all set to 0, and the low 8 bits fill the data bits, control bits, and end bits from high to low in sequence.

[0011] Optionally, the mapping unit includes a module smp2oct, a module SYSREF_detect, a module oct2lane and a module FC_LMFC_gen; wherein,

[0012] The module smp2oct maps the input converter sample data to 32 octets; the module SYSREF_detect is a reference clock detection module; the module oct2lane sends the generated 32 parallel octets to different channels according to link parameters F and L; the module FC_LMFC_gen generates frame clocks and local multi-frame clocks.

[0013] Optionally, the module smp2oct includes sub-modules smp_16prl and get_8b_from_16b; the data generated by the data combination module is mapped to 16 parallel channels in the sub-module smp_16prl, and if N'=16, the data is directly output from the sub-module smp_16prl to the next level; if N'=8, the data is further combined and output by the sub-module get_8b_from_16b.

[0014] Optionally, the synchronization module includes a submodule SYNC_detect and a submodule CGS_ILAS_gen; the submodule SYNC_detect continuously samples the SYNC synchronization request sent by the receiving end, and the submodule CGS_ILAS_gen implements control character insertion and ramp signal insertion in the data stream during the code group synchronization stage and the initial channel alignment sequence stage.

[0015] Optionally, the control character insertion module includes four delay modules and a control code detection module. The control code detection module identifies and replaces the control code in the data stream according to the content specified in the JESD204B protocol and gives an indication bit. The delay unit ensures that the input and output control signals and data streams are strictly synchronized.

[0016] The present invention provides a transmitting end circuit based on the JESD204B protocol, including a transport layer, a scrambling module and a data link layer. The transport layer realizes the mapping from the original sampled data to the channel data; the scrambling module scrambles the data output by the transport layer; the data link layer includes a synchronization module, a control character insertion module and an encoding module, the synchronization module realizes the synchronization process of the protocol, the control character insertion module inserts the control character into the data stream according to the rules of the protocol, and the encoding module realizes 8B / 10B encoding. The present invention can fully realize the link synchronization function of the transmitting end in the JESD204B protocol, fully realize the data sending function of the transmitting end in the JESD204B protocol, and refines the design structure of the transmitting end circuit in the JESD204B protocol, and the implementation is relatively simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of a transmitting end circuit based on the JESD204B protocol provided by the present invention;

[0018] Figure 2 It is a schematic diagram of the mapping relationship of data combination modules;

[0019] Figure 3 It is a schematic diagram of the structure of the mapping unit;

[0020] Figure 4 It is a structural diagram of the synchronization module;

[0021] Figure 5 It is a schematic diagram of the structure of the control character insertion module;

[0022] Figure 6 This is a schematic diagram of the link synchronization process of the transmitting circuit based on the JESD204B protocol in the configuration of M=4, S=1, F=4, L=2, N'=N=16, K=32. DETAILED DESCRIPTION

[0023] The following is a further detailed description of a transmitter circuit based on the JESD204B protocol proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] Embodiment 1

[0025] The present invention provides a transmitting end circuit based on the JESD204B protocol, such as Figure 1 As shown, it includes a transport layer, a scrambling module and a data link layer.

[0026] Please continue reading Figure 1, the transport layer realizes the mapping from the original sampled data to the channel data through a data combination module (combination) and a mapping unit (mapping): the data combination module combines the sample data according to the relationship of the link configuration parameters N’, N, and CS, and the mapping unit maps the data output by the data combination module to the corresponding output channels according to the link configuration; where N’ is the word length, N represents the resolution of the converter, and CS represents the control bit length. The scrambling module (scramble) realizes the scrambling function, and the scrambling function can be bypassed. The data link layer includes a synchronization module (synchronizer), a control character insertion module (alignment characters inserting), and an encoding module (encoder). The synchronization module realizes the synchronization process of the protocol, the control character insertion module inserts control characters into the data stream according to the rules of the protocol, and the encoding module realizes 8B / 10B encoding.

[0027] The mapping relationship of the data combination module is as Figure 2 shown, supporting N’ = 16 or 8, and completing the combination of sampled data, control bits, and end bits: when the sampling data accuracy is 8 < N ≤ 16, configure N’ = 16, and the 16-bit data fills the bit sampling data bits, control bits, and end bits in sequence; when N ≤ 8, configure N’ = 8, at this time, the high 8 bits are all set to 0, and the low 8 bits fill the data bits, control bits, and end bits from high to low in sequence.

[0028] The structure of the mapping unit is as Figure 3 shown, including module smp2oct, module SYSREF_detect, module oct2lane, and module FC_LMFC_gen; where the module smp2oct is a sample-octet mapping module that maps the input converter sample data to 32 octets; the module SYSREF_detect is a reference clock detection module; the module oct2lane is an octet-channel mapping module that sends the generated 32 parallel octets to different channels according to the link parameters F and L, where F is the number of octets per frame and L is the number of channels; the module FC_LMFC_gen is a frame clock generation module that generates a frame clock (FC, Frame Clock) and a local multi-frame clock (LMFC, Local Muti Frame Clock).

[0029] For details, please continue to refer to Figure 3, the module smp2oct includes submodules smp_16prl and get_8b_from_16b; the data generated by the data combination module is mapped to 16 parallel channels in the submodule smp_16prl, and the converter obtains M×S sample data in one clock cycle. When M×S=16, the 16 sample data are placed in the corresponding 16 parallel channels. For the configuration of M×S<16, each converter input continuously takes 16 / (M×S) groups of samples and sequentially places them in 16 parallel channels. At this time, the converter data rate is 16 / (M×S) times the channel data rate. If N'=16, the 16 parallel channel data are directly split into 32 octets, and the data is directly output from the sub-module smp_16prl to the next level; if N'=8, since the upper 8 bits are all 0 when processed by the data combination module, it is necessary to re-extract the lower 8 bits of valid data from the 16 parallel data, and generate 32 octets through odd-even sampling. This function is implemented by the sub-module get_8b_from_16b.

[0030] The synchronization module structure is as follows Figure 4 As shown, it includes a submodule SYNC_detect and a submodule CGS_ILAS_gen. The submodule SYNC_detect continuously samples the SYNC synchronization request sent by the receiving end. In the code group synchronization stage (CGS), after the submodule SYNC_detect receives the synchronization request sent by the receiving end, it sends a pulse SYNC_NE to the submodule CGS_ILAS_gen as a request signal for the code group synchronization stage. After receiving SYNC_NE, the submodule CGS_ILAS_gen enters the code group synchronization process and starts to send continuous control characters / K / . The receiving end circuit RX pulls up SYNC after receiving 4 consecutive / K / characters. After the submodule SYNC_detect samples the SYNC high signal, it gives a SYNC_PE to the submodule CGS_ILAS_gen as a start signal for the initial channel alignment sequence stage. The submodule CGS_ILAS_gen sends the initial channel alignment sequence (ILAS) within four consecutive multi-frame clocks. After the sending is completed, the submodule CGS_ILAS_gen is disabled and the output data is switched to user data. The submodule CGS_ILAS_gen also needs to synchronously output the control character identifier (CGS_ILAS_K) of the code group synchronization and initial channel sequence stage, and the encoding module will encode according to the encoding method of the control character. The phase of the data (output) control character identifier output by the encoding module remains strictly consistent.

[0031] The control character insertion module is as follows Figure 5As shown in the figure, it includes four delay modules (Delay) and a control code detection module (K_detect). The control character insertion module implements the control character insertion in the data stream. The receiving end that complies with the JESD204B protocol uses data recovery technology to identify and locate control characters in the data stream to achieve alignment and synchronization functions. The specific implementation method is as follows Figure 5 As shown, the frame clock generated by the mapping unit in the transport layer and the local multi-frame clock are first phase-aligned through the data generated by the delay module and the synchronization module. The control code detection module identifies the control characters that need to be inserted and replaced in the data stream according to the requirements of the JESD204B protocol, and generates the control character identification bit while inserting and replacing, and outputs it after the operation with the control character identification CGS_ILAS_K of the synchronization module. The module outputs the channel data and the control character position mark information, and the phase is completely consistent.

[0032] The transmitting end circuit based on the JESD204B protocol provided by the present invention is configured with M=4, S=1, F=4, L=2, N'=N=16, K=32. The link synchronization process is as follows: Figure 6 As shown. Figure 6 In the figure, (a) represents the link synchronization process, (b) represents the first multiframe, (c) represents the second multiframe, (d) represents the third multiframe, and (e) represents the fourth multiframe; the black circle in (c) represents all the link parameters sent; (b) to (e) are the rules specified by the protocol, and the corresponding parameters must be sent in this order.

[0033] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A transmitting circuit based on the JESD204B protocol, characterized in that: Comprising: A transport layer, including a data combination module and a mapping unit. The data combination module combines sample data according to the relationship of link configuration parameters N’, N, and CS, and the mapping unit maps the data output by the data combination module to corresponding output channels according to the link configuration. A scrambling module, which scrambles the data output by the transport layer or bypasses and directly outputs it to the next stage. A data link layer, including a synchronization module, a control character insertion module, and an encoding module. The synchronization module implements the synchronization process of the protocol. The control character insertion module inserts control characters into the data stream according to the rules of the protocol. The encoding module implements 8B / 10B encoding. The data combination module supports N’ = 16 or 8, and completes the combination of sampled data, control bits, and end bits: when the sampling data precision is 8 < N ≤ 16, N’ = 16 is configured, and 16-bit data fills the bit sampling data bits, control bits, and end bits in sequence. When N ≤ 8, N’ = 8 is configured. At this time, the high 8 bits are all set to 0, and the low 8 bits fill the data bits, control bits, and end bits from high to low in sequence. The mapping unit includes module smp2oct, module SYSREF_detect, module oct2lane, and module FC_LMFC_gen; wherein, module smp2oct maps the input converter sample data to 32 octets; module SYSREF_detect is a reference clock detection module; module oct2lane sends the generated 32 parallel octets to different channels according to link parameters F and L; module FC_LMFC_gen generates a frame clock and a local multi-frame clock.

2. The transmitting end circuit based on the JESD204B protocol as claimed in claim 1, characterized in that: Module smp2oct includes sub-module smp_16prl and sub-module get_8b_from_16b; the data generated by the data combination module is mapped to 16 parallel channels in sub-module smp_16prl. If N’ = 16, the data is directly output from sub-module smp_16prl to the next stage; if N’ = 8, the data is further combined by sub-module get_8b_from_16b and then output.

3. The transmitting end circuit based on the JESD204B protocol as claimed in claim 1, characterized in that: The synchronization module includes sub-module SYNC_detect and sub-module CGS_ILAS_gen; sub-module SYNC_detect continuously samples the SYNC synchronization request sent by the receiving end, and sub-module CGS_ILAS_gen implements the control character insertion and ramp signal insertion in the data stream during the code group synchronization stage and the initial channel alignment sequence stage.

4. The transmitting end circuit based on the JESD204B protocol as claimed in claim 1, characterized in that: The control character insertion module includes four delay modules and a control code detection module. The control code detection module identifies and replaces control codes in the data stream according to the content specified in the JESD204B protocol and gives an indication bit. The delay unit ensures that the input and output control signals and the data stream are strictly synchronized.

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