A SMD SD NAND Flash IC memory

Abstract

The present invention relates to the technical field of memory cards, and discloses a surface-mount SD NAND Flash IC memory with a high erasing and writing endurance, which comprises: an interface circuit electrically connected to an interface of an external device; a data transmission circuit for receiving data input from an external device and storing the data; a signal processing circuit for processing the data; the data transmission circuit comprises an SD NAND Flash controller and a customized SD connected to each other, the SD NAND Flash controller for receiving data input from an external device, and sequentially inputting the data into a first memory card and a second memory card, and storing the sequentially input data; a microcontroller for processing data input into the SD NAND Flash controller, collecting data output from the SD NAND Flash controller, and processing the data.

Description

Technical Field

[0001] The present invention relates to the technical field of memory cards, and more specifically to a surface mount SD NAND Flash IC memory. Background Art

[0002] Traditional T card and SD card are independent finished products in a module package. They are plug-in type and use the card's gold finger as a contact point for power supply and data transmission. At present, SD NAND Flash is directly attached to the PCB board, and the package is in the form of a surface mount IC, which has a relatively high stability when soldered on the PCB board. However, the fixing method of T card and SD card is plug-in type, and the memory has a low erase and write endurance, which shortens the service life of the memory.

[0003] Therefore, how to improve the erase and write endurance of a memory becomes a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a surface mount SD NAND Flash IC memory with a higher erasure and write endurance, in view of the defect of the prior art that the service life of the memory is shortened due to the low erasure and write endurance of the memory.

[0005] The technical solution adopted by the present invention to solve the technical problem is to construct a surface mount SD NAND Flash IC memory having:

[0006] an interface circuit electrically connected to an interface of an external device;

[0007] a data transmission circuit, used for receiving data input by the external device and storing the data;

[0008] a signal processing circuit, used for processing the data;

[0009] The interface circuit includes a single-chip microcomputer, and the single-chip microcomputer is used to generate a clock pulse signal;

[0010] The data transmission circuit includes an SD NAND Flash controller and a custom SD connected to each other, wherein the custom SD includes a first memory card and a second memory card;

[0011] The signal input end of the SD NAND Flash controller is connected to the signal output end of the external device, and is used to receive the data input by the external device and input the data into the first memory card and the second memory card in sequence;

[0012] The first memory card and the second memory card store the data input in sequence;

[0013] The signal processing circuit includes a microcontroller, and the microcontroller is used to process the data input into the SD NAND Flash controller;

[0014] The signal input end of the microcontroller is connected to the signal output end of the SD NAND Flash controller, and is used to collect the data output by the SD NAND Flash controller and process the data.

[0015] In some implementations, the storage interface defined by TF and SD is used for data management or the SD / SPI directly connected to the MCU can be used, and a Flash management program is already built in.

[0016] In some embodiments, the data transmission circuit further includes a first resistor, a second resistor and a third resistor, one end of the first resistor is connected to the power supply terminal, and the other end of the first resistor is connected to the bidirectional data terminal of the SD NAND Flash controller; one end of the second resistor is connected to the power supply terminal, and the other end of the second resistor is connected to the response signal terminal of the SDNAND Flash controller;

[0017] The third resistor is disposed between the clock signal terminal of the custom SD and the clock signal terminal of the SD NAND Flash controller.

[0018] In some embodiments, the data transmission circuit also includes a first capacitor, a second capacitor and a third capacitor, one end of the first capacitor is connected to the response signal end of the SD NAND Flash controller; one end of the second capacitor is connected to the bidirectional data end of the SD NAND Flash controller; one end of the third capacitor is connected to the clock signal end of the SD NAND Flash controller; the other ends of the first capacitor, the second capacitor and the third capacitor are respectively connected to a common end.

[0019] In some embodiments, the signal processing circuit also includes a fourth resistor and a fifth resistor connected in parallel, one end of the fourth resistor and the fifth resistor is connected to a power supply end; the other end of the fourth resistor is coupled to a signal end of the microcontroller; the other end of the fifth resistor is coupled to another signal end of the microcontroller.

[0020] In some embodiments, the signal processing circuit also includes a fourth capacitor and a fifth capacitor connected in parallel, one end of the fourth capacitor and the fifth capacitor are respectively connected to the power signal terminal of the microcontroller; one end of the fourth capacitor and the fifth capacitor are respectively connected to the common terminal.

[0021] In some embodiments, the interface circuit further includes a first transistor, a tenth resistor and an eleventh resistor, and the base of the first transistor is connected to the power signal terminal of the single chip microcomputer through the tenth resistor;

[0022] One end of the eleventh resistor is connected to the emitter and the power signal end of the first transistor respectively; the other end of the eleventh resistor is connected to the base of the first transistor.

[0023] In some embodiments, the interface circuit also includes a first crystal oscillator, a sixteenth resistor and a seventeenth resistor, wherein the first crystal oscillator is connected in parallel with the seventeenth resistor; one end of the first crystal oscillator is connected to one crystal oscillator end of the microcontroller; and the other end of the first crystal oscillator is connected to the other crystal oscillator end of the microcontroller through the sixteenth resistor.

[0024] In some embodiments, the interface circuit further includes a seventh capacitor and an eighth capacitor connected in series, one end of the seventh capacitor is connected to one end of the first crystal oscillator; one end of the eighth capacitor is connected to the other end of the first crystal oscillator.

[0025] The SMD SD NAND Flash IC memory of the present invention includes an interface circuit for electrically connecting to an interface of an external device; a data transmission circuit for receiving data input by an external device and storing the data; and a signal processing circuit for processing the data.

[0026] This technical solution has the following beneficial effects:

[0027] 1. Driver-free (ready to use), directly connected to MCU's SD / SPI, with built-in Flash management program;

[0028] 2. Machine mounting (high production efficiency / stable welding) LGA-8 package, convenient for machine mounting or hand mounting;

[0029] 3. Long erase and write life (the erase and write life of the built-in SLC / MLC / TLC wafer can reach 50,000-100,000 times, born for embedded systems);

[0030] 4. Stable and reliable, it has passed 10,000 random power-off and high and low temperature power-off tests. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0032] Figure 1a This is a data transmission circuit diagram of an embodiment of a surface mount SD NAND Flash IC memory provided by the present invention;

[0033] Figure 1b It is a data transmission circuit diagram of another embodiment of the surface mount SD NAND Flash IC memory provided by the present invention;

[0034] Figure 2 It is a signal processing circuit diagram of an embodiment of a surface mount SD NAND Flash IC memory provided by the present invention;

[0035] Figure 3 It is an interface circuit diagram of an embodiment of a surface mount SD NAND Flash IC memory provided by the present invention. DETAILED DESCRIPTION

[0036] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0037] like Figure 1a-Figure 3 As shown, in the first embodiment of the surface mount SD NAND Flash IC memory of the present invention, the surface mount SD NAND Flash IC memory includes a data transmission circuit (100a, b), a signal processing circuit 200 and an interface circuit 300.

[0038] The data transmission circuit (100a, 100b) is used to receive data input from an external device and store the data. The transmission mode can be parallel communication or serial communication. Parallel communication transmits each bit of data simultaneously, while serial communication transmits data one bit at a time.

[0039] The signal processing circuit 200 is used to process data input to the data transmission circuit (100a, 100b) to increase the data transmission rate.

[0040] The interface circuit 300 is used to establish an online programming SPI mode and an in-system programming function ICP, providing users with a variety of programming methods.

[0041] Specifically, the interface circuit 300 is also responsible for the storage and reading of the card clock and data, and reserves the RST, FUS and PGM signals required by other types of IC cards. The insertion and removal of the IC card can be identified by the switch on the IC card adapter socket.

[0042] Specifically, the interface circuit 300 is configured in the storage IC and is electrically connected to the interface of an external device (such as a mobile phone, a notebook or a camera) to establish an SDIO mode or an SPI mode to establish an initial state for the data transmission circuit (100a, 100b) to collect data.

[0043] The signal input end of the data transmission circuit (100a, 100b) is electrically connected to the signal output end of the external device. The data transmission circuit (100a, 100b) is used to receive data input by the external device and store the data according to the input data.

[0044] The signal input end of the signal processing circuit 200 is connected to the signal output end of the data transmission circuit (100a, 100b), and is used to receive data output by the data transmission circuit (100a, 100b) and process the data.

[0045] Specifically, the signal processing circuit 200 performs a batch data read test (i.e., data processing). First, a 2-byte data length is written, and then subsequent data streams are read one by one according to the length. This command is generally used in conjunction with the CMD_BULK_WR_TEST command to test the correctness of the external device and the data transmission circuit (100a, 100b) for batch data transmission.

[0046] The interface circuit 300 includes a single chip microcomputer U301 for generating a clock pulse signal.

[0047] The data transmission circuit (100a, 100b) includes an SD NAND Flash controller U101 and a customized SDU102 (a, b) connected to each other, wherein the customized SD U102 (a, b) includes a first memory card U102a and a second memory card U102b.

[0048] The SD NAND Flash controller U101 and the customized SD U102 (a, b) are provided with a clock signal (corresponding to the CLK terminal), a bidirectional data terminal (corresponding to the DAT terminal) and a response signal terminal (corresponding to the CMD terminal).

[0049] Among them, the clock signal (corresponding to the CLK end) transmits a command bit or data bit in each clock cycle. In the default speed mode of the SD bus, the frequency can vary between 0-25MHz. The bus manager of the SD card can freely generate a frequency of 0-5MHz without any restrictions. In the UHS-I speed mode, the clock frequency can reach up to 208M.

[0050] The response signal end (corresponding to the CMD end) is sent by the SD NAND Flash controller U101 to the customized SD card, which can be from the controller to a single SD card or to all cards on the SD bus.

[0051] The bidirectional data terminal (corresponding to the DAT terminal) can be transmitted from the SD card to the SD NAND Flash controller U101, and can also be transmitted from the SD NAND Flash controller U101 to the SD card.

[0052] Specifically, the signal input terminal of the SD NAND Flash controller U101 is connected to the signal output terminal of the external device, and is used to receive data input by the external device.

[0053] The signal output end (corresponding to CMD, DAT and CLK) of the SD NAND Flash controller U101 is connected to the signal input end (corresponding to CMD, DAT and CLK) of the customized SDU102 (a, b). More specifically, the signal output end (corresponding to CMD, DAT and CLK) of the SD NAND Flash controller U101 is connected to the signal input end (corresponding to CMD, DAT and CLK) of the first memory card U102a.

[0054] The signal output terminal (corresponding to CMD, DAT and CLK) of the SD NAND Flash controller U101 is connected to the signal input terminal (corresponding to CMD, DAT and CLK) of the second memory card U102b.

[0055] The SD NAND Flash controller U101 sequentially outputs the input data to the first memory card U102a and the second memory card U102b, and the memory cards store the sequentially input data.

[0056] Furthermore, the signal processing circuit 200 includes a microcontroller U201, which is used to process the data input to the SD NAND Flash controller U101 to increase the response speed of the input data.

[0057] The signal input terminal of the microcontroller U201 is connected to the signal output terminal of the SD NAND Flash controller U101, and is used to collect data output by the SD NAND Flash controller U101 and process the data.

[0058] This technical solution has the following beneficial effects:

[0059] No driver required (ready to use), directly connected to MCU's SD / SPI, built-in Flash management program;

[0060] Can be machine mounted (high production efficiency / stable welding) LGA-8 package, easy to machine or hand mount;

[0061] Long erase and write life (built-in SLC / MLC / TLC wafer erase and write life can reach 50,000-100,000 times, born for embedded systems);

[0062] Stable and reliable, it has passed 10,000 random power-off and high and low temperature power-off tests.

[0063] In some implementations, TF and SD are packaged in a surface mount format, and the storage interface defined by TF and SD is used for data management or directly connected to the SD / SPI of the MCU, and a Flash management program is built in.

[0064] In some implementations, in order to improve the performance of the data transmission circuit 100 a , a first resistor R101 , a second resistor R102 , and a third resistor R103 may be disposed in the data transmission circuit 100 a .

[0065] Specifically, one end of the first resistor R101 is connected to the power supply end (corresponding to VCC), the other end of the first resistor R101 is connected to the bidirectional data end (corresponding to the DAT end) of the SD NAND Flash controller U101, one end of the second resistor R102 is connected to the power supply end (corresponding to VCC), and the other end of the second resistor R102 is connected to the response signal end (corresponding to the CMD end) of the SD NAND Flash controller U101.

[0066] The third resistor R103 is disposed between the clock signal terminal (corresponding to the CLK terminal) of the customized SD U102 (a, b) and the clock signal terminal (corresponding to the CLK terminal) of the SD NAND Flash controller U101.

[0067] The driving signal input from the power supply end is input to the SD NAND Flash controller U101 via the first resistor R101 and the second resistor R102 to trigger the SD NAND Flash controller U101 to work, so that the SD NAND Flash controller U101 transmits data to the custom SD U102 (a, b).

[0068] In some implementations, the data transmission circuit 100a further includes a first capacitor C101, a second capacitor C102, and a third capacitor C103. The above capacitors are used to eliminate interference of medium and high frequency signals.

[0069] Specifically, one end of the first capacitor C101 is connected to the response signal end (corresponding to the CMD end) of the SD NAND Flash controller U101.

[0070] One end of the second capacitor C102 is connected to the bidirectional data end (corresponding to the DAT end) of the SD NAND Flash controller U101.

[0071] One end of the third capacitor C103 is connected to the clock signal end (corresponding to the CLK end) of the SD NAND Flash controller U101.

[0072] The other ends of the first capacitor C101 , the second capacitor C102 , and the third capacitor C103 are respectively connected to the common end.

[0073] In some embodiments, the signal processing circuit 200 further includes a fourth resistor R201 and a fifth resistor R202 , wherein the fourth resistor R201 and the fifth resistor R202 are connected in parallel.

[0074] Specifically, one end of the fourth resistor R201 and the fifth resistor R202 are connected to the power supply end (corresponding to 3.3V), and the 3.3V power supply signal is input to the microcontroller U201 through the fourth resistor R201 and the fifth resistor R202 to provide working power for its operation.

[0075] The other end of the fourth resistor R201 is connected to a signal end (corresponding to the SDD2 end) of the microcontroller U201.

[0076] The other end of the fifth resistor R202 is coupled to another signal end (corresponding to the SDD3 end) of the microcontroller U201.

[0077] In some implementations, the signal processing circuit 200 further includes a seventh resistor R204, a fourth capacitor C201, and a fifth capacitor C202, wherein the fourth capacitor C201 and the fifth capacitor C202 are connected in parallel.

[0078] Specifically, one end of the fourth capacitor C201 and one end of the fifth capacitor C202 are respectively connected to the power signal end (corresponding to the VCC end) of the microcontroller U201.

[0079] One end of the fourth capacitor C201 and one end of the fifth capacitor C202 are respectively connected to the common end.

[0080] Among them, one end of the seventh resistor R204 is connected to the power supply end (corresponding to 3.3V), and the other end of the seventh resistor R204 is connected to the power signal end of the microcontroller U201 (corresponding to the VCC end). The 3.3V input current is input into the microcontroller U201 through the seventh resistor R204 to provide working power for the microcontroller U201.

[0081] In some implementations, the interface circuit 300 further includes a first transistor Q301, a tenth resistor R301, and an eleventh resistor R302. The first transistor Q301 is a PNP transistor, which has the functions of switching and amplification.

[0082] Specifically, the base of the first transistor Q301 is connected to the power signal terminal (corresponding to the IC.VCC terminal) of the single-chip computer U301 through the tenth resistor R301.

[0083] One end of the eleventh resistor R302 is connected to the emitter of the first transistor Q301 and the power signal terminal (corresponding to the VCC terminal) respectively, and the other end of the eleventh resistor R302 is connected to the base of the first transistor Q301.

[0084] In some implementations, the interface circuit 300 further includes a first crystal oscillator X301 , a sixteenth resistor R307 , and a seventeenth resistor R308 , wherein the first crystal oscillator X301 is used to generate a pulse clock signal.

[0085] Among them, the first crystal oscillator X301 is connected in parallel with the seventeenth resistor R308, one end of the first crystal oscillator X301 is connected to a crystal oscillator end (corresponding to the XTAL1 end) of the microcontroller U301, and the other end of the first crystal oscillator X301 is connected to the other crystal oscillator end (corresponding to the XTAL2 end) of the microcontroller U301 through the sixteenth resistor R307.

[0086] In some implementations, the interface circuit 300 further includes a seventh capacitor C302 and an eighth capacitor C303 .

[0087] The seventh capacitor C302 and the eighth capacitor C303 are connected in series, one end of the seventh capacitor C302 is connected to one end of the first crystal oscillator X301, one end of the eighth capacitor C303 is connected to the other end of the first crystal oscillator X301, and the first crystal oscillator X301 generates

[0088] The generated pulse clock signal is input into the microcontroller U301.

[0089] It should be noted that the SD NAND Flash initialization should follow the following procedure example:

[0090] 1. Support initialization of votage

[0091] The host system can apply the operating voltage to initialize the SD NAND Flash and apply a fool clock of more than 74 cycles to the SD NAND Flash;

[0092] 2. Select the operating mode (SDIO mode or SPI mode

[0093] When using SPI mode operation, the host should drive 1pin (CD / DAT3) of SD NAND Flash at low level; CMDO problem, when using SDIO mode operation, the host should drive or detect SD NAND FlashVF 1 pin (1 pin pull-up register is pulled out) for ria'omam, SD NAND Flash maintains the selected operation mode, except re-issuing CMDO or poweron. The following is the SDIO mode initialization procedure;

[0094] 3. Send ACMD41 with Arg=0 and identify the operating voltage range of the card;

[0095] 4. Apply the indicated operating voltage to the SD NAND Flash and resend ACMD 41 and apply voltage to store and repeat ACMD 41 until the busy bit is cleared.

[0096] (Bit 31 Busy = 1) If the response times out, the host can recognize that it is not SD NAND Flash.

[0097] 5. Issue CMD2 and obtain the card ID (CID).

[0098] Issue CMD3 and obtain RCA. The RCA value changes randomly through access and is not equal to zero.

[0099] 6. Issue CMD7 and move to the transfer state. If necessary, the host can issue ACMD 42 and disable the pull-up resistor card detection;

[0100] 7. Issue ACMD13, poll the SD NAND Flash storage status and check the SD NAND Flash type value. If the valid 8 bits are "all zeros", it is SD NAND Flash. If not, stop initialization.

[0101] 8. Issue CMD7 and move to standby state. Issue CMD9 and obtain CSD. Sue CMD10 and obtain CID.

[0102] 9. Use CMD7 to return to the transfer status, issue ACMD6 and select the appropriate bus width;

[0103] The host can then access the data between the SD NAND Flash as a storage device.

[0104] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A surface mount SD NAND Flash IC memory, characterized in that: have: an interface circuit electrically connected to an interface of an external device; a data transmission circuit for receiving data inputted by the external device and storing the data; a signal processing circuit for processing the data; the interface circuit includes a single chip microcomputer for generating a clock pulse signal; the data transmission circuit includes an SD NAND Flash controller and a customized SD connected to each other, wherein the customized SD includes a first memory card and a second memory card; the signal input end of the SD NAND Flash controller is connected to the signal output end of the external device, and is used to receive the data inputted by the external device, and sequentially input the data into the first memory card and the second memory card; the first memory card and the second memory card store the sequentially inputted data; the signal processing circuit includes a microcontroller, and the microcontroller is used to process the data inputted by the SD NAND Flash controller; the signal input end of the microcontroller is connected to the signal output end of the SD NAND Flash controller, and is used to collect the data outputted by the SD NAND Flash controller and process the data; It can be used by using the storage interface defined by TF and SD for data management or directly connected to the SD / SPI of the MCU, and has a built-in Flash management program; The data transmission circuit also includes a first resistor, a second resistor and a third resistor, one end of the first resistor is connected to the power supply end, and the other end of the first resistor is connected to the bidirectional data end of the SD NAND Flash controller; one end of the second resistor is connected to the power supply end, and the other end of the second resistor is connected to the response signal end of the SD NAND Flash controller; the third resistor is arranged between the clock signal end of the custom SD and the clock signal end of the SD NAND Flash controller.

2. The surface-mount SD NAND FlashIC memory according to claim 1, characterized in that: The data transmission circuit also includes a first capacitor, a second capacitor and a third capacitor, one end of the first capacitor is connected to the response signal end of the SD NAND Flash controller; one end of the second capacitor is connected to the bidirectional data end of the SD NAND Flash controller; one end of the third capacitor is connected to the clock signal end of the SD NAND Flash controller; the other ends of the first capacitor, the second capacitor and the third capacitor are respectively connected to a common end.

3. The SMD SD NAND FlashIC memory according to claim 1, characterized in that: The signal processing circuit also includes a fourth resistor and a fifth resistor connected in parallel, one end of the fourth resistor and the fifth resistor is connected to the power supply end; the other end of the fourth resistor is coupled to a signal end of the microcontroller; the other end of the fifth resistor is coupled to another signal end of the microcontroller.

4. The SMD SD NAND FlashIC memory according to claim 3, characterized in that: The signal processing circuit also includes a fourth capacitor and a fifth capacitor connected in parallel, one end of the fourth capacitor and the fifth capacitor are respectively connected to the power signal end of the microcontroller; one end of the fourth capacitor and the fifth capacitor are respectively connected to the common end.

5. The SMD SD NAND FlashIC memory according to claim 1, characterized in that: The interface circuit also includes a first transistor, a tenth resistor and an eleventh resistor. The base of the first transistor is connected to the power signal terminal of the single-chip microcomputer through the tenth resistor; one end of the eleventh resistor is respectively connected to the emitter and the power signal terminal of the first transistor; and the other end of the eleventh resistor is connected to the base of the first transistor.

6. The SMD SD NAND FlashIC memory according to claim 5, characterized in that: The interface circuit further includes a first crystal oscillator, a sixteenth resistor and a seventeenth resistor, wherein the first crystal oscillator is connected in parallel with the seventeenth resistor; one end of the first crystal oscillator is connected to a crystal oscillator end of the single-chip computer; The other end of the first crystal oscillator is connected to the other crystal oscillator end of the single chip microcomputer through the sixteenth resistor.

7. The surface-mount SD NAND FlashIC memory according to claim 6, characterized in that: The interface circuit also includes a seventh capacitor and an eighth capacitor connected in series, one end of the seventh capacitor is connected to one end of the first crystal oscillator; one end of the eighth capacitor is connected to the other end of the first crystal oscillator.

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