Semiconductor package with multi-stage conduction clip for top side cooling

Abstract

A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, and an interconnect clip including a first section at least partially surrounding a central opening, a second section offset in a vertical direction from and spaced apart from the first section, and a support extending between the first section and the second section. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first section of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second section is flush with the upper surface of the semiconductor die, and the lower surface of the second section is conductively connected to the first bond pad.

Description

[0001] Related applications

[0002] This application is a continuation-in-part of U.S. Application 16 / 402,486, filed May 3, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor packaging, and more specifically, to the cooling and interconnect features of semiconductor packaging. Background Technology

[0004] Semiconductor packages are designed to provide connectivity compatibility between semiconductor dies and external devices such as printed circuit boards (PCBs) and to protect the semiconductor die from potentially damaging environmental conditions, such as temperature variations, humidity, dust particles, etc. In many semiconductor packages, a crucial design consideration is the package's cooling capability. Many semiconductor dies generate significant amounts of heat during typical operation. An example of such devices is power semiconductor devices, which are required to withstand considerably high voltages during normal operation, such as 200 volts or higher. Cooling features are often necessary to ensure the semiconductor die operates within a safe temperature range.

[0005] Bottom-side cooled packages are designed to remove heat from the semiconductor die toward the bottom of the package. In one example of this configuration, the semiconductor die is mounted on a metal substrate with load terminals (e.g., source, anode, etc.) facing the metal substrate. The lower surface of the metal substrate is exposed on the bottom side of the package. This package can be mounted on a circuit board and used with a heat sink that removes heat from the package substrate during operation.

[0006] Compared to bottom-side cooling configurations, dual-side cooling packages seek to provide improved heat dissipation capabilities. A dual-side cooling package includes features that provide a conduction path between the bottom side of the die and the lower side of the package (e.g., as described above) and between the top side of the die and the upper side of the package. A dual-side cooling package can be mounted on a circuit board, with a second heat sink mounted on top of the package to draw heat away from the upper side of the package. Generally, dual-side cooling packages should preferably draw heat away from the semiconductor die relatively uniformly in both directions (i.e., towards the bottom and towards the top). However, known top-side cooling features do not achieve this balance. Furthermore, they require costly and time-consuming processing steps, such as soldering, fusion, etc., to incorporate known top-side cooling features into the semiconductor package. Summary of the Invention

[0007] A semiconductor package is disclosed. According to an embodiment, the semiconductor package includes: a die pad including a die attachment surface; a semiconductor die mounted on the die attachment surface, the semiconductor die including a first bonding pad on an upper surface opposite to the die attachment surface; an interconnect clip including a first segment at least partially surrounding a central opening, a second segment offset in a vertical direction from and spaced apart from the first segment, and one or more support portions connecting the first and second segments; and an encapsulation covering an electrically insulating layer of the semiconductor die. The upper surface of the first segment of the interconnect clip is exposed from the upper surface of the encapsulation. The lower surface of the second segment is flush with the first bonding pad.

[0008] Individually or in combination, the upper surface of the first segment exposed from the upper surface of the encapsulation extends laterally across the outer edge side of the semiconductor die in each direction.

[0009] Individually or in combination, the central portion of the encapsulation is directly interfaced with the inner edge side of the first segment and extends to the upper surface of the encapsulation.

[0010] Alone or in combination, the semiconductor package further includes a metal heat column attached to the upper surface of the second segment and extending to the upper surface of the encapsulation, wherein the central portion of the encapsulation fills the area between the heat column and the inner edge side of the first segment.

[0011] Individually or in combination, the first section forms a closed shape around the central opening.

[0012] Alone or in combination, the semiconductor package further includes a first lead spaced apart from the die pads, and an interconnect clip electrically connects the first bonding pads to the first lead.

[0013] Alone or in combination, the interconnect clip also includes an end connector extending from the first segment toward the first lead, and the outer end of the end connector is in direct electrical contact with the first lead.

[0014] Individually or in combination, the connection point between the support and the first section is offset laterally from the connection point between the support and the second section.

[0015] Individually or in combination, each of the supports extends diagonally between the outer edge of the second section and the inner edge of the first section facing the central opening.

[0016] Individually or in combination, the interconnecting clip includes two pairs of supports, each pair of supports extending away from each other in opposite directions, each of the supports being separated from each other by a lateral gap, and the lateral gap being filled by an encapsulant.

[0017] Individually or in combination, the upper surface of the first segment and the lower surface of the second segment are substantially parallel to each other, and the upper surface of the first segment is substantially coplanar with the upper surface of the encapsulation.

[0018] Individually or in combination, the first section, the second section, and the support are integrally formed parts of a planar metal sheet.

[0019] A method for packaging a semiconductor device is disclosed. According to an embodiment, the method includes: providing a die pad including a die attachment surface; providing a semiconductor die including a first bonding pad on an upper surface of the semiconductor die; mounting the semiconductor die on the die pad such that the first bonding pad faces away from the die attachment surface; providing an interconnect clip including a first segment at least partially surrounding a central opening, a second segment offset in a vertical direction from and spaced apart from the first segment, and one or more support portions connecting the first and second segments; mounting the interconnect clip on the semiconductor die such that a lower surface of the second segment is flush with the upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bonding pad; and forming an electrically insulating encapsulation such that the semiconductor die is covered by the encapsulation and that the upper surface of the first segment of the interconnect clip is exposed from the upper surface of the encapsulation.

[0020] Individually or in combination, after the encapsulation is formed, the upper surface of the first segment exposed from the upper surface of the encapsulation extends laterally across the outer edge side of the semiconductor die in each direction.

[0021] Alone or in combination, after the encapsulation is formed, the central portion of the encapsulation is directly interfaced with the inner edge side of the first segment and extends to the upper surface of the encapsulation.

[0022] Alone or in combination, the method further includes providing a first lead spaced apart from the die pads and using interconnect clips to electrically connect the first bonding pads to the first lead.

[0023] Individually or in combination, the interconnect clip includes a plurality of supports, each of which is laterally spaced by gaps, and liquefied molding material flows through each of the gaps during encapsulation formation.

[0024] Individually or in combination, the liquefied molding material flowing through each of the gaps flows in a transverse direction toward the central opening.

[0025] Providing an interconnect clip, either alone or in combination, includes selecting the area of ​​the second segment to be correlated with the area of ​​the semiconductor die.

[0026] Alone or in combination, the interconnecting clip includes a planar metal sheet and an integral structure formed from the planar metal sheet, comprising a first section, a second section, and a support.

[0027] A semiconductor package is disclosed. According to an embodiment, the semiconductor package includes: a die pad including a die attachment surface; a semiconductor die mounted on the die attachment surface, the semiconductor die including a first bonding pad on an upper surface opposite to the die attachment surface; and an interconnect clip. The interconnect clip includes: a first segment at least partially surrounding a central opening; a second segment offset in a vertical direction from and spaced apart from the first segment; and a support extending between the first and second segments. The semiconductor package also includes an electrically insulating encapsulation covering the semiconductor die. The upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulation. The lower surface of the second segment is flush with the upper surface of the semiconductor die and is conductively connected to the first bonding pad.

[0028] Individually or in combination, the second segment is a planar pad with a closed geometric shape, and from the perspective of the plan view of the interconnect clip, the support surrounds the perimeter of the second segment.

[0029] Individually or in combination, the second segment has a rectangular geometry, and from the perspective of the plan view of the interconnecting clip, the support surrounds at least one corner of the second segment.

[0030] Individually or in combination, the support forms a complete closed loop extending between the outer edge of the second section and the inner edge of the first section facing the central opening.

[0031] Individually or in combination, from a plan view of the interconnect clip, the interconnect clip has an L-shaped geometry, and the semiconductor die also includes a second bonding pad on its upper surface, and the second bonding pad is outside the coverage area of ​​the interconnect clip.

[0032] A method for packaging a semiconductor device is disclosed. According to an embodiment, the method includes: providing a die pad including a die attachment surface; providing a semiconductor die including a first bonding pad on an upper surface of the semiconductor die; mounting the semiconductor die on the die pad such that the first bonding pad faces away from the die attachment surface; and providing an interconnect clip. The interconnect clip includes: a first segment at least partially surrounding a central opening; a second segment offset in a vertical direction from and spaced apart from the first segment; and a support extending between the first and second segments. The method further includes: mounting the interconnect clip on the semiconductor die such that a lower surface of the second segment is flush with the upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bonding pad; and forming an electrically insulating encapsulation such that the semiconductor die is covered by the encapsulation, and such that the upper surface of the first segment of the interconnect clip is exposed from the upper surface of the encapsulation.

[0033] Individually or in combination, the second section is a planar pad with a closed geometric shape, and from the perspective of the interconnect clamp plan view, the support surrounds the perimeter of the second section.

[0034] Alone or in combination, the encapsulation is formed such that the upper surface of the first segment of the interconnect clip is substantially coplanar with the planar surface of the encapsulation, and forming the encapsulation includes completely covering the interconnect clip with the encapsulation, and subsequently planarizing the encapsulation until the upper surface of the first segment is exposed from the planar surface of the encapsulation.

[0035] An interconnect clip is disclosed. According to an embodiment, the interconnect clip includes: a first segment that at least partially surrounds a central opening; a second segment that is offset from and spaced apart from the first segment in a vertical direction; and one or more support portions extending between the first and second segments.

[0036] Individually or in combination, the first section forms a closed shape around the central opening.

[0037] Individually or in combination, the first section completely surrounds the central opening.

[0038] Individually or in combination, the one or more supports extend diagonally between the outer edge of the second section and the inner edge of the first section facing the central opening.

[0039] Individually or in combination, the interconnecting clip includes a plurality of supports extending between the first and second sections, each of which is separated from the others by lateral gaps.

[0040] Individually or in combination, the interconnect clip includes only one of the support portions extending between the first and second sections.

[0041] Individually or in combination, the second segment is a planar pad with a closed geometric shape, wherein, from the perspective of the plan view of the interconnect clip, the support surrounds the perimeter of the second segment.

[0042] Individually or in combination, the second segment has a rectangular geometry, and from the perspective of the plan view of the interconnecting clip, the support surrounds at least one corner of the second segment.

[0043] Individually or in combination, the support forms a complete closed loop extending between the outer edge of the second section and the inner edge of the first section facing the central opening. Attached Figure Description

[0044] The elements in the accompanying drawings are not necessarily drawn to scale relative to each other. Similar reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and will be described in detail in the following description.

[0045] include Figure 1A , Figure 1B and Figure 1C Figure 1 depicts an interconnect clip according to an embodiment. Figure 1A A plan view of the interconnect clip is depicted. Figure 1B The edge of the interconnect clip is depicted Figure 1A The cross-sectional view of the plane A-A' indicated in the figure, and Figure 1C An isometric view of the interconnect clip is depicted.

[0046] Figure 2 An isometric view of an interconnect clip according to another embodiment is depicted.

[0047] include Figure 3A and Figure 3B Figure 3 depicts an interconnect clip mounted on an assembly of a lead frame and a semiconductor die according to an embodiment. Figure 3A A floor plan of the component was depicted, and Figure 3B A cross-sectional view of the component is depicted.

[0048] Figure 4 The flow of liquefied molding material during the encapsulation process in an assembly with interconnect clips, according to an embodiment, is depicted.

[0049] include Figure 5A , Figure 5B and Figure 5C Figure 5 depicts a semiconductor package including interconnect clips according to an embodiment. Figure 5A An isometric view of the top side of the semiconductor package is depicted. Figure 5B An isometric view of the lower side of the semiconductor package is depicted, and Figure 5C A cross-sectional view of the semiconductor package is depicted.

[0050] include Figure 6A and Figure 6B Figure 6 depicts a semiconductor package including interconnect clips according to another embodiment. Figure 6A An isometric view of the top side of the semiconductor package is depicted, and Figure 6B A cross-sectional view of the semiconductor package is depicted.

[0051] include Figure 7A and Figure 7B Figure 7 depicts a semiconductor package including interconnect clips according to another embodiment. Figure 7A An isometric view of the top side of the semiconductor package is depicted, and Figure 7B An isometric view of the lower side of the semiconductor package is depicted.

[0052] include Figure 8A and Figure 8B Figure 8 depicts an interconnect clip according to an embodiment. Figure 8A A plan view of the interconnect clip is depicted, and Figure 8B The edge of the interconnect clip is depicted Figure 8A The cross-sectional view of the plane B-B' indicated in the middle.

[0053] include Figure 9A , Figure 9B , Figure 9C and Figure 9D Figure 9 depicts a semiconductor package including the interconnect clips of Figure 8 according to an embodiment. Figure 9A A plan view of the top side of the semiconductor package is depicted. Figure 9B A side view of the semiconductor package is depicted. Figure 9C An isometric view of the top side of the semiconductor package is depicted, and Figure 9D A close-up isometric view depicting the interface connection between the interconnect clip and the semiconductor die.

[0054] Figure 10 An isometric view of a semiconductor package including the interconnect clips of FIG8 according to an embodiment is depicted. Detailed Implementation

[0055] This document describes embodiments of interconnect clips that provide advantageous top-side cooling capabilities and are easily integrated into semiconductor packages. The interconnect clips have a multi-level construction, wherein a first planar segment and a second planar segment are offset from each other in a vertical direction. In one embodiment, the first planar segment forms a closed shape (e.g., a loop shape) around a central opening, the second planar segment is disposed below the central opening, and discrete support structures extend between the first and second planar segments, with lateral gaps provided between the support structures. The interconnect clip is integrated into the semiconductor package, wherein the second segment is mounted flush with the upper surface of the semiconductor die, and the first segment is exposed on the upper side of the package body. For example, the exposed first segment can provide an interfacial connection that transfers heat from the top side of the package via a heat sink. Furthermore, the interconnect clip can provide electrical connections between bonding pads on the upper surface of the semiconductor die and package leads or contacts.

[0056] The multi-stage design of the interconnect clips advantageously allows for a large exposed surface area of ​​conductive metal on the upper surface of the package. Due to the lateral stability provided by the combination of the second planar segment and the bracket-like construction of the support structure, the interconnect clips can accommodate a large first segment when mounted on a semiconductor die. Therefore, a semiconductor package including the interconnect clips can have exposed conductive surfaces on the upper side of the package that extend beyond the die coverage area in each direction and are close to the outer side of the package.

[0057] Furthermore, various features of the interconnect clips are configured to interact with the liquefied molding material in a manner that maintains the stability of the interconnect clips during encapsulation. Specifically, the interconnect clips are designed to allow the liquefied molding material to flow uniformly through the lateral gaps between the support structures. This liquefied molding material accumulates in the central region of the package and interacts with the inner edge of the central opening in the first segment. Therefore, the interconnect clips remain horizontal and flush with the semiconductor die during encapsulation, and the first segment remains aligned with the upper surface of the package. This avoids costly and time-consuming measures for securing the interconnect clips, such as welding.

[0058] Referring to FIG1, an interconnect clip 100 according to an embodiment is depicted. The interconnect clip 100 includes a first segment 102 and a second segment 104. Both the first segment 102 and the second segment 104 include an upper surface 106 and a lower surface 108 facing opposite directions. According to an embodiment, the first segment 102 and the second segment 104 are planar pads having substantially the same thickness. The second segment 104 is spaced apart from the first segment 102 in the vertical direction. This means that at least a certain separation distance is provided between the lower surface 108 of the first segment 102 and the upper surface 106 of the second segment 104.

[0059] According to an embodiment, the first segment 102 at least partially surrounds the central opening 110. This means that an open passage is provided at a certain location within the outer perimeter 112 of the first segment 102 between the upper surface 106 and the lower surface 108 of the first segment 102. The inner edge sides 114 of the first segment 102 face the central opening 110. These inner edge sides 114 extend between the upper surface 106 and the lower surface 108 of the first segment 102, and are opposite to the outer edge sides 116 of the first segment 102, which define the outer perimeter 112 of the first segment 102.

[0060] According to the depicted embodiment, the first segment 102 completely surrounds the central opening 110. That is, the first segment 102 forms a closed shape around the central opening 110, such that the lateral portion of the first pad separates the inner edge sides 114 of the first segment 102 from the outer perimeter 112 in each direction. Alternatively, the first segment 102 can have a variety of open shape configurations, wherein at least one set of inner edge sides 114 extends to the outer perimeter 112 of the first segment 102. Examples of such open shape configurations include C-shapes, U-shapes, etc.

[0061] According to an embodiment, the second segment 104 is a continuous pad with a closed-shape geometry. For example, as shown, the second segment 104 has a rectangular geometry. More generally, the geometry of the second segment 104 may include curved shapes, elongated shapes, etc., and may be associated with different die and / or bonding pad geometries. Furthermore, embodiments of the interconnect clip 100 may include a plurality of discrete second segments 104.

[0062] According to the depicted embodiment, the second segment 104 is disposed directly below the central opening 110. Furthermore, the second segment 104 is smaller than the central opening 110. Therefore, the outer edge 118 of the second segment 104 is laterally spaced from the inner edge 114 of the first segment 102 in each direction, as... Figure 1A As shown. Alternatively, the second segment 104 may be larger than the central opening 110, and / or the second segment 104 may be offset laterally from the central opening 110. Generally, the second segment 104 may be located near the lateral centroid of the interconnect clip 100. In this way, when the interconnect clip 100 is mounted on a planar surface, the second segment 104 maintains the lateral stability of the clip by mitigating the leverage effect exerted by the first planar segment 102.

[0063] The interconnect clip 100 includes a support 120 connected between a first segment 102 and a second segment 104. The support 120 mechanically couples the first segment 102 to the second segment 104. Furthermore, the support 120 provides a thermally and electrically conductive connection between the first segment 102 and the second segment 104.

[0064] According to an embodiment, the interconnect clip 100 includes four support portions 120. More specifically, as shown in FIG1, the interconnect clip 100 may include two pairs of support portions 120, each pair of support portions 120 extending away from each other in opposite directions. This is merely a design example well suited to implement mechanical support for the first segment 102.

[0065] According to an embodiment, the connection point between the support portion 120 and the first segment 102 is laterally offset from the connection point between the support portion 120 and the second segment 104. In other words, the support portion 120 does not extend solely in the vertical direction between the first segment 102 and the second segment 104. Instead, the support portion 120 is oriented to connect laterally closer to the outer edge 116 of the first segment 102 than its connection point with the second segment 104. For example, in the depicted embodiment, each of the vertical support portions 120 extends diagonally between the second segment 104 and the first segment 102. Alternatively, the vertical support portion 120 may have one or more angled bends to achieve the laterally offset connection point. In either configuration, as the support portion 120 moves away from the second segment 104 and towards the first segment 102, the outward extension of the support portion 120 enhances structural support and stability by providing a bracket-like structure.

[0066] According to an embodiment, the support portions 120 are separated from each other by a lateral gap 122. This means that at least a certain separation distance is provided between the defined edge sides of the support portions 120 extending vertically between the second segment 104 and the first segment 102. Thus, from the side view angle of the interconnect clip 100 (e.g., as shown in the image), Figure 1B As shown, the transverse gaps 122 provide an open passage between the region directly below the lower surface 108 of the first segment 102 and the region directly above the upper surface 106 of the second segment 104. The dimensions, shape, and size of these transverse gaps 122 can vary from those shown. Generally, the arrangement, number, and size of the transverse gaps 122 can be customized to meet a wide variety of design factors. These design factors include facilitating the flow of liquefied molding material through the transverse gaps 122 and size requirements for the support structure 120. Instead of the depicted configuration, the transverse gaps 122 can be implemented as narrow slits and / or circular openings positioned between relatively large support structures 120.

[0067] According to an embodiment, the interconnect clip 100 includes an end connector 124. The end connector 124 is directly connected to the first segment 102 and extends outwardly to an outer end 126 away from the lower surface 108 of the first segment 102. The outer end 126 of the end connector 124 is disposed on the same side of the first segment 102 as the second segment 104. As shown, the end connector 124 and the first segment 102 may be portions of a continuous planar structure bent downwards at one end. Alternatively, the end connector 124 may be a portion of a separate structure attached to the first segment 102.

[0068] Each of the features discussed above in the interconnect clip 100 is formed of a thermally and electrically conductive material. Exemplary materials for the interconnect clip 100 include copper, aluminum, nickel, iron, zinc, and alloys thereof. In any case, the material used to form the interconnect clip 100 may be selected to provide a thermally conductive connection between the lower surface 108 of the second segment 104 and the upper surface 106 of the first segment 102. In this way, the interconnect clip 100 is configured to provide top-side cooling capability. Furthermore, the material used to form the interconnect clip 100 may be selected to provide a conductive connection between the lower surface 108 of the second segment 104 and the outer end 126 of the end connector 124. In this way, the interconnect clip 100 is configured to provide electrical interconnect capability.

[0069] According to an embodiment, the interconnect clip 100 is integrally formed from a planar metal sheet. For example, the interconnect clip 100 with the features discussed above can be provided by initially providing an undisturbed conductive metal sheet (e.g., a flat plate of a metal such as copper, aluminum, or their alloys, which is similar to or equivalent to a metal sheet used to form a package lead frame). Subsequently, the planar metal sheet can be processed to form a first segment 102 and a second segment 104 offset in the vertical direction, as well as a central opening 110. In one embodiment, this operation is accomplished by embossing or stamping the planar metal sheet. The lateral gap 122 can be formed simultaneously or separately using embossing, stamping, or etching processes. Thus, the first segment 102, the second segment 104, and the support portion 120 are integrally formed portions of a single planar metal sheet. In an embodiment, the end connector 124 is formed by bending the planar portion of the metal sheet before, during, or after the steps described above. Alternatively, the interconnecting clip 100 can be formed by connecting two separate conductive structures together using known techniques (e.g., welding, fusion, riveting, etc.).

[0070] Advantageously, the features of the interconnect clip 100 can be customized to match the specific characteristics of the semiconductor die and / or package design. For example, according to an embodiment, the interconnect clip 100 is formed by selecting the area of ​​the second segment 104 to be correlated with the specific semiconductor die to which it will be attached in the completed semiconductor package. This means that the second segment 104 has the same general shape as the semiconductor die, e.g., square, rectangular, etc., and the lateral surface area of ​​the second segment 104 is the same as or close to the surface area of ​​the semiconductor die (e.g., within + / - 10%). In this way, the manufacturer of the semiconductor package can provide an interconnect clip 100 preferably configured to achieve mechanical stability and thermal transfer with respect to a specific semiconductor die. Furthermore, this customization can be achieved using simple processing steps, e.g., by appropriately selecting the stamping / imprinting dimensions according to the techniques described above for forming the interconnect clip 100. As another example, the size of the outer perimeter 112 of the first segment 102 can be set to be close to or slightly smaller than the desired package size (e.g., approximately 90% of its lateral surface area).

[0071] refer to Figure 2 An interconnect clip 100 according to another embodiment is shown. Except that the support portion 120 is configured differently, Figure 2 The interconnect clip 100 is equivalent to the interconnect clip 100 described with reference to FIG1. Figure 2 In this embodiment, the interconnect clip 100 also includes two pairs of supports 120, wherein each pair of supports 120 extends away from each other in opposite directions. However, the supports 120 are provided at the corner position of the second pad and the central opening 110, instead of the central connection point configuration shown in FIG1. ​​Furthermore, the supports 120 have a larger cross-sectional diameter compared to the supports 120 of the interconnect clip 100 in FIG1. ​​This configuration may hopefully achieve higher mechanical strength and conductivity.

[0072] More generally, the construction of the vertical support 120 can differ from that shown in Figure 1- Figure 2 Specific embodiments. The arrangement, number, and size of the support 120 can be optimized with regard to a variety of design factors, such as the mechanical strength of the support 120, the conductivity (both thermal and electrical) of the support 120, and / or the size setting of the lateral gap 122 between the support 120.

[0073] Referring to FIG3, selected method steps for packaging a semiconductor device using interconnect clip 100 according to an embodiment are illustrated. In this method step, a lead frame 128 is provided. The lead frame 128 comprises a conductive and thermally conductive material, such as conductive materials like copper, aluminum, nickel, iron, zinc, etc., and alloys thereof. The lead frame 128 includes a die pad 130 having a die attachment surface 132. Furthermore, the lead frame 128 includes conductive leads 134 extending away from the die pad 130. In the depicted embodiment, the leads 134 of a first set 136 are directly connected to the die pad 130, and the leads 134 of a second set 138 are separated from the die pad 130. The leads 134 can be bent, wherein the outermost end of the leads 134 extends substantially parallel to the bottom side of the package, and wherein the leads may include positive or negative bumps (stand-off).

[0074] In this method step, a semiconductor die 140 is mounted on the die attachment surface 132 of the die pad 130. Generally, the semiconductor die 140 can have a wide range of device configurations, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), JFETs (Junction Field-Effect Transistors), diodes, etc. Generally, the semiconductor die 140 can comprise any semiconductor material from a wide range of semiconductor materials, including Type IV semiconductors such as silicon, silicon germanium, and silicon carbide, and Type III-V semiconductors such as gallium nitride and gallium arsenide. Generally, the semiconductor die 140 can be configured as a vertical device, configured to control current flow between oppositely oriented upper and lower surfaces, or the semiconductor die 140 can be configured as a lateral device, configured to control current flowing parallel to the main surface.

[0075] According to an embodiment, the semiconductor die 140 includes a first bonding pad 142 disposed on an upper surface of the semiconductor die 140 facing away from the die attachment surface 132 and a second bonding pad 144 disposed on a rear surface of the semiconductor die 140 facing the die attachment surface 132. These first bonding pads 142 and second bonding pads 144 provide terminal connections to the semiconductor die 140. For example, the first bonding pads 142 and second bonding pads 144 may be load terminals, such as anode and cathode terminals for a diode, or collector / emitter terminals for a switching device. For simplicity, only two bonding pads are shown. In practice, the semiconductor die 140 may include additional bonding pads, such as control terminals, such as gate, base, etc., for a three-terminal switching device. These additional bonding pads can be connected to the lead 134 using known techniques.

[0076] In this method step, the interconnect clip 100 is mounted on top of the semiconductor die 140. According to an embodiment, the interconnect clip 100 is mounted such that the lower surface 108 of the second segment 104 is flush with the upper surface of the semiconductor die 140. This means that the lower surface 108 of the second segment 104 is substantially parallel to the upper surface of the semiconductor die 140, and the two surfaces are mechanically coupled to each other, for example, through direct contact or through a medium (e.g., solder, sintering agent, adhesive, etc.).

[0077] According to an embodiment, the interconnect clip 100 is mounted such that the lower surface 108 of the second segment 104 is electrically and thermally connected to the first bonding pad 142. This conductive connection may be implemented through direct physical contact between the two surfaces, or it may be implemented through a conductive bonding material (e.g., solder, sintering agent, conductive adhesive, etc.).

[0078] According to an embodiment, the interconnect clip 100 is mounted such that the outer end 126 of the end connector 124 makes direct electrical contact with the first lead 134 from the lead frame 128. This conductive connection can be implemented through direct physical contact between the two surfaces, or it can be implemented through a conductive bonding material (e.g., solder, sintering agent, conductive adhesive, etc.). As a result of this connection, and the connection between the second segment 104 as described above and the first bonding pad 142, the interconnect clip 100 provides a direct electrical connection between the first bonding pad 142 and the first lead 134.

[0079] According to an embodiment, when installed, the interconnect clip 100 extends laterally beyond the outer edge side 146 of the semiconductor die 140 in each direction. This means that the outer edge side 146 of the semiconductor die 140 is entirely within the lateral coverage area of ​​the first segment 102 (as defined by the outer perimeter 112 of the first segment 102). This configuration differs from conventional interconnect clip 100 configurations, in which the clip provides a direct point-to-point connection between two terminals (e.g., bonding pads and leads) and thus extends only over one edge side of the semiconductor die. The installed interconnect clip 100 can provide a similar point-to-point connection between the first bonding pad 142 and the first lead 134, and a portion of the first segment 102 is positioned outside the current path between the first bonding pad 142 and the first lead 134. For example, the leftmost portion of the first segment 102 in FIG. 3 is positioned outside this current path.

[0080] refer to Figure 4The diagram illustrates selected method steps for encapsulating a semiconductor device using interconnect clip 100 according to an embodiment. In this method step, the component of FIG3 is encapsulated using an electrically insulating material for a molding process. Exemplary techniques for this molding process include injection molding, compression molding, and transfer molding. In these techniques, the component is placed within a cavity 148 of a molding tool, and the cavity is filled with a liquefied molding material. Examples of such molding materials include ceramics, epoxy resins, and thermosetting plastics. The liquefied molding material fills the cavity 148 to form the desired shape of the package body. Subsequently, the liquefied molding material hardens, and the package is removed from the molding cavity 148.

[0081] According to an embodiment, liquefied molding material flows through each of the transverse gaps 122 during encapsulation formation. More specifically, the liquefied molding material can flow in a transverse direction toward the central opening 110. Figure 4 The directional flow of the liquefied molding material is depicted by arrows. As the liquefied molding material continues to flow, it covers the second section 104 and eventually reaches the inner edge side 114 of the first section 102, until it forms the central portion of the encapsulation described earlier.

[0082] Advantageously, the interconnect clip 100 is designed to maintain the stability of the interconnect clip 100 and to allow the liquefied molding material to flow uniformly and consistently during the molding process described above. Specifically, the lateral gap 122 enables a relatively consistent flow of the molding material over the second segment 104. Once covered by the molding material, the second segment 104 acts as a foot holding the interconnect clip 100 in place. Furthermore, the inner edge side 114 of the first segment 102 provides a contact surface that engages with the liquefied molding material when it accumulates in the central opening 110. This allows for uniform filling of the molding material and maintains the first segment 102 in a relatively flat position parallel to the upper surface of the semiconductor die 140.

[0083] Referring to FIG5, a completed semiconductor package 200 according to an embodiment is depicted. The semiconductor package 200 includes a body of an encapsulation 202 formed according to the techniques described above. The encapsulation 202 is formed to completely cover the semiconductor die 140, wherein the outer ends of the leads 134 are exposed from the encapsulation 202 in a generally known manner.

[0084] According to an embodiment, the encapsulation 202 is formed such that the upper surface 106 of the first segment 102 of the interconnect clip 100 is exposed from the upper surface 204 of the encapsulation 202. This means that at least a portion of the upper surface 106 of the first segment 102 is not covered by the encapsulation 202 material and is therefore available for contact with a heat dissipation mechanism (e.g., a heat sink and / or a thermal interface material). As shown, the upper surface 106 of the first segment 102 is completely uncovered, such that the complete shape of the first segment 102 (in this case, a closed loop) is exposed from the encapsulation 202. This configuration can be achieved by appropriately setting the dimensions of the molding chamber in the molding technique described above. Alternatively, this configuration can be achieved by a two-step process, wherein the encapsulation 202 is initially formed to completely cover the interconnect clip 100, and then the upper surface 204 of the encapsulation 202 is planarized (e.g., by polishing or grinding) until the upper surface 106 of the first segment 102 is exposed from the encapsulation 202.

[0085] According to one embodiment, the encapsulation 202 is formed such that the upper surface 106 of the first segment 102 is substantially coplanar with the upper surface 204 of the encapsulation 202. This means that the upper surface 106 of the first segment 102 and the upper surface 204 of the encapsulation 202 together form a continuous planar surface providing the upper side of the packaged device. In other embodiments, the interconnect clip 100 may extend from the encapsulation 202 such that the upper surface 106 of the first segment 102 is offset from the upper surface 204 of the encapsulation 202 in a vertical direction.

[0086] According to an embodiment, the upper surface 106 of the first segment 102 is substantially parallel to the lower surface 108 of the second segment 104. When mounting the interconnect clip 100, this configuration orients the upper surface 106 of the first segment 102 along a transverse plane parallel to and spaced from the upper surface of the semiconductor die 140, as shown in FIG3. Therefore, when forming the encapsulation 202, for example as... Figure 4 As shown, the upper surface 106 of the first segment 102 is positioned coplanar with the upper surface 204 of the encapsulation 202.

[0087] According to an embodiment, the upper surface 106 of the first segment 102 exposed from the encapsulation 202 extends laterally across the outer edge side 146 of the semiconductor die 140 in each direction. This means that the outer edge side 146 of the semiconductor die 140 is laterally contained within the perimeter of the exposed conductive material of the first segment 102.

[0088] According to an embodiment, the encapsulation 202 includes a central portion 206 directly interfaced with the inner edge side 114 of the first segment 102. The central portion 106 of the encapsulation 202 extends to the upper surface 204 of the encapsulation 202, which may be coplanar with the upper surface 106 of the first segment 102 and / or with the upper surface 204 of the encapsulation 202 outside the perimeter of the first segment 102. According to an embodiment, the central portion 206 of the encapsulation 202 completely covers the upper surface 106 of the second segment 104.

[0089] The semiconductor package 200 of FIG. 5 can be mounted on a carrier (e.g., a printed circuit board) in a manner generally known. The carrier may include a socket with a heat sink that, when mounted, accommodates the semiconductor package 200 and interfaces with the die pad 130. A second heat sink may be mounted on top of the semiconductor package 200. Interconnect clip 100 provides a conductive path for heat to be dissipated from the top of the package via the second heat sink. Highly efficient heat transfer can occur due to the advantageously large exposed surface area of ​​the interconnect clip 100 as described above.

[0090] Referring to FIG6, a semiconductor package 200 including an interconnect clip 100 is depicted according to another embodiment. The semiconductor package 200 in the embodiment of FIG6 is configured equivalently to the semiconductor package 200 of FIG5, except that it additionally includes a hot plug 208. The heat column 208 is a discrete piece of thermally conductive material, for example, it may be a metal such as copper, aluminum, alloys, etc., or alloys thereof. The bottom surface of the heat column 208 is attached to the upper surface 106 of the second segment 104, for example, by a conductive adhesive such as solder, sintering agent, or tape. The heat column 208 extends to the upper surface of the encapsulation 202 such that the upper surface of the heat column 208 is exposed within the central opening 110. According to an embodiment, the upper surface of the heat column 208 is substantially coplanar with the upper surface 204 of the encapsulation 202 and / or substantially coplanar with the upper surface 106 of the first planar segment 102. In this example, the central portion 206 of the encapsulation 202 fills the area between the heat column 208 and the inner edge side 114 of the first segment 102. The described combination of the heat column 208 and the interconnect clip 100 may be preferred in some applications to provide further heat dissipation.

[0091] Referring to FIG. 7, a semiconductor package 200 according to another embodiment is depicted. Except for the lead configuration, the semiconductor package 200 is equivalent to the semiconductor package 200 described with reference to FIG. 5. The semiconductor package 200 of FIG. 7 is configured as a “leadless” or “zero-lead” package. According to this design, the package includes contacts 210 coplanar with the surface of the encapsulation material 202, instead of leads 134 extending from the package body. These contacts 210 are electrically connected to terminals of the semiconductor die 140 in a manner similar to that described above for the leads 134, and thus provide package-level connection terminals. The interconnect clip 100 described herein can be used to provide connection to one of these contacts 210. Alternatively, the interconnect clip 100 described herein can be provided solely as a heat dissipation feature.

[0092] Referring to FIG8, an interconnect clip 100 according to another embodiment is depicted. The interconnect clip 100 of FIG8 includes a first segment 102 surrounding a central opening 110, and a second segment 104 located below the central opening 110 and vertically separated from the first segment 102 by a support 120. Apart from the differences discussed below, each of these features may have the same properties (e.g., geometry, arrangement, material composition, etc.) as the correspondingly labeled features in the previously discussed embodiments.

[0093] Regarding the first difference from the previously discussed embodiments, the interconnect clip 100 of FIG8 includes only a single support 120 connecting the first segment 102 and the second segment 104. From Figure 8A When viewed from a plan view, the support portion 120 at least partially surrounds the second segment 104. That is, the support portion 120 is a continuous structure surrounding the perimeter of the second segment 104. Therefore, unlike the previously described embodiments, the interconnect clip 100 does not include a plurality of lateral gaps 122 between the plurality of discrete support portions 120.

[0094] According to the depicted embodiment, the support portion 120 surrounds the entire perimeter of the second segment 104. That is, the support portion 120 forms a complete closed loop that completely surrounds and abuts the second segment 104. Furthermore, the support portion 120 completely reaches and abuts the inner edge side 114 of the first segment 102 facing the central opening 110. Thus, the second segment 104 and the support portion 120 are jointly configured as a closed depression extending downward from the first segment 102.

[0095] In other embodiments, the support portion 120 may have a variety of opening shapes, such as C-shaped, U-shaped, etc. In any case, the support portion 120 may continuously cover a large percentage of the perimeter of the second segment 104. For example, the support portion 120 may continuously contact at least 50%, 75%, 95% or more of the total length of the perimeter of the second segment 104. In terms of angle, viewed from the center of the second segment 104, the support portion 120 may surround the second segment by at least 180°, 270°, 330° or more. In the case where the second segment 104 has acute corners, for example, in the case of a rectangle, the support portion may cover at least one of these corners.

[0096] Regarding the second difference from the previously discussed embodiments, the first segment 102 of the interconnect clip 100 of FIG8 has a different geometry when viewed from the plan view of FIG8. In the depicted example, the first segment 102 having an L-shaped geometry means having a geometry with two intersecting rectangular portions. More generally, the first segment 102 can have a wide range of various geometries. For example, the first segment 102 may include rounded portions. In another example, the first segment 102 may have a basically square geometry, as depicted in the embodiment of FIG1. ​​The choice of the specific geometry of the first segment 102 can depend on design considerations such as package type, die size, lead configuration, etc.

[0097] The interconnect clip 100 of Figure 8 can be formed according to the techniques described below. Initially, a planar metal sheet is provided, for example, a flat metal plate such as copper, aluminum, or their alloys. Subsequently, the planar metal sheet is shaped to form the desired geometry of the first planar portion, for example, the L-shaped geometry in the illustrated example. This is done, for example, using cutting and / or trimming techniques. Subsequently, an embossing process is performed. The embossing process offsets the portion of the planar metal sheet corresponding to the desired shape of the second segment 104. The offset portion of the planar metal sheet extending into the second segment 104 corresponds to the support portion 120. For example, this embossing process can be performed using known embossing or stamping techniques. Generally, the depth of the embossing can be selected to ensure a sufficient vertical separation distance between the upper surface 106 of the second segment 104 and the upper surface 106 of the first segment 102. More specifically, embossing can be performed to ensure that the upper surface 106 of the second segment 104 remains covered during polishing or grinding of the encapsulation, for example, according to the techniques described below. An example value for this vertical offset can be in the range of 200 μm to 1000 μm. Alternatively, the interconnect clip 100 of FIG8 can be formed by initially performing an embossing process and subsequently shaping the sheet metal (e.g., by cutting and / or trimming).

[0098] As shown in the figure, the position of the relief is chosen such that the single point of the central opening 114 (in this case, the corner) connects with the inner corner 150 of the L-shaped first segment 102. More generally, the position and size of the relief can be selected to meet a variety of design considerations, such as chip size, bonding pad structure, etc.

[0099] One advantage of the interconnect clip 100 of Figure 8 is the enhanced heat transfer between the second segment 104 and the first segment 102. In any of the embodiments described herein, the support portion(s) 120 represents a bottleneck point in the heat conduction path of the interconnect clip 100. Accordingly, during operation, the highest temperatures may occur within the support portion 120 and / or near the transition zone between the support portion 120 and the first and second segments 102, 104. The design of the support portion 120 in the interconnect clip 100 of Figure 8 advantageously extends this bottleneck point across a large cross-sectional diameter. By comparison, while the multiple discrete support portion structures 120 in the previously described embodiments of the interconnect clip 100 are advantageous for other considerations (e.g., enhanced molding adhesion), they limit the heat conduction path to a narrower cross-sectional diameter, thereby limiting heat transfer.

[0100] Another advantage of the interconnect clip 100 in Figure 8 is its ease of manufacture. Because the second segment 104, the first segment 102, and the support portion 120 can be formed as a single integral part of a monolithic metal sheet, only minimal processing steps are required. Specifically, only the embossing step described above (e.g., stamping or embossing) is necessary to form the second segment 104 and the support portion 120 with the described geometry and their relationship to the first segment 102. This embossing step readily forms contact pads that can achieve full or near-full contact with the die surface. Any burrs generated by the trimming process will not contact the die due to the formation of the depression (i.e., the second segment 104). Furthermore, the cutting and / or trimming techniques used for shaping the interconnect clip can readily produce an interconnect clip 100 with any desired geometry.

[0101] Referring to FIG. 9, a semiconductor package 200 according to an embodiment is depicted, including the interconnect clip 100 from the embodiment of FIG. 8. In FIG. 9, the encapsulation 202 is depicted as semi-transparent, allowing the internal features of the semiconductor package 200 to be seen. The semiconductor package 200 includes die pads 130, conductive leads 134, and a semiconductor die 140. Each of these features may be similar to or equivalent to the correspondingly labeled features in the semiconductor package 200 described with reference to FIG. 5. The semiconductor die 140 is mounted on the die attachment surface 132 of the die pads 130 in a manner similar to that previously described, wherein the first bonding pad 142 faces away from the die attachment surface 132.

[0102] The interconnect clip 100 is mounted in a manner similar to that previously described, wherein the second segment 104 is flush with the semiconductor die 140 and is electrically connected to the first bonding pad 142. The opposite end of the interconnect clip 100 in the first segment 102 contacts a pad segment of the lead frame 128, which is connected to multiple leads 134. In both connections, a conductive bonding material such as solder, sintering agent, conductive adhesive, etc., can be provided between the two surfaces to form a reliable mechanical and electrical connection. Unlike the embodiment of FIG. 5, the leads 134 of the package of FIG. 9 are offset vertically from the die pad 130. Therefore, the interconnect clip 100 can directly contact these offset leads at the lower surface 108 of the first planar portion 102. Alternatively, if a vertical drop is required to implement this electrical connection, the end of the first segment 102 may include a structure similar to or equivalent to the previously described end connector 124.

[0103] like Figure 9C and Figure 9D As shown, the geometry of the second planar portion 104 reflects the geometry of the first bonding pad 142 of the semiconductor chip, i.e., a basic rectangular shape with a small notch in the lower corner. Since the first bonding pad 142 occupies a large portion (e.g., at least 90% of the total area) of the upper surface of the semiconductor die 140, the geometry of the second planar portion 104 is adapted to maximize heat extraction capability. Meanwhile, the semiconductor die 140 includes a second bonding pad 152 located outside the coverage area of ​​the interconnect clip 100. The second bonding pad 152 can be a control terminal of the semiconductor die, such as a gate terminal, base terminal, etc. The second bonding pad 152 can be electrically connected via a conductive bonding wire 154 to a single lead 134, which is isolated from the leads to which the interconnect clip 100 is connected. The L-shaped configuration of the interconnect clip 100 allows access to the second bonding pad 152, thereby enabling this electrical connection before or after the interconnect clip 100 is installed.

[0104] Unlike the embodiment described with reference to FIG. 5, the semiconductor package 200 of FIG. 9 is configured such that the interconnect clip 100 is exposed at the lower side 212 of the encapsulation 202 corresponding to the interface connection side of the package 200 (e.g., Figure 9D (As indicated in the diagram). The interface connection side refers to the side where the lead 134 extends at least to the plane of the encapsulation, thereby enabling the package to be mounted to and electrically connected to a substrate (e.g., a PCB). In this arrangement, the interconnect clip 100 acts as a bottom-side cooling feature that can cooperate with a heat sink mechanism in the substrate. Meanwhile, the die pad 130 is exposed at the upper surface 204 of the encapsulation (as shown in the diagram). Figure 9D (as indicated in the figure), and can mate with a heat sink structure connected to the second top side. Therefore, the cooling side of the interconnect clip 100 is flipped compared to the embodiment in FIG5.

[0105] refer to Figure 10 In Figure 9, the semiconductor package 200 is depicted as having an opaque encapsulation 202. The encapsulation 202 has a configuration similar to the previously described embodiments, wherein the encapsulation 202 completely covers the semiconductor die 140, and the upper surface 106 of the first segment 102 of the interconnect clip 100 is exposed from the upper surface 204 of the encapsulation 202. The upper surface 106 of the first segment 102 is exposed from the encapsulation 202. In the depicted embodiment, the upper surface 106 of the first segment 102 is substantially coplanar with the lower side 212 of the encapsulation 202.

[0106] According to an embodiment, Figure 10 The encapsulation 202 of the semiconductor package is formed by a two-step process, wherein the encapsulation 202 is initially formed to completely cover the interconnect clip 100, and then the lower side 212 of the encapsulation 202 is planarized (e.g., by polishing or grinding) until the upper surface 106 of the first segment 102 is exposed from the encapsulation 202 and substantially coplanar with the encapsulation 202.

[0107] Similar to the previously described embodiments, Figure 10 The interconnect clip 100 in the package provides a highly conductive transport path between the semiconductor die 140 and the lead 134. At the same time, the interconnect clip 100 provides a highly thermally conductive transport path at the exposed upper surface 106 of the first segment 102, thus allowing for efficient heat extraction.

[0108] More generally, the principles described herein can be applied to a wide range of diverse package constructions. In general, these package constructions include any package design in which heat dissipation is desired on the upper surface of the semiconductor die, and / or in which the semiconductor die includes at least one upward-facing bonding pad requiring electrical connection. Examples of these package constructions include leaded packages, leadless packages, chip carrier packages, surface mount packages, stacked die packages, molded packages, chamber packages, and so on.

[0109] As used herein, the term "substantially" encompasses absolute conformity to a specific requirement as well as minor deviations from that requirement attributable to variations in manufacturing processes, assembly, and other factors that may cause deviations from design objectives. The term "substantially" will cover any deviations that are within the process tolerances required to achieve practical conformity, and that the component described herein functions according to application requirements.

[0110] The terms “electrical connection”, “direct electrical connection”, etc., used in this document describe permanent low-impedance connections between electrically connected components, such as direct contact between related components or low-impedance connections achieved via metals and / or highly doped semiconductors.

[0111] Spatial relative terms such as “below,” “under,” “down,” “above,” and “up” are used for convenience in describing the positioning of one element relative to a second element. These terms are intended to cover different device orientations other than those shown in the figures. Furthermore, terms such as “first,” “second,” etc., are used to describe various elements, regions, segments, etc., and these terms are not intended to be limiting. Similar reference numerals throughout this specification denote similar elements.

[0112] As used herein, the terms “having,” “comprising,” “including,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. As used herein, the singular article is intended to include both the plural and the singular unless the context clearly indicates otherwise.

[0113] Having understood the variations and applications described above, it should be understood that this invention is not limited by the foregoing description or the accompanying drawings. Rather, this invention is defined only by the claims and their legal equivalents.

Claims

1. A semiconductor package, comprising: A die pad, the die pad including a die attachment surface; A semiconductor die, the semiconductor die being mounted on a die attachment surface, and the semiconductor die including a first bonding pad and a second bonding pad on an upper surface of the semiconductor die opposite to the die attachment surface. Interconnect clip, the interconnect clip comprising: The first section at least partially surrounds the central opening; A second segment, which is offset vertically from and spaced apart from the first segment; and A support portion extending between the first section and the second section; and An electrically insulating encapsulation covering the semiconductor die. The upper surface of the first segment of the interconnect clip is exposed from the planar surface of the encapsulation. The lower surface of the second segment is flush with the upper surface of the semiconductor die, and the lower surface of the second segment is conductively connected to the first bonding pad. From the perspective of the plan view of the interconnect clip, the second bonding pad is outside the coverage area of ​​the interconnect clip. From the perspective of the plan view of the interconnect clip, the interconnect clip has an L-shaped geometry, and The first segment includes a first elongated span and a second elongated span intersecting the first elongated span, wherein the first elongated span and the second elongated span form the inner corner of the outer edge of the interconnect clip, and wherein the central opening is connected to the inner corner.

2. The semiconductor package according to claim 1, wherein, The second section is a planar pad with a closed geometric structure, wherein, from the perspective of the plan view of the interconnect clip, the support surrounds the perimeter of the second section.

3. The semiconductor package according to claim 2, wherein, The second segment has a rectangular geometry, and wherein, from the perspective of the plan view of the interconnecting clip, the support surrounds at least one corner of the second segment.

4. The semiconductor package according to claim 2, wherein, The support portion forms a complete closed loop extending between the outer edge of the second section and the inner edge of the first section facing the central opening.

5. A method for packaging a semiconductor device, the method comprising: Provides die pads including die attachment surfaces; A semiconductor die is provided, the semiconductor die including a first bonding pad and a second bonding pad on the upper surface of the semiconductor die; The semiconductor die is mounted on the die pad, such that the first bonding pad is away from the die attachment surface; An interconnect clip is provided, the interconnect clip comprising: The first section at least partially surrounds the central opening; A second segment, which is offset vertically from and spaced apart from the first segment; and A support portion extending between the first section and the second section; The interconnect clip is mounted on the semiconductor die such that the lower surface of the second segment is flush with the upper surface of the semiconductor die, and the lower surface of the second segment is conductively connected to the first bonding pad; and An electrically insulating encapsulation is formed, such that the semiconductor die is covered by the encapsulation, and the upper surface of the first segment of the interconnect clip is exposed from the upper surface of the encapsulation. From the perspective of the plan view of the interconnect clip, the second bonding pad is outside the coverage area of ​​the interconnect clip. From the perspective of the plan view of the interconnect clip, the interconnect clip has an L-shaped geometry, and The first segment includes a first elongated span and a second elongated span intersecting the first elongated span, wherein the first elongated span and the second elongated span form the inner corner of the outer edge of the interconnect clip, and wherein the central opening is connected to the inner corner.

6. The method according to claim 5, wherein, The second segment is a planar pad with a closed geometric shape, wherein, from the perspective of the plan view of the interconnect clip, the first segment surrounds the perimeter of the second segment.

7. The method according to claim 5, wherein, The encapsulation is formed such that the upper surface of the first segment of the interconnect clip is substantially coplanar with the upper surface of the encapsulation, and wherein forming the encapsulation includes completely covering the interconnect clip with the encapsulation, and subsequently planarizing the encapsulation until the upper surface of the first segment is exposed from the planar surface of the encapsulation.

8. An interconnect clip, comprising: The first section at least partially surrounds the central opening; The second segment is offset from and separated from the first segment in the vertical direction; as well as One or more support portions, the one or more support portions extending between the first section and the second section, From the perspective of the plan view of the interconnect clip, the interconnect clip has an L-shaped geometry, and The first segment includes a first elongated span and a second elongated span intersecting the first elongated span, wherein the first elongated span and the second elongated span form the inner corner of the outer edge of the interconnect clip, and wherein the central opening is connected to the inner corner.

9. The interconnect clip according to claim 8, wherein, The one or more support portions extend diagonally between the outer edge of the second section and the inner edge of the first section facing the central opening.

10. The interconnect clip according to claim 8, wherein, The interconnecting clip includes a plurality of support portions extending between the first segment and the second segment, each of the support portions being separated from the others by a lateral gap.

11. The interconnect clip according to claim 8, wherein, The number of the support portions extending between the first section and the second section is one.

12. The interconnect clip according to claim 11, wherein, The second section is a planar pad with a closed geometric structure, wherein, from the perspective of the plan view of the interconnect clip, the support surrounds the perimeter of the second section.

13. The interconnect clip according to claim 12, wherein, The second segment has a rectangular geometry, and wherein, from the perspective of the plan view of the interconnecting clip, the support surrounds at least one corner of the second segment.

14. The interconnect clip according to claim 12, wherein, The support portion forms a complete closed loop extending between the outer edge of the second section and the inner edge of the first section facing the central opening.

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