Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure penetrating the plurality of gate electrodes in the memory cell region and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate; a dummy channel structure penetrating the plurality of gate electrodes in the connection region and including a dummy channel layer extending in the vertical direction; a first semiconductor layer disposed between the substrate and a lowermost gate electrode of the plurality of gate electrodes and surrounding the channel structure in the memory cell region; and an insulating separation structure disposed between the substrate and the lowermost gate electrode of the plurality of gate electrodes and surrounding the dummy channel layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0052383, filed on May 3, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically, to a semiconductor device including a channel structure extending in a vertical direction and a method of manufacturing the semiconductor device. Background Technology

[0003] As the integration density of memory devices increases, memory devices with vertical transistor structures are better suited to meet the demands than those with traditional planar transistor structures. Memory devices with vertical transistor structures include channel structures disposed on a substrate and extending in a vertical direction perpendicular to the upper surface of the substrate. However, as the number of gate electrodes stacked in the vertical direction increases to increase the integration density of memory devices, it becomes increasingly difficult to manufacture these devices. Summary of the Invention

[0004] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer extending in a vertical direction perpendicular to the upper surface of the substrate; a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer extending in a vertical direction; a first semiconductor layer disposed in the memory cell region and disposed between the substrate and the lowermost gate electrode of the plurality of gate electrodes, the first semiconductor layer at least partially surrounding the channel structure; and an insulating separation structure disposed between the substrate and the lowermost gate electrode of the plurality of gate electrodes and at least partially surrounding the dummy channel layer.

[0005] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer and a gate insulating layer extending in a vertical direction perpendicular to the upper surface of the substrate; a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer and a dummy gate insulating layer extending in a vertical direction; and a first semiconductor layer disposed in the memory cell region and disposed between the substrate and the lowermost gate electrode of the plurality of gate electrodes. A gate insulating layer separation region is formed at the lower part of the channel structure. The first semiconductor layer at least partially surrounds the channel layer in the gate insulating layer separation region. The dummy gate insulating layer covers the outer wall of the dummy channel layer.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer extending in a vertical direction perpendicular to the upper surface of the substrate; a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer extending in a vertical direction; and a first semiconductor layer disposed in the memory cell region and disposed between the substrate and the lowermost gate electrode of the plurality of gate electrodes, the first semiconductor layer at least partially surrounding the channel structure. A gate insulating layer separation region is formed at the lower portion of the channel structure. The first semiconductor layer at least partially surrounds the channel layer in the gate insulating layer separation region. The dummy channel structure may be spaced apart from the first semiconductor layer.

[0007] According to an exemplary embodiment of the inventive concept, a method of manufacturing a semiconductor device includes: forming a substrate including a memory cell region and a connection region; forming a sacrificial layer in the memory cell region and an etch stop layer in the connection region; forming a molded stack on the sacrificial layer and the etch stop layer; forming a channel structure in the memory cell region and a dummy channel structure in the connection region, the channel structure and the dummy channel structure penetrating the molded stack; forming a word line dicing opening penetrating the molded stack; removing a portion of the sacrificial layer in a region of the sacrificial layer exposed through the word line dicing opening to expose the sidewalls of the channel structure; and forming a first semiconductor layer in the region from which the sacrificial layer has been removed. The channel structure includes a channel layer and a gate insulating layer. The dummy channel structure includes a dummy channel layer and a dummy gate insulating layer. Attached Figure Description

[0008] Figure 1 This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0009] Figure 2 This is a plan view illustrating a representative structure of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0010] Figure 3 It is along Figure 2 The sectional view taken by line A1-A1'.

[0011] Figure 4 It is along Figure 2 The sectional view taken by line A2-A2'.

[0012] Figure 5 It is along Figure 2 The sectional view taken by line A3-A3'.

[0013] Figure 6 Is Figure 5 A horizontal section view at the first vertical level LV1.

[0014] Figure 7 yes Figure 6 A magnified view of part of BX1.

[0015] Figure 8 yes Figure 5 A magnified view of part of the CX1.

[0016] Figure 9 yes Figure 5 A magnified view of part of the CX2.

[0017] Figure 10 and Figure 11 This is a cross-sectional view showing an exemplary embodiment of a semiconductor device according to the inventive concept.

[0018] Figure 12 Is Figure 10 A horizontal section view at the first vertical level LV1.

[0019] Figures 13 to 23 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0020] Figure 24 This is a cross-sectional view showing an exemplary embodiment of a semiconductor device according to the inventive concept.

[0021] Figures 25A to 37B This is a schematic diagram illustrating stages in a method for manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0022] Exemplary embodiments of the inventive concept will now be described more fully below with reference to the accompanying drawings. Throughout this application, the same reference numerals denote the same elements.

[0023] Figure 1 This is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an exemplary embodiment of the inventive concept, and more specifically, an equivalent circuit diagram of a vertical NAND (VNAND) flash memory device according to an exemplary embodiment of the inventive concept.

[0024] Reference Figure 1 The memory cell array (MCA) includes components mounted on a substrate (not shown) in the vertical direction. Figure 1 Multiple memory cell strings MS are arranged in the Z-direction. The vertical direction (Z-direction) can be perpendicular to the main surface of the substrate. Each of the multiple memory cell strings MS can include multiple memory cells MC1, ..., MCn-1 and MCn connected in series, a string select transistor SST, and a ground select transistor GST. The multiple memory cells MC1, MC2, ..., MCn-1 and MCn can store data. Multiple word lines WL1, WL2, ..., Wn-1 and Wn can be connected to the multiple memory cells MC1, MC2, ..., MCn-1 and MCn respectively to control a corresponding memory cell among the multiple memory cells MC1, MC2, ..., MCn-1 and MCn.

[0025] The gate terminal of the ground select transistor GST can be connected to the ground select line GSL, and the source terminal of the ground select transistor GST can be connected to the common source line CSL. The gate terminal of the series select transistor SST can be connected to the series select line SSL. The source terminal of the series select transistor SST can be connected to the drain terminal of a corresponding memory cell among multiple memory cells MC1, MC2, ..., MCn-1 and MCn. The drain terminal of the series select transistor SST can be connected to a corresponding bit line among multiple bit lines BL (BL1, BL2, ... and BLm). Figure 1 The illustration exemplarily shows each memory cell string (MS) including one ground select transistor (GST) and two string select transistors (SST), but the inventive concept is not limited thereto. For example, each memory cell string (MS) may include one or three or more ground select transistors and one or three or more string select transistors.

[0026] When a signal is applied to the gate terminal of the serial select transistor SST via the serial select line SSL, signals applied via multiple bit lines BL can be provided to multiple memory cells MC1, MC2, ..., MCn-1 and MCn to perform data write operations. When a signal is applied to the gate terminal of the ground select transistor GST via the ground select line GSL, erase operations can be performed on multiple memory cells MC1, MC2, ..., MCn-1 and MCn.

[0027] Figures 2 to 9This is a view illustrating an exemplary semiconductor device according to an inventive concept. Figure 2 This is a plan view illustrating a representative structure of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 3 It is along Figure 2 The sectional view taken by line A1-A1'. Figure 4 It is along Figure 2 The sectional view taken by line A2-A2'. Figure 5 It is along Figure 2 A sectional view taken from line A3-A3'. Figure 6 Is Figure 5 A horizontal section view at the first vertical level LV1. Figure 7 yes Figure 6 A magnified view of part of BX1. Figure 8 yes Figure 5 A magnified view of part of the CX1. Figure 9 yes Figure 5 A magnified view of part of the CX2. Figure 2 For ease of explanation and understanding, some components of a semiconductor device are shown in the diagram.

[0028] Reference Figures 2 to 9 In the semiconductor device 100 according to an exemplary embodiment, the substrate 110 includes a memory cell region MCR, a connection region CON, and a peripheral circuit region PERI. The connection region CON may be disposed between the memory cell region MCR and the peripheral circuit region PERI. A memory cell array MCA is disposed in the memory cell region MCR. The memory cell array MCA may be included as shown in reference... Figure 1 In a vertical channel NAND memory device operating in the manner described, a peripheral circuit transistor 190T for driving the memory cell array MCA is disposed in the peripheral circuit region PERI. The peripheral circuit transistor 190T includes a peripheral circuit active region 192, a peripheral circuit gate electrode 194 disposed on the peripheral circuit active region 192, and a peripheral circuit contact 196 connecting the peripheral circuit active region 192 and the peripheral circuit gate electrode 194. The connection region CON may include a pad (also referred to as a "solder pad") portion PAD for connecting the memory cell array MCA and the peripheral circuit transistor 190T in the memory cell region MCR.

[0029] like Figure 3As shown, substrate 110 may include a main surface 110M extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The main surface 110M of substrate 110 may be, for example, the upper surface of substrate 110. The first horizontal direction (X direction) and the second horizontal direction (Y direction) may be parallel to the main surface 110M of substrate 110 and may be perpendicular to each other. Substrate 110 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (Si-Ge). Substrate 110 may be a bulk wafer or an epitaxial layer. In some embodiments, substrate 110 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0030] A first semiconductor layer 122 and a second semiconductor layer 124 are sequentially disposed in a memory cell region (MCR) of a substrate 110. The first semiconductor layer 122 and the second semiconductor layer 124 may extend in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The first semiconductor layer 122 may comprise undoped polysilicon or doped polysilicon, and the second semiconductor layer 124 may comprise undoped polysilicon or doped polysilicon. The first semiconductor layer 122 may be used as a common source line extension region and may be connected with… Figure 1 This corresponds to a portion of the common source line CSL. The first semiconductor layer 122 can be disposed on the main surface 110M.

[0031] A lower gate stack 130S is disposed on a substrate 110 and can extend in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The lower gate stack 130S is disposed on a second semiconductor layer 124. The lower gate stack 130S includes a plurality of lower gate electrodes 132 and a plurality of lower insulating layers 134. The plurality of lower gate electrodes 132 and the plurality of lower insulating layers 134 can be alternately arranged in a vertical direction (Z direction) perpendicular to the main surface 110M of the substrate 110.

[0032] like Figure 8 As shown, in an exemplary embodiment, each of the lower gate electrodes 132 includes a buried conductive layer 132A and a conductive barrier layer 132B covering the upper surface, lower surface and sidewalls of the buried conductive layer 132A.

[0033] like Figure 3As shown, an upper gate stack 135S is disposed on a lower gate stack 130S. The upper gate stack 135S includes a plurality of upper gate electrodes 136 and a plurality of upper insulating layers 138. The plurality of upper gate electrodes 136 and the plurality of upper insulating layers 138 can be arranged alternately along the vertical direction (Z direction). A first interlayer insulating layer 144 is disposed between the lower gate stack 130S and the upper gate stack 135S. For example, the first interlayer insulating layer 144 can contact the highest layer in the lower insulating layer 134 and the lowest layer in the upper insulating layer 138. A second interlayer insulating layer 146 and an upper interlayer insulating layer 148 can be sequentially disposed on the upper gate stack 135S. For example, the second interlayer insulating layer 146 can be disposed on the upper gate stack 135S. For example, the second interlayer insulating layer 146 can be disposed on the highest layer in the upper insulating layer 138.

[0034] In an exemplary embodiment, the plurality of lower gate electrodes 132 and the plurality of upper gate electrodes 136 correspond to Figure 1 The diagram shows the ground select line GSL, word lines WL1, WL2, ..., WLn-1 and WLn, and the serial select line SSL constituting the memory cell string MS. For example, the lowermost gate electrode 132 can be used as the ground select line GSL, the uppermost gate electrode 136 can be used as the serial select line SSL, and the remaining lower gate electrodes in the lower gate electrode 132 and the remaining upper gate electrodes in the upper gate electrode 136 can be used as word lines WL1, WL2, ..., WLn-1 and WLn. In some embodiments, the uppermost of the remaining upper gate electrodes in the upper gate electrode 136 is used as a dummy word line. Therefore, a memory cell string MS can be provided in which the ground select transistor GST, the serial select transistor SST, and the memory cell transistors MC1, MC2, ..., MCn-1 and MCn connected in series between the ground select transistor GST and the serial select transistor SST can be provided.

[0035] like Figure 2 As shown, multiple word line cut regions (WLCs) are disposed on the substrate 110 and can extend in a first horizontal direction (X direction). A lower gate stack 130S and an upper gate stack 135S disposed between a pair of word line cut regions (WLCs) can form a block, and the pair of word line cut regions (WLCs) can define the width of the lower gate stack 130S and the upper gate stack 135S in a second horizontal direction (Y direction).

[0036] Multiple common source lines 180, each perpendicularly stacked with a plurality of word line cutting regions WLC, can all extend in a first horizontal direction (X direction) and can be arranged in a second horizontal direction (Y direction). Insulating spacers 182 can be disposed on the opposite sidewalls of each of the multiple common source lines 180. For example, each of the insulating spacers 182 can be disposed between each of a plurality of lower gate electrodes 132 and each of the multiple common source lines 180, and can be disposed between each of a plurality of upper gate electrodes 136 and each of the multiple common source lines 180. The multiple common source lines 180 can extend into the substrate 110 (or extend to a level below the main surface 110M of the substrate 110).

[0037] like Figure 3 As shown, a plurality of common-source regions 112 may be disposed in the substrate 110 below the common-source line 180 and may be arranged in a second horizontal direction (Y direction). Each of the plurality of common-source regions 112 may be a heavily doped n-type impurity region. Each of the plurality of common-source regions 112 may serve as a source region for supplying current to memory cells. The plurality of common-source regions 112 may be stacked with a plurality of word line cut regions (WLCs), respectively. Each of the common-source regions 112 may contact a portion of the first semiconductor layer 122, so that the first semiconductor layer 122 may be electrically connected to each of the common-source lines 180 through each of the common-source regions 112.

[0038] Reference Figure 3 and Figure 5 Multiple channel structures 150 can pass through the upper gate stack 135S and the lower gate stack 130S in the memory cell region MCR, and can extend from the main surface 110M of the substrate 110 in the vertical direction (Z direction). The multiple channel structures 150 can be arranged at predetermined distances from each other in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a third horizontal direction (e.g., diagonal direction). The multiple channel structures 150 can be arranged in a zigzag or staggered manner.

[0039] Multiple channel structures 150 include a lower channel structure 150L and an upper channel structure 150U. The lower channel structure 150L is disposed in a lower channel via 150HL that penetrates the lower gate stack 130S and the first interlayer insulating layer 144. A gate insulating layer 152 and a channel layer 154 are sequentially disposed on the inner surface of the lower channel via 150HL, and a buried insulating layer 156 is disposed on the channel layer 154 to fill the remaining space of the lower channel via 150HL. A conductive plug 158 is disposed at the top of the lower channel via 150HL and contacts the channel layer 154. In an exemplary embodiment, the conductive plug 158 blocks the entrance to the lower channel via 150HL. Therefore, the upper channel structure 150U may include a gate insulating layer 152, a channel layer 154, a buried insulating layer 156, and a conductive plug 158.

[0040] An upper channel structure 150U is disposed in an upper channel via 150HU that penetrates the upper gate stack 135S and the second interlayer insulating layer 146. A gate insulating layer 152 and a channel layer 154 are sequentially disposed on the inner sidewall of the upper channel via 150HU, and a buried insulating layer 156 is disposed on the channel layer 154 to fill the remaining space of the upper channel via 150HU. A conductive plug 158 is disposed at the top of the upper channel via 150HU and contacts the channel layer 154. In an exemplary embodiment, the conductive plug 158 blocks the entrance to the upper channel via 150HU. In an exemplary embodiment, the buried insulating layer 156 is omitted, and the channel layer 154 is formed in a pillar shape to fill the remaining space of the lower channel via 150HL and the upper channel via 150HU. For example, when the buried insulating layer 156 is omitted, the channel layer 154 can be enlarged to occupy the volume occupied by the buried insulating layer 156.

[0041] Reference Figure 8 The gate insulating layer 152 (e.g., 152L) includes a tunnel insulating layer 152A, a charge storage layer 152B, and a barrier insulating layer 152C sequentially disposed on the sidewall 154S of the channel layer 154. The thickness of each of the tunnel insulating layer 152A, the charge storage layer 152B, and the barrier insulating layer 152C is not limited to... Figure 8 The thickness shown can be varied.

[0042] The tunnel insulating layer 152A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, and / or tantalum oxide. The charge storage layer 152B may store the charge passing through the tunnel insulating layer 152A from the channel layer 154, and may include silicon nitride, boron nitride, silicon boron nitride, or doped polysilicon. The barrier insulating layer 152C may include silicon oxide, silicon nitride, and / or a metal oxide having a dielectric constant higher than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof.

[0043] A gate insulating layer separation region 152SR may be formed at the lower portion of the lower channel via 150HL. The sidewalls 154S of the channel layer 154 may be at least partially surrounded by a first semiconductor layer 122 at the gate insulating layer separation region 152SR. For example, the first semiconductor layer 122 may contact a portion of the sidewalls 154S. Here, the portion of the gate insulating layer 152 located at a level higher than the gate insulating layer separation region 152SR may be referred to as the lower gate insulating layer 152L, and the portion of the gate insulating layer 152 located at a level lower than the gate insulating layer separation region 152SR may be referred to as the bottom gate insulating layer 152F. In an exemplary embodiment, the bottom gate insulating layer 152F is spaced apart from the lower gate insulating layer 152L in the vertical direction (Z direction). The first semiconductor layer 122 may contact between the bottom gate insulating layer 152F and the lower gate insulating layer 152L and at least partially surround the sidewalls 154S of the channel layer 154. For example, a portion of the first semiconductor layer 122 may be placed between the bottom gate insulating layer 152F and the bottom gate insulating layer 152L to space these layers apart from each other.

[0044] In an exemplary embodiment, such as Figure 8 As shown, the first semiconductor layer 122 includes protrusions 122P that project upward and downward in the vertical direction (Z direction) at portions of the lower gate insulating layer 152L and the bottom gate insulating layer 152F. In an exemplary embodiment, the portion of the protrusion 122P of the first semiconductor layer 122 that contacts the barrier insulating layer 152C protrudes further than the portion of the protrusion 122P that contacts the tunnel insulating layer 152A and the charge storage layer 152B, thereby forming a raised step 122PS at the protrusion 122P. However, the inventive concept is not limited thereto.

[0045] like Figure 3 As shown, the bit line contact BLC can penetrate the upper interlayer insulating layer 148 and contact the conductive plug 158 of the upper channel structure 150U. In an embodiment, the bit line BL is disposed on the upper interlayer insulating layer 148 to contact the bit line contact BLC. The bit line BL can extend in a second horizontal direction (Y direction). When data is read from the memory cell array MCA, data can be read from the bit line BL. When data is written to the memory cell array MCA, data can be applied to the bit line BL to write the data to the memory cell array MCA.

[0046] In a block, the uppermost gate electrode 136 can be divided into two parts in a plan view by a series-separating insulating layer 174. The series-separating insulating layer 174 can extend from the same level as the upper surface of the second interlayer insulating layer 146 to a level below the lower surface of the uppermost gate electrode 136. In some embodiments, different Figure 3As shown, the series separation insulating layer 174 extends from the same level as the upper surface of the second interlayer insulating layer 146 to the level below the lower surface of the next uppermost upper gate electrode 136, such that each of the two uppermost upper gate electrodes is separated into two parts in the plan view by the series separation insulating layer 174.

[0047] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7 In the connection region CON, an insulating separation structure 160 is disposed on the substrate 110. The insulating separation structure 160 includes a first insulating layer 162 disposed on the substrate 110, a second insulating layer 164 disposed on the first insulating layer 162, and an etch stop layer 166 covering the sidewalls of the first insulating layer 162 and the sidewalls of the second insulating layer 164. The first insulating layer 162 and the etch stop layer 166 may include materials having etch selectivity relative to the second insulating layer 164. For example, the first insulating layer 162 and the etch stop layer 166 may include silicon oxide, and the second insulating layer 164 may include silicon nitride.

[0048] In an embodiment, the etch stop layer 166 includes a first portion 166P1 that is perpendicularly stacked to the word line cutting region WLC (e.g., common source line 180) and extends in a first horizontal direction (X direction), and a second portion 166P2 that extends in a second horizontal direction (Y direction) in the edge of the connection region CON. Figure 7 As shown, the second portion 166P2 of the etch stop layer 166 has a first sidewall 166S1 and a second sidewall 166S2 opposite to the first sidewall 166S1. In an embodiment, the first sidewall 166S1 of the second portion 166P2 of the etch stop layer 166 contacts the sidewalls of the first insulating layer 162 and the second insulating layer 164, and the second sidewall 166S2 of the second portion 166P2 of the etch stop layer 166 contacts the first semiconductor layer 122. In an embodiment, the upper surface of the etch stop layer 166 is located at the same level as the upper surface of the second insulating layer 164. In an embodiment, the lower surface of the etch stop layer 166 is located at a level below the main surface 110M of the substrate 110.

[0049] In an embodiment, such as Figure 4As shown, the first portion 166P1 of the etch stop layer 166 has a width W21 in the second horizontal direction (Y direction) that is larger than the width W31 of the word line dicing region WLC in the second horizontal direction (Y direction). Therefore, the first portion 166P1 of the etch stop layer 166 can cover the bottom surface of the common source line 180 and the bottom surface of the insulating spacer 182 on the sidewall of the common source line 180. In an embodiment, the second insulating layer 164 is spaced apart from the common source line 180 due to the first portion 166P1 of the etch stop layer 166. A portion of the first portion 166P1 of the etch stop layer 166 can be placed between the word line dicing region WLC and the second insulating layer 164. In an embodiment, the second insulating layer 164 is not superimposed on the word line dicing region WLC (e.g., the common source line 180).

[0050] In an embodiment, the second insulating layer 164 is the unremoved portion of the sacrificial layer used to form the first semiconductor layer 122. In a manufacturing process according to an exemplary embodiment of the inventive concept, after forming the first insulating layer 162 and the second insulating layer 164 on the substrate 110, portions of the first insulating layer 162, the second insulating layer 164, and the substrate 110 are removed, and then an etch stop layer 166 is formed in the etched region. For example, portions of the first insulating layer 162, the second insulating layer 164, and the substrate 110 may be removed to create openings, in which the etch stop layer 166 may then be formed. The remaining first insulating layer 162 and the second insulating layer 164 in the memory cell region MCR may respectively refer to the first sacrificial layer (see, for example, ...). Figure 25A 162P) and the second sacrificial layer (see, for example, Figure 25A (164P). When the word line cutting region WLC in the memory cell region MCR is used to make the second sacrificial layer (see, for example, Figure 25A When 164P is exposed, the etch stop layer 166 can be exposed in the connection region CON. Therefore, the second sacrificial layer in the memory cell region MCR is selectively removed only (see, for example, Figure 25A (164P), then remove the first sacrificial layer in the memory cell region MCR (see, for example, Figure 25A The first semiconductor layer 122 is formed between the substrate 110 and the second semiconductor layer 124 in the memory cell region MCR. However, in an exemplary embodiment, the first insulating layer 162 and the second insulating layer 164 are retained and not removed in the connection region CON between the substrate 110 and the second semiconductor layer 124.

[0051] The lower gate stack 130S and the upper gate stack 135S can extend in the connection region CON to form a pad portion PAD. A second semiconductor layer 124 can be disposed on the insulating separation structure 160. The pad portion PAD can be disposed on the second semiconductor layer 124. (Example...) Figure 5As shown, in the connection region CON, as the distance from the main surface 110M of the substrate 110 increases, the plurality of lower gate electrodes 132 and the plurality of upper gate electrodes 136 can extend to have a shorter width in the first horizontal direction (X direction). For example, when the first height is greater than the second height, the width of the lower gate electrode 132 at the first height can be smaller than the width of the lower gate electrode 132 at the second height. For example, when the third height is greater than the fourth height, the width of the upper gate electrode 136 at the third height can be smaller than the width of the upper gate electrode 136 at the fourth height. The pad portion PAD can refer to the portion of the lower gate electrode 132 and the upper gate electrode 136 that is provided in a stepped manner. The lower cover insulating layer 142L can be provided on the portion of the lower gate stack 130S constituting the pad portion PAD. The upper cover insulating layer 142U can be provided on the portion of the upper gate stack 135S constituting the pad portion PAD. Figure 2 As shown, pad contact 172 may be disposed in connection region CON to connect to each of the lower gate electrodes 132 or each of the upper gate electrodes 136.

[0052] Reference Figure 4 and Figure 5 In the connection region CON, multiple dummy channel structures D150 penetrate the upper gate stack 135S and the lower gate stack 130S, and can extend from the main surface 110M of the substrate 110 in the vertical direction (Z direction). Each of the multiple dummy channel structures D150 may include a lower dummy channel structure D150L and an upper dummy channel structure D150U. The lower dummy channel structure D150L is disposed in a lower dummy channel via D150HL that penetrates the first interlayer insulating layer 144, the lower gate stack 130S, and the lower cover insulating layer 142L. The lower dummy channel structure D150L can extend from the main surface 110M of the substrate 110. The upper dummy channel structure D150U is disposed in an upper dummy channel via D150HU that penetrates the second interlayer insulating layer 146, the upper gate stack 135S, and the upper cover insulating layer 142U. The lower dummy channel structure D150L includes a dummy gate insulating layer D152, a dummy channel layer D154, and a dummy buried insulating layer D156 sequentially disposed on the inner surface of the lower dummy channel hole D150HL, and may further include a dummy conductive plug D158 blocking the upper entrance of the lower dummy channel hole D150HL. The upper dummy channel structure D150U includes a dummy gate insulating layer D152, a dummy channel layer D154, and a dummy buried insulating layer D156 sequentially disposed on the inner sidewall of the upper dummy channel hole D150HU, and may further include a dummy conductive plug D158 blocking the upper entrance of the upper dummy channel hole D150HU. The dummy channel structure D150 can be formed to give the semiconductor device 100 structural stability during the manufacturing process of the semiconductor device 100.

[0053] In an embodiment, the lower portion of the dummy channel structure D150 is at least partially surrounded by the second semiconductor layer 124 and the insulating separation structure 160. For example, the lower portion of the lower dummy channel structure D150L may be at least partially surrounded by the second semiconductor layer 124 and the insulating separation structure 160. In an embodiment, the bottom of the dummy channel structure D150 is covered by the substrate 110. For example, the bottom of the lower dummy channel structure D150L may be covered by the substrate 110. Since the dummy gate insulating layer D152 is disposed on the outer surface of the lower dummy channel hole D150HL, the outer sidewall and lower surface of the dummy channel layer D154 may be completely covered by the dummy gate insulating layer D152, and the dummy channel layer D154 does not contact the second semiconductor layer 124, the insulating separation structure 160, or the substrate 110. Furthermore, since the first semiconductor layer 122 and the insulating separation structure 160 are respectively disposed on the substrate 110 in the memory cell region MCR and the connection region CON, the dummy channel structure D150 is not stacked perpendicularly to the first semiconductor layer 122. That is, the dummy channel structure D150 in the connection region CON can be configured to be spaced apart from the first semiconductor layer 122.

[0054] The D150C virtual channel structure can be optionally located in the edge portion of the memory cell region MCR. For example... Figure 7 As shown, the lower portion of the cell dummy channel structure D150C may be at least partially surrounded by the first semiconductor layer 122. In an embodiment, the dummy gate insulating layer D152 is not formed in the portion of the cell dummy channel structure D150C that is at least partially surrounded by the first semiconductor layer 122. In an embodiment, the dummy channel layer D154 of the cell dummy channel structure D150C contacts the first semiconductor layer 122.

[0055] Reference Figure 7 In the first vertical horizontal LV1 (see Figure 5 or Figure 6 At this location, the dummy gate insulating layer D152 of the lower dummy channel structure D150L can be at least partially surrounded by the second insulating layer 164, and can have a sidewall D152S contacting the second insulating layer 164. On the other hand, as Figure 5 As shown, at the first vertical horizontal LV1, the gate insulating layer 152 is not disposed on the channel layer 154 of the lower channel structure 150L, ​​and as... Figure 7As shown, the sidewall 154S of the channel layer 154 contacts the first semiconductor layer 122. In an exemplary embodiment, at the first vertical horizontal level LV1, the lower channel structure 150L has a first width W11 in the first horizontal direction (X direction), and the lower dummy channel structure D150L has a second width W12 in the first horizontal direction (X direction) that is greater than the first width W11. In an exemplary embodiment, the cell dummy channel structure D150C has a third width W13 in the first horizontal direction (X direction) that is greater than the first width W11 and less than the second width W12.

[0056] In the memory cell region MCR, the channel layer 154 exposed at the lower portion of the channel structure 150 contacts the first semiconductor layer 122, thus the channel layer 154 is electrically connected to the common source line 180. In the connection region CON, the dummy channel layer D154 of the dummy channel structure D150 is electrically insulated from the common source line 180 because the lower portion of the dummy channel structure D150 contacts the insulating separation structure 160.

[0057] In the semiconductor device according to the comparative example, in the connection region CON, a first semiconductor layer 122 is formed on the lower portion of the dummy channel structure D150, and the dummy channel layer D154 of the dummy channel structure D150 and the channel layer 154 of the channel structure 150 are jointly connected to the common source line 180 via the first semiconductor layer 122. In this case, due to defects or faults occurring in the dummy channel layer D154 or the dummy gate insulating layer D152 during the manufacturing process of the dummy channel structure D150, defects or faults may occur in the channel structure 150 electrically connected to the dummy channel structure D150 via the common source line 180.

[0058] In the semiconductor device 100 according to an exemplary embodiment of the inventive concept, an insulating separation structure 160 is disposed below a dummy channel structure D150 (e.g., D150L), and the dummy channel layer D154 of the dummy channel structure D150 is not electrically connected to the common source line 180. Therefore, even if defects or faults occur in the dummy channel layer D154 or the dummy gate insulating layer D152 during the manufacturing process of the dummy channel structure D150, the channel structure 150 in the memory cell region MCR can still function normally, thus the semiconductor device 100 can have improved reliability.

[0059] Figure 10 and Figure 11 This is a cross-sectional view showing a semiconductor device 100A according to an exemplary embodiment of the inventive concept. Figure 12 Is Figure 10 A horizontal section view at the first vertical level LV1. Figure 10 Corresponding to along Figure 2 The sectional view taken by line A1-A1'. Figure 11 Corresponding to along Figure 2 The sectional view taken by line A2-A2'. Figures 10 to 12 In the figures, the same reference numerals are used to represent the same figures. Figures 1 to 9 The components shown are the same components.

[0060] Reference Figures 10 to 12 In the semiconductor device 100A according to an exemplary embodiment of the inventive concept, a common source line 180A is connected to a first semiconductor layer 122. The common source line 180A may comprise doped polysilicon and may be formed simultaneously with the first semiconductor layer 122 in the process of forming the first semiconductor layer 122. Figure 11 As shown, a first portion 166P1 of the etch stop layer 166 can cover the bottom of the common source line 180A. Due to the first portion 166P1 of the etch stop layer 166, the common source line 180A can be spaced apart from the second insulating layer 164 in the second horizontal direction (Y direction). For example, the first portion 166P1 can be placed between the common source line 180A and the etch stop layer 166 to prevent the common source line 180A from contacting the etch stop layer 166.

[0061] Figures 13 to 23 This is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Specifically, Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 20 and Figure 22 Corresponding to along Figure 2 The sectional view taken by line A3-A3'. Figure 17 , Figure 18 , Figure 19 , Figure 21 and Figure 23 This is a horizontal sectional view at the first vertical level LV1 in the corresponding attached drawing. Figures 13 to 23 In the figures, the same reference numerals are used to represent the same figures. Figures 1 to 11 The components shown are the same components.

[0062] Reference Figure 13The semiconductor device 100B according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160B having an upper surface located at the same level LV2 as the upper surface of the second semiconductor layer 124. For example, the etch stop layer 166B may have an upper surface coplanar with the upper surface of the second semiconductor layer 124 and may have a lower surface located at a level lower than the main surface 110M of the substrate 110. In the manufacturing process according to an exemplary embodiment of the inventive concept, after the first insulating layer 162, the second insulating layer 164, and the second semiconductor layer 124 are sequentially formed on the substrate 110, portions of the first insulating layer 162, the second insulating layer 164, the second semiconductor layer 124, and the substrate 110 are removed to form a removal region, and then the etch stop layer 166B is formed to fill the removal region.

[0063] Reference Figure 14 The semiconductor device 100C according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160C having an upper surface at the same level LV2A as the upper surface of the lowermost lower gate electrode 132. For example, an etch stop layer 166C may have an upper surface at the same level LV2A as the upper surface of the lowermost lower gate electrode 132, and may have a lower surface at a level lower than the main surface 110M of the substrate 110. In the manufacturing process according to an exemplary embodiment of the inventive concept, a first insulating layer 162, a second insulating layer 164, a second semiconductor layer 124, a lower insulating layer 134, and a lower sacrificial layer (see, for example, ...) are sequentially formed on the substrate 110. Figure 26 After (312), the first insulating layer 162, the second insulating layer 164, the second semiconductor layer 124, the lower insulating layer 134, and the lower sacrificial layer (see example, Figure 26 The portion of the substrate 110 and the portion of the substrate 312) are used to form a removal region, and then an etch stop layer 166C is formed to fill the removal region.

[0064] Reference Figure 15 A semiconductor device 100D according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160D having a lower surface coplanar with the main surface 110M of the substrate 110. For example, an etch stop layer 166D may have an upper surface located at the same level LV2 as the upper surface of the second semiconductor layer 124, and may have a lower surface coplanar with the main surface 110M of the substrate 110. In a manufacturing process according to an exemplary embodiment of the inventive concept, after a first insulating layer 162, a second insulating layer 164, and a second semiconductor layer 124 are sequentially formed on the substrate 110, portions of the first insulating layer 162, the second insulating layer 164, and the second semiconductor layer 124 are removed to form a removal region, and then an etch stop layer 166D is formed to fill the removal region.

[0065] Reference Figure 16 and Figure 17 A semiconductor device 100E according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160E, which includes an etch stop layer 166E comprising a plurality of openings 166EH. In an embodiment, a second insulating layer 164E is disposed in each of the plurality of openings 166EH. Two adjacent dummy channel structures D150 (e.g., D150L) in a second horizontal direction (Y direction) may be disposed in each of the plurality of openings 166EH.

[0066] Reference Figure 18 The semiconductor device 100F according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160F, which includes an etch stop layer 166F that includes a plurality of openings 166FH. A dummy channel structure D150 (e.g., D150L) may be disposed in each of the plurality of openings 166FH. A second insulating layer 164F may be disposed in each of the plurality of openings 166FH and may at least partially surround one of the dummy channel structures D150.

[0067] Reference Figure 19 A semiconductor device 100G according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160G, which includes an etch stop layer 166G comprising a plurality of openings 166GH. Two adjacent dummy channel structures D150 (e.g., D150L) in a second horizontal direction (Y direction) may be disposed in each of the plurality of openings 166GH. In each of the plurality of openings 166GH, an intermediate insulating layer 168 may also be disposed between a second insulating layer 164G and a dummy channel structure D150 (e.g., D150L). The intermediate insulating layer 168 may comprise silicon oxide.

[0068] Reference Figure 20 and Figure 21A semiconductor device 100H according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160H, which includes a plurality of first insulating layers 162H and a plurality of etch stop layers 166H. The plurality of etch stop layers 166H may be disposed on a corresponding one of the plurality of first insulating layers 162H. In an exemplary embodiment, each of the plurality of etch stop layers 166H and each of the plurality of first insulating layers 162H is configured to at least partially surround a sidewall of a dummy channel structure D150 (e.g., D150L). In the connection region CON, in an exemplary embodiment, a third semiconductor layer 122EX is also disposed between the substrate 110 and the second semiconductor layer 124. The third semiconductor layer 122EX may at least partially surround the plurality of etch stop layers 166H and the plurality of first insulating layers 162H. Therefore, the third semiconductor layer 122EX may be spaced apart from the dummy channel structure D150. For example, an etch stop layer 166H and a first insulating layer 162H may be placed between a portion of the third semiconductor layer 122EX and the lower dummy channel structure D150L to prevent the portion of the third semiconductor layer 122EX from contacting the lower dummy channel structure D150L. The third semiconductor layer 122EX may include doped polysilicon and may be formed simultaneously with the first semiconductor layer 122 and the common source line 180A, but the inventive concept is not limited thereto.

[0069] Reference Figure 22 and Figure 23 A semiconductor device 100I according to an exemplary embodiment of the inventive concept includes an insulating separation structure 160I, which includes a first insulating layer 162 and an etch stop layer 166I. The etch stop layer 166I may be disposed on the first insulating layer 162. In an exemplary embodiment, the lower surface level LV3A of the dummy channel structure D150 (e.g., D150L) in the connection region CON is lower than the lower surface level LV3B of the channel structure 150 (e.g., 150L) in the memory cell region MCR. For example, in the process of forming the lower channel via 150HL and the lower dummy channel via D150HL, a level difference may occur between the bottom surface of the lower channel via 150HL and the bottom surface of the lower dummy channel via D150HL due to the difference between the etch rate of the etch stop layer 166I in the connection region CON and the etch rate of the second sacrificial layer 164P in the memory cell region. In an exemplary embodiment, with Figure 22 As shown, the lower surface level LV3A of the dummy channel structure D150 (e.g., D150L) in the connection region CON is equal to or higher than the lower surface level LV3B of the channel structure 150 (e.g., 150L) in the memory cell region MCR.

[0070] Figure 24This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor device according to the inventive concept. Figure 24 In the figures, the same reference numerals are used to represent, for example, Figures 1 to 23 The components shown are the same components.

[0071] Reference Figure 24 In the semiconductor device 200 according to an exemplary embodiment of the inventive concept, the peripheral circuit region PERI2 is located at a vertical level lower than the memory cell region MCR and the connection region CON (or below the memory cell region MCR and the connection region CON). The lower substrate 210 is located at a vertical level lower than the substrate 110. The upper surface level LV4 of the lower substrate 210 is lower than the upper surface level of the substrate 110. An active region can be defined in the lower substrate 210 by means of an isolation layer 222. A plurality of driving transistors 230T are disposed in the active region. In an exemplary embodiment, each of the plurality of driving transistors 230T includes a driving circuit gate structure 232 and an impurity region 212 located on the opposite side of the driving circuit gate structure 232 in the active region of the lower substrate 210.

[0072] Multiple wirings 242, multiple contact plugs 246, and an interlayer insulating layer 250 may be disposed on the lower substrate 210. The multiple contact plugs 246 may be connected between the multiple wirings 242 and between the multiple wirings 242 and the multiple driving transistors 230T. In an exemplary embodiment, the interlayer insulating layer 250 covers the multiple wirings 242 and the multiple contact plugs 246.

[0073] The substrate 110 is disposed on the lower interlayer insulating layer 250. The insulating separation structure 160 can separate the substrate 110 in the memory cell region MCR and the substrate 110 in the connection region CON. For example, the lower surface of the etch stop layer 166 can be coplanar with the lower surface of the substrate 110 and can contact the upper surface of the lower interlayer insulating layer 250.

[0074] Figures 25A to 37B This is a schematic diagram illustrating stages in a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Specifically, Figure 25A , Figure 26 , Figure 27 , Figure 28A , Figure 29 , Figure 31B , Figure 35A and Figure 37B Is along Figure 2 The sectional view corresponding to the section view intercepted by line A3-A3'. Figure 30 , Figure 31A , Figure 36 and Figure 37A Is along Figure 2 The sectional view corresponding to the section view intercepted by line A1-A1'. Figure 25B , Figure 28B , Figure 31C and 35B It is a horizontal sectional view at the first vertical level LV1 in the corresponding figure. Figure 31D , Figure 32 , Figure 33 , Figure 34 and Figure 35C It corresponds to Figure 31B A partial sectional view of CX1. Figures 25A to 37B In the figures, the same reference numerals are used to denote the same figures as those in the figures below. Figures 1 to 24 The components shown are the same components.

[0075] Reference Figure 25A and Figure 25B A first insulating layer 162 and a second insulating layer 164 are formed on the main surface 110M of a substrate 110, which includes a memory cell region MCR and a connection region CON. For example, the first insulating layer 162 is formed on the main surface 110M, and the second insulating layer 164 is formed on the first insulating layer 162. For example, the second insulating layer 164 can be formed using a material that has etch selectivity relative to the first insulating layer 162. For example, the first insulating layer 162 may include silicon oxide, and the second insulating layer 164 may include silicon nitride.

[0076] Subsequently, in the connection region CON, portions of the second insulating layer 164, the first insulating layer 162, and the substrate 110 are removed to form a first removal region, which is then filled with an insulating material to form an etch stop layer 166. In an embodiment, as... Figure 25B As shown, the etch stop layer 166 includes: a first portion 166P1, which is perpendicularly stacked with the word line cut region WLC and extends in a first horizontal direction (X direction); and a second portion 166P2, which extends in a second horizontal direction (Y direction) in the portion of the connection region CON adjacent to the memory cell region MCR. In an exemplary embodiment, the first portion 166P1 of the etch stop layer 166 has a width W21 in the second horizontal direction (Y direction) that is larger than the width W31 of the word line cut region WLC in the second horizontal direction (Y direction).

[0077] After the etch stop layer 166 is formed, the portion of the first insulating layer 162 retained in the memory cell region MCR and the portion of the second insulating layer 164 retained in the memory cell region MCR can be referred to as the first sacrificial layer 162P and the second sacrificial layer 164P, respectively.

[0078] Reference Figure 26A lower molded stack 310S is formed on the second sacrificial layer 164P and the insulating separation structure 160. In an embodiment, the lower molded stack 310S includes a plurality of alternately arranged lower insulating layers 134 and a plurality of lower sacrificial layers 312. In some embodiments, the plurality of lower insulating layers 134 may include an insulating material such as silicon oxide or silicon oxynitride, and the plurality of lower sacrificial layers 312 may include silicon nitride, silicon oxynitride, doped polysilicon, or undoped polysilicon.

[0079] Reference Figure 27 In the connection region CON, the lower molded stack 310S is sequentially patterned to form the lower pad portion PADL. In some embodiments, the lower pad portion PADL may be formed in the form of a step with a horizontal difference along a first horizontal direction (X direction). In an exemplary embodiment, a first portion of the first width of the first pair of lower insulating layers 134 and lower sacrificial layers 312 disposed on the second semiconductor layer 124 is removed, and a second portion of the second width of the second pair of lower insulating layers 134 and lower sacrificial layers 312 disposed on the first pair of lower insulating layers 134 and lower sacrificial layers 312 is removed to form a step shape, wherein the second width is greater than the first width.

[0080] Reference Figure 28A and Figure 28B A lower cover insulating layer 142L is formed to cover the lower pad portion PADL. The lower cover insulating layer 142L may include an insulating material such as silicon oxide or silicon oxynitride. A first interlayer insulating layer 144 is formed on the lower cover insulating layer 142L.

[0081] In the memory cell region MCR and the connection region CON, a lower channel via 150HL and a lower dummy channel via D150HL are formed in the lower molded stack 310S. While a gate insulating layer 152, a channel layer 154, and a buried insulating layer 156 are sequentially formed on the inner surface of the lower channel via 150HL, a dummy gate insulating layer D152, a dummy channel layer D154, and a dummy buried insulating layer D156 are sequentially formed on the inner surface of the lower dummy channel via D150HL. The upper portions of the gate insulating layer 152, channel layer 154, and buried insulating layer 156 in the lower channel via 150HL, as well as the upper portions of the dummy gate insulating layer D152, dummy channel layer D154, and dummy buried insulating layer D156 in the lower dummy channel via D150HL, are removed to form a second removal region. Then, conductive plugs 158 and dummy conductive plugs D158 are formed in the second removal region to block the entrances of the lower channel via 150HL and the lower dummy channel via D150HL, respectively. Therefore, a lower channel structure 150L and a lower dummy channel structure D150L can be formed in the lower channel via 150HL and the lower dummy channel via D150HL, respectively.

[0082] Reference Figure 29Multiple upper insulating layers 138 and multiple upper sacrificial layers 316 are alternately formed on the first interlayer insulating layer 144 to form an upper molded stack 315S. In the connection region CON, the upper molded stack 315S can be sequentially patterned to form an upper pad portion PADU, and then an upper cover insulating layer 142U and a second interlayer insulating layer 146 are formed to cover the upper pad portion PADU.

[0083] Subsequently, in the memory cell region MCR and the connection region CON, an upper channel hole 150HU and an upper dummy channel hole D150HU are formed in the upper molded stack 315S, respectively. An upper channel structure 150U and an upper dummy channel structure D150U are formed in the upper channel hole 150HU and the upper dummy channel hole D150HU, respectively. The upper channel structure 150U and the upper dummy channel structure D150U can be formed by a method similar to that used to form the lower channel structure 150L and the lower dummy channel structure D150L.

[0084] Subsequently, a portion of the topmost sacrificial layer 316 can be removed from the memory cell region MCR, and then a string separation insulating layer 174 can be formed to fill the removed area. The removal step of said portion of the topmost sacrificial layer 316 may include removing the portion of the second interlayer insulating layer 146 that coincides with said portion of the topmost sacrificial layer 316.

[0085] Reference Figure 30 A mask pattern is formed on the second interlayer insulating layer 146, and then portions of the upper molded stack 315S and the lower molded stack 310S are removed to form the word line cutting opening 330H1. For example, a mask can be used to remove portions of the upper molded stack 315S and the lower molded stack 310S, while retaining the remaining portions of the upper molded stack 315S and the lower molded stack 310S. In an exemplary embodiment, the upper surface of the substrate 110 may be exposed on the bottom surface of the word line cutting opening 330H1.

[0086] A cover layer 320 is formed to cover the upper surface of the second interlayer insulating layer 146 and the sidewalls of the word line cutting opening 330H1. In some embodiments, the cover layer 320 may be formed using a material with poor step coverage characteristics, so that the cover layer 320 is not provided on the first sacrificial layer 162P and the second sacrificial layer 164P exposed on the sidewalls of the word line cutting opening 330H1, but the inventive concept is not limited thereto.

[0087] Reference Figure 31A , Figure 31B , Figure 31C and Figure 31DThe second sacrificial layer 164P exposed on the sidewall of the word line dicing opening 330H1 is removed to form a lateral opening 330HE in the region where the second sacrificial layer 164P is removed. In the memory cell region MCR, the sidewall 152S of the gate insulating layer 152 of the lower channel structure 150L (see...) Figure 31D The dummy gate insulating layer D152 of the cell dummy channel structure D150C is exposed by the lateral opening 330HE. Additionally, in the memory cell region MCR, the sidewall D152S of the dummy gate insulating layer D152 of the cell dummy channel structure D150C can be exposed by the lateral opening 330HE.

[0088] In some embodiments, the removal process of the second sacrificial layer 164P can be a wet etching process using a phosphoric acid solution as an etchant. During the removal process of the second sacrificial layer 164P, the etch stop layer 166 can be exposed on the sidewall of the word line cutting opening 330H1 in the connection region CON; however, the second insulating layer 164, surrounded by the etch stop layer 166 which has etch selectivity relative to the second sacrificial layer 164P, is not exposed to the etching environment.

[0089] Reference Figure 32 The portions of the first sacrificial layer 162P and the blocking insulating layer 152C exposed by the lateral opening 330HE can be removed. For example, the portions of the first sacrificial layer 162P and the blocking insulating layer 152C can be removed. Figure 31D A portion of the first sacrificial layer 162P and the barrier insulating layer 152C shown are used to create Figure 32 The view shown.

[0090] Reference Figure 33 This allows for the removal of a portion of the charge storage layer 152B exposed by the lateral opening 330HE. For example, it allows for the removal of a portion of the charge storage layer 152B, such as... Figure 32 The portion shown is exposed by the transverse opening 330HE to create Figure 33 The view shown. At this time, the edge portion of the charge storage layer 152B exposed by the lateral opening 330HE can also be etched to form a gate insulating layer recessed region 152R extending upward and downward from the lateral opening 330HE.

[0091] Reference Figure 34 The portion of the tunnel insulation layer 152A exposed by the transverse opening 330HE can be removed to expose the sidewall 154S of the trench layer 154. For example, the portion of the tunnel insulation layer 152A exposed by the transverse opening 330HE can be removed. Figure 33The portion shown is exposed by the lateral opening 330HE. Therefore, a gate insulating layer separation region 152SR surrounded by the lateral opening 330HE can be formed, and the gate insulating layer 152 can be separated into a lower gate insulating layer 152L and a bottom gate insulating layer 152F through the gate insulating layer separation region 152SR. At this time, the edge portion of the barrier insulating layer 152C exposed by the lateral opening 330HE can also be etched. For example, the barrier insulating layer 152C can be etched such that the barrier insulating layer 152C does not extend beyond the charge storage layer 152B.

[0092] Reference Figure 35A , Figure 35B and Figure 35C A first semiconductor layer 122 is formed in the word line cutting opening 330H1 and the lateral opening 330HE. The first semiconductor layer 122 can be formed to fill the space between the substrate 110 and the second semiconductor layer 124. Figure 34 The gate insulating layer separation region 152SR and the lateral opening 330HE shown are connected to the sidewall 154S of the channel layer 154. A portion of the first semiconductor layer 122 can be filled with... Figure 34 The gate insulating layer recessed region 152R shown in the figure thus forms Figure 35A and Figure 35C The protrusion 122P shown is formed at the gate insulating layer recess region 152R. Figure 35C The raised step 122PS is shown in the figure.

[0093] Reference Figure 36 A portion of the first semiconductor layer 122 and the cover layer 320 formed on the sidewall of the word line dicing opening 330H1 can be removed (see reference). Figure 31A ), to form a character line cutting opening 330H2.

[0094] The lower sacrificial layer 312 exposed through the letter line cutting opening 330H2 can be removed (see...). Figure 31A 312) and the upper sacrificial layer (see 312) Figure 31A (316) to form a molded opening 330H3. The sidewalls of multiple channel structures 150 and multiple dummy channel structures D150 can be exposed through the molded opening 330H3.

[0095] Reference Figure 37A and Figure 37B The word line cutting opening 330H2 and the molding opening 330H3 can be filled with metal. The metal in the word line cutting opening 330H2 can be removed to form a lower gate electrode 132 between the lower insulating layers 134 of the lower molding stack 310S and an upper gate electrode 136 between the upper insulating layers 138 of the upper molding stack 315S.

[0096] It can be done Figure 36 The word line cutout 330H2 shown injects impurities into the substrate 110 to form impurities in the substrate 110 exposed by the word line cutout 330H2. Figure 37A The common source region 112 is shown in the figure.

[0097] It is possible Figure 36 The letter line cutting opening 330H2 shown is formed on the sidewall. Figure 37A The insulating spacer 182 and common source line 180 are shown.

[0098] Refer again Figure 3 An upper interlayer insulating layer 148 may be formed on the second interlayer insulating layer 146. The bit line contact BLC may penetrate the upper interlayer insulating layer 148 to be electrically connected to the channel structure 150. A bit line BL may be formed on the upper interlayer insulating layer 148 to connect to the bit line contact BLC, and the bit line BL may extend in the second horizontal direction (Y direction).

[0099] Semiconductor device 100 can be manufactured by performing the above process.

[0100] According to the method for manufacturing the semiconductor device 100 described above, since an etch stop layer 166 is formed on the substrate 110 in the connection region CON, the removal of the second insulating layer 164 in the connection region CON can be prevented during the process of removing the second sacrificial layer 164P in the memory cell region MCR. Therefore, the dummy channel layer D154 of the dummy channel structure D150 is not electrically connected to the common source line 180. Even if defects or faults occur in the dummy channel layer D154 or the dummy gate insulating layer D152 during the process of forming the dummy channel structure D150, the channel structure 150 in the memory cell region MCR can still operate normally; therefore, the semiconductor device 100 can have improved reliability.

[0101] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to embodiments of the inventive concept without departing from the spirit and scope thereof.

Claims

1. A semiconductor device comprising: a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate; a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer extending in the vertical direction; a first semiconductor layer disposed in the memory cell region and disposed between the substrate and a lowermost gate electrode of the plurality of gate electrodes, the first semiconductor layer at least partially surrounding the channel structure; and an insulative separation structure disposed between the substrate and the lowermost gate electrode of the plurality of gate electrodes and at least partially surrounding the dummy channel layer, wherein the insulative separation structure includes: a first insulative layer disposed on the substrate; a second insulative layer disposed on the first insulative layer; and an etch stop layer covering sidewalls of the first insulative layer and sidewalls of the second insulative layer. The first semiconductor layer at least partially surrounds the channel layer, and 2. The semiconductor device of claim 1, wherein, the insulative separation structure is spaced apart from the dummy channel layer. The channel structure further includes a gate insulative layer disposed on sidewalls of the channel layer, 3. The semiconductor device of claim 1, wherein, the gate insulative layer is not disposed between the first semiconductor layer and the channel layer, the dummy channel structure further includes a dummy gate insulative layer disposed on sidewalls of the dummy channel layer, and at least a portion of the dummy gate insulative layer is disposed between the insulative separation structure and the dummy channel layer. a gate insulative layer separation region is disposed at a lower portion of the channel structure, 4. The semiconductor device of claim 3, wherein, the first semiconductor layer is in contact with the channel layer in the gate insulative layer separation region, and the dummy gate insulative layer covers sidewalls and a lower surface of the dummy channel layer.

5. The semiconductor device of claim 1, further comprising a second semiconductor layer disposed between the first semiconductor layer and the lowermost gate electrode and disposed between the insulative separation structure and the lowermost gate electrode, the second semiconductor layer at least partially surrounds the channel structure and the dummy channel structure. wherein, The etch stop layer has a first sidewall and a second sidewall, 6. The semiconductor device of claim 1, wherein, the first sidewall of the etch stop layer contacts the sidewalls of the first insulative layer and the sidewalls of the second insulative layer, and the second sidewall of the etch stop layer contacts the first semiconductor layer. an upper surface of the insulative separation structure is at a same level as or above an upper surface of the first semiconductor layer, and 7. The semiconductor device of claim 1, wherein, a lower surface of the insulative separation structure is at a same level as or below an upper surface of the substrate. The etch stop layer includes a plurality of openings, and 8. The semiconductor device of claim 1, wherein, at least a portion of the dummy channel structure and at least a portion of the second insulative layer are disposed in each of the plurality of openings.

9. The semiconductor device of claim 1, further comprising a common source line disposed in a word line cut region of the substrate and penetrating the plurality of gate electrodes, the etch stop layer includes a first portion vertically overlying the common source line. wherein, A width of the first portion of the etch stop layer is greater than a width of the word line cut region.

10. The semiconductor device of claim 9, wherein, A portion of the first portion of the etch stop layer is disposed between the common source line and the second insulative layer.

11. The semiconductor device of claim 9, wherein, ​ 12. The semiconductor device according to claim 1, wherein the first insulating layer covers a first portion of a sidewall of the dummy channel structure, and the etching stopper layer covers a second portion of the sidewall of the dummy channel structure.

13. The semiconductor device according to claim 12, further comprising a third semiconductor layer disposed between the substrate and the lowermost gate electrode in the connection region and connected to the first semiconductor layer, wherein the third semiconductor layer surrounds the etching stopper layer and the first insulating layer, wherein the third semiconductor layer is spaced apart from the dummy channel structure.

14. A semiconductor device, comprising: a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer and a gate insulating layer extending in a vertical direction perpendicular to an upper surface of the substrate; a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer and a dummy gate insulating layer extending in the vertical direction; and a first semiconductor layer disposed in the memory cell region and disposed between the substrate and a lowermost gate electrode of the plurality of gate electrodes, wherein a gate insulating layer separation region is formed at a lower portion of the channel structure, the first semiconductor layer at least partially surrounds the channel layer in the gate insulating layer separation region, and the dummy gate insulating layer covers an outer sidewall of the dummy channel layer, wherein the insulative separation structure includes: a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; and an etching stopper layer covering a sidewall of the first insulating layer and a sidewall of the second insulating layer.

15. The semiconductor device according to claim 14, further comprising an insulative separation structure disposed between the substrate and the lowermost gate electrode in the connection region and at least partially surrounding the dummy channel structure, at least a portion of the dummy gate insulating layer is disposed between the insulative separation structure and the dummy channel layer. wherein, 16. The semiconductor device according to claim 15, further comprising a second semiconductor layer disposed between the first semiconductor layer and the lowermost gate electrode and disposed between the insulative separation structure and the lowermost gate electrode, the second semiconductor layer surrounds the channel structure and the dummy channel structure, wherein, an upper surface of the insulative separation structure is at the same level as or higher than a lower surface of the second semiconductor layer, and a lower surface of the insulative separation structure is at the same level as or lower than an upper surface of the substrate. the etching stopper layer is in contact with the first semiconductor layer.

17. The semiconductor device of claim 15, wherein, 18. The semiconductor device according to claim 17, further comprising a common source line disposed in a word line cut region of the substrate and penetrating the plurality of gate electrodes, the etching stopper layer includes a first portion vertically stacked with the common source line. wherein, a portion of the first portion of the etching stopper layer is disposed between the common source line and the second insulating layer.

19. The semiconductor device of claim 18, wherein, 20. A semiconductor device, comprising: ​ a substrate including a memory cell region and a connection region; a plurality of gate electrodes stacked on the substrate; a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate; a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer extending in the vertical direction; and a first semiconductor layer disposed in the memory cell region and disposed between the substrate and a lowermost gate electrode of the plurality of gate electrodes, the first semiconductor layer at least partially surrounding the channel structure, wherein a gate insulating layer separation region is disposed at a lower portion of the channel structure, the first semiconductor layer at least partially surrounds the channel layer in the gate insulating layer separation region, and the dummy channel structure is spaced apart from the first semiconductor layer, wherein the insulating separation structure includes: a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; and an etching stop layer covering sidewalls of the first insulating layer and sidewalls of the second insulating layer.

21. The semiconductor device of claim 20, further comprising an insulating separation structure disposed between the substrate and the lowermost gate electrode and at least partially surrounding the dummy channel structure, the dummy channel structure further including a dummy gate insulating layer between the insulating separation structure and the dummy channel layer. wherein, 22. The semiconductor device of claim 21, further comprising a common source line disposed in a word line cut region of the substrate and penetrating the plurality of gate electrodes, the insulating separation structure vertically stacked with the common source line. wherein, the etching stop layer in contact with the first semiconductor layer and including a first portion vertically stacked with the common source line.

23. The semiconductor device of claim 22, wherein, a portion of the first portion of the etching stop layer is disposed between the common source line and the second insulating layer.

24. The semiconductor device of claim 23, wherein, ​

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