Sidewall passivation for HEMT devices

Abstract

Some embodiments of the present invention relate to a high electron mobility transistor (HEMT) including a heterojunction structure arranged above a semiconductor substrate. The heterojunction structure includes a binary III / V semiconductor layer made of a first III-nitride material serving as a channel region of the e-HEMT and a ternary III / V semiconductor layer arranged above the binary III / V semiconductor layer and made of a second III-nitride material serving as a barrier layer. A source region and a drain region are arranged above the ternary III / V semiconductor layer and are laterally spaced apart from each other. A gate structure is arranged above the heterojunction structure and between the source region and the drain region. The gate structure is made of a third III-nitride material. A first passivation layer is disposed around a sidewall of the gate structure and is made of a fourth III-nitride material. Embodiments of the present invention also relate to sidewall passivation for a HEMT device.

Description

[0001] This application is a divisional application of patent application number 201510212686.5, entitled “Sidewall passivation for HEMT devices”, filed on April 29, 2015. Technical Field

[0002] Embodiments of the present invention relate to integrated circuit devices, and more particularly, to sidewall passivation for HEMT devices. Background Art

[0003] A high electron mobility transistor (HEMT), also known as a heterostructure FET (HFET) or modulation doped FET (MODFET), is a type of field effect transistor. Whereas a conventional n-type MOSFET includes a gate electrode disposed above a p-type doped channel region separating an n-type source / drain region, for example, a HEMT device uses a heterojunction as a channel, rather than using a doped region as a channel. The heterojunction is defined by an interface where two materials with different band gaps are in contact with each other. A III-N (trinitride) device is a type of HEMT in which the heterojunction consists of a Group III material (e.g., Al, Ga, In) and a nitride (N) material. These III-N devices show very promising performance in high power and high frequency applications. For example, III-N devices can be used in high power-high frequency applications such as transmitters for cell phone base stations, direct broadcast satellite (DBS) receivers, electronic countermeasure systems, and the like. Summary of the invention

[0004] An embodiment of the present invention provides a high electron mobility transistor (HEMT), comprising: a heterojunction structure arranged above a semiconductor substrate, the heterojunction structure comprising: a binary III / V semiconductor layer made of a first III-nitride material and serving as a channel region of the HEMT, and a ternary III / V semiconductor layer arranged above the binary III / V semiconductor layer and made of a second III-nitride material and serving as a barrier layer; a source region and a drain region arranged above the ternary III / V semiconductor layer and laterally spaced apart from each other; a gate structure arranged above the heterojunction structure and between the source region and the drain region, wherein the gate structure is made of a third III-nitride material; and a first passivation layer disposed around a sidewall of the gate structure and made of a fourth III-nitride material.

[0005] According to another embodiment of the present invention, a method for forming an enhancement mode, high electron mobility transistor (e-HEMT) on a substrate is provided, comprising: forming a binary III-nitride channel layer above the substrate; forming a ternary III-nitride barrier layer above the binary III-nitride channel layer, wherein the ternary III-nitride barrier layer contacts the binary III-nitride channel layer at a heterojunction interface; forming a binary III-nitride gate layer above the ternary III-nitride barrier layer, and doping the binary III-nitride gate layer with donor or acceptor impurities; removing a selected portion of the doped binary III-nitride gate layer to form a patterned doped binary III-nitride gate structure having a gate upper surface and a gate outer sidewall, and exposing an upper surface region of the ternary III-nitride barrier layer; and forming a first conformal passivation layer over the gate upper surface, the gate outer sidewall, and the exposed upper surface region of the ternary III-nitride barrier layer.

[0006] According to another embodiment of the present invention, there is provided an enhancement mode high electron mobility transistor (HEMT) formed on a substrate, comprising: an AlN buffer layer located above the substrate; an AlGaN buffer layer located above the AlN buffer layer; a GaN channel layer located above the AlGaN buffer layer; an AlGaN barrier layer located above the GaN channel layer; a GaN gate structure located above the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and a gate structure outer sidewall; and an AlN or BN conformal passivation layer located above the gate structure upper surface and adjacent to the gate structure outer sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 Some embodiments of cross-sectional views of HEMT devices according to some embodiments of the present invention are shown.

[0009] Figure 2 A flow chart showing a method of manufacturing an e-HEMT device according to some embodiments of the present invention.

[0010] Figures 3 to 11 A series of cross-sectional views are shown that collectively illustrate a method of fabricating a HEMT device according to some embodiments of the present invention. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] HEMT devices use a heterojunction between two materials with different band gaps as a channel. For example, in some III-NHEMT devices, a wide bandgap AlGaN layer can form a heterojunction with a narrow bandgap GaN layer. The lattice constants of these two materials are usually slightly different. The difference in the lattice structure of these types of materials produces strain, which can lead to piezoelectrically induced polarization and form band bending at the heterojunction interface. For example, GaN HEMTs typically have a strong surface polarization that causes them to operate in a normally-on (depletion mode) state. In order to overcome the surface polarization and control the flow of charge carriers in enhancement mode devices, a gate of p-GaN material with a high work function can be formed directly on top of the AlGaN layer.

[0014] However, GaN HEMTs with AlGaN / GaN as the Schottky barrier and p-GaN gates as the control gates result in large gate leakage. In addition, in order to form an enhancement-mode device structure, many III-N surfaces are subject to process-induced traps or damage. These traps or damage mainly lead to gate leakage or device leakage current that degrades device performance. In an attempt to limit the number of traps (and thus improve device performance), the present invention describes a technique for forming a passivation layer on the III-N surface (e.g., the sidewalls of p-GaN). This passivation layer terminates and passivates the dangling bonds on the surface of the gate sidewall surface to limit the number of interface traps and thus helps improve device performance. Therefore, gate leakage can be reduced by introducing such a passivation layer.

[0015] Figure 1 Some embodiments of a cross-sectional view of a HEMT device 100 according to the present invention are shown. The HEMT device 100 includes a heterojunction structure 102 disposed above a semiconductor substrate 104. The heterojunction structure 102 is composed of a binary III / V semiconductor layer 106 and a ternary III / V semiconductor layer 108 disposed above the binary III / V semiconductor layer 106. The binary III / V semiconductor layer 106 is made of a first III-nitride material and serves as the channel region of an e-HEMT. The ternary III / V semiconductor layer 108 is made of a second III-nitride layer and serves as a barrier layer somewhat similar to the gate dielectric for a conventional MOSFET. In some embodiments, the binary III / V semiconductor layer 106 is made of gallium nitride (GaN), and the ternary III / V semiconductor layer 108 is made of aluminum gallium nitride (Al x Ga 1-x N, where 0 < x < 1).

[0016] One or more buffer layers 110 may be disposed between the heterostructure 102 and the substrate 104. These buffer layers 110 can help gradually distribute the strain over their thickness, where the strain is caused by the lattice mismatch between the substrate 104 and the binary III / V layer 106. By distributing the strain, these buffer layers 110 can help avoid trap formation in some respects. The illustrated buffer layers 110 include an uppermost buffer layer 112 adjacent to the binary III / V layer 106 and a lower buffer layer 114 located between the uppermost buffer layer 112 and the substrate 104. In some embodiments, the uppermost buffer layer 112 may be made of AlGaN, and the lower buffer layer 114 may be made of AlN. In other embodiments, more than two buffer layers may be included between the heterostructure 102 and the substrate 104.

[0017] Conductive source region 116 and drain region 118 are disposed above ternary III / V semiconductor layer 108 and are laterally spaced apart from each other. Conductive source region 116 and drain region 118 have respective lower regions that abut ternary III / V semiconductor layer 108 and are ohmically connected to ternary III / V semiconductor layer 108. In some embodiments, source region 116 / drain region 118 are directly above and abut ternary III / V semiconductor layer 108 and are spaced apart from binary III / V semiconductor layer 106. However, in other embodiments, source region 116 / drain region 118 extend through ternary III / V semiconductor layer 108 and abut binary III / V semiconductor layer 106.

[0018] The gate structure 120 is disposed above the heterojunction structure 102 and laterally disposed between the conductive source region 116 and the drain region 118. The gate structure 120 is made of a third III-nitride material. For example, in some embodiments, the gate structure 120 can be made of GaN that has been doped with donor impurities to form an n-type gate structure or has been doped with acceptor impurities to form a p-type gate structure. These dopants help to cause the resulting HEMT device 100 to operate in an enhancement mode as opposed to a depletion mode.

[0019] A first conformal passivation layer 122 is disposed around the gate structure sidewalls 120A, 120B and over the gate structure upper surface 120C. The first conformal passivation layer 122 is also disposed over the upper surface 108A of the ternary III / V semiconductor layer 108. In some embodiments, this first conformal passivation layer 122, which may be made of aluminum nitride (AlN) or boron nitride (BN), may be a high-quality thin film to prevent current leakage from the gate structure 120. Therefore, in some embodiments, the first conformal passivation layer 122 is grown by atomic layer deposition (ALD) techniques, which, while time-consuming, produce very high-quality films. In some embodiments, the first conformal passivation layer 122 may have a thickness between about 5 angstroms and about 500 angstroms. In addition to providing high-quality films, ALD techniques are advantageous because they can be implemented at relatively low temperatures, for example, between 200°C and 500°C, which helps limit thermal budget issues, and because ALD techniques provide good step coverage compared to PVD.

[0020] A second conformal passivation layer 124 is disposed over the first conformal passivation layer 122. The second conformal passivation layer 124 can help protect the first conformal passivation layer 122 during processing. In some embodiments, the second conformal passivation layer 124 can be made of a nitride (e.g., SiN) or an oxide (e.g., SiO2). The thickness of the second conformal passivation layer 124 can be greater than the thickness of the first conformal passivation layer 122, and the second conformal passivation layer 124 can be formed by a technique different from the technique used to form the first conformal passivation layer 122. For example, in some embodiments, the second conformal passivation layer 124 can have a thickness of about 50 nanometers to about 500 nanometers. In addition, for example, in some embodiments, the second conformal passivation layer 124 can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0021] Conductive source / drain regions 116, 118 extend downward through first passivation layer 122 and second passivation layer 124 to be ohmically connected to ternary III / V semiconductor layer 108. Conductive source / drain regions 116, 118 may be a metal such as copper, aluminum, tungsten, nickel, iron, cobalt, silver, gold, or platinum, for example.

[0022] A conformal dielectric capping layer 126 is disposed over the conductive source region 116 / drain region 118. For example, in some embodiments, the conformal dielectric capping layer 126 is a nitride (e.g., SiN) or an oxide (e.g., SiO2). In some embodiments, the thickness of the conformal dielectric capping layer 126 is greater than or equal to the thickness of the second conformal passivation layer 124.

[0023] The metal electrode pad or metal electrode contact 128 extends downward through the dielectric cap layer 126 and through the first passivation layer 122 and the second passivation layer 124 to form an ohmic connection with the gate structure 120. In some embodiments, the metal electrode pad or metal electrode contact 128 is formed by PVD or CVD. The metal electrode pad or metal electrode contact 128 may extend downward along the sidewalls of the cap layer 126 and the sidewalls of the first passivation layer 122 and the second passivation layer 124 before making ohmic contact with the upper surface area of ​​the gate structure 120.

[0024] Due to the difference in band gap between the binary III / V layer 106 and the ternary III-V layer 108, highly mobile charge carriers in the form of a two-dimensional electron gas (2DEG) are established at the interface between the layers 106, 108. Thus, during operation, a voltage applied to the gate electrode 120 controls the number of carriers (e.g., 2DEG) that can flow from the source 116 through the channel region in the layer 106 to the drain 118 (or vice versa). Thus, whether the HEMT 100 is in a conductive state or a resistive state can be controlled by controlling the 2DEG with the help of the gate electrode 120. In many cases, the HEMT device 100 is an enhancement mode device that operates similar to a silicon MOSFET device by being normally in a non-conductive state (normally off). Due to the nature of the heterojunction interface between 106 / 108 and the formation of a 2DEG at this heterojunction interface in the HEMT, such devices formed in III-N material systems tend to be normally-on or depletion mode devices. The high electron mobility of the 2DEG at the interface of the AlGaN / GaN layers allows III-N devices such as HEMT devices to conduct electricity without applying a gate potential.

[0025] In the off state, conventional enhancement mode HEMT (e-HEMT) devices may experience current leakage from their gate structures. In some cases, the passivation layer 122 can help limit this current leakage by about an order of magnitude.

[0026] Figure 2 Flowcharts of some embodiments of methods of manufacturing HEMT devices according to some embodiments of the present invention are shown. Although the methods are shown and described below as a series of steps or events, it will be understood that the order in which these steps or events are shown should not be interpreted as limiting. For example, some steps may be performed in a different order and / or simultaneously with other steps or events other than those shown and / or described herein. In addition, not all of the steps shown may be necessary to implement one or more aspects or embodiments described herein. In addition, one or more steps shown herein may be implemented in one or more separate steps and / or stages.

[0027] In step 202, a first buffer layer made of a first III-nitride material is formed over a substrate. In step 204, a second buffer layer is formed over the first buffer layer, wherein the second buffer layer is made of a second III-nitride material different from the first III-nitride material. In step 206, a binary III-nitride channel layer is formed over the second buffer layer. In step 208, a ternary III-nitride barrier layer is formed over the binary III-nitride channel layer. The ternary III-nitride barrier layer contacts the binary III-nitride channel layer at a heterojunction interface. In step 210, a binary III-nitride gate layer is formed over the ternary III-nitride barrier layer, and the binary III-nitride gate layer is doped with donor or acceptor impurities. In step 212, selected portions of the doped binary III-nitride gate layer are removed to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate outer sidewalls. The removal of these selected portions exposes the upper surface region of the ternary III-nitride barrier layer. In step 214, a first conformal passivation layer is formed over the gate upper surface, gate outer sidewalls, and the exposed upper surface region of the ternary III-nitride barrier layer. The first conformal passivation layer can help reduce gate sidewall traps and thus help limit current leakage from the gate structure during operation of the device.

[0028] Now go to Figures 3 to 11 , a series of cross-sectional views can be seen that collectively illustrate the formation of a HEMT device according to some embodiments. It will be understood that although specific structural components are disclosed in these cross-sectional views, these specific structural components are not required in all embodiments.

[0029] Figure 3 with by Figure 2 Reference numerals 202 to 210 are consistent with some embodiments of structures formed. Figure 3The structure includes a substrate 302 that can take various different forms. In some embodiments, the substrate 302 is a silicon substrate, a silicon carbide (SiC) substrate, or a sapphire substrate. Then, a first buffer layer 304 is formed over the substrate 302, for example, by an epitaxial growth technique. In some cases, the first buffer layer 304 can be referred to as the lower buffer layer. In some cases, the first buffer layer 304 is an aluminum nitride (AlN) layer. Then, a second buffer layer 306 is formed over the first buffer layer 304, for example, by an epitaxial growth technique. In some cases, the second buffer layer 306 can be referred to as the uppermost buffer layer. In some cases, the second buffer layer 306 is an AlGaN layer. Then, a binary III-nitride channel layer 308 is formed over the second buffer layer 306, for example, by an epitaxial growth technique. In some cases, the binary III-nitride channel layer 308 is a GaN layer. A ternary III-nitride barrier layer 310 is formed over the binary III-nitride channel layer 308, for example, by an epitaxial growth technique. In some embodiments, the ternary III-nitride barrier layer 310 is an Al x Ga 1- x N layer, where 0 < x < 1. A binary III-nitride gate layer 312 is formed over the ternary III-nitride barrier layer 310, for example, by an epitaxial growth technique, and the binary III-nitride gate layer 312 is doped with donor or acceptor impurities. In some embodiments, the binary III-nitride gate layer 312 is an n-type or p-type GaN layer.

[0030] In Figure 4 , a gate structure mask layer is formed and patterned over the binary III-nitride gate layer. The gate structure mask layer can be a photoresist layer, a hard mask layer such as a nitride layer, and / or other individual layers or combinations of layers. With the patterned gate structure mask 402 in place, etching is performed to selectively remove the exposed portions of the binary III-nitride gate layer 312, leaving a gate structure 312' having the gate structure mask 402 over it. Then the patterned gate structure mask 402 is removed.

[0031] In Figure 5 , a first conformal passivation layer 502 is formed by atomic layer deposition (ALD). In some embodiments, the first conformal passivation layer 502 is AlN or BN and is deposited to have a thickness between about 5 angstroms and 500 angstroms. To limit gate sidewall traps, the first conformal passivation layer 502 directly abuts the sidewalls and the upper surface of the gate electrode 312'.

[0032] In Figure 6In the embodiment of the present invention, a second conformal passivation layer 602 is formed over the first conformal passivation layer 502 to protect the first conformal passivation layer 502 during processing. In some embodiments, the second conformal passivation layer is a nitride such as, for example, SiN or an oxide such as, for example, SiO2. In some embodiments, the second conformal passivation layer 602 is formed by a different technique than the formation of the first conformal passivation layer 502. For example, the second conformal passivation layer 602 can be formed by CVD, PECVD, or PVD having a deposition rate faster than that of ALD to keep the process throughput at a good level. To help protect the first conformal passivation layer 502, the thickness of the second passivation layer 602 can be in the range of about 50 nm and about 500 nm.

[0033] exist Figure 7 , a source / drain mask 700 has been formed over the second conformal passivation layer. With the source / drain mask 700 in place, an etch, such as, for example, a dry etch, is performed to form source / drain openings 702 that extend through the first conformal passivation layer 502 and the second conformal passivation layer 602 and terminate on the ternary III-nitride barrier layer 310. Some portions of the ternary III-nitride barrier layer 310 may be removed / consumed during this etch, and other portions may remain below the source / drain openings 702 that are located over the ternary III-nitride barrier layer 310. Figure 8 In the embodiment of the present invention, the source / drain mask 700 is removed and the source / drain openings are filled with a conductive material such as a metal. The initially formed metal extends over the entire exposed surface of the second conformal passivation layer. Subsequently, a mask (not shown) such as a photoresist mask is formed over the source / drain regions, and an etch such as a dry etch is performed to form the conductive source / drain regions 802 shown.

[0034] exist Fig. 9 In the embodiment of the present invention, a conformal dielectric cap layer 902 is formed. In some embodiments, the conformal dielectric cap layer is a nitride such as, for example, SiN or an oxide such as, for example, SiO2.

[0035] exist Fig.10 In the embodiment of the present invention, a gate electrode mask 1000 is formed over the dielectric cap layer. With the gate electrode mask in place, an etch such as a dry etch is performed to form a gate electrode opening 1002. The gate electrode opening extends through the dielectric cap layer, the first conformal passivation layer, and the second conformal passivation layer. The gate electrode opening terminates on the patterned doped binary III-nitride gate structure.

[0036] exist Fig.11In the embodiment of the present invention, a conductive gate electrode liner 1100 is formed in the gate electrode opening. In some embodiments, the conductive gate electrode liner is deposited by PVD or CVD. For example, the conductive gate electrode layer may include a metal such as aluminum, copper, tungsten or nickel or may include other conductive materials such as doped polysilicon.

[0037] As can be understood from the above, the present invention describes a technique for forming a passivation layer over the sidewalls of a gate electrode to limit interface traps. The passivation layer terminates and passivates dangling bonds on the surface of the gate sidewall surface to limit the number of interface traps and help improve device performance. Specifically, the passivation layer reduces gate leakage current.

[0038] Accordingly, some embodiments of the present invention are directed to a high electron mobility transistor (HEMT) comprising a heterojunction structure disposed over a semiconductor substrate. The heterojunction structure comprises a binary III / V semiconductor layer made of a first III-nitride material serving as a channel region of the e-HEMT and a ternary III / V semiconductor layer disposed over the binary III / V semiconductor layer and made of a second III-nitride material serving as a barrier layer. A source region and a drain region are disposed over the ternary III / V semiconductor layer and are laterally spaced apart from each other. A gate structure is disposed over the heterojunction structure and between the source region and the drain region. The gate structure is made of a third III-nitride material. A first conformal passivation layer is disposed around sidewalls of the gate structure and is made of a fourth III-nitride material.

[0039] In the above HEMT, the third III-nitride material of the gate structure is a binary III / V semiconductor material and has the same binary semiconductor composition as the first III-nitride material, and the fourth III-nitride material of the first passivation layer is a binary III / V semiconductor material and has a different binary semiconductor composition than the first III-nitride material and the second III-nitride material.

[0040] In the above HEMT, wherein the gate structure is a doped n-type or a doped p-type gate structure, and wherein the binary III / V semiconductor layer is an intrinsic semiconductor material.

[0041] In the above HEMT, wherein the first passivation layer is conformal and has a thickness between 5 angstroms and 500 angstroms.

[0042] In the above HEMT, it further includes: a second passivation layer having a thickness of 50 nm to 500 nm and conformally covering the first passivation layer, wherein a material composition of the second passivation layer is different from a material composition of the first passivation layer.

[0043] In the above HEMT, it also includes: one or more buffer layers located below the binary III / V semiconductor layer, wherein the uppermost buffer layer is made of the second III-nitride material, and wherein the lower buffer layer located below the uppermost buffer layer is made of the first III-nitride material.

[0044] In the above-mentioned HEMT, it also includes: one or more buffer layers located below the binary III / V semiconductor layer, wherein the uppermost buffer layer is made of the second III-nitride material, and wherein the lower buffer layer located below the uppermost buffer layer is made of the first III-nitride material, and wherein the first passivation layer is made of the same material as the lower buffer layer.

[0045] In the above HEMT, it also includes: one or more buffer layers located below the binary III / V semiconductor layer, wherein the uppermost buffer layer is made of the second III-nitride material, and wherein the lower buffer layer located below the uppermost buffer layer is made of the first III-nitride material, wherein the first passivation layer is made of the same material as the lower buffer layer, wherein the first III-nitride material of the binary III / V semiconductor layer is GaN; and the second III-nitride material of the ternary III / V semiconductor layer is Al x Ga 1-x N; the third III-nitride material of the gate structure is n-type GaN or p-type GaN; and the fourth III-nitride material of the first passivation layer is AlN or BN.

[0046] In the above HEMT, it also includes: a second passivation layer, which is conformally disposed above the first passivation layer and has a second thickness, which is greater than the first thickness of the first passivation layer; a capping layer, which is conformally disposed above the upper surface area of ​​the second passivation layer; and a metal gate electrode, including an edge located above the upper surface area of ​​the capping layer and including an inner sidewall, which extends downward along the sidewall of the opening through the capping layer, through the second passivation layer and through the first passivation layer to be directly electrically connected to the upper surface of the gate structure.

[0047] Other embodiments of the present invention relate to a method of forming an enhancement mode, high electron mobility transistor (e-HEMT) on a substrate. In the method, a binary III-nitride channel layer is formed over the substrate. A ternary III-nitride barrier layer is formed over the binary III-nitride channel layer. The ternary III-nitride barrier layer contacts the binary III-nitride channel layer at a heterojunction interface. A binary III-nitride gate layer is formed over the ternary III-nitride barrier layer, and the binary III-nitride gate layer is doped with a donor or acceptor impurity. Selected portions of the doped binary III-nitride gate layer are removed to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate outer sidewalls. The removal of the selected portions of the gate layer exposes an upper surface region of the ternary III-nitride barrier layer. A first conformal passivation layer is formed over the gate upper surface, over the gate outer sidewalls, and over the exposed upper surface region of the ternary III-nitride barrier layer.

[0048] In the above method, wherein the first conformal passivation layer is formed by atomic layer deposition (ALD).

[0049] In the above method, the method further includes: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from that of forming the first conformal passivation layer.

[0050] In the above method, it also includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technique different from forming the first conformal passivation layer, wherein the first conformal passivation layer is formed by ALD and has a thickness between about 5 angstroms and about 500 angstroms, and wherein the second conformal passivation layer is formed by CVD, PECVD or PVD and has a thickness between about 50nm and about 500nm to protect the first conformal passivation layer during processing.

[0051] In the above method, it also includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technology different from the technology for forming the first conformal passivation layer, wherein the method also includes: forming a source / drain mask above the second conformal passivation layer; with the source / drain mask in place, etching to form source / drain openings, the source / drain openings extending through the first conformal passivation layer and the second conformal passivation layer and terminating on the ternary III-nitride barrier layer; and filling the source / drain openings with a conductive material.

[0052] In the above method, it also includes: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than forming the first conformal passivation layer, wherein the method further includes: forming a source / drain mask over the second conformal passivation layer; with the source / drain mask in place, performing etching to form source / drain openings, the source / drain openings extending through the first conformal passivation layer and the second conformal passivation layer and terminating on the ternary III-nitride barrier layer; and filling the ternary III-nitride barrier layer with a conductive material. Source / drain opening, the method also includes: patterning the conductive material to form a source / drain conductive body; forming a dielectric cap layer above the source / drain conductive body; forming a gate electrode mask above the dielectric cap layer; with the gate electrode mask in place, performing etching to form a gate electrode opening extending through the dielectric cap layer, the first conformal passivation layer and the second conformal passivation layer, wherein the gate electrode opening terminates on the patterned doped binary III-nitride gate structure; and forming a conductive gate electrode liner in the gate electrode opening.

[0053] In the above method, it also includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than forming the first conformal passivation layer, wherein the method also includes: forming a source / drain mask above the second conformal passivation layer; with the source / drain mask in place, performing etching to form source / drain openings, the source / drain openings extending through the first conformal passivation layer and the second conformal passivation layer and terminating on the ternary III-nitride barrier layer; and filling the source / drain openings with a conductive material, the method also includes: patterning the The invention relates to a method for forming a gate electrode liner in the gate electrode opening, wherein the binary III-nitride channel layer is made of GaN and the ternary III-nitride barrier layer is made of Al. x Ga 1-x N; the patterned doped binary III-nitride gate structure is n-type GaN or p-type GaN; the first conformal passivation layer is AlN or BN; the second conformal passivation layer is SiO2 or SiN; and the dielectric cap layer is SiN or SiO2.

[0054] In the above method, it also includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technology different from that of forming the first conformal passivation layer, wherein the method also includes: forming a first buffer layer before forming the binary III-nitride channel layer above the substrate; and forming a second buffer layer above the first buffer layer before forming the binary III-nitride channel layer above the substrate.

[0055] In the above method, it also includes: forming a second conformal passivation layer above the first conformal passivation layer, wherein the second conformal passivation layer is formed by a technology different from that of forming the first conformal passivation layer, wherein the method also includes: forming a first buffer layer before forming the binary III-nitride channel layer above the substrate; and forming a second buffer layer above the first buffer layer before forming the binary III-nitride channel layer above the substrate, wherein the first conformal passivation layer is made of the same material as the first buffer layer.

[0056] Still other embodiments relate to a high electron mobility transistor (HEMT) formed on a substrate. The HEMT includes an AlN buffer layer located above the substrate. An AlGaN buffer layer is disposed above the AlN buffer layer. A GaN channel layer is disposed above the AlGaN buffer layer. An AlGaN barrier layer is disposed above the GaN channel layer. A GaN gate structure is disposed above the AlGaN barrier layer. The GaN gate structure is doped with an acceptor or donor impurity and has a gate structure upper surface and a gate structure outer sidewall. An AlN or BN conformal passivation layer is disposed above the gate structure upper surface and adjacent to the gate structure outer sidewall.

[0057] In the above HEMT, the HEMT further includes: a second passivation layer having a thickness of 50 nm to 500 nm and conformally covering the AlN or BN conformal passivation layer, wherein a material composition of the second passivation layer is different from a material composition of the AlN or BN conformal passivation layer.

[0058] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A high electron mobility transistor, comprising: a heterojunction structure arranged above the semiconductor substrate, the heterojunction structure comprising: a binary III / V semiconductor layer made of a first III-nitride material serving as a channel region of the high electron mobility transistor and a ternary III / V semiconductor layer arranged above the binary III / V semiconductor layer and made of a second III-nitride material serving as a barrier layer; a source region and a drain region disposed above the ternary III / V semiconductor layer and laterally spaced apart from each other; a gate structure disposed over the heterojunction structure and between the source region and the drain region, wherein the gate structure is made of a third III-nitride material and has an etched sidewall; and A first passivation layer made of BN, the first passivation layer of BN conformally extending directly over all sidewall surfaces of the etched sidewalls of the gate structure and an edge portion of an upper surface of the gate structure to expose a remaining portion of the upper surface, the first passivation layer of BN terminating and passivating dangling bonds on the etched sidewalls to reduce the number of traps on the etched sidewalls; A second passivation layer conformally covers the first passivation layer, and the first passivation layer and the second passivation layer are directly stacked on a portion of the etched sidewall of the gate structure in a lateral direction, and the second passivation layer has no physical contact with the gate structure.

2. The high electron mobility transistor according to claim 1, wherein: The material of the second passivation layer is SiO2 or SiN. Compared with the second passivation layer, the first passivation layer reduces the number of traps on the sidewall of the gate structure.

3. The high electron mobility transistor according to claim 1, wherein: The third III-nitride material of the gate structure is a binary III / V semiconductor material and has the same binary semiconductor composition as the first III-nitride material, and the BN of the first passivation layer is a binary III / V semiconductor material and has a different binary semiconductor composition than the first III-nitride material and the second III-nitride material.

4. The high electron mobility transistor according to claim 1, wherein: The gate structure is a doped n-type or a doped p-type gate structure, and wherein the binary III / V semiconductor layer is an intrinsic semiconductor material.

5. The high electron mobility transistor according to claim 1, wherein: The first passivation layer is conformal and has a thickness between 5 angstroms and 500 angstroms.

6. The high electron mobility transistor according to claim 5, wherein: The second passivation layer has a thickness of 50 nm to 500 nm, a minimum thickness of the second passivation layer is 100 times a minimum thickness of the first passivation layer, wherein a material composition of the second passivation layer is different from a material composition of the first passivation layer.

7. The high electron mobility transistor according to claim 1, further comprising: One or more buffer layers are located below the binary III / V semiconductor layer, wherein an uppermost buffer layer is made of the second III-nitride material, and wherein a lower buffer layer located below the uppermost buffer layer is made of a fourth III-nitride material.

8. The high electron mobility transistor according to claim 7, wherein: The first passivation layer and the lower buffer layer are made of different materials.

9. The high electron mobility transistor according to claim 8, wherein: The first III-nitride material of the binary III / V semiconductor layer is GaN; The second III-nitride material of the ternary III / V semiconductor layer is Al x Ga 1-x N; The third III-nitride material of the gate structure is n-type GaN or p-type GaN.

10. The high electron mobility transistor according to claim 1, wherein: The second passivation layer has a second thickness, the second thickness is greater than the first thickness of the first passivation layer, and further includes: a capping layer conformally disposed over an upper surface region of the second passivation layer; and A metal gate electrode includes an edge located above the upper surface area of ​​the cover layer and includes an inner sidewall, which extends downward along the sidewall of the opening through the cover layer, through the second passivation layer and through the first passivation layer to be directly electrically connected to the upper surface of the gate structure.

11. A method for forming an enhancement mode, high electron mobility transistor on a substrate, comprising: forming a binary III-nitride channel layer over the substrate; forming a ternary III-nitride barrier layer over the binary III-nitride channel layer, wherein the ternary III-nitride barrier layer contacts the binary III-nitride channel layer at a heterojunction interface; forming a binary III-nitride gate layer over the ternary III-nitride barrier layer and doping the binary III-nitride gate layer with donor or acceptor impurities; etching selected portions of the doped binary III-nitride gate layer to form a patterned doped binary III-nitride gate structure having a gate upper surface and etched gate outer sidewalls and exposing an upper surface region of the ternary III-nitride barrier layer; and forming a first conformal passivation layer made of BN over the gate upper surface, the etched gate outer sidewalls, and the exposed upper surface region of the ternary III-nitride barrier layer, the first conformal passivation layer of BN extending directly over all sidewall surfaces of the etched gate outer sidewalls and edge portions of the gate upper surface to expose the remaining portion of the gate upper surface, the first conformal passivation layer of BN terminating and passivating dangling bonds on all etched sidewall surfaces to reduce the number of traps of the etched gate outer sidewalls; A second conformal passivation layer is formed over the first conformal passivation layer, and the first conformal passivation layer and the second conformal passivation layer are stacked directly on a portion of the etched gate outer sidewall in a lateral direction, and the second conformal passivation layer is spaced apart from the binary III-nitride gate structure without physical contact.

12. The method for forming an enhancement mode high electron mobility transistor on a substrate according to claim 11, wherein: The second conformal passivation layer is SiO2 or SiN, Compared with the second conformal passivation layer used to protect the first conformal passivation layer, the first conformal passivation layer reduces the number of traps on the outer sidewall of the gate.

13. The method for forming an enhancement mode high electron mobility transistor on a substrate according to claim 11, wherein: The first conformal passivation layer is formed by atomic layer deposition.

14. The method for forming an enhancement mode high electron mobility transistor on a substrate according to claim 11, wherein: The second conformal passivation layer is formed by a different technique than forming the first conformal passivation layer.

15. The method for forming an enhancement mode high electron mobility transistor on a substrate according to claim 14, wherein: The first conformal passivation layer is formed by atomic layer deposition and has a thickness between 5 angstroms and 500 angstroms, and wherein the second conformal passivation layer is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition and has a thickness between 50nm and 500nm to protect the first conformal passivation layer during processing.

16. The method of forming an enhancement mode, high electron mobility transistor on a substrate according to claim 14, further comprising: forming a source / drain mask over the second conformal passivation layer; With the source / drain mask in place, performing an etch to form source / drain openings extending through the first conformal passivation layer and the second conformal passivation layer and terminating on the ternary III-nitride barrier layer; as well as The source / drain openings are filled with a conductive material.

17. The method of forming an enhancement mode, high electron mobility transistor on a substrate according to claim 16, further comprising: patterning the conductive material to form source / drain conductive bodies; forming a dielectric cap layer over the source / drain conductive body; forming a gate electrode mask over the dielectric cap layer; With the gate electrode mask in place, performing etching to form a gate electrode opening extending through the dielectric cap layer, the first conformal passivation layer, and the second conformal passivation layer, wherein the gate electrode opening terminates on the patterned doped binary III-nitride gate structure; as well as A conductive gate electrode liner is formed in the gate electrode opening.

18. The method of forming an enhancement mode, high electron mobility transistor on a substrate according to claim 17, wherein: The binary III-nitride channel layer is made of GaN; The ternary III-nitride barrier layer is composed of Al x Ga 1-x Made of N; The patterned doped binary III-nitride gate structure is n-type GaN or p-type GaN; and The dielectric capping layer is SiN or SiO2.

19. The method of forming an enhancement mode, high electron mobility transistor on a substrate according to claim 14, further comprising: before forming the binary III-nitride channel layer over the substrate, forming a first buffer layer; as well as Before forming the binary III-nitride channel layer over the substrate, a second buffer layer is formed over the first buffer layer.

20. The method of forming an enhancement mode, high electron mobility transistor on a substrate according to claim 19, wherein: The first conformal passivation layer is made of the same material as the first buffer layer.

21. An enhancement mode high electron mobility transistor formed on a substrate, comprising: An AlN buffer layer is located above the substrate; An AlGaN buffer layer, located above the AlN buffer layer; A GaN channel layer, located above the AlGaN buffer layer; An AlGaN barrier layer, located above the GaN channel layer; a GaN gate structure overlying the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has etched outer sidewalls of the gate structure; and a BN conformal passivation layer extending directly over all sidewall surfaces of the etched outer sidewalls of the GaN gate structure and an edge portion of an upper surface of the GaN gate structure to expose a remaining portion of the upper surface; A second passivation layer conformally covers the BN conformal passivation layer, and the BN conformal passivation layer and the second passivation layer are directly stacked on a portion of the etched outer side wall of the gate structure in a lateral direction, and the second passivation layer has no physical contact with the GaN gate structure, wherein the BN conformal passivation layer reduces the number of traps on the etched outer side wall of the GaN gate structure compared to the second passivation layer.

22. The enhancement mode high electron mobility transistor according to claim 21, wherein: The second passivation layer has a thickness of 50 nm to 500 nm, and a material composition of the second passivation layer is different from a material composition of the BN conformal passivation layer.

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