Display device

Abstract

A display device is provided, which includes a display unit, a timing controller and a scan driver. The display unit includes a scan line and a pixel connected to the scan line. The timing controller operates in a first mode and a second mode, and generates a start signal based on a vertical synchronization signal provided from the outside. The scan driver generates a scan signal based on the start signal and sequentially provides the scan signal to the scan line. The timing controller generates the start signal immediately after applying a pulse of the vertical synchronization signal in the first mode, and generates the start signal before applying a pulse of the vertical synchronization signal in the second mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0055082 filed on May 10, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure generally relates to a display device. Background Art

[0004] Display devices are used to visually present information to a user. Various applications such as televisions, computers, mobile phones, and head-mounted displays include display devices.

[0005] The display device may include a display panel and a driver. The display panel includes scan lines, data lines and pixels. The driver includes a scan driver configured to provide scan signals to the scan lines and a data driver configured to provide data signals to the data lines. Each of the plurality of pixels emits light having a brightness corresponding to the data signal provided by the corresponding data line in response to the scan signal provided by the corresponding scan line.

[0006] Recently, various types of wearable electronic devices have been developed. One variation of a wearable display device is mounted on a head-mounted display device called a head-mounted display (HMD). An HMD is a display device worn on or around the head that displays images using a small display in front of one or both eyes. HMDs have many applications, such as gaming, engineering, aviation, and medicine.

[0007] HMD can provide fast responsiveness to keep up with the user's head or body movements. Accordingly, the display device can be driven at a higher frequency to quickly refresh the image.

[0008] In currently available devices, the display device can be selectively driven in modes with different driving conditions (e.g., different driving frequencies, etc.). However, during the mode switching process, the image may be disconnected or may not be displayed. Accordingly, degradation of display quality, such as reduced brightness, may occur. Summary of the invention

[0009] Embodiments provide a display device capable of displaying a seamless image during mode switching between modes having different driving conditions.

[0010] According to one aspect of the present disclosure, a display device is provided, which includes a display unit, a timing controller and a scan driver, wherein the display unit includes scan lines and pixels connected to the scan lines, the timing controller is configured to operate in a first mode and a second mode and generate a start signal based on a vertical synchronization signal, and the scan driver is configured to generate a scan signal based on the start signal and sequentially provide the scan signal to the scan lines, wherein the timing controller generates the start signal immediately after a pulse of the vertical synchronization signal is applied in the first mode, and generates the start signal before a pulse of the vertical synchronization signal is applied in the second mode.

[0011] A first frame period before the mode of the display device is switched from the first mode to the second mode may include a first pulse and a second pulse of the start signal, and a pulse of the vertical synchronization signal may represent the start of the frame period.

[0012] In the first frame period, the start signal may have a second pulse immediately after the scan signal generated based on the first pulse of the start signal is supplied to the scan line. A width of the second frame period in the second mode may be smaller than a width of the first frame period in the first mode.

[0013] The timing controller may generate the start signal based on a horizontal synchronization signal provided from the outside. A width of a period of the horizontal synchronization signal in the second mode may be smaller than a width of a period of the horizontal synchronization signal in the first mode.

[0014] In the second mode, a time interval from a time when the start signal is generated to a time when a pulse of the vertical synchronization signal is applied may be equal to or less than three times a period of the horizontal synchronization signal.

[0015] The number of pulses of the horizontal synchronization signal included in the second frame period may be equal to the number of pulses of the horizontal synchronization signal included in the first frame period.

[0016] The timing controller may include a counter and a start signal generator, wherein the counter is configured to output a count value by counting the number of pulses of a horizontal synchronization signal relative to a vertical synchronization signal, and the start signal generator is configured to generate a start signal by comparing the count value with a predetermined value.

[0017] The counter may count the number of pulses of the horizontal synchronization signal upward in the first mode, and count the number of pulses of the horizontal synchronization signal backward from a reference value in the second mode.

[0018] During the period in which the scan signal generated based on the first pulse of the start signal is provided to the scan line in the second mode, the start signal may have a second pulse. In the second mode, the scan signal may be synchronously provided to at least two scan lines.

[0019] The display unit may include a first display area, a second display area, and a third display area divided by some of the scan lines. The first display area and the third display area may display a color image in a first mode and a monochrome image in a second mode. At a time when the scan signal is supplied to a second scan line corresponding to the second display area among the scan lines, the start signal may have a second pulse.

[0020] In the second mode, the scan signals may be synchronously provided to a first scan line corresponding to the first display area and a third scan line corresponding to the third display area among the scan lines.

[0021] The display device may further include a data driver configured to generate a data signal. The display unit may further include a data line. The pixel may be connected to the data line. In the second mode, during the period when the scan signal is provided to the first scan line corresponding to the first display area among the scan lines, the data driver may provide black data corresponding to black to the data line.

[0022] According to another aspect of the present disclosure, a display device including a display unit, a timing controller and a scan driver is provided. The display unit includes a scan line and a pixel connected to the scan line. The timing controller is configured to operate in a first mode and a second mode, and to generate a start signal based on a vertical synchronization signal provided from the outside. In addition, after applying a pulse of the vertical synchronization signal in the first mode, the timing controller generates a start signal. Then, in the second mode, the timing controller generates a start signal at the time when the pulse of the vertical synchronization signal is applied. The scan driver is configured to generate a scan signal based on the start signal, and sequentially provide the scan signal to the scan line.

[0023] The display unit may include a first display area, a second display area, and a third display area divided by some of the scan lines. The first display area and the third display area may display a color image in a first mode and a monochrome image in a second mode. The number of first scan lines corresponding to the first display area among the scan lines may be greater than the number of third scan lines corresponding to the third display area among the scan lines.

[0024] According to another aspect of the present disclosure, a system and method for controlling a display device are described. The method may include: selecting a first mode; transmitting a first vertical synchronization signal to a pixel; based on the first mode, transmitting a first start signal to the pixel after the first vertical synchronization signal; selecting a second mode; transmitting a second vertical synchronization signal to the pixel; and based on the second mode, transmitting a second start signal to the pixel synchronously with the second vertical synchronization signal or before the second vertical synchronization signal.

[0025] In some cases, the first mode includes a normal mode, and the second mode includes a low persistence mode (LPM).In some cases, based on the second mode, the second vertical synchronization signal is preceded by a vertical front porch (VFP) period and followed by a vertical back porch (VBP) period.

[0026] In some cases, the first vertical synchronization signal and the first start signal are transmitted during the first horizontal synchronization signal, and the second vertical synchronization signal and the second start signal are transmitted during the second horizontal synchronization signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, the exemplary embodiments may be used in different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, the element referred to may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the specification, similar reference numerals indicate similar elements.

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0031] Figure 3 It is shown that the Figure 1 A block diagram of an example of a scan driver in a display device shown in FIG.

[0032] Figure 4 It is shown in Figure 1 0 is a waveform diagram showing an example of a signal measured in the display device.

[0033] Figure 5 It is shown in Figure 1 ] is a waveform diagram of a comparative example of a signal measured in a display device shown in FIG.

[0034] Figure 6 It is shown that the Figure 1 A block diagram of an example of a timing controller in a display device shown in FIG.

[0035] Figure 7 It is shown in Figure 10 is a waveform diagram of another example of a signal measured in the display device shown in .

[0036] Figure 8 It is shown in Figure 1 0 is a waveform diagram of yet another example of a signal measured in the display device shown in . DETAILED DESCRIPTION

[0037] The present disclosure describes systems and methods for providing a display device with reduced luminous degradation upon mode switching. The mode switching may correspond to a switch from a normal mode to a low persistence mode (LPM). For example, the low persistence mode may be used to prevent motion blur.

[0038] In some examples, the display device may perform a mode switch when it needs to access system resources. The mode switch may be implemented through a system call interface or by an interrupt such as a page fault.

[0039] The present disclosure can be applied to display devices with different shapes. The present disclosure shows specific examples in detail. However, the present invention is not limited to certain shapes. On the contrary, the present disclosure can be applied to various changes, equivalent materials and substitutes.

[0040] In the following embodiments and drawings, elements that are not directly related to the present disclosure are omitted from the description, and the dimensional relationship between the various elements in the drawings is shown only for ease of understanding, rather than limiting the actual proportions. It should be noted that when assigning reference numerals to the elements of each drawing, similar reference numerals indicate similar elements even if similar elements are shown in different drawings.

[0041] Figure 1 is a block diagram showing a display device 100 according to an embodiment of the present disclosure.

[0042] Reference Figure 1 , the display device 100 may include a display unit 110 (or a display panel), a scan driver 120 (or a gate driver), a data driver 130 (or a source driver), a timing controller 140 and an emission driver 150 .

[0043] The display unit 110 may include scan lines SL1 to SLn (also referred to as gate lines), data lines DL1 to DLm, emission control lines EL1 to ELn, and pixels PXL, where n is a positive integer and m is a positive integer. The pixels PXL may be arranged in an area (e.g., a pixel area) defined by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the emission control lines EL1 to ELn.

[0044] Each pixel PXL may be coupled to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the emission control lines EL1 to ELn. For example, the pixel PXL may be coupled to the scan line SLi, the previous scan line SLi-1 adjacent to the scan line SLi, the data line DLj, and the emission control line ELi, where i and j are positive integers.

[0045] The pixel PXL may be initialized in response to a scan signal provided through the previous scan line SLi-1 (or a scan signal provided at a previous time or a previous gate signal). The pixel PXL may store or record a provided data signal in response to a scan signal provided through the scan line SLi (or a scan signal or a gate signal provided at a current time). The pixel PXL may emit light having a brightness corresponding to the stored data signal in response to an emission control signal provided through the emission control line ELi.

[0046] The display unit 110 may include display areas DA1, DA2, and DA3. For example, the display unit 110 may include a first display area DA1, a second display area DA2, and a third display area DA3. The first display area DA1, the second display area DA2, and the third display area DA3 may be distinguished from each other by a certain number of scan lines SL1 to SLn, and are arranged adjacent to each other. However, the present disclosure is not limited thereto.

[0047] The first display area DA1 may include first to p-th scan lines SL1 to SLp (p is a positive integer less than n), first to p-th emission control lines EL1 to ELp, and pixels PXL.

[0048] The second display area DA2 may include (p+1)th to qth scan lines SLp+1 to SLq (q is an integer greater than p and less than n), (p+1)th to qth emission control lines ELp+1 to ELq, and pixels PXL.

[0049] The third display area DA3 may include the (q+1)th to nth scan lines SLq+1, SLn, (q+1)th to nth emission control lines ELq+1, ELn, and pixels PXL. The number of the (q+1)th to nth scan lines SLq+1, SLn, SLn (i.e., nq) may be equal to the number of the first to pth scan lines SL1, SLp, but the present disclosure is not limited thereto. For example, the number of the (q+1)th to nth scan lines SLq+1, SLn (i.e., nq) may be less than the number of the first to pth scan lines SL1, SLp (i.e., p).

[0050] In some embodiments, the display device 100 may be driven in a first mode (or normal mode) or a second mode (or low persistence mode or low power mode). The first mode may be a conventional mode in which an image is displayed in the entire display unit 110, and the second mode may be a mode in which an image is displayed in a portion of the display unit 110 or an image with a high refresh rate (i.e., a frame image). For example, an image may be displayed in the first display area DA1, the second display area DA2, and the third display area DA3 in the first mode, and an image may be displayed in the second display area DA2 in the second mode. In the second mode, no image may be displayed in the first display area DA1 and the third display area DA3. For example, when the display device 100 is included (or installed) in a wearable device (e.g., an HMD) or when the display device 100 displays an AOD image (e.g., a clock image), the display device 100 may be driven in the second mode.

[0051] For example, when the display device 100 is included in a wearable device or when the display device 100 is used as a wearable device, the viewing range of the user (or the user's eyes) relative to the display device 100 may vary according to the spacing distance between the user and the display device 100. Accordingly, a faster refreshed image (e.g., a color image) may be arranged in the second display area DA2 within the user's viewing range. No image may be displayed in the first display area DA1 or the third display area DA3 beyond the user's viewing range. A monochrome image (e.g., a black image) may be displayed in the first display area DA1 or the third display area DA3.

[0052] At the same time, the first power supply voltage VDD and the second power supply voltage VSS may be provided to the display unit 110. The first power supply voltage VDD and the second power supply voltage VSS may be voltages used for the operation of the pixel PXL, and the first power supply voltage VDD may have a voltage level higher than that of the second power supply voltage VSS. In addition, an initialization power supply voltage Vint may be provided to the display unit 110. The first power supply voltage VDD, the second power supply voltage VSS and the initialization power supply voltage Vint may be provided to the display unit 110 from a separate power supply.

[0053] The scan driver 120 may generate a scan signal based on the scan control signal SCS, and sequentially provide the scan signal to the scan lines SL1 to SLn. The scan control signal SCS may include a start signal (or a start pulse) and a clock signal, etc., and may be provided from the timing controller 140. For example, the scan driver 120 may include a shift register (or a stage), wherein the shift register (or a stage) is configured to sequentially generate and output a pulse-form scan signal corresponding to the pulse-form start signal by using a clock signal.

[0054] The emission driver 150 may generate an emission control signal based on the emission drive control signal ECS, and sequentially or synchronously provide the emission control signal to the emission control lines EL1 to ELn. The emission drive control signal ECS may include an emission start signal and an emission clock signal, etc., and may be provided from the timing controller 140. For example, the emission driver 150 may include a shift register configured to sequentially generate and output a pulse-form emission control signal corresponding to the pulse-form emission start signal by using the emission clock signal.

[0055] The data driver 130 may generate a data signal based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and provide the data signal to the display unit 110 (or the pixel PXL). The data control signal DCS is a signal for controlling the operation of the data driver 130, and may include a load signal (or a data enable signal) for instructing the output of a valid data signal, etc.

[0056] The timing controller 140 may receive input image data DATA1 and a control signal CS from the outside (e.g., a graphics processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and generate image data DATA2 by converting the input image data DATA1. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like. The vertical synchronization signal may represent the start of a frame data (i.e., data corresponding to a frame period for displaying one frame of an image), and the horizontal synchronization signal may represent the start of a data row (i.e., one data row among a plurality of data rows included in the frame data). For example, the timing controller 140 may convert the input image data DATA1 in an RGB format into image data DATA2 in an RGB format corresponding to the arrangement of the pixels PXL in the display unit 110.

[0057] In some embodiments, the timing controller 140 may generate a start signal based on a vertical synchronization signal and a horizontal synchronization signal included in the control signal CS.

[0058] In an embodiment, the timing controller 140 may generate the start signal immediately after applying the pulse of the vertical synchronization signal in the first mode, and generate the start signal before applying the pulse of the vertical synchronization signal in the second mode. Figure 7 A description is given of a configuration in which a start signal is generated in the timing controller 140 .

[0059] Meanwhile, at least one of the scan driver 120, the data driver 130, the timing controller 140, and the emission driver 150 may be formed in the display unit 110. In addition, at least one of the scan driver 120, the data driver 130, the timing controller 140, and the emission driver 150 may be implemented with an integrated circuit (IC) to be coupled to the display unit 110 in a tape carrier package (TCP) form. At least two of the scan driver 120, the data driver 130, the timing controller 140, and the emission driver 150 may be implemented with a single IC.

[0060] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel PXL in a display device 100 is shown in FIG.

[0061] Reference Figure 2 , the pixel PXL may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting device LD.

[0062] Each of the first to seventh transistors T1 to T7 may be implemented with a P-type transistor, but the present disclosure is not limited thereto. For example, some of the first to seventh transistors T1 to T7 may be implemented with an N-type transistor.

[0063] The first electrode of the first transistor T1 (driving transistor) may be coupled to the second node N2. The first electrode of the first transistor T1 may also be coupled to the first power line (i.e., the power line to which the first power voltage VDD is applied) via the fifth transistor T5. The second electrode of the first transistor T1 may be coupled to the first node N1. The second electrode of the first transistor T1 may also be coupled to the anode of the light emitting device LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to the third node N3. The first transistor T1 may control the amount of current flowing from the first power line to the second power line (i.e., the power line transmitting the second power voltage VSS) via the light emitting device LD in correspondence with the voltage of the third node N3.

[0064] The second transistor T2 (switching transistor) may be coupled between the data line DLj and the second node N2. The gate electrode of the second transistor T2 may be coupled to the scan line SLi. When a scan signal is supplied to the scan line SLi, the second transistor T2 may be turned on to electrically couple the data line DLj and the first electrode of the first transistor T1 to each other.

[0065] The third transistor T3 may be coupled between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be coupled to the scan line SLi. When a scan signal is supplied to the scan line SLi, the third transistor T3 may be turned on to electrically couple the first node N1 and the third node N3 to each other. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be diode-coupled.

[0066] The storage capacitor Cst may be coupled between the first power line and the third node N3. The storage capacitor Cst may store a voltage corresponding to the data signal and a threshold voltage of the first transistor T1.

[0067] The fourth transistor T4 may be coupled between the third node N3 and an initialization power line (i.e., a power line transmitting an initialization power voltage Vint). A gate electrode of the fourth transistor T4 may be coupled to a previous scan line SLi-1. When a scan signal is supplied to the previous scan line SLi-1, the fourth transistor T4 may be turned on to supply the initialization power voltage Vint to the third node N3. The initialization power voltage Vint may be set to have a voltage level lower than a voltage level of the data signal.

[0068] The fifth transistor T5 may be coupled between the first power line and the second node N2. A gate electrode of the fifth transistor T5 may be coupled to the emission control line ELi. When the emission control signal is supplied to the emission control line ELi, the fifth transistor T5 may be turned off, otherwise it may be turned on.

[0069] The sixth transistor T6 may be coupled between the first node N1 and the light emitting device LD. A gate electrode of the sixth transistor T6 may be coupled to the emission control line ELi. When an emission control signal is supplied to the emission control line ELi, the sixth transistor T6 may be turned off, otherwise it may be turned on.

[0070] The seventh transistor T7 may be coupled between the initialization power line and the anode of the light emitting device LD. The gate electrode of the seventh transistor T7 may be coupled to the scan line SLi. When the scan signal is supplied to the scan line SLi, the seventh transistor T7 may be turned on to supply the initialization power voltage Vint to the anode of the light emitting device LD.

[0071] The anode of the light emitting device LD may be coupled to the first transistor T1 via the sixth transistor T6. The cathode of the light emitting device LD may be coupled to the second power supply line. The light emitting device LD may generate light having a predetermined brightness corresponding to the current supplied from the first transistor T1. The first power supply voltage VDD may be set to have a voltage level higher than that of the second power supply voltage VSS so that current flows through the light emitting device LD.

[0072] Figure 3 It is shown that the Figure 10 is a block diagram of an example of a scan driver 120 in a display device 100 shown in FIG.

[0073] Reference Figure 3 , the scan driver 120 may include stages ST1 to ST4 (or scan stages or scan stage circuits). The stages ST1 to ST4 may be respectively coupled to corresponding scan lines SL1 to SL4, and commonly coupled to a clock signal line (i.e., a signal line transmitting clock signals CLK1 and CLK2). The stages ST1 to ST4 may have substantially the same circuit structure.

[0074] Each of the stages ST1 to ST4 may include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0075] The first input terminal 101 may receive a carry signal. The carry signal may include a start signal FLM (or a start pulse) or an output signal (i.e., a scan signal) of a previous stage (or a previous terminal stage). For example, the first input terminal 101 of the first stage ST1 may receive the start signal FLM, and the first input terminal 101 of each of the other stages ST2 to ST4 may receive a scan signal of the previous stage. That is, the scan signal of the previous stage of the corresponding stage may be provided to the corresponding stage as a carry signal.

[0076] The second input terminal 102 of the first stage ST1 may be coupled to the first clock signal line to receive the first clock signal CLK1, and the third input terminal 103 of the first stage ST1 may be coupled to the second clock signal line to receive the second clock signal CLK2. The second input terminal 102 of the second stage ST2 may be coupled to the second clock signal line to receive the second clock signal CLK2, and the third input terminal 103 of the second stage ST2 may be coupled to the first clock signal line to receive the first clock signal CLK1. Similar to the first stage ST1, the second input terminal 102 of the third stage ST3 may be coupled to the first clock signal line to receive the first clock signal CLK1, and the third input terminal 103 of the third stage ST3 may be coupled to the second clock signal line to receive the second clock signal CLK2. Similar to the second stage ST2, the second input terminal 102 of the fourth stage ST4 may be coupled to the second clock signal line to receive the second clock signal CLK2, and the third input terminal 103 of the fourth stage ST4 may be coupled to the first clock signal line to receive the first clock signal CLK1. That is, the first and second clock signal lines may be alternately coupled to the second and third input terminals 102 and 103 , or the first and second clock signals CLK1 and CLK2 may be alternately provided to the second and third input terminals 102 and 103 of each stage.

[0077] The pulses of the first clock signal CLK1 provided through the first clock signal line and the pulses of the second clock signal CLK2 provided through the second clock signal line may not overlap each other in time. Each of the plurality of pulses may have a gate-on voltage level (or a turn-on voltage level). The gate-on voltage level may be a voltage level provided to the gate electrode of the transistor provided in each of the stages ST1 to ST4 to turn on the transistor.

[0078] Stages ST1 to ST4 may receive a first voltage VGH (or a high voltage level) and a second voltage VGL (or a low voltage level). The first voltage VGH may be set as a gate-off voltage level (or an off voltage level), and the second voltage VGL may be set as a gate-on voltage level.

[0079] Figure 4 It is shown in Figure 1 2 is a waveform diagram of an example of a signal measured in the display device 100. Figure 4 Graphs 1 and 2 show signals measured in the display device 100 driven in the first mode.

[0080] Reference Figure 1 and Figure 4 The vertical synchronization signal Vsync defines a frame period (or a start time of a frame period) for displaying a frame image. In addition, the horizontal synchronization signal Hsync defines a horizontal period at which a scan signal is output from the scan driver 120 or a data signal is output from the data driver 130.

[0081] The horizontal synchronization signal Hsync may be a pulse signal that periodically has a logic low level. A period of the horizontal synchronization signal Hsync may be defined as one horizontal time.

[0082] At the first time t1 (or at the first time point), the vertical synchronization signal Vsync may change from a logic high level to a logic low level. The vertical synchronization signal Vsync may have the same pulse width as that of the horizontal synchronization signal Hsync, but the present disclosure is not limited thereto.

[0083] At the second time t2, the start signal FLM may change from a logic high level (or a gate-off voltage level) to a logic low level (or a gate-on voltage level). Figure 4 4 shows a case where the second time t2 is a time after a lapse of one horizontal time from the first time t1, but the present disclosure is not limited thereto.

[0084] Figure 4The first time interval FLTE_H shown in can be preset as a time interval defining the output time of the start signal FLM with respect to the horizontal synchronization signal Hsync. For example, the first time interval FLTE_H can correspond to two horizontal times or more.

[0085] Based on the pulse of the vertical synchronization signal Vsync and the pulse of the horizontal synchronization signal Hsync, the timing controller 140 (see Figure 1 ) may generate a start signal FLM having a logic low level. Then, at a time after a specific time has elapsed from a time when a pulse of the vertical synchronization signal Vsync is generated, the timing controller 140 may output the start signal FLM having a logic low level. For example, at a second time t2 after a horizontal time has elapsed from a first time t1 at which a pulse of the vertical synchronization signal Vsync is generated, the timing controller 140 may output the start signal FLM having a logic low level.

[0086] At the same time, despite Figure 4 2 shows a case where the pulse width of the start signal FLM corresponds to two horizontal times, but the present disclosure is not limited thereto, and the pulse width of the start signal FLM may correspond to one horizontal time or three or more horizontal times.

[0087] At the third time t3 , the start signal FLM may be changed from a logic low level to a logic high level.

[0088] In addition, at the third time t3, the first scanning signal GW[1] (ie, provided to the reference Figure 1 The scanning signal of the first scanning line SL1 described above may be changed from a logic high level to a logic low level. Figure 3 The described scan driver 120 may output the first scan signal GW[1] corresponding to the start signal FLM having a logic low level.

[0089] According to reference Figure 3 According to the configuration of the scan driver 120 described above, the scan signals GW[1] to GW[n] may sequentially have a logic low level. The scan signals GW[1] to GW[n] having a logic low level may be sequentially provided to the scan lines SL1 to SLn (see Figure 1 ). For example, at the fourth time t4, the i-th scan signal GW[i] having a logic low level may be supplied to the i-th scan line SLi (see Figure 1 ).

[0090] At the fifth time t5, the nth scan line SLn (see Figure 1) the nth scan signal GW[n] may change from a logic high level to a logic low level. At a sixth time t6, the nth scan signal GW[n] may change to a logic high level.

[0091] During a period in which the scan signals GW[1] to GW[n] are sequentially output (ie, a period between the third time t3 and the sixth time t6), the data driver 130 (see Figure 1 ) The data signal outputted may have a valid value Normal DATA (or a voltage corresponding to the valid value). The display period (or recording period) may be defined as a period in which the scanning signals GW[1] to GW[n] having a logic low level are sequentially outputted.

[0092] Subsequently, at a seventh time t7 , the vertical synchronization signal Vsync may be changed from a logic high level to a logic low level.

[0093] At an eighth time t8 corresponding to the second time t2, the start signal FLM may change from a logic high level to a logic low level. At a ninth time t9 corresponding to the third time t3, the first scan signal GW[1] may change from a logic high level to a logic low level.

[0094] That is, a period between the first time t1 and the seventh time t7 may be defined as one frame period (eg, the first frame period FRAME1 ), and the display device 100 may repeatedly operate by using the frame period as a period.

[0095] Meanwhile, during a period in which the scan signals GW[1] to GW[n] having a logic low level are not output in a frame period, the data signal may have an invalid value (or a voltage corresponding to the invalid value). For example, in a period between the first time t1 and the third time t3, a period between the sixth time t6 and the ninth time t9, etc., the data signal may have a voltage corresponding to a block image (or a block color or a block gray value).

[0096] The period during which the scan signals GW[1] to GW[n] having a logic low level are not output in the frame period may be defined as a first porch period P_PORCH1 (or a vertical porch or blanking period). The sixth time t6 to the ninth time t9 are examples of a period, and the first porch period P_PORCH1 is a period between the end time of a display period and the start time of another display period.

[0097] Figure 5 It is shown in Figure 1 2 is a waveform diagram of a comparative example of a signal measured in the display device 100 shown in FIG. Figure 5 2 shows signals measured in the display device 100 which can be driven in the second mode or whose mode is switched from the first mode to the second mode.

[0098] Reference Figure 5 The operation of the display device 100 in the first frame period FRAME1 is similar to that of the reference Figure 4 The operations of the display device 100 described are substantially the same, and therefore, overlapping descriptions will not be repeated.

[0099] In a period (ie, a display period) between the third time t3 and the sixth time t6, the first to p-th scanning signals GW[1] to GW[p] may be sequentially provided to the reference PWM signal. Figure 1 The first to p-th scan lines SL1 to SLp corresponding to the first display area DA1 described above are sequentially provided with the (p+1)-th to q-th scan lines GW[p+1] and GW[q], respectively. Figure 1 The (p+1)th scanning line SLp+1 to the qth scanning line SLq corresponding to the second display area DA2 described above. Subsequently, the (q+1)th scanning signal GW[q+1] to the nth scanning signal GW[n] may be sequentially provided to the reference digits. Figure 1 The third display area DA3 described above corresponds to the (q+1)th scan line SLq+1 to the nth scan line SLn.

[0100] Meanwhile, during or before the first frame period FRAME1, a mode control signal for allowing the mode of the display device 100 to change from the first mode to the second mode may be provided to the display device 100 from an external source (eg, a graphics processor) (see Figure 1 )(or timing controller 140).

[0101] At the seventh time t7 , the mode of the display device 100 may start to be switched to the second mode.

[0102] In some embodiments, the period of the horizontal synchronization signal Hsync may be reduced. For example, the second period PW2 (i.e., one horizontal time in the second mode) of the horizontal synchronization signal Hsync in the second frame period FRAME2 (and the third frame period FRAME3) of driving the display device 100 in the second mode may be reduced to about 60% of the first period PW1 of the horizontal synchronization signal Hsync in the first frame period FRAME1 of driving the display device 100 in the first mode.

[0103] Therefore, the width of the frame period is reduced, and the frame image is displayed with relatively low persistence during a relatively short period of time. In addition, degradation of display quality such as motion blur can be reduced or prevented.

[0104] In addition, in the second frame period FRAME2 in which the display device 100 is driven in the second mode, referring to Figure 4The described first porch period P_PORCH1 (ie, a period during which the scan signals GW[ 1 ] to GW[n] having a logic low level are not output) may be omitted.

[0105] Therefore, the width of the frame period is reduced, and the frame image is displayed with lower persistence. In addition, the degradation of display quality can be further reduced.

[0106] In order to eliminate the first edge period P_PORCH1, after the last scan signal is output at the previous frame period, the first scan signal is output at the current frame period immediately, and the start signal FLM is generated at the last period of the previous frame period (or the period in which the scan signals GW[1] to GW[n] having a logic low level are output).

[0107] like Figure 5 As shown in , the start signal FLM may have a pulse having a logic low level at the eleventh time t11. The eleventh time t11 may be a time after a first time interval FLTE_H has elapsed from the seventh time t7 at which the vertical synchronization signal Vsync having a logic low level appears. The first time interval FLTE_H may have a width almost equal to a width of one frame period in the second mode.

[0108] When the start signal FLM is delayed from the seventh time t7 by the first time interval FLTE_H, the scan signals GW[ 1 ] to GW[n] may not be output in the second frame period FRAME2 .

[0109] Therefore, in the first frame period FRAME1, the pixel PXL (see Figure 2 ) are maintained by the scan signals GW[1] to GW[n]. The pixel PXL may additionally emit light during the second frame period FRAME2 (or the first delay time P_DELAY1) based on the pre-recorded data signal.

[0110] Reference Figure 2 The driving current described as flowing through the light emitting device LD via the first transistor T1 may leak through the third transistor T3 and the fourth transistor T4. As time passes, the voltage of the third node N3 is changed by the leakage current. In addition, the driving current is continuously reduced, and the brightness of the pixel PXL may be reduced. Since the brightness reduction during one frame period is within 1% of the target brightness, the brightness reduction in the first frame period FRAME1 (or the brightness reduction during the display device 100 is driven in the first mode) may not be observed by the user. However, when the brightness is additionally reduced during the second frame period FRAME2, the user may observe the brightness reduction in the second frame period FRAME2.

[0111] At the twelfth time t12 , the start signal FLM may be changed from a logic low level to a logic high level, and the scan signals GW[ 1 ] to GW[n] may sequentially have a logic low level in response to the start signal FLM.

[0112] For example, at the period between the twelfth time t12 and the fourteenth time t14, Figure 1 The first scanning signal GW[1] to the pth scanning signal GW[p] corresponding to the first display area DA1 described above may sequentially have a logic low level. Figure 1 The (p+1)th to qth scan signals GW[p+1] to GW[q] corresponding to the described second display area DA2 may sequentially have a logic low level.

[0113] Meanwhile, at the thirteenth time t13, the vertical synchronization signal Vsync may have a pulse having a logic low level, and corresponding to the vertical synchronization signal Vsync, just before the fifteenth time t15, the start signal FLM may have a pulse having a logic low level. At the fifteenth time t15, the first scan signal GW[1] may have a logic low level again.

[0114] Also, at the fifteenth time t15, the (q+1)th scanning signal GW[q+1] may have a logic low level. Figure 1 The (q+1)th to nth scan signals GW[q+1] to GW[n] corresponding to the described third display area DA3 may sequentially have a logic low level.

[0115] That is, in the second mode, the first scanning signal GW[1] to the p-th scanning signal GW[p] may be sequentially provided to the reference Figure 1 The first display area DA1 described above corresponds to the first scan line SL1 to the p-th scan line SLp. At the same time, the (q+1)-th scan signal GW[q+1] to the n-th scan signal GW[n] may be sequentially provided to the reference display area DA1. Figure 1 The third display area DA3 described above corresponds to the (q+1)th scan line SLq+1 to the nth scan line SLn.

[0116] As reference Figure 1As described, in the second mode, the same black image is displayed in the first display area DA1 and the third display area DA3, and accordingly, data signals corresponding to the same black grayscale value may be provided to the first display area DA1 and the third display area DA3. Therefore, the scan signals are synchronously provided to the first to p-th scan lines SL1 to SLp corresponding to the first display area DA1 and the (q+1)th scan lines SLq+1 to SLn corresponding to the third display area DA3, and the width of the frame period may be further reduced.

[0117] Since a black image is displayed in the first display area DA1 and the third display area DA3 in the second mode, the data signal may have a voltage corresponding to a black grayscale value at a period between the twelfth time t12 and the fourteenth time t14. Therefore, the first scanning signal GW[1] to the p-th scanning signal GW[p] corresponding to the first display area DA1 have a logic low level. During a previous black period VFP (or vertical front edge) and a next black period VBP (or vertical back edge) divided based on the vertical synchronization signal Vsync (for example, relative to the thirteenth time t13), the data signal may have a voltage corresponding to a black grayscale value. The previous black period VFP and the next black period VBP (the period between the twelfth time t12 and the fourteenth time t14) may be generally referred to as a black period.

[0118] At the same time, since an image is displayed in the second display area DA2 in the second mode, the data signal may have a valid value LPM DATA during the period between the fourteenth time t14 and the fifteenth time t15, during which the (p+1)th scanning signal GW[p+1] to the qth scanning signal GW[q] corresponding to the second display area DA2 have a logic low level.

[0119] As reference Figure 5 As described, the start signal FLM may be delayed by a first time interval FLTE_H (approximately one frame period) based on the vertical synchronization signal Vsync to have a pulse having a logic low level at a time when the q-th scanning signal GW[q] (i.e., the last scanning signal provided to the second display area DA2) has a logic high level. However, during the first time interval FLTE_H, the brightness is additionally reduced, and therefore, the brightness reduction may be observed by the user.

[0120] According to the embodiment of the present disclosure, the start signal FLM having a logic low level may be generated in the display device 100 before or in synchronization with a time when the vertical synchronization signal Vsync has a pulse having a logic low level.

[0121] Therefore, the display device 100 may select the first mode, transmit the first vertical synchronization signal Vsync to the pixel PXL, and transmit the first start signal FLM to the pixel PXL after the first vertical synchronization signal Vsync based on the first mode (for example, as shown in FIG. 1 ). Figure 4 The display device 100 may select the second mode, transmit the second vertical synchronization signal Vsync to the pixel PXL, and based on the second mode, transmit the second start signal FLM to the pixel PXL before the second vertical synchronization signal Vsync (for example, as described in reference to Figure 5 As described below Figure 7 In another embodiment, as described in Figure 8 As described, the second start signal FLM is transmitted to the pixel PXL in synchronization with the second vertical synchronization signal Vsync.

[0122] In some cases, the first mode includes a normal mode, and the second mode includes a low persistence mode (LPM).In some cases, based on the second mode, the second vertical synchronization signal Vsync is preceded by a vertical front porch VFP and followed by a vertical back porch VBP.

[0123] In some cases, the first vertical synchronization signal Vsync and the first start signal FLM are transmitted during the first horizontal synchronization signal Hsync, and the second vertical synchronization signal Vsync and the second start signal FLM are transmitted during the second horizontal synchronization signal Hsync.

[0124] Figure 6 It is shown that the Figure 1 1 is a block diagram of an example of a timing controller 140 in a display device 100 shown in FIG. Figure 6 2 briefly illustrates the timing controller 140 with respect to the function of generating the start signal FLM.

[0125] Reference Figure 1 , Figure 5 and Figure 6 The timing controller 140 may include a counter 610 (or a counting circuit) and a start signal generator 620 (or a start signal generating circuit). The counter 610 and the start signal generator 620 may be implemented using logic circuits.

[0126] The counter 610 may count pulses (or the number of pulses) of the horizontal synchronization signal Hsync with respect to the vertical synchronization signal Vsync, and output a count value CV of the pulses.

[0127] Will refer to Figure 5Describe an example. The counter 610 may start counting the pulses of the horizontal synchronization signal Hsync at the first time t1 when the pulse of the horizontal synchronization signal Hsync is applied. The counter 610 may also reset the count value of the pulse at the seventh time t7 when the next pulse of the vertical synchronization signal Vsync is applied, and re-count the pulses of the horizontal synchronization signal Hsync.

[0128] The number of pulses of the horizontal synchronization signal Hsync in the second mode may be equal to the number of pulses of the horizontal synchronization signal Hsync in the first mode. In the second mode, the number of pulses of the horizontal synchronization signal Hsync is included in the second frame period FRAME2 or the third frame period FRAME3. In the first mode, the pulses of the horizontal synchronization signal Hsync are included in the first frame period FRAME1. However, the present disclosure is not limited thereto.

[0129] In some embodiments, in response to the mode switching control signal C_LPM (or the mode switching signal from the first mode to the second mode), the counter 610 may count pulses of the horizontal synchronization signal Hsync in the reverse direction relative to the vertical synchronization signal Vsync. The mode switching control signal C_LPM is a mode control signal for allowing the mode of the display device 100 to switch from the first mode to the second mode. The mode switching control signal C_LPM may include a reference Figure 1 The control signal CS described above may be provided to the timing controller 140 from the outside (eg, a graphics processor).

[0130] Will refer to Figure 5 Describe an example. The counter 610 may count the pulse of the horizontal synchronization signal Hsync backward from a reference value (or a reference number) at a first time t1 when the pulse of the vertical synchronization signal Vsync is applied.

[0131] In an example, when the counter 610 counts pulses of the horizontal synchronization signal Hsync in the forward direction in the first mode, the counter 610 may output a count value CV having a value of 3 at the third time t3. In another example, when the counter 610 counts pulses of the horizontal synchronization signal Hsync in the reverse direction in the second mode, the counter 610 may output a count value CV having a value of 3 at the fifth time t5. The operation of the display device 100 related thereto will be described later with reference to FIG. Figure 7 Give a description.

[0132] The start signal generator 620 may compare the count value CV with a predetermined value, and when the count value CV is equal to the predetermined value, the start signal generator 620 may generate a start signal FLM based on the horizontal synchronization signal Hsync. The generated start signal FLM may be provided to the scan driver 120.

[0133] Will refer to Figure 5 Describe an example. The start signal generator 620 may receive a count value CV having a value of 1 at the second time t2 (or just before the second time t2). When the count value CV having a value of 1 is equal to a predetermined value (e.g., a value of 1), the start signal generator 620 may generate a start signal FLM by sampling and holding the horizontal synchronization signal Hsync.

[0134] As reference Figure 6 As described above, in the first mode, after applying the pulse of the vertical synchronization signal Vsync, the timing controller 140 generates the start signal FLM by counting the pulses of the horizontal synchronization signal Hsync in the forward direction, and in the second mode, before applying the pulse of the vertical synchronization signal Vsync, the start signal FLM is generated by counting the pulses of the horizontal synchronization signal Hsync in the reverse direction. Therefore, in the process of allowing the mode of the display device 100 to switch from the first mode to the second mode, the reference signal FLM does not occur. Figure 5 The first delay time P_DELAY1 is described, and the display quality will not be reduced.

[0135] Figure 7 It is shown in Figure 1 FIG. 1 is a waveform diagram of another example of a signal measured in the display device 100 shown in FIG. Figure 7 It is shown in Figure 5 The waveform diagram corresponding to the waveform diagram shown in .

[0136] Reference Figure 7 The operation of the display device 100 in the first frame period FRAME1 can be similar to that of the reference Figure 5 The operation of the display device 100 described above is substantially the same. In addition, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be the same as those of the reference Figure 5 The vertical synchronization signal Vsync and the horizontal synchronization signal Hsync described above are substantially the same, so the overlapping description will not be repeated.

[0137] In the first frame period FRAME1 or before the first frame period FRAME1, the mode switching control signal C_LPM (see Figure 6 ) may be provided to the timing controller 140. The mode switching control signal C_LPM is used to allow the mode of the display device 100 to switch from the first mode to the second mode.

[0138] The timing controller 140 may reverse count the pulses of the horizontal synchronization signal Hsync, and generate and output the start signal FLM at a sixth time t6 when the count value CV (or the reverse count value) becomes 2.

[0139] The twenty-first time t21 at which the start signal FLM having a logic low level is output in the second mode may be a time of a second time interval PRE_FLTE_H before the seventh time t7 at which a pulse of the vertical synchronization signal Vsync is generated. The size of the second time interval PRE_FLTE_H may be equal to the reference time. Figure 4 Describes the size of the first time interval FLTE_H.

[0140] At the same time, since the start signal FLM is generated based on the horizontal synchronization signal Hsync in the first frame period FRAME1 (i.e., the horizontal synchronization signal Hsync having the first period PW1 in the first mode), the start signal FLM may be output at the edge period P_PORCH2 of the first frame period FRAME1 (i.e., after the scanning signals GW[1] to GW[n] are output in the first frame period FRAME1). That is, just before the mode of the display device 100 is switched from the first mode to the second mode (i.e., at a period between a pulse of the vertical synchronization signal Vsync and a next pulse adjacent to the pulse of the vertical synchronization signal Vsync), two start signals FLM may be output in the first frame period FRAME1.

[0141] At the seventh time t7, the first scan signal GW[1] may change to a logic low level in response to the pulse of the start signal FLM. After the seventh time t7, the scan signals GW[1] to GW[n] may sequentially have a logic low level.

[0142] For example, in the period between the seventh time t7 and the tenth time t10, Figure 1 The first scanning signal GW[1] to the p-th scanning signal GW[p] corresponding to the first display area DA1 described above may sequentially have a logic low level. Figure 1 The (p+1)th to qth scan signals GW[p+1] to GW[q] corresponding to the described second display area DA2 may sequentially have a logic low level.

[0143] At the thirteenth time t13, the vertical synchronization signal Vsync may have a pulse with a logic low level, and corresponding to the vertical synchronization signal Vsync, at the twelfth time t12 a specific time before the thirteenth time t13 (for example, a time equal to or less than three horizontal times or two horizontal times), the start signal FLM may have a pulse with a logic low level.

[0144] In addition, at the thirteenth time t13, the (q+1)th scanning signal GW[q+1] may have a logic low level. Figure 1 The (q+1)th to nth scan signals GW[q+1] to GW[n] corresponding to the described third display area DA3 may sequentially have a logic low level.

[0145] Since a black image is displayed in the first display area DA1 (and the third display area DA3) in the second mode, the data signal may have a voltage corresponding to a black grayscale value during a period between the thirteenth time t13 and the fourteenth time t14, during which the first scan signal GW[1] to the pth scan signal GW[p] corresponding to the first display area DA1 have a logic low level.

[0146] At the same time, refer to Figure 5 The described previous black period VFP (ie, a period during which a voltage corresponding to a black gray value is output just before the vertical synchronization signal Vsync is generated) may be set to a value of 0.

[0147] As reference Figure 7 As described above, in the first frame period FRAME1 just before the mode of the display device 100 is switched from the first mode to the second mode (or at the edge period P_PORCH2 of the first frame period FRAME1), the start signal FLM having a logic low level is generated and output earlier than the vertical synchronization signal Vsync having a logic low level. Figure 5 The first delay time P_DELAY1 described above can prevent degradation of display quality in a process of allowing the mode of the display device 100 to be switched from the first mode to the second mode.

[0148] Figure 8 It is shown in Figure 1 FIG. 1 is a waveform diagram of another example of a signal measured in the display device 100. Figure 8 It is shown in Figure 7 The waveform diagram corresponding to the waveform diagram shown in .

[0149] Reference Figure 8 In the second mode, the start signal FLM is referenced Figure 7 The described start signal FLM is different in that the start signal FLM has a logic low level in synchronization with the vertical synchronization signal Vsync.

[0150] Except for the start signal FLM, the signals (ie, the scanning signals GW[1] to GW[n] and the data signals) are connected to the reference signal. Figure 7 The signals described are substantially the same or similar, and therefore, overlapping descriptions will not be repeated.

[0151] In the first frame period FRAME1 or before the first frame period FRAME1, a mode switching control signal C_LPM (see Figure 6 ) can be provided to the timing controller 140.

[0152] The timing controller 140 may reverse count the pulses of the horizontal synchronization signal Hsync, and generate and output the start signal FLM at the seventh time t7 when the count value CV (or the reverse count value) becomes 0. However, in the second mode, the timing controller 140 may output the start signal FLM having a logic low level in response to the vertical synchronization signal Vsync having a logic low level without counting the pulses of the horizontal synchronization signal Hsync.

[0153] Since the start signal FLM is output in synchronization with the vertical synchronization signal Vsync, the second frame period FRAME2 (and the third frame period FRAME3 ) may include a porch period P_PORCH3 during which the scan signals GW[ 1 ] to GW[n] are not output. Figure 8 The width of the second frame period FRAME2 shown in FIG. Figure 7 The width of the second frame period FRAME2 shown in FIG. Figure 1 The third display area DA3 (or the number of the (q+1)th scanning lines SLq+1 to the nth scanning lines SLn corresponding to the third display area DA3) is set to be smaller than the reference Figure 1 When describing the first display area DA1 (or the number of the first to p-th scan lines SL1 to SLp corresponding to the first display area DA1), Figure 8 The width of the second frame period FRAME2 shown in FIG. Figure 7 The width of the second frame period FRAME2 shown in .

[0154] At the thirteenth time t13, the vertical synchronization signal Vsync may have a pulse having a logic low level, and the start signal FLM may have a logic low level corresponding to the vertical synchronization signal Vsync. Subsequently, the first to p-th scanning signals GW[1] to GW[p] may sequentially have a logic low level.

[0155] Also, at the thirteenth time t13, the (q+1)th scanning signal GW[q+1] may have a logic low level. At a period between the thirteenth time t13 and the fourteenth time t14, the (q+1)th scanning signal GW[q+1] to the nth scanning signal GW[n] corresponding to the third display area DA3 may sequentially have a logic low level.

[0156] As reference Figure 8As described above, at the time when the mode of the display device 100 is switched from the first mode to the second mode, the start signal FLM having a logic low level is generated and output in synchronization with the vertical synchronization signal Vsync. Figure 5 The described first delay time P_DELAY1 is reduced to the second delay time P_DELAY2 (eg, several horizontal times), and degradation of display quality in allowing the mode of the display device 100 to be switched from the first mode to the second mode may be reduced or prevented.

[0157] In the display device 100 according to the present disclosure, when the display device 100 is driven in a mode of displaying an image with low persistence, the start signal FLM as a basis of the scanning signal may be generated earlier than the vertical synchronization signal Vsync, or generated synchronously with the vertical synchronization signal Vsync. Therefore, the display device 100 may display a seamless image during the mode switching process.

[0158] While the present invention has been described in conjunction with its preferred embodiments, it will be understood by those skilled in the art that various modifications and variations may be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.

[0159] Thus, the scope of the present invention should not be limited by the specific embodiments described herein, but should be defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: A display unit, the display unit comprising scan lines and pixels connected to the scan lines; a timing controller configured to operate in a first mode and a second mode and to generate a start signal based on a vertical synchronization signal; as well as a scan driver configured to generate a scan signal based on the start signal and sequentially supply the scan signal to the scan lines, The timing controller generates the start signal immediately after applying a pulse of the vertical synchronization signal in the first mode, and generates the start signal before applying the pulse of the vertical synchronization signal in the second mode.

2. The display device according to claim 1, wherein: A first frame period before the display device switches from the first mode to the second mode includes a first pulse and a second pulse of the start signal, and the pulse of the vertical synchronization signal represents the start of a frame period.

3. The display device according to claim 2, wherein: In the first frame period, immediately after the scan signal generated based on the first pulse of the start signal is supplied to the scan line, the start signal has the second pulse.

4. The display device according to claim 2, wherein: A width of a second frame period in the second mode is smaller than a width of the first frame period in the first mode.

5. The display device according to claim 4, wherein: The timing controller generates the start signal based on a horizontal synchronization signal provided from the outside, The width of the period of the horizontal synchronization signal in the second mode is smaller than the width of the period of the horizontal synchronization signal in the first mode.

6. The display device according to claim 5, wherein: In the second mode, a time interval from a time when the start signal is generated to a time when the pulse of the vertical synchronization signal is applied is equal to or less than three times the period of the horizontal synchronization signal.

7. The display device according to claim 5, wherein: The number of pulses of the horizontal synchronization signal included in the second frame period is equal to the number of pulses of the horizontal synchronization signal included in the first frame period.

8. The display device according to claim 7, wherein: The timing controller comprises: a counter configured to output a count value by counting the number of pulses of the horizontal synchronization signal with reference to the vertical synchronization signal; and A start signal generator is configured to generate the start signal by comparing the count value with a predetermined value.

9. The display device according to claim 8, wherein: The counter counts the number of pulses of the horizontal synchronization signal upward in the first mode, and counts the number of pulses of the horizontal synchronization signal backward from a reference value in the second mode.

10. The display device according to claim 1, wherein: In the second mode, the start signal has a second pulse while the scan signal generated based on the first pulse of the start signal is supplied to the scan line.

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