Anti-fuse memory cell and method for forming the same

Abstract

An anti-fuse memory cell and a method for forming the same, the anti-fuse memory cell comprising: a semiconductor substrate; an active region located in the semiconductor substrate, the active region comprising an interconnection region and a strip region, the strip region being located on one side of the interconnection region and connected to the interconnection region; a gate dielectric layer covering the entire surface of the active region; an upper electrode layer located on the gate dielectric layer, the upper electrode layer completely covering the gate dielectric layer on the surface of the active region; a first contact plug penetrating the upper electrode layer and the gate dielectric layer and connected to the interconnection region; and a second contact plug connected to the upper electrode layer. The programming voltage of the anti-fuse memory cell of the present invention is reduced.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a fuse storage unit and a forming method thereof. Background Art

[0002] Antifuse is a very important programmable interconnect unit. Semiconductor devices based on antifuse have very superior performance, which is mainly reflected in the following aspects: (1) It is non-volatile. The antifuse is programmed by programming voltage. After programming, the antifuse changes from one state to another. This state change is irreversible, and the changed programming state can be permanently saved. (2) It has high reliability. Studies have shown that the reliability of antifuse devices is one order of magnitude higher than that of application-specific integrated circuits. (3) It is 100% testable. Antifuse exhibits two completely different electrical characteristics before and after programming. The use of test circuits can achieve full coverage testing of large-scale antifuse arrays. (4) It is small in size, fast in speed, and low in power consumption. The use of advanced semiconductor process processing methods can make the antifuse extremely small, thereby effectively reducing the parasitic capacitance of the antifuse itself. On the other hand, after programming, the antifuse resistance can be as small as tens of ohms. Therefore, antifuse devices are not only fast, but also low in power consumption.

[0003] The antifuse is non-conductive when not activated, but becomes a conductor after activation (breakdown, metal diffusion, amorphous silicon becoming polysilicon, etc.), forming an electrical connection. It can selectively allow two devices or chips that were originally electrically isolated to be electrically connected, and can provide different resistance values ​​for performing logic operations.

[0004] The basic structure of the existing anti-fuse unit is a sandwich structure, including upper and lower electrodes and an anti-fuse dielectric layer located between the upper and lower electrodes. The more mature anti-fuse structures currently include: ONO (silicon oxide-silicon nitride-silicon oxide) electric fuse, amorphous silicon anti-fuse and gate oxide anti-fuse. Among them, since the formation process of ONO electric fuse and amorphous silicon anti-fuse is incompatible with the existing CMOS process, the most popular anti-fuse structure is gate oxide anti-fuse, which uses the substrate, gate oxide layer and gate electrode as the sandwich structure of the anti-fuse. However, the programming voltage of the existing gate oxide anti-fuse is still relatively large. Summary of the invention

[0005] The technical problem to be solved by the present invention is how to reduce the programming voltage of the existing gate oxide layer anti-fuse.

[0006] The present invention provides an anti-fuse storage unit, comprising:

[0007] Semiconductor substrate;

[0008] An active region located in the semiconductor substrate, the active region comprising an interconnection region and a strip region, the strip region being located on one side of the interconnection region and connected to the interconnection region;

[0009] A gate dielectric layer covering the entire surface of the active area;

[0010] An upper electrode layer located on the gate dielectric layer, wherein the upper electrode layer completely covers the gate dielectric layer on the surface of the active area;

[0011] A first contact plug penetrating the upper electrode layer and the gate dielectric layer and connected to the interconnection region;

[0012] A second contact plug connected to the upper electrode layer.

[0013] Optionally, the active area is in a rectangular, square or irregular shape, and the upper electrode layer is in a rectangular, square or irregular shape.

[0014] Optionally, the area of ​​the upper electrode layer is greater than or equal to the area of ​​the active region.

[0015] Optionally, a first through hole is provided in the upper electrode layer and the gate dielectric layer, the bottom of the first through hole exposes the surface of the interconnection region, and the first contact plug is located in the first through hole; a second through hole is provided on the upper electrode layer on one side of the interconnection region, and the second contact plug is located in the second through hole.

[0016] Optionally, an insulating layer is provided between the first contact plug and the upper electrode layer, an upper surface of the insulating layer is not lower than an upper surface of the upper electrode layer, and a bottom surface of the insulating layer contacts the interconnection region.

[0017] Optionally, the conductivity of the insulating layer is lower than the conductivity of the gate dielectric layer.

[0018] Optionally, when programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes the gate dielectric layer to be broken down.

[0019] The present invention also provides a method for forming an anti-fuse memory cell, comprising:

[0020] Providing a semiconductor substrate, wherein the semiconductor substrate has an active region, wherein the active region includes an interconnection region and a strip region, wherein the strip region is located on one side of the interconnection region and connected to the interconnection region;

[0021] forming a gate dielectric layer covering the entire surface of the active area;

[0022] forming an upper electrode layer on the gate dielectric layer, wherein the upper electrode layer completely covers the gate dielectric layer on the surface of the active area;

[0023] forming a first contact plug penetrating through the upper electrode layer and the gate dielectric layer and connected to the interconnection region;

[0024] A second contact plug connected to the upper electrode layer is formed.

[0025] Optionally, the active area is in a rectangular, square or irregular shape, and the upper electrode layer is in a rectangular, square or irregular shape.

[0026] Optionally, the area of ​​the upper electrode layer is greater than or equal to the area of ​​the active region.

[0027] Optionally, the formation process of the first contact plug includes: forming a dielectric layer on the upper electrode layer; etching the dielectric layer, the upper electrode layer and the gate dielectric layer to form a first through hole in the dielectric layer, the upper electrode layer and the gate dielectric layer, wherein the bottom of the first through hole exposes the surface of the interconnection area; and forming the first contact plug in the first through hole.

[0028] Optionally, before forming the first contact plug, an insulating layer is formed on the sidewall of the first through hole, the upper surface of the insulating layer is not lower than the upper surface of the upper electrode layer, and the bottom surface of the insulating layer contacts the interconnection region.

[0029] Optionally, the conductivity of the insulating layer is lower than the conductivity of the gate dielectric layer.

[0030] Optionally, the formation process of the second contact plug includes: etching the dielectric layer to form a second through hole in the dielectric layer, wherein the bottom of the second through hole exposes a portion of the surface of the upper electrode layer on one side of the interconnection region; and forming a second contact plug in the second through hole.

[0031] Optionally, when programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes the gate dielectric layer to be broken down.

[0032] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0033] In the anti-fuse memory cell of the present invention, since the upper electrode layer completely covers the gate dielectric layer on the surface of the active area, and the gate dielectric layer covers the entire surface of the active area, the upper electrode layer completely covers the surface of the active area, that is, the upper electrode layer covers not only the strip area but also the interconnection area. Compared with the anti-fuse memory cell in which the upper electrode layer only covers the strip area (the overlapping area between the upper electrode layer and the active area is small), the anti-fuse memory cell of the present invention fully utilizes the interconnection area under the condition of the same design size, increases the coverage area of ​​the upper electrode layer, greatly increases the overlapping area between the upper electrode layer and the active area, and increases the boundary length of the overlapping area between the active area and the upper electrode layer. Therefore, the stress effect (different materials contacting each other will generate stress) of the boundary area (the area corresponding to the boundary of the overlapping area between the active area and the upper electrode layer) is enhanced, so that more charges are gathered in the boundary area, and the electric field in the boundary area is enhanced. When programming is performed, the gate dielectric layer between the active area and the upper electrode layer is easily broken down, thereby effectively reducing the programming voltage of the anti-fuse memory cell. Furthermore, since the first contact plug is formed to penetrate the upper electrode layer, due to the stress effect (different materials in contact will produce stress) at the overlapping boundary between the first contact plug and the upper electrode layer, the electric field will gather in the boundary area between the two, making the gate dielectric layer between the upper electrode layer and the active area more easily broken down, further reducing the programming voltage of the anti-fuse memory cell.

[0034] Furthermore, when the active area is of an irregular shape, when a gate dielectric layer and an upper electrode layer located on the gate dielectric layer are subsequently formed on the active area, the boundary length of the overlapping area between the active area and the upper electrode layer is further increased (compared to the solution in which the upper electrode layer completely covers the active area in the present application), so that the stress effect (stress will be generated when different materials are in contact) of the boundary area (the area corresponding to the boundary of the overlapping area between the active area and the upper electrode layer) is further enhanced, so that more charges are gathered in the boundary area, and the electric field of the boundary area (the area corresponding to the boundary of the overlapping area between the active area and the upper electrode layer) is further enhanced, so that the gate dielectric layer between the active area and the upper electrode layer is more easily broken down during programming, thereby further reducing the programming voltage of the anti-fuse memory cell. In addition, when the active area is of an irregular shape, the irregular area on the semiconductor substrate can be fully utilized for the formation process of the anti-fuse memory cell (the regular area is used to form other devices of the integrated circuit, such as transistors, etc.), which can effectively improve the integration of the integrated circuit.

[0035] The method for forming the anti-fuse memory unit of the present invention has a simple forming process, and the formed anti-fuse memory unit can reduce the programming voltage of the anti-fuse memory unit while maintaining a high degree of integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1-10It is a structural schematic diagram of the formation process of the anti-fuse memory unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As mentioned in the background art, the existing gate oxide anti-fuse still requires a relatively large programming voltage during programming.

[0038] Research has found that, in one embodiment, the gate oxide anti-fuse structure generally includes a semiconductor substrate, an active area located in the semiconductor substrate, the active area including an interconnection area and a strip area connected to the interconnection area; a gate oxide layer located on the strip area; an upper electrode layer located on the gate oxide layer; a dielectric layer covering the upper electrode layer and the semiconductor substrate; a first contact plug and a second contact plug located in the dielectric layer, the first contact plug being electrically connected to the interconnection area, and the second contact plug being electrically connected to the upper electrode layer. When programming the gate oxide anti-fuse structure, a programming voltage is applied to the first contact plug and the second contact plug, and the gate oxide layer is broken down under the action of the programming voltage. Since the overlapping area or boundary length of the strip area and the upper electrode layer of the aforementioned gate oxide anti-fuse structure is fixed, it is difficult to reduce the programming voltage, so that the programming voltage is still large during programming, and the programming process may cause reliability problems (for example, the programming high voltage overshoots the high voltage of other parts of the circuit).

[0039] To this end, the present invention provides an anti-fuse memory cell and a method for forming the same, so as to reduce the programming voltage of the anti-fuse memory cell.

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0041] Figure 1-10 It is a structural schematic diagram of the formation process of the anti-fuse memory unit according to an embodiment of the present invention.

[0042] refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 A top view structural schematic diagram is provided, providing a semiconductor substrate 201, wherein the semiconductor substrate 201 has an active area 205, wherein the active area 205 includes an interconnection area 204 and a strip area 203, wherein the strip area 203 is located on one side of the interconnection area 204 and connected to the interconnection area 204.

[0043] The material of the semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 201 is silicon.

[0044] The semiconductor substrate 201 has an active region 205, and the active region 205 is subsequently used as the lower electrode of the anti-fuse memory cell. Impurity ions are doped in the active region 205, and the impurity ions are P-type impurity ions or N-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions. In this embodiment, only one active region 205 in the semiconductor substrate 201 is used as an example for description. In other embodiments, the number of the active regions 205 is greater than one.

[0045] A shallow trench isolation structure 202 is also formed in the semiconductor substrate 201. The shallow trench isolation structure 202 is used to isolate different active areas 205 to prevent electrical connection between different active areas 205. The material of the shallow trench isolation structure 202 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0046] In one embodiment, the formation process of the shallow trench isolation structure 202 includes: forming a mask layer on the semiconductor substrate 201, the mask layer having an opening exposing the surface of the semiconductor substrate; etching the semiconductor substrate 201 along the opening to form a trench in the semiconductor substrate 201; filling the trench with isolation material to form a shallow trench isolation structure 202.

[0047] The portion of the semiconductor substrate surrounded by the shallow trench isolation structure 202 serves as an active area 205 .

[0048] In this embodiment, the active area 205 includes an interconnection area 204 and a strip area 203. The strip area 203 serves as the main structure of the lower electrode of the anti-fuse memory cell. The interconnection area 204 is connected to an interconnection line for applying a programming voltage. Specifically, the interconnection area 204 is subsequently used to connect to the first contact plug.

[0049] The shape of the active area 205 can be a rectangle, a square or an irregular shape. The irregular shape means that the shape of the active area 205 is a non-regular polygon, such as Figure 2As shown, the active area 205 is of an irregular shape (including two rectangles of different sizes). When the active area 205 is of an irregular shape, when a gate dielectric layer and an upper electrode layer located on the gate dielectric layer are subsequently formed on the active area 205, the boundary length of the overlapping area between the active area 205 and the upper electrode layer is further increased (compared to the solution in which the upper electrode layer completely covers the active area in the present application), so that the stress effect (different materials in contact will generate stress) of the boundary area (the area corresponding to the boundary of the overlapping area between the active area 205 and the upper electrode layer) is further enhanced, so that more charges are gathered in the boundary area, and the electric field of the boundary area (the area corresponding to the boundary of the overlapping area between the active area 205 and the upper electrode layer) is further enhanced. When programming, the gate dielectric layer between the active area 205 and the upper electrode layer is more easily broken down, thereby further reducing the programming voltage of the anti-fuse memory cell. In addition, when the active area 205 is irregular in shape, the irregular area on the semiconductor substrate can be fully utilized for the formation process of the anti-fuse memory unit (the regular area is used to form other devices of the integrated circuit, such as transistors, etc.), which can effectively improve the integration of the integrated circuit.

[0050] In one embodiment, the active region 205 may be formed simultaneously with other active regions used to form other devices (such as transistors, memories).

[0051] refer to Figure 3 , forming a gate dielectric layer 206 covering the entire surface of the active area 205.

[0052] The gate dielectric layer 206 covers the entire surface of the active region 205. In one embodiment, the gate dielectric layer 206 not only covers the entire surface of the active region 205, but also covers the surface of the shallow trench isolation structure 202.

[0053] In one embodiment, the gate dielectric layer 206 is made of silicon oxide, and the formation process includes thermal oxidation and deposition process. It should be noted that in other embodiments, the gate dielectric layer can be made of other suitable materials.

[0054] refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 , an upper electrode layer 207 is formed on the gate dielectric layer 206 , and the upper electrode layer 207 completely covers the gate dielectric layer 206 on the surface of the active area 205 .

[0055] The upper electrode layer 207 serves as the upper electrode of the anti-fuse memory cell. In this embodiment, since the upper electrode layer 207 completely covers the gate dielectric layer 206 on the surface of the active area 205, and the gate dielectric layer 206 covers the entire surface of the active area 205, in this application, the upper electrode layer 207 completely covers the surface of the active area 205, that is, the upper electrode layer 207 not only covers the strip area 203 but also covers the interconnection area 204. Compared with the anti-fuse memory cell in which the upper electrode layer only covers the strip area (the overlapping area between the upper electrode layer and the active area is small), the anti-fuse memory cell in this application makes full use of the interconnection area 204 under the condition of the same design size, increases the coverage area of ​​the upper electrode layer, greatly increases the overlapping area between the upper electrode layer and the active area, and increases the boundary length of the overlapping area between the active area 205 and the upper electrode layer (refer to Fig.10 The position of the thick solid line frame in the middle), therefore, the stress effect (different materials contacting each other will produce stress) of the boundary area (the area corresponding to the boundary of the overlapping area of ​​the active area 205 and the upper electrode layer 207) will be enhanced, so that more charges will be gathered in the boundary area, and the electric field in the boundary area will be enhanced. When programming, the gate dielectric layer between the active area 205 and the upper electrode layer will be easily broken down, thereby effectively reducing the programming voltage of the anti-fuse memory cell.

[0056] The shape of the upper electrode layer 207 may be rectangular, square or irregular, and the material of the upper electrode layer 207 may be polysilicon or metal, and the metal may be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0057] The area of ​​the upper electrode layer 207 is greater than or equal to the area of ​​the active region 205 .

[0058] In this embodiment, the upper electrode layer 207 completely covers the gate dielectric layer 206 on the surface of the active area 205. The upper electrode layer 207 may also cover the gate dielectric layer on the shallow trench isolation layer 202. The upper electrode layer 207 may be formed by a deposition process.

[0059] Combined with reference Figure 6-Figure 10 , forming a first contact plug 212 penetrating the upper electrode layer 207 and the gate dielectric layer 206 and connected to the interconnection region 204 (refer to Fig. 9 ); forming a second contact plug 213 connected to the upper electrode layer 207 (reference Fig. 9 ).

[0060] The first contact plug 212 and the second contact plug 213 are used to apply a programming voltage to the first contact plug 212 and the second contact plug 213 when programming the anti-fuse memory cell, and the programming voltage causes the gate dielectric layer 206 to be broken down. Before and after the gate dielectric layer 206 is broken down, the resistance between the upper electrode layer 207 and the active area 205 changes greatly. Before the gate dielectric layer 206 is broken down, the upper electrode layer 207 and the active area 205 present a high resistance state, and after the gate dielectric layer 206 is broken down, the upper electrode layer 207 and the active area 205 present a low resistance state, so that data "1" or "0" is stored according to whether the gate dielectric layer 206 is broken down.

[0061] In one embodiment, the process of forming the first contact plug includes: referring to Figure 6 , a dielectric layer 208 is formed on the upper electrode layer 207, and the dielectric layer 208 can be formed by a deposition process. The material of the dielectric layer 208 can be SiO2, SiN, SiON, SiCN, SiC, low-K (dielectric constant) or ultra-low-K material; refer to Figure 7 , etching the dielectric layer 208, the upper electrode layer 207 and the gate dielectric layer 206, forming a first through hole 209 in the dielectric layer 208, the upper electrode layer 207 and the gate dielectric layer 206, wherein the bottom of the first through hole 209 exposes the surface of the interconnection region 204, and the etching may be performed by anisotropic dry etching, such as a plasma etching process; Figure 8 and Fig. 9 , forming a first contact plug 212 in the first through hole, the specific process includes: forming a metal layer in the first through hole and on the surface of the dielectric layer 208, the metal layer fills the first through hole, planarizing and removing the metal layer above the surface of the dielectric layer 208, and forming a first metal plug 212 in the first through hole.

[0062] The material of the first metal plug 212 is metal, and the metal may be one or more of W, Al, Cu, Ti, Ta, and Co.

[0063] In one embodiment, before forming the first contact plug 212, an insulating layer 211 is formed on the sidewall of the first through hole 209 (see Figure 8 ), the upper surface of the insulating layer 211 is not lower than the upper surface of the upper electrode layer 207, the bottom surface of the insulating layer 211 contacts the interconnection region 204, the conductivity of the insulating layer 211 is lower than the conductivity of the gate dielectric layer 206, and the insulating layer 211 is used to prevent the first contact plug 212 from being electrically connected to the upper electrode layer 207. In one embodiment, the material of the insulating layer 211 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0064] In one embodiment, the formation process of the second contact plug 213 includes: etching the dielectric layer 208, forming a second through hole 210 in the dielectric layer 208 (refer to Figure 8 ), the bottom of the second through hole 210 exposes a portion of the surface of the upper electrode layer 207 on one side of the interconnection region 204; a second contact plug 213 is formed in the second through hole 210, and the material of the second contact plug 213 is metal.

[0065] The steps of forming the first contact plug 212 and the second contact plug 213 can be performed separately or simultaneously. When the steps of forming the first contact plug 212 and the second contact plug 213 are performed simultaneously (i.e., when forming the first through hole 209, the second through hole 210 can be formed simultaneously, and then a metal layer is formed simultaneously in the first through hole 209 and the second through hole 210 and on the surface of the dielectric layer 208, and then the metal layer on the surface of the dielectric layer 208 is removed by planarization, and the first contact plug 212 is formed in the first through hole 209, and the second contact plug 213 is formed in the second through hole 210), in order to prevent the upper electrode layer 207 at the bottom of the second through hole 210 from being further etched when etching the first through hole 209, an etching stop layer is formed on the surface of the upper electrode layer 207 at a position corresponding to the second through hole 210 before forming the dielectric layer 208.

[0066] In the present embodiment, since the first contact plug 212 is formed to penetrate the upper electrode layer 207, due to the stress effect (different materials in contact will produce stress) at the overlapping boundary between the first contact plug 212 and the upper electrode layer 207, the electric field will gather in the boundary area between the two, making the gate dielectric layer 206 between the upper electrode layer 207 and the active area 205 more easily broken down, further reducing the programming voltage of the anti-fuse memory cell.

[0067] The present invention also provides an anti-fuse storage unit, please refer to Fig. 9 and Fig.10 ,include:

[0068] Semiconductor substrate 201;

[0069] An active region 205 located in the semiconductor substrate 201, wherein the active region 205 includes an interconnection region 204 and a strip region 203, wherein the strip region 203 is located at one side of the interconnection region 204 and connected to the interconnection region 204;

[0070] A gate dielectric layer 206 covering the entire surface of the active area 205;

[0071] An upper electrode layer 207 located on the gate dielectric layer 206 , wherein the upper electrode layer 207 completely covers the gate dielectric layer 206 on the surface of the active region 205 ;

[0072] A first contact plug 212 penetrating the upper electrode layer 207 and the gate dielectric layer 206 and connected to the interconnection region 204;

[0073] A second contact plug 213 connected to the upper electrode layer 207 .

[0074] In one embodiment, the active area 205 is in a rectangular, square or irregular shape, and the upper electrode layer 207 is in a rectangular, square or irregular shape.

[0075] The area of ​​the upper electrode layer 207 is greater than or equal to the area of ​​the active region.

[0076] Specifically, a first through hole is formed in the upper electrode layer 207 and the gate dielectric layer 206 , the bottom of the first through hole exposes the surface of the interconnection region 204 , and the first contact plug 212 is located in the first through hole.

[0077] An insulating layer 211 is provided between the first contact plug 212 and the upper electrode layer 207 ; a shallow trench isolation structure 202 is provided in the semiconductor substrate 201 around the active area 205 .

[0078] The upper surface of the insulating layer 211 is not lower than the upper surface of the upper electrode layer 207 , the bottom surface of the insulating layer 211 contacts the interconnection region 204 , and the conductivity of the insulating layer 211 is lower than that of the gate dielectric layer 206 .

[0079] When programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug 212 and the second contact plug 213 , and the programming voltage causes the gate dielectric layer 206 to be broken down.

[0080] It should be noted that the limitations or descriptions of the same or similar structures in this embodiment as those in the aforementioned embodiments are not repeated in this embodiment. For details, please refer to the limitations or descriptions of the corresponding parts in the aforementioned anti-fuse memory unit formation process embodiment.

[0081] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An anti-fuse memory cell, characterized in that: include: Semiconductor substrate; An active region located in the semiconductor substrate, the active region comprising an interconnection region and a strip region, the strip region being located on one side of the interconnection region and connected to the interconnection region; A gate dielectric layer covering the entire surface of the active area; an upper electrode layer located on the gate dielectric layer, wherein the upper electrode layer completely covers the gate dielectric layer on the surface of the active area; A first contact plug penetrating the upper electrode layer and the gate dielectric layer and connected to the interconnection region; A second contact plug connected to the upper electrode layer.

2. The anti-fuse memory cell according to claim 1, wherein: The active area is in a rectangular, square or irregular shape, and the upper electrode layer is in a rectangular, square or irregular shape.

3. The anti-fuse memory cell according to claim 1 or 2, characterized in that: The area of ​​the upper electrode layer is greater than or equal to the area of ​​the active region.

4. The anti-fuse memory cell according to claim 1, wherein: A first through hole is provided in the upper electrode layer and the gate dielectric layer, the bottom of the first through hole exposes the surface of the interconnection area, and the first contact plug is located in the first through hole; a second through hole is provided on the upper electrode layer on one side of the interconnection area, and the second contact plug is located in the second through hole.

5. The anti-fuse memory cell according to claim 4, wherein: An insulating layer is provided between the first contact plug and the upper electrode layer, the upper surface of the insulating layer is not lower than the upper surface of the upper electrode layer, and the bottom surface of the insulating layer contacts the interconnection region.

6. The anti-fuse memory cell according to claim 5, wherein: The conductivity of the insulating layer is lower than the conductivity of the gate dielectric layer.

7. The anti-fuse memory cell according to claim 1, wherein: When programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes the gate dielectric layer to be broken down.

8. A method for forming an anti-fuse memory cell, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has an active region, wherein the active region includes an interconnection region and a strip region, wherein the strip region is located on one side of the interconnection region and connected to the interconnection region; forming a gate dielectric layer covering the entire surface of the active area; forming an upper electrode layer on the gate dielectric layer, wherein the upper electrode layer completely covers the gate dielectric layer on the surface of the active area; forming a first contact plug penetrating through the upper electrode layer and the gate dielectric layer and connected to the interconnection region; A second contact plug connected to the upper electrode layer is formed.

9. The method for forming an anti-fuse memory cell according to claim 8, wherein: The active area is in a rectangular, square or irregular shape, and the upper electrode layer is in a rectangular, square or irregular shape.

10. The method for forming an anti-fuse memory cell according to claim 8 or 9, characterized in that: The area of ​​the upper electrode layer is greater than or equal to the area of ​​the active region.

11. The method for forming an anti-fuse memory cell according to claim 8, wherein: The formation process of the first contact plug includes: forming a dielectric layer on the upper electrode layer; etching the dielectric layer, the upper electrode layer and the gate dielectric layer to form a first through hole in the dielectric layer, the upper electrode layer and the gate dielectric layer, wherein the bottom of the first through hole exposes the surface of the interconnection area; and forming the first contact plug in the first through hole.

12. The method for forming an anti-fuse memory cell according to claim 11, wherein: Before forming the first contact plug, an insulating layer is formed on the sidewall of the first through hole, the upper surface of the insulating layer is not lower than the upper surface of the upper electrode layer, and the bottom surface of the insulating layer contacts the interconnection region.

13. The method for forming an anti-fuse memory cell according to claim 12, wherein: The conductivity of the insulating layer is lower than the conductivity of the gate dielectric layer.

14. The method for forming an anti-fuse memory cell according to claim 8, wherein: The formation process of the second contact plug includes: etching the dielectric layer to form a second through hole in the dielectric layer, the bottom of the second through hole exposing a portion of the surface of the upper electrode layer on one side of the interconnection area; forming the second contact plug in the second through hole.

15. The method for forming an anti-fuse memory cell according to claim 8, wherein: When programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes the gate dielectric layer to be broken down.

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