Vertical memory device

Abstract

A vertical memory device includes a plurality of channels, a channel connection pattern, a plurality of gate electrodes, and sequentially stacked etch stop and blocking patterns on a substrate. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connection pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The plurality of gate electrodes are spaced apart from each other in the first direction on the channel connection pattern and extend in the second direction to surround the plurality of channels. The etch stop and blocking patterns are sequentially stacked in a third direction on end portions of the channel connection pattern in the third direction, the third direction being parallel to the upper surface of the substrate and crossing the second direction, the etch stop and blocking patterns including different materials from each other.

Description

[0001] Cross-reference to related applications

[0002] The entire contents of Korean Patent Application No. 10-2019-0054233, entitled "Vertical Memory Devices and Methods of Manufacturing the Same", filed with the Korean Intellectual Property Office on May 9, 2019, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to vertical storage devices and methods of manufacturing the same. Background Technology

[0004] During the fabrication of VNAND flash memory devices, a sacrificial layer can be formed between the substrate and the mold, a channel can be formed through the mold and the sacrificial layer, an opening can be formed through the mold and the sacrificial layer, the sacrificial layer exposed through the opening can be removed to form a gap, and the gap can be filled with a polysilicon layer so that the channels can be connected to each other. Summary of the Invention

[0005] An embodiment can be implemented by providing a vertical memory device comprising: a substrate; a plurality of channels on the substrate, each channel extending in a first direction perpendicular to an upper surface of the substrate; a channel connection pattern extending in a second direction parallel to the upper surface of the substrate to cover the outer walls of the plurality of channels, the channel connection pattern connecting the plurality of channels to each other; a plurality of gate electrodes located on the channel connection pattern and spaced apart from each other in the first direction, each gate electrode extending in the second direction to surround the plurality of channels; and an etch stop pattern and a blocking pattern sequentially stacked at the ends of the channel connection pattern in a third direction parallel to the upper surface of the substrate and intersecting the second direction, wherein the etch stop pattern and the blocking pattern comprise different materials from each other.

[0006] An embodiment can be implemented by providing a vertical memory device comprising: a substrate; a channel connection pattern on the substrate; a plurality of gate electrodes spaced apart from each other on the channel connection pattern and in a first direction perpendicular to an upper surface of the substrate, each gate electrode extending in a second direction parallel to the upper surface of the substrate; a channel on the substrate and extending through the plurality of gate electrodes and the channel connection pattern in the first direction; and a seed pattern located between the substrate and the channel connection pattern and between the channel and the channel connection pattern, the seed pattern comprising silicon and impurities.

[0007] An embodiment can be implemented by providing a vertical memory device comprising: a substrate including a first region and a second region surrounding the first region; a plurality of channels located on the first region of the substrate, each channel extending in a first direction perpendicular to an upper surface of the substrate; a channel connection pattern located on the first region of the substrate and extending in a second direction parallel to the upper surface of the substrate, the channel connection pattern covering the outer walls of the plurality of channels and connecting the plurality of channels to each other; a sacrificial layer structure located on the second region of the substrate and extending in the second direction at a height substantially equal to the height of the channel connection pattern, the sacrificial layer structure including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer stacked sequentially in the first direction; a support layer located on the channel connection pattern and the sacrificial layer structure; and a plurality of gate electrodes located on the support layer and spaced apart from each other in the first direction, each gate electrode extending in the second direction to surround the plurality of channels.

[0008] An embodiment can be implemented by providing a vertical memory device, the vertical memory device comprising: a substrate including a cell region and an extended region surrounding the cell region; a plurality of channels located on the cell region of the substrate, each channel extending in a first direction perpendicular to the upper surface of the substrate, wherein the memory cell is located on the cell region of the substrate, and a contact pin for applying a signal to the memory cell is located on the extended region of the substrate; a channel connection pattern located on the cell region of the substrate, the channel connection pattern covering the outer walls of the channels and connecting the plurality of channels to each other; and spaced apart from each other along the first direction on the cell region and the extended region of the substrate. A gate electrode structure comprising a plurality of gate electrodes, each gate electrode surrounding the plurality of channels; a common source line (CSL) extending through the gate electrode structure and the channel connection pattern to contact the upper surface of the substrate, the CSL extending in a second direction parallel to the upper surface of the substrate to separate each of the gate electrode structure and the channel connection pattern in a third direction parallel to the upper surface of the substrate and intersecting the second direction; and spacers located on the sidewalls of the CSL, wherein the maximum width of the spacers located on the cell region of the substrate in the third direction is greater than the maximum width of the spacers located on the extended region of the substrate in the third direction.

[0009] An embodiment can be implemented by providing a vertical memory device comprising: a substrate; a plurality of channels on the substrate, each channel extending in a first direction perpendicular to an upper surface of the substrate; a channel connection pattern on the substrate, the channel connection pattern covering the outer walls of the channels and connecting the plurality of channels to each other; a gate electrode structure on the substrate and including a plurality of gate electrodes spaced apart from each other in the first direction, each gate electrode surrounding the plurality of channels; and a common source line (CSL) extending through the gate electrode structure and the channel connection pattern to contact the upper surface of the substrate, the CSL extending in a second direction parallel to the upper surface of the substrate to separate each of the gate electrode structure and the channel connection pattern in a third direction parallel to the upper surface of the substrate and intersecting the second direction, wherein etch stop patterns, barrier patterns and spacers comprising silicon oxide, metal oxide and metal silicide, respectively, are sequentially stacked between the channel connection pattern and the CSL in the third direction.

[0010] An embodiment can be implemented by providing a method for manufacturing a vertical memory device, the method comprising: sequentially forming a sacrificial layer structure and a support layer on a substrate; alternately and repeatedly stacking an insulating layer and a sacrificial layer on the support layer; forming a channel through the sacrificial layer structure, the support layer, the insulating layer, and the sacrificial layer to contact an upper surface of the substrate; forming a first opening through the insulating layer, the sacrificial layer, and the support layer to expose at least a portion of the sacrificial layer structure; removing the at least a portion of the sacrificial layer structure exposed through the first opening to form a first gap exposing a portion of a lower surface of the support layer; oxidizing the exposed portion of the lower surface of the support layer and removing the oxidized portion; removing the sacrificial layer structure to form a second gap exposing the outer sidewalls of the channel; forming a channel connection pattern to partially fill the second gap, the channel connection pattern surrounding the channel and exposing a portion of the upper surface of the substrate; oxidizing the exposed portion of the upper surface of the substrate and the sidewalls of the channel connection pattern to form an etch stop pattern; removing the sacrificial layer to form a third gap; and forming a gate electrode in the third gap.

[0011] An embodiment can be implemented by providing a method for manufacturing a vertical memory device, the method comprising: sequentially forming a sacrificial layer structure and a support layer on a substrate; alternately and repeatedly stacking an insulating layer and a sacrificial layer on the support layer; forming a channel through the sacrificial layer structure, the support layer, the insulating layer, and the sacrificial layer to contact an upper surface of the substrate; forming an opening through the insulating layer, the sacrificial layer, and the support layer to expose at least a portion of the sacrificial layer structure; removing the at least a portion of the sacrificial layer structure exposed through the opening to form a first gap exposing a portion of a lower surface of the support layer; removing The process includes: removing the exposed portion of the lower surface of the support layer; removing the sacrificial layer structure to form a second gap exposing the outer wall of the channel; forming a seed layer comprising amorphous silicon, carbon, nitrogen, or oxygen on the exposed upper surface of the substrate, the lower surface of the support layer, and the outer wall of the channel exposed through the second gap; forming a channel connection pattern to partially fill the second gap, the channel connection pattern surrounding the channel and exposing the portion of the seed layer on the upper surface of the substrate; removing the sacrificial layer to form a third gap; and forming a gate electrode in the third gap.

[0012] An embodiment can be implemented by providing a method for manufacturing a vertical memory device, the method comprising: forming a sacrificial layer structure on a substrate; alternately and repeatedly stacking an insulating layer and a sacrificial layer on the sacrificial layer structure; forming a channel through the sacrificial layer structure, the insulating layer, and the sacrificial layer to contact an upper surface of the substrate; forming an opening through the insulating layer and the sacrificial layer to expose at least a portion of the sacrificial layer structure; removing the at least a portion of the sacrificial layer structure exposed through the opening to form a first gap exposing the upper surface of the substrate and an outer wall of the channel; forming a seed layer comprising amorphous silicon, carbon, nitrogen, or oxygen on the exposed upper surface of the substrate and the outer wall of the channel exposed through the first gap; forming a channel connection pattern to partially fill the first gap, the channel connection pattern surrounding the channel and exposing a portion of the seed layer on the upper surface of the substrate; removing the exposed portion of the seed layer to expose the upper surface of the substrate; removing the sacrificial layer to form a second gap; and forming a gate electrode in the second gap. Attached Figure Description

[0013] The features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0014] Figures 1 to 7 A top view and a cross-sectional view of a vertical storage device according to an example embodiment are shown;

[0015] Figures 8 to 44 Top and cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown;

[0016] Figure 45A and Figure 45B A cross-sectional view of a vertical storage device according to an example embodiment is shown;

[0017] Figures 46 to 48 Cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown;

[0018] Figure 49A and Figure 49B A cross-sectional view of a vertical storage device according to an example embodiment is shown;

[0019] Figures 50 to 52 Cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown;

[0020] Figure 53A , Figure 53B and Figure 54 A cross-sectional view of a vertical storage device according to an example embodiment is shown;

[0021] Figures 55 to 61 Cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown;

[0022] Figure 62A , Figure 62B and Figure 63 A cross-sectional view of a vertical storage device according to an example embodiment is shown;

[0023] Figure 64 A cross-sectional view of one stage of a method for manufacturing a vertical storage device according to an example embodiment is shown, along with a cross-sectional view taken along line A-A' in the corresponding top view; and

[0024] Figure 65 and Figure 66 A cross-sectional view of a vertical storage device according to an example embodiment is shown. Detailed Implementation

[0025] In the following text, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In an example embodiment, the second direction and the third direction may be substantially perpendicular to each other.

[0026] Figures 1 to 7 A top view and a cross-sectional view of a vertical storage device according to an example embodiment are shown. For example, Figure 1 and Figure 2 It is a top view. Figures 3 to 7 It is a cross-sectional view.

[0027] Figure 3 It shows along Figure 2 A cross-sectional view taken from line A-A'. Figure 4 It shows along Figure 2 A cross-sectional view taken from line C-C'. Figure 5A It shows along Figure 2 A cross-sectional view taken from line E-E'. Figure 6 It shows along Figure 2 A cross-sectional view taken by line F-F'. Figure 7 It shows along Figure 2 A cross-sectional view taken from line G-G'. Figures 2 to 5A as well as Figures 6 to 7 It is about Figure 1 The graph of region X, Figure 5B and Figure 5C They are about Figure 5A The graph of region Y and region Z.

[0028] Reference Figures 1 to 7 The vertical memory device may include: a channel 260 extending in a first direction on a substrate 100; a channel connection pattern 375 covering the outer sidewalls of the channel 260 to connect the channels 260 to each other; a gate electrode structure including gate electrodes 422, 424, and 426 spaced apart from each other in the first direction on the channel connection pattern 375 to surround the channel 260; a first common source line (CSL) 440 and a second CSL 450 extending in a second direction on the substrate 100 to separate the gate electrodes 422, 424, and 426 and each of the channel connection patterns 375 (e.g., extending between the gate electrodes 422, 424, and 426 and the channel connection pattern 375) in a third direction; and a first etch stop pattern 390 and a second barrier pattern 415 sequentially stacked in the third direction on the sidewalls of the ends of the channel connection pattern 375 (e.g., the ends of the channel connection pattern 375 relative to or in the third direction).

[0029] The vertical memory device may further include: an impurity region 105 located on the upper part of the substrate 100; a support layer 150 located between the channel connection pattern 375 and the lowermost gate electrode among the gate electrodes 422, 424, and 426; a support pattern structure including support patterns 152, 154, and 156 that are in contact with the upper surface of the substrate 100 and connected to the support layer 150; a seed pattern 365 (located between the channel connection pattern 375 and the upper surface of the substrate 100, between the seed pattern 375 and the lower surface of the support layer 150, or between the seed pattern 365 and the outer sidewall of each channel 260); and a first sacrificial layer 110, a second sacrificial layer 120, and a third sacrificial layer 120 located on the substrate 100. The sacrificial layer structure of sacrificial layer 130; the insulating pattern 175 located between adjacent or adjacent gate electrodes in a first direction in gate electrodes 422, 424 and 426; the charge storage structure 250 covering the outer walls and bottom surface (e.g., the surface facing the substrate) of each channel 260; the fill pattern 270 filling the space defined by each channel 260; the pads 280 (on each channel 260, fill pattern 270 and charge storage structure 250); the first to third separator layers 190, 290 and 460; the first conductive connection portion 455 and the second conductive connection portion 465; the second spacer 430 (located on the first CSL). 440, on the sidewalls of each of the second CSL 450 and the third separator layer 460; first to third insulating intermediate layers 200, 300 and 470 sequentially stacked on the gate electrode structure; first contact pin 480 (extending through the second insulating intermediate layer 300 and the third insulating intermediate layer 470 to contact the upper surface of the pad 280); second contact pin 490 (extending through the first to third insulating intermediate layers 200, 300 and 470 and the insulating pattern 175 to contact the upper surface of each of the gate electrodes 422, 424 and 426); and bit lines and upper wiring electrically connected to the first contact pin 480 and the second contact pin 490, respectively.

[0030] Substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, GaSb, etc. In one embodiment, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0031] The substrate 100 may include a first region I and a second region II, in which memory cells may be formed, and in which second contact pins 490 (for applying signals to the memory cells) may be formed. The second region II of the substrate 100 may at least partially surround the first region I of the substrate 100. In one embodiment, the first region I and the second region II of the substrate 100 may be referred to as the cell region and the extension region, respectively.

[0032] The channel 260 may be located on a first region I of the substrate 100 and may have, for example, a cup shape. The outer walls of the channel 260 may be covered by the charge storage structure 250. The internal space defined by the channel 260 may be filled with a fill pattern 270. The channel 260 may include, for example, undoped polysilicon, and the fill pattern 270 may include oxides, for example, silicon oxide.

[0033] In one embodiment, channels 260 may be formed in each of the second and third directions to form a channel array. A channel array may be connected by a channel connection pattern 375, the channel array including a channel 260 surrounded by a gate electrode structure located between adjacent CSLs in the third direction of the first CSL 440 and the second CSL 450.

[0034] The charge storage structure 250 may include: an upper portion covering most of the outer sidewall of the channel 260 and extending through the gate electrode structure; and a lower portion covering the bottom surface of the channel 260 on the substrate 100. For example, the upper and lower portions of the charge storage structure 250 may be spaced apart from each other in a first direction by portions of the channel connection pattern 375 that contact the lower outer sidewall of the channel 260. The lower surface of the upper portion of the charge storage structure 250 and the upper surface of the lower portion of the charge storage structure 250 may contact the channel connection pattern 375.

[0035] The charge storage structure 250 may include a tunnel insulating pattern 240, a charge storage pattern 230, and a first barrier pattern 220 sequentially stacked from the outer wall of the channel 260 along a horizontal direction (e.g., a second direction and / or a third direction). For example, the tunnel insulating pattern 240, the charge storage pattern 230, and the first barrier pattern 220 may respectively include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxides (e.g., silicon oxide).

[0036] In one embodiment, the bottom (e.g., substrate-facing) surfaces of the tunnel insulating pattern 240 and charge storage pattern 230 at the upper part of the charge storage structure 250 may be higher than the bottom surface of the first blocking pattern 220 at the upper part of the charge storage structure 250 (e.g., farther from the substrate 100 in a first direction). In one embodiment, the height (e.g., in the first direction) of the bottom surface of the first blocking pattern 220 at the upper part of the charge storage structure 250 may gradually decrease as the bottom surface of the first blocking pattern 220 moves further away from the outer wall of the channel 260 in the horizontal direction (e.g., the first blocking pattern 220 at the upper part of the charge storage structure 250 may have a sloping or inclined bottom surface), such as Figure 5C As shown.

[0037] Pad 280 may be located on channel 260, charge storage structure 250 and fill pattern 270, and may be connected to channel 260. Pad 280 may include, for example, doped polysilicon.

[0038] The channel connection pattern 375 may be located on a first region I of the substrate 100 and may extend along a second direction. In one embodiment, a plurality of channel connection patterns 375 spaced apart from each other in a third direction (e.g., by each of the first CSL 440 and the second CSL 450 and the second spacer 430 covering each of their opposite sidewalls in the third direction) may be located on the substrate 100.

[0039] In one embodiment, the sidewalls at the ends of the channel connection pattern 375 may be recessed inward (e.g., in the third direction) toward the center portion of the channel connection pattern 375.

[0040] In one embodiment, the sidewalls at the ends of the channel connection pattern 375 may have an asymmetrical shape relative to or about an imaginary line S extending through the central portion of the channel connection pattern 375 in a horizontal direction (e.g., along a third direction). (For example, the sidewall profile of the portion of the channel connection pattern 375 away from the substrate 100 may differ from the sidewall profile of the portion of the channel connection pattern 375 close to the substrate 100 relative to the line that bisects the channel connection pattern 375.) In one embodiment, a first distance D1 from a channel 260 along a third direction to the upper portion of the sidewall at the end of the channel connection pattern 375 may be less than a second distance D2 from the channel 260 along a third direction to the lower portion of the sidewall at the end of the channel connection pattern 375.

[0041] The channel connection pattern 375 may include, for example, polysilicon doped with impurities.

[0042] In one embodiment, the channel connection pattern 375 may include an air gap 380. In one embodiment, the air gap 380 may not be formed at, for example, a portion of the channel connection pattern 375 adjacent to or near the end of each of the first CSL 440 and the second CSL 450, but may be formed at a portion of the channel connection pattern 375 distant from each of the first CSL 440 and the second CSL 450 or at a distance from each of the first CSL 440 and the second CSL 450.

[0043] The gate electrode structure may include gate electrodes 422, 424, and 426 stacked at a plurality of horizontal heights and spaced apart from each other in a first direction, and an insulating pattern 175 may be located between adjacent gate electrodes in the gate electrodes 422, 424, and 426. The insulating pattern 175 may include an oxide, such as silicon oxide. In one embodiment, the gate electrode structure may include at least one first gate electrode 422, a plurality of second gate electrodes 424, and at least one third gate electrode 426 sequentially stacked in the first direction. The plurality of gate electrode structures may be spaced apart from each other in a third direction (by a first CSL 440 and a second CSL 450 and / or a third separator layer 460 extending in a second direction and a second spacer 430 covering each of their opposite sidewalls in the third direction).

[0044] In one embodiment, the gate electrode structure may form a stepped structure, the length of which in a second direction decreases from the lowest layer (e.g., closer to substrate 100) along a first direction toward the highest layer (e.g., farther from substrate 100). Each step of the stepped structure may include a gate electrode and an insulating pattern 175 directly thereon.

[0045] The first to third gate electrodes 422, 424, and 426 may each include a gate conductive pattern and a gate blocking pattern covering the surface of the gate conductive pattern. The gate conductive pattern may include a low-resistance metal, such as tungsten, titanium, tantalum, platinum, etc., and the gate blocking pattern may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0046] The first CSL 440 and the second CSL 450 (extending along the second direction) and the second spacer 430 can all separate or isolate each or multiple sets of gate electrodes 422, 424 and 426 in a third direction. The first CSL 440 can extend continuously on the first region I and the second region II of the substrate 100, and the second CSL 450 can extend discontinuously on the first region I and the second region II of the substrate 100, the second CSL 450 having a cutout portion on the second region II of the substrate 100.

[0047] In one embodiment, the cutout portion of the second CSL 450 may overlap with the first separator layer 190 in the first direction, and the two gate electrodes located on opposite sides of the cutout portion of the second CSL 450 in the third direction may not be separated from each other due to the cutout portion of the second CSL 450. A portion of the gate electrode connected to the adjacent gate electrodes in the third direction may be referred to as the first conductive connection portion 455.

[0048] The first separator layer 190 may extend through and separate the first gate electrode 422 located on the second region II of the substrate 100, and a plurality of first separator layers 190 may be formed in the third direction. The first separator layer 190 may include an oxide, such as silicon oxide.

[0049] The third separator layer 460 may extend along a second direction on a second region II of the substrate 100 between adjacent CSLs (in the third direction) of the first CSL 440 and the second CSL 450, and may, together with a second spacer 430 covering each opposite sidewall of the third separator layer 460, separate or isolate each gate electrode 422, 424, and 426. In one embodiment, the third separator layer 460 may extend along the second direction and may have a cutout portion identical to that of the second CSL 450, the portion of the two gate electrodes located at the opposite sidewall of the cutout portion of the third separator layer 460 along the third direction may be referred to as the second conductive connection portion 465.

[0050] The second separation layer 290 may extend in a second direction over a first region I and a second region II of the substrate 100 in a channel block including channels 260 connected to each other by a channel connection pattern 375, and may extend through the upper portion of some of the channels 260 in the channel block.

[0051] Reference Figure 19 The second separator layer 290 can extend not only from above or from the top through the upper part of the several channels 260, but also through the first insulating intermediate layer 200, the third gate electrode 426 and the insulating pattern 175 located at the two upper horizontal heights, and a portion of the insulating pattern 175 located at the third horizontal height. The second separator layer 290 can extend along a second direction in the first region I of the substrate 100, and can further extend along a second direction through the upper two stepped layers of the stepped structure in the second region II of the substrate 100.

[0052] The first CSL 440, the second CSL 450, and the third separator layer 460 may each include metals, such as tungsten, copper, aluminum, etc.

[0053] Each sidewall of the opposing sidewalls (along the third direction) of each of the first CSL 440, the second CSL 450, and the third separator layer 460 may be covered by the second spacer 430 and may be insulated from the adjacent gate electrodes of the gate electrodes 422, 424, and 426. The second spacer 430 may comprise an oxide, such as silicon oxide.

[0054] Impurity region 105 may be located on the upper portion of substrate 100 to contact the bottom surface of each of the first CSL 440, the second CSL 450, and the third separator layer 460. Impurity region 105 may comprise, for example, single-crystal silicon doped with n-type impurities. The contact resistance between each of the first CSL 440, the second CSL 450, and the third separator layer 460 and the substrate 100 may be reduced due to impurity region 105.

[0055] The support layer 150 may extend along a second direction on a first region I and a second region II of the substrate 100. The support layer 150 may be located on a channel connection pattern 375 on the first region I of the substrate 100, and may be located on a sacrificial layer structure on the second region II of the substrate 100. The sacrificial layer structure may include a first sacrificial layer 110, a second sacrificial layer 120, and a third sacrificial layer 130 sequentially stacked on the second region II of the substrate 100. The first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 may respectively comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxide (e.g., silicon oxide).

[0056] In one embodiment, the bottom surface of the end of the support layer 150 (e.g., in the third direction or relative to the third direction) may be higher than the bottom surface of the other portions thereof.

[0057] The support pattern structure can be connected to the support layer 150. The support pattern structure can face the channel connection pattern 375 on the first region I of the substrate 100 and can face the sacrificial layer structure on the second region II of the substrate 100 to contact the sidewalls of the sacrificial layer structure.

[0058] In one embodiment, the support pattern structure may include: a first support pattern 152 located on a first region I of the substrate 100; a second support pattern 154 extending in a third direction at the boundary between the first region I and the second region II of the substrate 100; and a third support pattern 156 extending from the second support pattern 154 on the second region II of the substrate 100.

[0059] In one embodiment, a plurality of first support patterns 152 may be spaced apart from each other in a second direction, and each of the plurality of first support patterns 152 may be connected to, for example, an end of the support layer 150 in a third direction. A plurality of third support patterns 156 may be spaced apart from each other in a third direction. For example, a sacrificial layer structure may be located on a second region II of the substrate 100 between adjacent third support patterns 156 in a third direction, and the sidewalls of the sacrificial layer structure may contact the sidewalls of the third support patterns 156.

[0060] The support layer 150 may include doped or undoped polysilicon, and the support pattern structure may include a material substantially the same as that of the support layer 150.

[0061] In one embodiment, each of the first CSL 440, the second CSL 450, and the third partition layer 460 may extend through the support layer 150 or the support pattern structure and partition the support layer 150 or the support pattern structure in a third direction.

[0062] In one embodiment, the sidewall of the end of the channel connection pattern 375 in the third direction may be recessed toward the center portion of the channel connection pattern 375 in the third direction, and correspondingly, the portion of the sidewall of the second spacer 430 facing the sidewall of that end of the channel connection pattern 375 may protrude toward the center portion of the channel connection pattern 375.

[0063] In one embodiment, at a height below the lower or bottom surface of the first gate electrode 422 (e.g., the surface facing the substrate) (e.g., at a horizontal height closer to the substrate 100 than the bottom surface of the first gate electrode 422), the maximum third-direction width (first width W1) of the second spacer 430 extending through the support layer 150 (e.g., in a top view) covering a portion of each of the opposing sidewalls of the first CSL 440 and the second CSL 450 may be greater than the maximum third-direction width (second width W2) of the second spacer 430 covering a portion of each of the first CSL 440 and the second CSL 450 extending through the first support pattern 152, the second support pattern 154, and the third support pattern 156 (e.g., in a top view). For example, the maximum third-direction width of the second spacer 430 on the first region I of the substrate 100 may be greater than the maximum third-direction width of the second spacer 430 on the second region II of the substrate 100.

[0064] The bottom surface of the second spacer 430, which covers the portion of each of the first CSL 440 and the second CSL 450 extending through each of the opposing sidewalls of the first support pattern 152, the second support pattern 154 and the third support pattern 156 (e.g., in a top view), may be deeper than the bottom surface of the second spacer 430, which covers the portion of each of the first CSL 440 and the second CSL 450 extending through each of the opposing sidewalls of the support layer 150 (e.g., in a top view).

[0065] For example, the bottom surface of the second spacer 430 on the first region I of the substrate 100 may have a varying depth, while the bottom surface of the second spacer 430 on the second region II of the substrate 100 may have a constant depth.

[0066] The first etch stop pattern 390 and the second barrier pattern 415 may be sequentially stacked in a third direction between the sidewall of the end of the channel connection pattern 375 and the second spacer 430. The first etch stop pattern 390 and the second barrier pattern 415 may also be located between the upper surface of the substrate 100 and the second spacer 430, between the bottom surface and sidewall of the support layer 150 and the second spacer 430, and between the sidewall of the support pattern structure and the second spacer 430. In one embodiment, the first etch stop pattern 390 and the second barrier pattern 415 may both be conformally formed and may be separated in a third direction by a first CSL 440, a second CSL 450, and a third separator layer 460.

[0067] Based on the shape of the sidewall at the end of the channel connection pattern 375 in the third direction and the shape of the bottom surface of the adjacent support layer 150, the first etch stop pattern 390 may include (e.g., curved) a first portion P1 and (e.g., flat) a second portion P2 and a third portion P3, the first portion P1 protruding (e.g., convexly protruding) toward the center portion of the channel connection pattern 375 in the third direction, and the second portion P2 and the third portion P3 extending upward and downward, respectively, in the first direction. The distance from a channel 260 to the second portion P2 of the first etch stop pattern 390 (in the third direction) may be less than the distance from the channel 260 to the third portion P3 of the first etch stop pattern 390 (in the third direction).

[0068] The first etch stop pattern 390 may include, for example, silicon oxide, and the second stop pattern 415 may include a metal oxide, such as aluminum oxide.

[0069] The second blocking pattern 415 may also cover the lower and upper surfaces and sidewalls of each of the gate electrodes 422, 424 and 426.

[0070] The seed pattern 365 may include silicon and impurities. Impurities may include, for example, carbon, nitrogen, and oxygen.

[0071] The first to third insulating intermediate layers 200, 300 and 470 may include oxides, such as silicon oxide, and may be merged with each other.

[0072] The first contact 480 may be located on the pad 280, and the current applied by the bit line may flow through the first contact 480 and the pad 280 into the channel 260. The second contact 490 may be located on the second region II of the substrate 100, so that a signal can be applied to each gate electrode 422, 424 and 426.

[0073] In vertical memory devices, an air gap 380 may be present in the channel connection pattern 375 used to connect the channel 260. In one embodiment, the air gap 380 may not be formed at the portion of the channel connection pattern 375 adjacent to the second spacer 430, and may be spaced apart from that portion. For example, metal may not penetrate into the air gap 380, thereby preventing degradation of the characteristics of other components. In one embodiment, a seed pattern 365 may be located between the channel connection pattern 375 and the substrate 100, the support layer 150, or the channel 260, and the air gap 380 will not expand due to differences in crystallinity between them when the channel connection pattern 375 is formed. In one embodiment, the seed pattern 365 may be located on the upper surface of the substrate 100 and the sidewalls of the channel connection pattern 375, and will not damage the substrate 100 and the channel connection pattern 375 when etching processes for forming gate electrodes 422, 424, and 426 are performed. Reference will be made below. Figures 8 to 44 Describe these characteristics in detail.

[0074] Figures 8 to 44 Top and cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown. Figure 8 , Figure 10 , Figure 14 , Figure 18 , Figure 20 , Figure 30 , Figure 32 and Figure 40 It is a top view. Figure 9 , Figures 11 to 13 , Figures 15 to 17 , Figure 19 , Figures 21 to 29 , Figure 31 , Figure 33 and Figures 41 to 44 These are cross-sectional views. All these views are about... Figure 1 The region X.

[0075] Figure 9 , Figure 12 , Figures 15 to 16 , Figure 21 , Figure 23 , Figure 26 , Figure 28 , Figure 33 , Figure 35 , Figure 38 and Figure 41 The cross-sectional views taken along line A-A' in the corresponding top view are shown respectively. Figure 11 A cross-sectional view taken along line B-B' in the corresponding top view is shown. Figure 13 and Figure 17 The cross-sectional views taken along line C-C' in the corresponding top view are shown respectively. Figure 19A cross-sectional view taken along line D-D' in the corresponding top view is shown. Figure 22 , Figures 24 to 25 , Figure 27 , Figure 29 , Figure 31 , Figure 34 , Figures 36 to 37 , Figure 39 and Figure 42 A cross-sectional view taken along line E-E' in the corresponding top view is shown. Figure 43 It is a cross-sectional view taken along line F-F' in the corresponding top view. Figure 44 It is a cross-sectional view taken along line G-G' in the corresponding top view.

[0076] Reference Figure 8 and Figure 9 The first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 can be stacked sequentially on the substrate 100. The first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 can be partially removed to form a first opening 142, a second opening 144, and a third opening 146 that can expose the upper surface of the substrate 100. A support layer 150 can be formed on the substrate 100 and the third sacrificial layer 130 to at least partially fill each of the first opening 142, the second opening 144, and the third opening 146.

[0077] For example, n-type impurities can be implanted into substrate 100.

[0078] The first sacrificial layer 110 and the third sacrificial layer 130 may comprise oxides (e.g., silicon oxide), the second sacrificial layer 120 may comprise nitrides (e.g., silicon nitride), and the support layer 150 may comprise a material having etch selectivity relative to the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130, such as polycrystalline silicon doped with n-type impurities or undoped polycrystalline silicon. In one embodiment, the support layer 150 may be formed by depositing amorphous silicon and crystallizing it through a thermal treatment process or by a deposition process of other layers, such that the support layer 150 may comprise polycrystalline silicon.

[0079] In one embodiment, a plurality of first openings 142 may be formed on a first region I of the substrate 100 along a second direction (e.g., spaced apart) and also along a third direction (e.g., spaced apart). Second openings 144 may extend along a third direction at or on the boundary between the first region I and the second region II of the substrate 100, and a third opening 146 may be connected to the second openings 144 on the second region II of the substrate 100 to extend along the second direction. A plurality of second openings 144 may be formed along a third direction (e.g., spaced apart). In one embodiment, the first openings 142 in the second direction may be aligned with the third openings 146 extending along the second direction.

[0080] The support layer 150 may have a constant thickness, and a first recess may be formed in the portion of the support layer 150 located in each of the first opening 142, the second opening 144, and the third opening 146. The portions of the support layer 150 located in the first opening 142, the second opening 144, and the third opening 146 may be referred to as the first support pattern 152, the second support pattern 154, and the third support pattern 156, respectively.

[0081] An insulating layer 170 may be formed on the support layer 150 to fill the first recess, and the upper portion of the insulating layer 170 may be planarized. The insulating layer 170 may include an oxide (e.g., silicon oxide), and the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0082] Reference Figure 10 and Figure 11 A fourth sacrificial layer 180 may be formed on the insulating layer 170, and a first separating layer 190 may be formed on the second region II of the substrate 100, passing through a portion of the fourth sacrificial layer 180.

[0083] The first separating layer 190 can be formed by partially removing the fourth sacrificial layer 180 to form a fourth opening and filling the fourth opening with an insulating material. In one embodiment, a plurality of first separating layers 190 can be formed to be spaced apart from each other in a third-order direction and can be formed in connection with the subsequently formed first conductive connection portion 455 (see reference). Figure 40 (At the overlapping locations in the first direction). In one embodiment, the first separating layer 190 may overlap with the third support pattern 156 in the first direction.

[0084] The fourth sacrificial layer 180 may include a material that is etch-selective relative to the insulating layer 170, such as a nitride, like silicon nitride, and the first separating layer 190 may have a material that is etch-selective relative to the fourth sacrificial layer 180, such as an oxide, like silicon oxide.

[0085] Reference Figure 12 and Figure 13 The insulating layer 170 and the fourth sacrificial layer 180 can be alternately and repeatedly formed on the fourth sacrificial layer 180 along the first direction to form a mold on the substrate 100.

[0086] A photoresist pattern can be formed on the uppermost insulating layer 170 to partially cover it, and the photoresist pattern can be used as an etching mask to etch the uppermost insulating layer 170 and the uppermost fourth sacrificial layer 180 located below it. Therefore, the insulating layer 170 located below the uppermost fourth sacrificial layer 180 can be partially exposed. After a trimming process to reduce the area of ​​the photoresist pattern, the reduced photoresist pattern can be used as an etching mask to etch the uppermost insulating layer 170, the uppermost fourth sacrificial layer 180, the partially exposed insulating layer 170, and the fourth sacrificial layer 180 located below it. The trimming and etching processes can be repeated to form a stepped structure comprising multiple stepped layers on the second region II of the substrate 100, each stepped layer comprising a fourth sacrificial layer 180 and an insulating layer 170 directly thereon, and a mold comprising the stepped structure can be formed on the first region I and the second region II of the substrate 100.

[0087] Reference Figure 14 and Figure 15 A first insulating intermediate layer 200 can be formed on the uppermost insulating layer 170, and a channel hole 210 passing through the first insulating intermediate layer 200 and the mold can be formed by a dry etching process to expose the upper surface of the substrate 100.

[0088] The first insulating intermediate layer 200 may include oxides, such as silicon oxide.

[0089] In one embodiment, a dry etching process can be performed until the upper surface of the substrate 100 is exposed, and the upper portion of the substrate 100 can be further removed during the dry etching process. In one embodiment, a plurality of channel holes 210 can be formed in each of the second and third directions, and an array of channel holes can be defined.

[0090] Reference Figure 16 and Figure 17 Charge storage structure 250, channel 260, fill pattern 270 and pad 280 can be formed in the channel hole 210.

[0091] For example, a charge storage structure layer and a channel layer may be sequentially formed on the sidewall of the channel hole 210, the exposed upper surface of the substrate 100, and the upper surface of the first insulating intermediate layer 200. A fill layer may be formed on the channel layer to fill the remaining portion of the channel hole 210. The channel layer and the charge storage structure layer may be planarized until the upper surface of the first insulating intermediate layer 200 is exposed.

[0092] Through a planarization process, charge storage structure 250 and channel 260 (both of which can be cup-shaped and stacked sequentially on the sidewall of channel hole 210 and the upper surface of substrate 100) can be formed, and filling pattern 270 can fill the internal space formed by channel 260.

[0093] Since the channel hole 210 with the channel 260 formed therein can define the channel hole array, the channel 260 in the channel hole 210 can also define the channel array.

[0094] In one embodiment, the charge storage structure 250 may include a first barrier pattern 220, a charge storage pattern 230, and a tunnel insulating pattern 240 stacked in sequence. For example, the first barrier pattern 220, the charge storage pattern 230, and the tunnel insulating pattern 240 may respectively include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxides (e.g., silicon oxide).

[0095] The channel 260 may include, for example, undoped polysilicon, and the filling pattern 270 may include an oxide such as silicon oxide.

[0096] The upper portion of the fill pattern 270, the channel 260, and the charge storage structure 250 can be removed to form the second recess. A pad layer can be formed on the first insulating intermediate layer 200 to fill the recess, and the pad can be planarized until the upper surface of the first insulating intermediate layer 200 can be exposed to form a pad 280. The pad 280 may include, for example, doped polysilicon.

[0097] Reference Figure 18 and Figure 19 A second separating layer 290 can be formed through the selected fourth sacrificial layer 180 and the selected insulating layer 170.

[0098] The second separating layer 290 can be formed by the following operations: forming an etching mask on the first insulating intermediate layer 200; etching the first insulating intermediate layer 200, a selected insulating layer 170 and a selected fourth sacrificial layer 180 to form a fifth opening; and filling the fifth opening with an insulating material.

[0099] In one embodiment, the second separator layer 290 may extend through the upper portion of the selected channel 260. In one embodiment, the second separator layer 290 may extend through the first insulating intermediate layer 200, the fourth sacrificial layer 180 located at the two upper horizontal levels, and the insulating layer 170 located at the two upper horizontal levels and another insulating layer 170 below it. The second separator layer 290 may extend along a second direction on the first region I and the second region II of the substrate 100, and may extend through the two upper stepped layers of the stepped structure. For example, the selected fourth sacrificial layer 180 located at the two upper horizontal levels may be separated by the second separator layer 290 in a third direction.

[0100] Reference Figures 20 to 22 A second insulating intermediate layer 300 can be formed on the first insulating intermediate layer 200 and the pad 280, and a sixth opening 310, a seventh opening 320 and an eighth opening 330 can be formed through the first insulating intermediate layer 200, the second insulating intermediate layer 300 and the mold by a dry etching process.

[0101] In one embodiment, a dry etching process can be performed until the upper surface of the support layer 150 or the upper surfaces of the first support pattern 152, the second support pattern 154, and the third support pattern 156 are exposed. The upper portion of the support layer 150 or the upper portion of the first support pattern 152, the second support pattern 154, and the third support pattern 156 can also be removed during the dry etching process. When the sixth opening 310, the seventh opening 320, and the eighth opening 330 are formed, the insulating layer 170 and the fourth sacrificial layer 180 of the mold can be exposed.

[0102] In one embodiment, the sixth opening 310, the seventh opening 320, and the eighth opening 330 can all extend along a second direction, and a plurality of sixth openings 310, a plurality of seventh openings 320, and a plurality of eighth openings 330 can be formed in a third direction. The sixth opening 310, the seventh opening 320, and the eighth opening 330 can all expose the upper surface of the third support pattern 156 on the second region II of the substrate 100, the sixth opening 310 and the seventh opening 320 can both expose the upper surface of the first support pattern 152 on the first region I of the substrate 100, and the eighth opening 330 can be aligned with the second separator layer 290 in the second direction.

[0103] When the sixth opening 310, the seventh opening 320 and the eighth opening 330 are formed, the insulating layer 170 can be transformed into an insulating pattern 175 extending along the second direction, and the fourth sacrificial layer 180 can be transformed into a fourth sacrificial pattern 185 extending along the second direction.

[0104] In one embodiment, the sixth opening 310 may extend continuously along a second direction on the first region I and the second region II of the substrate 100, and the seventh opening 320 may be discontinuous at a portion of the second region II of the substrate 100. For example, the fourth sacrificial patterns 185 extending along the second direction on opposite sides of the seventh opening 320 in a third direction may be connected to each other at the discontinuous portions of the seventh opening 320. In one embodiment, the discontinuous portions of the seventh opening 320 or the connecting portions of the fourth sacrificial patterns 185 may overlap with the fourth sacrificial pattern 185 and the first separating layer 190 located at a third horizontal level in a third direction.

[0105] In one embodiment, the eighth opening 330 may extend discontinuously and may be discontinuous at a portion of the second region II of the substrate, and a plurality of eighth openings 330 may be formed to be spaced apart from each other along a second direction on the second region II of the substrate 100.

[0106] Reference Figure 23 and Figure 24 A first spacer layer can be formed on the sidewalls of the sixth opening 310, the seventh opening 320 and the eighth opening 330 and on the upper surface of the second insulating intermediate layer 300. The portion of the first spacer layer located at the bottom of the sixth opening 310, the seventh opening 320 and the eighth opening 330 can be removed by an anisotropic etching process to form the first spacer 337. The upper surface of the support layer 150 and the upper surfaces of the first support pattern 152, the second support pattern 154 and the third support pattern 156 can be partially exposed.

[0107] The exposed portions of the support layer 150 and the exposed portions of the first support pattern 152, the second support pattern 154, and the third support pattern 156, as well as a portion of the second sacrificial layer 120 and the third sacrificial layer 130 below them, can be removed, thereby allowing the sixth opening 310, the seventh opening 320, and the eighth opening 330 to expand downwards to form the ninth opening 315, the tenth opening 325, and the eleventh opening 335, respectively (see reference). Figure 30 Both the ninth opening 315 and the tenth opening 325 can expose the upper surface of the first sacrificial layer 110 on the first region I of the substrate 100. The ninth opening 315, the tenth opening 325, and the eleventh opening 335 can all expose the upper surface of the substrate 100 at the edges of the first region I and the second region II of the substrate 100. Both the ninth opening 315 and the tenth opening 325 can expose the upper surface of the first sacrificial layer 110 and can further extend through the upper surface of the first sacrificial layer 110. The ninth opening 315, the tenth opening 325, and the eleventh opening 335 can all expose the upper surface of the substrate 100 and further extend through the upper portion of the substrate 100.

[0108] In one embodiment, the first spacer 337 may comprise, for example, undoped amorphous silicon or undoped polycrystalline silicon. When the first spacer 337 comprises undoped amorphous silicon, the undoped amorphous silicon may crystallize during other deposition processes.

[0109] In one embodiment, when the ninth opening 315, the tenth opening 325, and the eleventh opening 335 are formed, the first spacer 337 may have already been formed, and the width of its downwardly expanding portion (e.g., the lower part of the ninth opening 315, the tenth opening 325, and the eleventh opening 335) may be smaller than the width of the sixth opening 310, the seventh opening 320, and the eighth opening 330, respectively, for example, smaller than the width of the upper part of the ninth opening 315, the tenth opening 325, and the eleventh opening 335, respectively.

[0110] When the second sacrificial layer 120 and the third sacrificial layer 130 are partially removed, the sidewalls of the sixth opening 310, the seventh opening 320 and the eighth opening 330 can be covered by the first spacer 337, and the insulating pattern 175 and the fourth sacrificial pattern 185 included in the mold can remain unremoved.

[0111] In the following text, not all of the openings in the ninth opening 315, the tenth opening 325 and the eleventh opening 335 will be shown, but only the ninth opening 315 will be shown. However, except in special cases, the description of the ninth opening 315 may be applied to the tenth opening 325 and / or the eleventh opening 335.

[0112] Reference Figure 25 The first sacrificial layer 110 and the third sacrificial layer 130 exposed by the ninth opening 315 can be partially removed to form the first gap 332.

[0113] In one embodiment, the first gap 332 can be formed by removing only the portions of the first sacrificial layer 110 and the third sacrificial layer 130 adjacent to the ninth opening 315, and the first gap 332 can be formed by using a wet etching process, for example, hydrofluoric acid, or by using a dry etching process, for example, hydrogen fluoride.

[0114] When the first gap 332 is formed, the lower part of the support layer 150 adjacent to the ninth opening 315 and the upper part of the substrate 100 adjacent to the ninth opening 315 can be exposed.

[0115] In one embodiment, the third sacrificial layer 130 can be partially removed through the ninth opening 315, and the first sacrificial layer 110 can be removed in small quantities. Furthermore, the widths of the lower and upper first gaps 332 formed by removing the first and third sacrificial layers 110 and 130, respectively, in the third direction can be different from each other. The width of the upper first gap 332 in the third direction can be greater than the width of the lower first gap 332 in the third direction. For example, the distance along the third direction from the upper first gap 332 to the channel 260 or charge storage structure 250 can be less than the distance along the third direction from the lower first gap 332 to the channel 260 or charge storage structure 250.

[0116] Reference Figure 26 and Figure 27 The silicon-containing layer can be oxidized, for example, by a wet oxidation process. For example, the upper portion of the substrate 100 exposed through the ninth opening 315 and the first gap 332, the upper portions of the first support pattern 152, the second support pattern 154 and the third support pattern 156 exposed through the ninth opening 315 and the first gap 332, the lower portion of the support layer 150 exposed through the ninth opening 315 and the first gap 332, and the surface of the first spacer 337 can be oxidized to transform it into the fifth sacrificial pattern 340.

[0117] Reference Figure 28 and Figure 29 The fifth sacrificial pattern 340, the first sacrificial layer 110, and the third sacrificial layer 130 can be removed, and the second sacrificial layer 120 can be removed, thereby forming the second gap 350.

[0118] In one embodiment, the fifth sacrificial pattern 340, as well as the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130, can be removed by using a wet etching process, for example, hydrofluoric acid (HF), and the second sacrificial layer 120 can be removed by using a wet etching process, for example, phosphoric acid (H3PO4).

[0119] When the fifth sacrificial pattern 340 and the first sacrificial layer 110, the second sacrificial layer 120 and the third sacrificial layer 130 are removed to form the second gap 350, the portion of the charge storage structure 250 exposed through the second gap 350 can also be removed to expose the outer wall of the channel 260, and the charge storage structure 250 can be divided into an upper part (extending through the mold to cover most of the outer wall of the channel 260) and a lower part (covering the bottom surface of the channel 260 on the substrate 100).

[0120] In one embodiment, the portion of the second gap 350 adjacent to the outer wall of the channel 260 may have an upper surface higher than the lower surface of the support layer 150 and a lower surface lower than the upper surface of the substrate 100.

[0121] In one embodiment, the bottom surface of the upper portion of the charge storage structure 250 (e.g., the surface facing the substrate) and the top surface of the lower portion of the charge storage structure 250 (e.g., the surface facing away from the substrate 100) may not have a constant height. For example, the bottom surfaces of the tunnel insulating pattern 240 and the charge storage pattern 230 in the upper portion of the charge storage structure 250 may be higher than the bottom surface of the included first blocking pattern 220. In one embodiment, the bottom surfaces of the tunnel insulating pattern 240 and the charge storage pattern 230 in the upper portion of the charge storage structure 250 may be substantially flat, while the bottom surface of the first blocking pattern 220 may gradually decrease in height as the distance from the outer sidewall of the channel 260 in the horizontal direction increases (e.g., it may be slanted or inclined).

[0122] In one embodiment, the top surface of the lower portion of the charge storage structure 250 may not have a constant height. For example, the top surfaces of the tunnel insulating pattern 240 and the charge storage pattern 230 in the lower portion of the charge storage structure 250 may be lower than the top surface of the first blocking pattern 220. In one embodiment, the top surfaces of the tunnel insulating pattern 240 and the charge storage pattern 230 in the lower portion of the charge storage structure 250 may be substantially flat, while the top surface of the first blocking pattern 220 may gradually increase in height as the distance from the outer wall of the channel 260 in the horizontal direction increases. In one embodiment, the top surface of the first blocking pattern 220 in the lower portion of the charge storage structure 250 may be substantially flat.

[0123] As described above, the fifth sacrificial pattern 340 formed by oxidizing the lower portion of the support layer 150 and the upper portion of the substrate 100 exposed by the first gap 332 can be removed, and the width of the portion of the second gap 350 adjacent to the ninth opening 315 in the first direction can be greater than the width of its other portions in the first direction.

[0124] When the second gap 350 is formed, the support layer 150 and the first support pattern 152, the second support pattern 154 and the third support pattern 156 will not be removed, so the mold will not fall off.

[0125] The first spacer 337 can be removed, and a seed layer 360 can be formed on the silicon-containing layer (e.g., on the upper surface of the substrate 100, the upper surfaces of the first support pattern 152, the second support pattern 154 and the third support pattern 156, the lower surface and sidewalls of the support layer 150 and the outer sidewalls of the channel 260).

[0126] In one embodiment, the seed layer 360 may include amorphous silicon and may also include impurities such as carbon, nitrogen and / or oxygen.

[0127] Reference Figure 30 and Figure 31 This can form a channel connection layer 370 to fill the second gap 350.

[0128] The channel connection layer 370 can be formed in the second gap 350 on the seed layer 360, and can also be formed on the sidewalls and bottom of the ninth opening 315 and on the upper surface of the second insulating intermediate layer 300.

[0129] The channel interconnect layer 370 may include, for example, amorphous silicon doped with n-type impurities. The channel interconnect layer 370 may later be crystallized during other deposition processes to include polycrystalline silicon.

[0130] An air gap 380 can be formed in the channel connecting layer 370 within the second gap 350. In one embodiment, the air gap 380 can be formed in a region away from the ninth opening 315 along a third direction. For example, the air gap 380 may not be formed in the region corresponding to the first gap 332 and in the space between the first gap 332 in the channel connecting layer 370. The width of the portion of the second gap 350 adjacent to the ninth opening 315 in the first direction can be greater than the width of other portions of the second gap 350 in the first direction, and the channel connecting layer 370 can more easily fill the portion of the second gap 350 adjacent to the ninth opening 315 compared to other portions of the second gap 350, thereby allowing the air gap 380 to be formed in other portions.

[0131] When the channel connection layer 370 is formed, the seed layer 360 has already been formed on the silicon-containing layer (e.g., it has been formed on the upper surface of the substrate 100, the upper surface of the first support pattern 152, the second support pattern 154 and the third support pattern 156, the lower surface and sidewalls of the support layer 150 and the outer sidewalls of the channel 260), and even if the channel connection layer 370 crystallizes, due to the difference in crystallinity between the silicon-containing layers, an air gap 380 will not be formed in the region adjacent to the ninth opening 315.

[0132] When the channel connection layer 370 is formed to fill the second gap 350, the channels 260 forming the channel array can be connected to each other.

[0133] Figure 32 The thickness of the channel connection layer 370 in the ninth opening 315 and the eleventh opening 335 is shown. For example, the channel connection layer 370 in the ninth opening 315 may extend in a second direction and may have a first thickness T1 in a third direction (e.g., from the sidewall of the ninth opening 315 inward).

[0134] At a first height H1 along a first direction from the upper surface of the substrate 100, the portion of the channel connection layer 370 located on the sidewall of the eleventh opening 335 may have a first thickness T1 measured in a second and / or second direction (e.g., inward from the sidewall of the eleventh opening 335). In one embodiment, at a second height H2 (lower than the first height H1 along the first direction from the upper surface of the substrate 100, e.g., closer to the substrate 100), the portion of the channel connection layer 370 extending inward from the sidewall of the eleventh opening 335 along the second direction may have a first thickness T1 in the second direction, and the portion of the channel connection layer 370 extending inward from the sidewall of the eleventh opening 335 along the third direction may have a second thickness T2 in the second direction, the second thickness T2 being greater than the first thickness T1.

[0135] When performing the etching process for forming the eleventh opening 335, each opposite end of the eleventh opening 335 in the second direction at the first height H1 may be semi-circular, and each opposite end of the eleventh opening 335 in the second direction at the second height H2, which is lower than the first height H1, may be elliptical. For example, at the second height H2, the thickness of the channel connection layer 370 at each opposite end of the eleventh opening 335 in the second direction may be greater than the thickness of the channel connection layer 370 at each opposite end of the eleventh opening 335 in the third direction.

[0136] Reference Figure 33 and Figure 34 The channel connection layer 370 can be partially removed to form a channel connection pattern 375 in the second gap 350.

[0137] In one embodiment, the channel connection pattern 375 can be formed by a back etching process, so that the portion of the channel connection layer 370 located in the ninth opening 315 can be removed.

[0138] The channel connection layer 370 can be formed not only in the ninth opening 315, but also in the tenth opening 325 and the eleventh opening 335. To remove the portion of the channel connection layer 370 located in the eleventh opening 335, the portion with a second thickness T2 at the second height H2 can be removed. For example, an etch-back process can be performed, thereby allowing for over-etching of the channel connection layer 370. In one embodiment, an air gap 380 may not be formed in the region of the second gap 350 adjacent to the ninth opening 315, and the air gap 380 will not be exposed even if the channel connection layer 370 in the ninth opening 315 is excessively removed.

[0139] In one embodiment, a seed layer 360 may be formed on the upper surface of the substrate 100, and the seed layer 360 may include impurities (e.g., carbon, nitrogen, oxygen, etc.) and may be used as an etch stop layer to protect the substrate 100 during the removal of the channel interconnect layer 370.

[0140] After the channel connection pattern 375 is formed, a portion of the seed layer 360 can be removed, and the seed pattern 365 can be retained between the channel connection pattern 375 and the upper surface of the substrate 100 or the lower surface of the support layer 150.

[0141] For example, an n-type impurity can be implanted into the upper portion of the substrate 100 exposed through the ninth opening 315 to form an impurity region 105. The impurity region 105 can reduce the contact resistance between the substrate 100 and the first CSL 440 and CSL 450, as well as the third separation layer 460 that will be formed subsequently.

[0142] Reference Figure 35 and Figure 36 An oxidation process can be performed on the silicon-containing layer to form a first etch stop pattern 390 on the upper surface of the substrate 100, the sidewalls of the channel connection pattern 375, the sidewalls of the first support pattern 152, the second support pattern 154 and the third support pattern 156, and the sidewalls and lower surface of the support layer 150.

[0143] The first etch stop pattern 390 may include, for example, silicon oxide.

[0144] Reference Figure 37 The fourth sacrificial pattern 185 exposed through the ninth opening 315 can be removed to form a third gap 400 between adjacent insulating patterns 175 along the first direction, and the outer wall of the first blocking pattern 220 can be partially exposed through the third gap 400.

[0145] In one embodiment, the fourth sacrificial pattern 185 can be removed by a wet etching process using phosphoric acid (H3PO4) or sulfuric acid (H2SO4). The first etch stop pattern 390, which has been formed on the upper surface of the substrate 100, the sidewalls of the channel connection pattern 375, the sidewalls of the first support pattern 152, the second support pattern 154 and the third support pattern 156, and the sidewalls and lower surface of the support layer 150, will not be damaged during the wet etching process.

[0146] Reference Figure 38 and Figure 39 A second barrier layer 410 may be formed on the exposed outer wall of the first barrier pattern 220, the inner wall of the third gap 400, the surface of the insulating pattern 175, the first etch stop pattern 390, and the upper surface of the second insulating intermediate layer 300, and a gate electrode layer may be formed on the second barrier layer 410.

[0147] The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked in sequence. The gate electrode layer may include a low-resistance metal (e.g., tungsten, titanium, tantalum, platinum, etc.), and the gate barrier layer may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The second barrier layer 410 may include a metal oxide (e.g., aluminum oxide).

[0148] The gate electrode layer can be partially removed to form a gate electrode in each third gap 400. In one embodiment, the gate electrode layer can be partially removed by a wet etching process.

[0149] The gate electrodes can extend along a second direction and can be formed in a third direction (e.g., spaced apart). In one embodiment, multiple gate electrodes can be formed in the third direction. For example, multiple gate electrodes, all extending along the second direction, can be spaced apart from each other through a ninth opening 315. In one embodiment, multiple gate electrodes, all extending along the second direction, can be spaced apart from each other through a tenth opening 325. In one embodiment, these gate electrodes can be electrically connected to each other through a first conductive connection portion 455, which can be formed on a second region II of the substrate 100 to overlap with the first separation layer 190.

[0150] Each gate electrode extending along the second direction on the second region II of the substrate 100 at each horizontal height other than the two horizontal heights mentioned above can be further separated in the third direction by an eleventh opening 335. In one embodiment, the gate electrodes located on opposite sides of the eleventh opening 335 can be electrically connected to each other by a second conductive connection portion 465.

[0151] Gate electrodes located at multiple horizontal heights can form a gate electrode structure. The gate electrode structure may include a first gate electrode 422, a second gate electrode 424, and a third gate electrode 426. In one embodiment, the gate electrode structure may include at least one first gate electrode 422, multiple second gate electrodes 424, and at least one third gate electrode 426. In one embodiment, the first to third gate electrodes 422, 424, and 426 may all be formed at one or more horizontal heights.

[0152] The gate electrode can be formed by replacing the fourth sacrificial pattern 185, which forms a stepped structure on the second region II of the substrate 100. Hereinafter, the stepped structure of the fourth sacrificial pattern 185 may be referred to as the stepped structure of the gate electrode.

[0153] Reference Figures 40 to 44A second spacer layer can be formed on the second barrier layer 410, and the second spacer layer can be anisotropically etched to form a second spacer 430 on the sidewall of the ninth opening 315, and the upper surface of the second barrier layer 410 located on the first etch stop pattern 390 can be partially exposed.

[0154] The portion of the second barrier layer 410 not covered by the second spacer 430 can be etched to form the second barrier pattern 415, and the portion of the second barrier layer 410 located on the upper surface of the second insulating intermediate layer 300 can be removed. In one embodiment, the upper portion of the first etch stop pattern 390 and the upper portion of the impurity region 105 can be partially removed.

[0155] A conductive layer may be formed on the upper surface of the impurity region 105, the second spacer 430, and the second insulating intermediate layer 300 to fill the remainder of the ninth opening 315, and the conductive layer may be planarized until the upper surface of the second insulating intermediate layer 300 is exposed to form a first CSL 440. While the first CSL 440 is being formed, a second CSL 450 may be formed in the tenth opening 325, and a third spacer layer 460 may be formed in the eleventh opening 335. The first CSL 440, the second CSL 450, and the third spacer layer 460 may comprise a metal (e.g., tungsten).

[0156] Refer again Figures 1 to 7 After the third insulating intermediate layer 470 is formed on the second insulating intermediate layer 300, the first CSL 440, the second CSL 450, the third separator layer 460, the second spacer 430, and the second barrier pattern 415, a first contact plug 480 can be formed through the second insulating intermediate layer 300 and the third insulating intermediate layer 470 to contact the upper surface of the pad 280 located in the first region I of the substrate 100, and a second contact plug 490 can be formed through the first insulating intermediate layer 200, the second insulating intermediate layer 300, the third insulating intermediate layer 470, the insulating pattern 175, and the second barrier pattern 415 to contact the upper surface of each gate electrode.

[0157] Bit lines can be formed to contact the upper surface of the first contact pin 480, and upper wiring can be formed to contact the upper surface of the second contact pin 490, thereby enabling the fabrication of a vertical storage device.

[0158] As described above, the first sacrificial layer 110 and the third sacrificial layer 130 exposed through the ninth opening 315 can be partially removed to form the first gap 332. The surfaces of the support layer 150 and the substrate 100 exposed through the first gap 332 can be oxidized and removed to enlarge the entrance of the first gap 332. The first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 can be removed to form the second gap 350, and the channel connection layer 370 can fill the second gap 350. For example, an air gap 380 can be formed in the channel connection layer 370 in a region away from the ninth opening 315.

[0159] In one embodiment, prior to forming the channel interconnect layer 370, a seed layer 360 (including amorphous silicon) may be formed on a silicon-containing layer (e.g., the upper surface of the substrate 100, the lower surface and sidewalls of the support layer 150, and the outer sidewalls of the channel 260). During the formation of the channel interconnect layer 370, due to the crystallinity differences between the silicon-containing layers, the air gap 380 will not be enlarged or formed in the region of the channel interconnect layer 370 adjacent to the opening 315 or the channel 260. The seed layer 360 may comprise doped polycrystalline silicon, and when the channel interconnect layer 370 is etched to form the channel interconnect pattern 375, the substrate 100 or the support layer 150 will not be damaged.

[0160] In one embodiment, the first etch stop pattern 390 can be formed by oxidizing the upper surface of the substrate 100, the sidewalls of the channel connection pattern 375, and the lower surface and sidewalls of the support layer 150, and the substrate 100, the channel connection pattern 375, and the support layer 150 will not be damaged when the third gap 400 is formed.

[0161] Figure 45A and Figure 45B A cross-sectional view of a vertical storage device according to an example embodiment is shown. Figure 45B It shows Figure 45A An enlarged cross-sectional view of region Y. Apart from the shape of the channel connection pattern and / or the second spacer, this vertical storage device can be coupled with... Figures 1 to 7 The vertical storage devices are essentially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated descriptions can be omitted here.

[0162] Reference Figure 45A and Figure 45BThe sidewalls at the ends of the channel connection pattern 375 may be symmetrical with respect to or about an imaginary line S (e.g., in a first direction) that passes through or bisects the center portion of the channel connection pattern 375. For example, the distance from a channel 260 along a third direction to the upper part of the sidewall at the end of the channel connection pattern 375 may be substantially the same as the distance from the channel 260 along a third direction to the lower part of the sidewall at the end of the channel connection pattern 375, which may be a first distance D1.

[0163] In one embodiment, the distance from a channel 260 to a second portion P2 of the first etch stop pattern 390 can be substantially the same as the distance from the channel 260 to a third portion P3 of the first etch stop pattern 390.

[0164] Figures 46 to 48 Cross-sectional views are shown of various stages in a method for manufacturing a vertical storage device according to an example embodiment. This method may include reference to... Figures 8 to 44 and Figures 1 to 7 For processes that are essentially the same or similar, repeated descriptions can be omitted in this article.

[0165] Reference Figure 46 It can be executed and referenced. Figures 8 to 24 The processes shown are basically the same or similar.

[0166] According to this embodiment, the ninth opening 315 may further extend through the first sacrificial layer 110, thereby exposing the upper surface of the substrate 100.

[0167] Reference Figure 47 It can be executed and referenced. Figure 25 The processes shown are basically the same or similar.

[0168] For example, portions of the first sacrificial layer 110 and the third sacrificial layer 130 adjacent to the ninth opening 315 can be removed to form a first gap 332, and the upper first gap 332 and the lower first gap 332 can have the same width in the third direction.

[0169] Reference Figure 48 It can be executed and referenced. Figures 26 to 34 The processes shown are basically the same or similar.

[0170] For example, the sidewalls at the ends of the channel connection pattern 375 may be symmetrical with respect to an imaginary line passing through the central portion of the channel connection pattern 375.

[0171] Refer again Figure 45A and Figure 45B It can be executed and referenced. Figures 35 to 44 as well as Figures 1 to 7The processes shown are essentially the same or similar to those used to manufacture vertical storage devices.

[0172] Figure 49A and Figure 49B A cross-sectional view of a vertical storage device according to an example embodiment is shown. Figure 49B It shows Figure 49A An enlarged cross-sectional view of region Y. Apart from the shape of the channel connection pattern and / or the second spacer, this vertical storage device can be coupled with... Figures 1 to 7 The vertical storage devices are essentially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated descriptions can be omitted.

[0173] Reference Figure 49A and Figure 49B The sidewalls at the ends of the channel connection pattern 375 may be symmetrical with respect to or about an imaginary line (e.g., in a first direction) that passes through the central portion of the channel connection pattern (e.g., bisects the channel connection pattern). For example, the distance from a channel 260 along a third direction to the upper part of the sidewall at the end of the channel connection pattern 375 may be substantially the same as the distance from the channel 260 along a third direction to the lower part of the sidewall at the end of the channel connection pattern 375, which may be a first distance D1.

[0174] In one implementation, with Figures 1 to 7 Unlike vertical storage devices, the first etch stop pattern 390 may include a first portion P1 and a second portion P2, but may not include a third portion P3.

[0175] Figures 50 to 52 Cross-sectional views are shown of various stages in a method for manufacturing a vertical storage device according to an example embodiment. This method may include reference to... Figures 8 to 44 and Figures 1 to 7 The processes shown are essentially the same or similar, so their repeated descriptions can be omitted.

[0176] Reference Figure 50 It can be executed and referenced. Figures 8 to 24 The processes shown are basically the same or similar.

[0177] In one embodiment, the ninth opening 315 may not expose the first sacrificial layer 110, but may expose the upper surface of the second sacrificial layer 120.

[0178] Reference Figure 51 It can be executed and referenced. Figure 25 The processes shown are basically the same or similar.

[0179] In one implementation, only the portion of the first sacrificial layer 110 adjacent to the ninth opening 315 may be removed to form the first gap 332.

[0180] Reference Figure 52 It can be executed and referenced. Figures 26 to 34 The processes shown are basically the same or similar.

[0181] In one embodiment, the sidewalls at the ends of the channel connection pattern 375 may be symmetrical with respect to an imaginary line passing through the central portion of the channel connection pattern 375. In one embodiment, the lower portion of the ninth opening 315 adjacent to the channel connection pattern 375 may be asymmetrical with respect to the imaginary line.

[0182] Refer again Figure 49A and Figure 49B It can be executed and referenced. Figures 35 to 44 and Figures 1 to 7 The processes shown are essentially the same or similar to those used to manufacture vertical storage devices.

[0183] Figure 53A , Figure 53B and Figure 54 A cross-sectional view of a vertical storage device according to an example embodiment is shown. Figure 53A and Figure 53B A cross-sectional view taken along line A-A' in the corresponding top view is shown. Figure 54 A cross-sectional view taken along line G-G' in the corresponding top view is shown. Figure 53B It shows Figure 53A An enlarged cross-sectional view of region W.

[0184] In addition to the second etch stop layer and the second etch stop pattern, this vertical memory device can be connected with... Figures 1 to 7 The vertical storage devices are essentially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated descriptions can be omitted.

[0185] Reference Figure 53A , Figure 53B and Figure 54 On the first region I of the substrate 100, the vertical memory device may further include a second etch stop pattern 505 located between the upper surface of the substrate 100 and the first support pattern 152, and on a portion of the sidewall of the first support pattern 152. The portion of the second etch stop pattern 505 located between the upper surface of the substrate 100 and the first support pattern 152 may have a sidewall facing the first CSL 440, which may contact the second blocking pattern 415, and may also contact the first etch stop pattern 390 above and below the second blocking pattern 415. For example, the first etch stop pattern 390 may be divided into two parts in a region adjacent to the sidewall of this portion of the second etch stop pattern 505.

[0186] In one embodiment, on the second region II of the substrate 100, the vertical memory device may further include a second etch stop layer 500 located between the upper surface of the substrate 100 and each of the second support pattern 154 and the third support pattern 156, and between the sacrificial layer structure and the support layer 150. A portion of the second etch stop layer 500 located between the upper surface of the substrate 100 and each of the second support pattern 154 and the third support pattern 156 may have a sidewall facing the first CSL 440, which may contact the second blocking pattern 415 and also contact the first etch stop pattern 390 above and below the second blocking pattern 415. For example, the first etch stop pattern 390 may be divided into two parts in a region adjacent to the sidewall of this portion of the second etch stop layer 500.

[0187] The second etch stop layer 500 and the second etch stop pattern 505 may include a material that has etch selectivity relative to the support layer 150, such as an oxide like silicon oxide.

[0188] Figures 55 to 61 Cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown. Figure 55 , Figure 57 , Figure 59 and Figure 61 A cross-sectional view taken along line A-A' in the corresponding top view is shown. Figure 56 , Figure 58 and Figure 60 A cross-sectional view taken along line E-E' in the corresponding top view is shown.

[0189] Reference Figure 55 It can be executed and referenced. Figure 8 and Figure 9 The processes shown are basically the same or similar.

[0190] In one embodiment, after partially removing the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130 to form the first opening 142, the second opening 144, and the third opening 146, respectively, a second etch stop layer 500 and a support layer 150 may be sequentially formed on the exposed upper surface of the substrate 100 and on the third sacrificial layer 130 to at least partially fill each of the first opening 142, the second opening 144, and the third opening 146.

[0191] The second etch stop layer 500 may include a material that has etch selectivity relative to the support layer 150, such as an oxide like silicon oxide. In one embodiment, the second etch stop layer 500 may be partially integrated with the third sacrificial layer 130 and / or the first sacrificial layer 110.

[0192] An insulating layer 170 can be formed on the support layer 150 to fill the first recess, and the upper part of the insulating layer 170 can be planarized.

[0193] Reference Figure 56 It can be executed and referenced. Figures 10 to 25 The processes shown are basically the same or similar.

[0194] In one implementation, only the first sacrificial layer 110 and the third sacrificial layer 130 exposed through the ninth opening 315 and the second etch stop layer 500 may be removed to form the first gap 332.

[0195] Reference Figure 57 and Figure 58 It can be executed and referenced. Figure 26 and Figure 27 The processes shown are basically the same or similar.

[0196] In one embodiment, the upper portion of the substrate 100 exposed through the ninth opening 315 and the first gap 332, the upper portions of the first support pattern 152, the second support pattern 154 and the third support pattern 156 exposed through the ninth opening 315 and the first gap 332, the lower portion of the support layer 150 exposed through the ninth opening 315 and the first gap 332, and the surface of the first spacer 337 can be oxidized to transform into a fifth sacrificial pattern 340.

[0197] Reference Figure 59 and Figure 60 It can be executed and referenced. Figure 28 and Figure 29 The processes shown are basically the same or similar.

[0198] In one embodiment, the fifth sacrificial pattern 340, the first sacrificial layer 110, and the third sacrificial layer 130 may be removed, and the second sacrificial layer 120 may be removed to form the second gap 350.

[0199] In an example embodiment, the fifth sacrificial pattern 340, as well as the first sacrificial layer 110, the second sacrificial layer 120, and the third sacrificial layer 130, can be removed by using a wet etching process, for example, with hydrofluoric acid (HF), and the second etch stop layer 500 can be partially removed and partially retained.

[0200] For example, a portion of the second etch stop layer 500 located between the upper surface of the substrate 100 and the first support pattern 152, and between the sidewall of the second sacrificial layer 120 and the opposite sidewall of the first support pattern 152, may be retained on the first region I of the substrate 100. This portion may be referred to hereinafter as the second etch stop pattern 505. The second etch stop pattern 505 may be retained between the upper surface of the substrate 100 and the first support pattern 152 in a region relatively far from or on the far side of the ninth opening 315, and may be retained on a portion of the sidewall of the first support pattern 152.

[0201] Refer again Figure 54 The portion of the second etch stop layer 500 adjacent to the ninth opening 315 between the upper surface of the substrate 100 and the third support pattern 156 can be removed, and the remaining portion can remain on the second region II of the substrate 100.

[0202] The second sacrificial layer 120 can be removed by a wet etching process using, for example, phosphoric acid (H3PO4), and the support layer 150 or support patterns 152, 154, and 156, including doped polysilicon, can be partially removed. In one embodiment, portions of the support layer 150 or support patterns 152, 154, and 156 covered by a second etch stop layer 500 or second etch stop pattern 505 including silicon oxide may not be removed by the wet etching process.

[0203] The first spacer 337 can be removed, and a seed layer 360 can be formed on the silicon-containing layer (e.g., the upper surface of the substrate 100, the upper surfaces of the first support pattern 152, the second support pattern 154 and the third support pattern 156, the lower surface and sidewalls of the support layer 150, and the exposed outer sidewalls of the channel 260).

[0204] Reference Figure 61 It can be executed and referenced. Figures 30 to 36 The processes described are basically the same or similar.

[0205] In one embodiment, an oxidation process can be performed on the silicon-containing layer to form a first etch stop pattern 390 on the upper surface of the substrate 100, the sidewalls of the channel connection pattern 375, the sidewalls of the first support pattern 152, the second support pattern 154 and the third support pattern 156, and the lower surface and sidewalls of the support layer 150.

[0206] Refer to Figure 53 again and Figure 54 It can be executed and referenced. Figures 37 to 44 and Figures 1 to 7 The processes shown are essentially the same or similar to those used to manufacture vertical storage devices.

[0207] Figure 62A , Figure 62B and Figure 63 A cross-sectional view of a vertical storage device according to an example embodiment is shown. Figure 62A and Figure 62B A cross-sectional view taken along line A-A' in the corresponding top view is shown. Figure 63 A cross-sectional view taken along line G-G' in the corresponding top view is shown. Figure 62B It shows Figure 62A An enlarged cross-sectional view of region W.

[0208] In addition to including a third and fourth etch stop pattern instead of the second etch stop layer and the second etch stop pattern, this vertical storage device can be coupled with... Figures 1 to 7 The vertical storage devices are essentially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated descriptions can be omitted here.

[0209] Reference Figure 62A , Figure 62B and Figure 63 On the first region I of the substrate 100, the vertical storage device may further include a third etch stop pattern 510 located between the upper surface of the substrate 100 and the first support pattern 152, and a fourth etch stop pattern 515 located on a portion of the sidewall of the first etch stop pattern 390.

[0210] The upper surface of the third etch stop pattern 510 may be higher than the upper surface of the substrate 100, and the lower surface of the third etch stop pattern 510 may be lower than the upper surface of the substrate 100. The sidewall of the third etch stop pattern 510 facing the first CSL 440 may contact the second blocking pattern 415.

[0211] The fourth etch stop pattern 515 may protrude from the sidewall of the channel connection pattern 375 in a third direction, and may have a convex shape facing the center portion of the channel connection pattern 375 in a third direction.

[0212] On the second region II of the substrate 100, the vertical memory device may further include a third etch stop pattern 510 located between the upper surface of the substrate 100 and each of the second support pattern 154 and the third support pattern 156, and a fourth etch stop pattern 515 located between each of the second support pattern 154 and the third support pattern 156 and the sidewall of the second sacrificial layer 120 of the sacrificial layer structure.

[0213] The upper surface of the third etch stop pattern 510 may be higher than the upper surface of the substrate 100, and the lower surface of the third etch stop pattern 510 may be lower than the upper surface of the substrate 100. The sidewall of the third etch stop pattern 510 facing the first CSL 440 may contact the second blocking pattern 415.

[0214] The fourth etch stop pattern 515 may protrude from the sidewall of each of the second support pattern 154 and the third support pattern 156 in a third direction, and may have a convex shape in the third direction toward the second sacrificial layer 120.

[0215] The third etch stop pattern 510 may include oxides (e.g., impurity-doped silicon oxide) in the material contained in the substrate 100, and the fourth etch stop pattern 515 may include oxides (e.g., oxynitrides) in the material contained in the second sacrificial layer 120.

[0216] Figure 64 Cross-sectional views of various stages in a method for manufacturing a vertical storage device according to an example embodiment are shown, along with a cross-sectional view taken along line A-A' in the corresponding top view. The method may include reference to... Figures 55 to 61 , Figure 62A , Figure 62B and Figure 63 The processes shown are essentially the same or similar, so their repeated descriptions can be omitted in this article.

[0217] Reference Figure 64 It can be executed and referenced. Figure 55 The processes shown are basically the same or similar.

[0218] In one embodiment, instead of forming a second etch stop layer 500, an oxidation process can be performed on the silicon-containing layer to form a third etch stop pattern 510 and a fourth etch stop pattern 515. For example, the upper surface of the substrate 100 exposed through the first opening 142, the second opening 144, and the third opening 146 can be oxidized to form the third etch stop pattern 510, and the sidewalls of the second sacrificial layer 120 exposed through the first opening 142, the second opening 144, and the third opening 146 can be oxidized to form the fourth etch stop pattern 515.

[0219] In one embodiment, the third etch stop pattern 510 may include silicon oxide doped with impurities, and the fourth etch stop pattern 515 may include oxynitride (e.g., silicon oxynitride).

[0220] Executable and referenced Figures 56 to 61 , Figure 62A , Figure 62B and Figure 63The processes shown are essentially the same or similar to those used to manufacture vertical storage devices.

[0221] Figure 65 and Figure 66 A cross-sectional view of a vertical storage device according to an example embodiment is shown. Figure 65 A cross-sectional view taken along line A-A' in the corresponding top view is shown. Figure 66 A cross-sectional view taken along line E-E' in the corresponding top view is shown.

[0222] In addition to the CSL and CSL board, this vertical storage device can be used with... Figures 1 to 7 The vertical storage devices are substantially the same or similar. Therefore, the same reference numerals refer to the same elements, and repeated descriptions may be omitted herein.

[0223] Reference Figure 65 and Figure 66 The vertical storage device may also include a CSL plate 600 between the substrate 100 and the channel connection pattern 375, the first support pattern 152, the second support pattern 154 and the third support pattern 156, and may not form a CSL extending along the first direction.

[0224] For example, only the second spacer 430 may be formed in each of the ninth opening 315, the tenth opening 325 and the eleventh opening 335, and no impurity region may be formed on the upper part of the substrate 100.

[0225] CSL plate 600 may include, for example, metal, metal nitride, metal silicide, etc., and channel 260 may be electrically connected to CSL plate 600 on substrate 100 via channel connection pattern 375.

[0226] Through summarization and review, it was found that if the polysilicon layer does not completely fill the gaps, voids may be generated in the polysilicon layer.

[0227] One or more embodiments may provide vertical storage devices with improved characteristics.

[0228] In the vertical memory device according to the example embodiment, the air gap in the channel connection pattern can be formed away from the CSL, and characteristic degradation due to metal penetration into the air gap can be prevented. Additionally, the upper surface of the substrate adjacent to the channel connection pattern can be protected by a seed pattern and an etch stop pattern, and the vertical memory device can have enhanced characteristics.

[0229] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A vertical memory device, the vertical memory device comprising: a substrate; a plurality of channels on the substrate, each of the channels extending in a first direction perpendicular to an upper surface of the substrate; a channel connection pattern extending in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the plurality of channels, the channel connection pattern connecting the plurality of channels to each other; a plurality of gate electrodes on the channel connection pattern and spaced apart from each other in the first direction, each of the gate electrodes extending in the second direction to surround the plurality of channels; and an etching stop pattern and a barrier pattern sequentially stacked in a third direction at ends of the channel connection pattern, the third direction being parallel to the upper surface of the substrate and crossing the second direction, and the etching stop pattern and the barrier pattern comprising different materials from each other, wherein sidewalls of the ends of the channel connection pattern are recessed in the third direction toward a central portion of the channel connection pattern.

2. The vertical memory device according to claim 1, wherein: the channel connection pattern comprises doped polysilicon, the etching stop pattern comprises silicon oxide, and the barrier pattern comprises metal oxide. the sidewalls of the ends of the channel connection pattern have a shape that is asymmetric in the first direction with respect to an imaginary line passing through a central portion of the channel connection pattern.

3. The vertical memory device of claim 1, wherein, a distance from one of the plurality of channels in the third direction to an upper portion of the sidewalls of the ends of the channel connection pattern is smaller than a distance from the one of the channels in the third direction to a lower portion of the sidewalls of the ends of the channel connection pattern.

4. The vertical memory device of claim 3, wherein, the sidewalls of the ends of the channel connection pattern have a shape that is symmetric in the first direction with respect to an imaginary line passing through a central portion of the channel connection pattern.

5. The vertical memory device of claim 1, wherein, 6. The vertical memory device according to claim 1, further comprising a support layer between the channel connection pattern and a lowermost one of the plurality of gate electrodes, the support layer comprising doped polysilicon. the etching stop pattern and the barrier pattern are on sidewalls and a lower surface of the support layer.

7. The vertical memory device of claim 6, wherein, 8. The vertical memory device according to claim 6, wherein: the support layer extends in the second direction, and a bottom surface of an end portion of the support layer is higher than a bottom surface of other portions of the support layer.

9. The vertical memory device according to claim 6, further comprising at least one support pattern in contact with the upper surface of the substrate and connected to an end portion of the support layer, the at least one support pattern comprising substantially the same material as a material of the support layer. the at least one support pattern comprises a plurality of support patterns spaced apart from each other in the second direction.

10. The vertical memory device of claim 9, wherein, 11. The vertical memory device according to claim 9, wherein: ​ The substrate includes a first region and a second region surrounding the first region, the plurality of channels is formed on the first region, and The at least one support pattern includes: at least one first support pattern, the at least one first support pattern is located on the first region of the substrate; a second support pattern, the second support pattern is located on a boundary between the first region and the second region of the substrate, the second support pattern extends in the third direction; and at least one third support pattern, the at least one third support pattern is located on the second region of the substrate, the at least one third support pattern extends from the second support pattern in the second direction.

12. The vertical memory device of claim 11, wherein: The at least one first support pattern includes a plurality of first support patterns spaced apart from each other in the second direction, The at least one third support pattern includes a plurality of third support patterns spaced apart from each other in the third direction.

13. The vertical memory device of claim 12, further comprising a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked in the first direction between the substrate and the support layer, the first oxide layer, the nitride layer, and the second oxide layer are located between adjacent third support patterns in the plurality of third support patterns in the third direction.

14. The vertical memory device of claim 1, further comprising a seed pattern located between the substrate and the channel connection pattern, the seed pattern includes silicon and impurities.

15. The vertical memory device of claim 14, wherein, The impurities include carbon, nitrogen, or oxygen.

16. The vertical memory device of claim 14, wherein, The seed pattern is located between the outer sidewall of the channel and the channel connection pattern.

17. The vertical memory device of claim 1, wherein, The blocking pattern covers a lower surface, an upper surface, and a sidewall of each of the gate electrodes, the sidewall faces the outer sidewall of each of the channels.

18. The vertical memory device of claim 17, wherein: The blocking pattern is a second blocking pattern, and The vertical memory device further includes a charge storage structure covering at least a portion of the outer sidewall of each of the channels, the charge storage structure includes a tunnel insulating pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction substantially parallel to the upper surface of the substrate.

19. The vertical memory device of claim 18, wherein: The charge storage structure includes an upper portion and a lower portion, the upper portion of the charge storage structure covers an upper portion of the outer sidewall of each of the channels, the lower portion of the charge storage structure contacts the upper surface of the substrate and covers a lower portion and a bottom surface of the outer sidewall of each of the channels, and A bottom surface of the tunnel insulating pattern and a bottom surface of the charge storage pattern of the upper portion of the charge storage structure are higher than a bottom surface of the first blocking pattern of the upper portion.

20. A vertical memory device, the vertical memory device comprising: a substrate; a channel connection pattern, the channel connection pattern is located on the substrate; a plurality of gate electrodes located on the channel connection pattern and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate; a channel located on the substrate and extending in the first direction through the plurality of gate electrodes and the channel connection pattern; and a seed pattern located between the substrate and the channel connection pattern and between the channel and the channel connection pattern, the seed pattern including silicon and an impurity. The impurity includes carbon, nitrogen, or oxygen.

21. The vertical memory device of claim 20, wherein, 22. A vertical memory device, the vertical memory device comprising: a substrate including a first region and a second region surrounding the first region; a plurality of channels located on the first region of the substrate, each of the channels extending in a first direction perpendicular to an upper surface of the substrate; a channel connection pattern located on the first region of the substrate and extending in a second direction parallel to the upper surface of the substrate, the channel connection pattern covering outer sidewalls of the plurality of channels and connecting the plurality of channels to each other; a sacrificial layer structure located on the second region of the substrate and extending in the second direction at a height substantially equal to a height of the channel connection pattern, the sacrificial layer structure including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction; a support layer located on the channel connection pattern and the sacrificial layer structure; and a plurality of gate electrodes located on the support layer and spaced apart from each other in the first direction, each of the gate electrodes extending in the second direction to surround the plurality of channels. The first sacrificial layer, the second sacrificial layer, and the third sacrificial layer respectively include an oxide, a nitride, and an oxide.

24. The vertical memory device of claim 22, further comprising a support pattern structure connected to the support layer, the support pattern structure including:

23. The vertical memory device of claim 22, wherein, at least one first support pattern located on the first region of the substrate and adjacent to an end portion of the channel connection pattern in a third direction, the third direction being parallel to the upper surface of the substrate and intersecting the second direction; a second support pattern located on a boundary between the first region and the second region of the substrate, the second support pattern extending in the third direction; and at least one third support pattern located on the second region of the substrate, the at least one third support pattern contacting the sacrificial layer structure and extending in the second direction from the second support pattern. ​ ​ ​

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