Memory element, programmable metallization unit and method for manufacturing the same

Abstract

Some embodiments relate to a memory element. The memory element includes a top electrode overlying a bottom electrode. A data storage layer overlies the bottom electrode. The bottom electrode holds the underside of the data storage layer. The top electrode overlies the data storage layer. A top surface of the bottom electrode is aligned with a top surface of the top electrode.

Description

Technical Field

[0001] The embodiments of the present invention relate to a memory element, a programmable metallization unit and a manufacturing method thereof. Background Art

[0002] Many modern electronic devices include electronic memory. Electronic memory can be volatile memory or non-volatile memory. Non-volatile memory can retain its stored data without power, while volatile memory loses its stored data when power is off. Programmable metallization cell (PMC) random access memory (RAM) (which may also be called conductive bridging RAM, CBRAM, nanobridge or electrolytic memory) is a promising candidate for the next generation of non-volatile electronic memory due to its advantages over current electronic memory. Compared with current non-volatile memory (e.g., flash random access memory), PMCRAM generally has better performance and reliability. Compared with current volatile memory (e.g., dynamic random access memory (DRAM) and static random access memory (SRAM)), PMCRAM generally has better performance and density and has lower power consumption. Summary of the invention

[0003] In some embodiments, the present disclosure relates to a memory element comprising: a bottom electrode; a data storage layer overlying the bottom electrode, wherein the bottom electrode holds the underside of the data storage layer; and a top electrode overlying the data storage layer, wherein a top surface of the bottom electrode is aligned with a top surface of the top electrode.

[0004] In other embodiments, the present disclosure relates to a programmable metallization unit, which includes: a bottom dielectric layer overlying a conductive line; a bottom electrode disposed in the bottom dielectric layer, wherein the bottom electrode is U-shaped and contacts the conductive line; a data storage layer overlying the bottom electrode, wherein the data storage layer is U-shaped so that the upper surface of the bottom electrode extends continuously along the lower surface of the data storage layer; and a top electrode overlying the data storage layer.

[0005] In other embodiments, the present disclosure relates to a method for manufacturing a memory element. The method includes: forming a bottom dielectric layer above a conductive line; patterning the bottom dielectric layer to form an opening above the conductive line, wherein the opening has a curved sidewall so that the width of the opening increases continuously from the bottom surface of the bottom dielectric layer to the top surface of the bottom dielectric layer; forming a memory layer stack above the conductive line and in the opening, wherein the memory layer stack includes a top electrode overlying a bottom electrode; and performing a planarization process on the memory layer stack to align the top surface of the top electrode with the top surface of the bottom electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of memory elements including programmable metallization cells are shown.

[0008] Figure 2A to Figure 2B as well as FIG. 3A to FIG. 3B Show Figure 1 Cross-sectional views of various alternative embodiments of memory elements are shown.

[0009] Figure 4 A cross-sectional view of some embodiments of a memory element including two programmable metallization cells is shown.

[0010] Figure 5 Show Figure 4 A top view of some embodiments of memory elements shown, as shown by Figure 4 and Figure 5 As shown by the cutting lines in .

[0011] Figures 6 to 11 Cross-sectional views of some embodiments of methods of forming a memory element including a programmable metallization cell are shown.

[0012] Fig.12 The method is shown in a flow chart format illustrating some embodiments of a method of forming a memory element including a programmable metallization cell. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] A programmable metallization cell generally includes a data storage layer arranged between a top electrode and a bottom electrode. When a set voltage is applied across the top electrode and the bottom electrode, a conductive bridge is formed in the data storage layer (causing a low resistance state). When a reset voltage is applied across the top electrode and the bottom electrode, the conductive bridge is erased in the data storage layer (causing a high resistance state).

[0016] During the fabrication of the programmable metallization cell, a memory cell stack is formed over a substrate. The memory cell stack includes a data storage layer disposed between a top electrode layer and a bottom electrode layer. A hard mask layer is formed over the top electrode layer. Separate etching processes are then performed to define the top electrode and the bottom electrode. For example, a first etching process (e.g., a first plasma etching process) is performed to define the top electrode by patterning the top electrode layer. During the first etching process, material from the top electrode layer (e.g., titanium nitride) will be re-deposited onto the sidewalls of the hard mask layer. During a second etching process (e.g., a second plasma etching process) for defining the bottom electrode, material from the top electrode and / or the bottom electrode layer may be etched and redistributed onto the sidewalls of the data storage layer. Since the material is conductive, the material may electrically short the top electrode to the bottom electrode, rendering the programmable metallization cell inoperable. In addition, a wet cleaning process (e.g., using a cleaning solution such as hydrofluoric acid and / or deionized water) used after a separate etching process (e.g., to reduce redeposited conductive material) may damage the interface between the top electrode and / or the bottom electrode and the data storage layer, thereby causing delamination between the layers. This may partially impair the stability, durability and / or switching time of the programmable metallization cell.

[0017] In some embodiments of the present disclosure, in order to prevent material from being re-deposited from the top electrode and / or bottom electrode layer onto the sidewalls of the memory cell stack, the memory cell stack may be formed by a planarization process (e.g., a chemical-mechanical planarization (CMP) process) rather than a separate etching process. In such an embodiment, a dielectric layer is formed over the conductive line, and a mask layer is formed over the outer region of the dielectric layer. An etching process is performed to define an opening in the dielectric layer directly above the central portion of the conductive line. A memory cell stack is formed within the opening so that the upper surface of the memory cell stack is recessed below the top surface of the dielectric layer. A planarization process is performed on the memory cell stack until the top surface of the dielectric layer is reached, thereby defining a programmable metallization unit. Through the planarization process, the layers within the programmable metallization unit have U-shaped profiles, respectively. After the programmable metallization unit is formed, a wet cleaning process (e.g., the above-mentioned wet cleaning process) is performed on the programmable metallization unit. The U-shaped profile of the layers in the programmable metallization unit mitigates and / or prevents peeling between layers. The memory cell stack is not formed by a plasma etching process, thereby reducing and / or eliminating the redeposition of conductive material on the top electrode and / or the bottom electrode. Therefore, this method is conducive to forming a programmable metallization cell without etching the memory cell stack, and thereby preventing the top electrode from short-circuiting with the bottom electrode. In addition, replacing a separate etching process with a planarization process reduces the cost and time associated with forming the programmable metallization cell and reduces peeling at the interface between the top electrode and / or the bottom electrode and the data storage layer. This partially improves the stability, durability and / or increases the switching time of the programmable metallization cell.

[0018] Reference Figure 1 , cross-sectional views of some embodiments of memory elements 100 including memory cells 116 are provided.

[0019] The memory cell 116 includes a bottom electrode 108 and a top electrode 112, wherein a data storage layer 110 (also referred to as an insulator layer or electrolyte in some embodiments) is disposed between the top electrode 112 and the bottom electrode 108. The memory cell 116 is disposed within the bottom dielectric layer 106 such that a top surface of the memory cell 116 is aligned with a top surface of the bottom dielectric layer 106, and a bottom surface of the memory cell 116 is aligned with a bottom surface of the bottom dielectric layer 106. In some embodiments, the memory cell 116 is configured as a programmable metallization cell (PMC) random access memory (RAM), which may also be referred to as a conductive bridge RAM, CBRAM, nanobridge, or electrolytic memory.

[0020] The memory cell 116 is often disposed on an inter-level dielectric (ILD) layer 102, wherein a bottom conductive line 104 is disposed within the ILD layer 102. The bottom conductive line 104 electrically couples the bottom electrode 108 to an underlying metal layer and / or complementary metal-oxide-semiconductor (CMOS) element (e.g., a transistor, a diode, etc.), which may be overlying a semiconductor substrate (not shown). A via 122 overlies the top electrode 112 and electrically couples the top electrode 112 to an upper conductive layer (e.g., an upper conductive line 124). The via 122 extends through the upper ILD structure 120. The upper conductive line 124 extends beyond the sidewalls of the via 122 and may be electrically coupled to an overlying bit line (not shown).

[0021] The bottom electrode 108 includes a central bottom electrode region 108c and a peripheral bottom electrode region 108p, and the peripheral bottom electrode region 108p extends upward from the central bottom electrode region 108c. Similarly, the data storage layer 110 and the top electrode 112 include central regions 110c and 112c above the central bottom electrode region 108c, and peripheral regions 110p and 112p above the peripheral bottom electrode region 108p, respectively.

[0022] In some embodiments, the bottom dielectric layer 106 has a pair of sidewalls 106s1, 106s2, and the pair of sidewalls 106s1, 106s2 directly contact the outer sidewall of the bottom electrode 108. The pair of sidewalls 106s1, 106s2 respectively have an inclined section overlying the curved section, so that the sidewalls (e.g., the outer sidewall and / or the inner sidewall) of the bottom electrode 108 respectively have an inclined section overlying the curved section. In addition, the sidewalls (e.g., the outer sidewall and / or the inner sidewall) of the data storage layer 110 respectively have an inclined section overlying the curved section, and the sidewalls (e.g., the outer sidewall and / or the inner sidewall) of the top electrode 112 respectively have an inclined section overlying the curved section. The bottom electrode 108 is located below the bottom surface and the outer sidewall of the data storage layer 110 and cups the bottom surface and the outer sidewall of the data storage layer 110. The data storage layer 110 is located below and supports the bottom surface and outer sidewalls of the top electrode 112. The top surface of the bottom electrode 108, the top surface of the data storage layer 110, the top surface of the top electrode 112, and the top surface of the bottom dielectric layer 106 are aligned. It is understood that the alignment described herein anticipates some small misalignment, such as due to tolerances that may exist in the surfaces and / or portions of the aligned layers and / or structures (e.g., during a chemical mechanical planarization (CMP) process used to form the device).

[0023] In some embodiments, the pair of sidewalls 106s1, 106s2, the outer sidewall of the bottom electrode 108, the outer sidewall of the data storage layer 110, and the outer sidewall of the top electrode 112 are defined from a cross-sectional view. For example, if the memory cell 116 is circular or elliptical when viewed from above, the pair of sidewalls 106s1, 106s2 are a single continuous sidewall when viewed from above, and thus, "a pair" of sidewalls 106s1, 106s2 refers to the property of this single continuous sidewall when drawn in a cross-sectional view. In addition, if the memory cell 116 is circular or elliptical when viewed from above, any length and / or width associated with the cross-sectional view of the layer including the memory cell 116 corresponds to the diameter of the circle or the length defined between two vertices on the major axis of the ellipse, respectively.

[0024] In some embodiments, the inner sidewall 112sw of the top electrode 112 has an inclined section 112ss overlying the curved section 112cs so that the first width W1 of the top electrode 112 is smaller than the second width W2 of the top electrode 112. Figure 1 As can be seen, the width of the top electrode 112 increases continuously from the first width W1 to the second width W2. In addition, the inner sidewall 110sw of the data storage layer 110 has an inclined section 110ss overlying the curved section 110cs. In addition, the inner sidewall 108sw of the bottom electrode 108 has an inclined section 108ss overlying the curved section 108cs.

[0025] During operation, the memory cell 116 relies on a redox reaction to form and dissolve a conductive bridge between the top electrode 112 and the bottom electrode 108 in the conductive bridge region 114 of the data storage layer 110. The presence of a conductive bridge in the conductive bridge region 114 between the top electrode 112 and the bottom electrode 108 generates a low resistance state, while the absence of a conductive bridge in the conductive bridge region 114 results in a high resistance state. Therefore, by applying an appropriate bias between the top electrode 112 and the bottom electrode 108 to form or dissolve a conductive bridge in the conductive bridge region 114, the memory cell 116 can be switched between a high resistance state and a low resistance state.

[0026] In some embodiments, the top electrode 112 and the bottom electrode 108 are made of silver. In these and / or other embodiments, to facilitate such switching, one of the top electrode 112 or the bottom electrode 108 is electrochemically inert, while the other is electrochemically active to help facilitate switching. For example, in some embodiments, the top electrode 112 may be relatively electrochemically inert and may include titanium nitride, tantalum nitride, silver, tantalum, titanium, platinum, nickel, hafnium, zirconium, and / or tungsten, among others; and / or the bottom electrode 108 may be electrochemically active and may be made of silver, copper, aluminum, or tellurium, among others. In other embodiments, the composition of the top electrode 112 and the bottom electrode 108 may be flipped relative to the above, so that the top electrode 112 is electrochemically active and the bottom electrode 108 is inert. In some embodiments, the data storage layer 110 may be in the form of a solid electrolyte film, which is a solid material with highly mobile ions. For example, in some embodiments, the data storage layer 110 may be made of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), amorphous silicon or silicon nitride (Si 3 N 4 ), etc.

[0027] In some embodiments, such as those further described herein, Figure 2A As shown, the top electrode 112 includes a conductive barrier layer overlying an electrochemically inert layer or an electrochemically active layer. Figure 1 In the embodiment, the top electrode 112 may include a titanium nitride layer (i.e., a conductive barrier layer) overlying a silver layer (i.e., an electrochemically inert layer) so that the titanium nitride layer provides a stable interface for the overlying vias and / or conductive lines (e.g., vias 122). In some embodiments, if the conductive barrier layer (e.g., titanium nitride layer) is omitted and the vias and / or conductive lines are disposed directly on the electrochemically inert layer or the electrochemically active layer (e.g., a silver layer), migration of the conductive material (e.g., silver) in the electrochemically inert layer or the electrochemically active layer may occur. This may partially cause a short circuit between the top electrode 112 and the bottom electrode 108 and / or cause a non-ohmic contact between the overlying vias and / or conductive lines (e.g., vias 122) and the top electrode 112.

[0028] By overlying the memory cell 116 along the pair of sidewalls 106s1, 106s2 of the bottom dielectric layer 106, redeposition of conductive material from the top electrode 112 and / or the bottom electrode 108 to the data storage layer 110 is mitigated during fabrication of the memory cell 116. By mitigating redeposition of conductive material from the top electrode 112 and / or the bottom electrode 108, the top electrode 112 and the bottom electrode 108 are not electrically shorted together by the conductive material, and thus the memory cell 116 can be changed between a high resistance state and a low resistance state.

[0029] although Figure 1 The memory cell 116 is described as a programmable metallization cell (PMC) random access memory (RAM) cell, however, it should be understood that the memory cell 116 is not limited to such an element. Rather, in alternative embodiments, the memory cell 116 may be a phase-change random-access memory (PCRAM) cell, a resistive random-access memory (RRAM) cell, a magnetoresistive random-access memory (MRAM) cell, a spin-transfer torque magnetoresistive random-access memory (STT-MRAM) cell, etc. In such an embodiment, the memory cell 116 may be formed so that the top surface of the top electrode, the top surface of the bottom electrode, and the top surface of the data storage layer are respectively aligned with substantially straight horizontal lines so that the top electrode and the bottom electrode are not electrically coupled together (e.g., coupled together by redeposited conductive material).

[0030] Reference Figure 2A , provide the basis Figure 1 A cross-sectional view of a memory element 200 a of some alternative embodiments of the memory element 100 is shown, wherein the conductive barrier layer 202 overlies the top electrode 112 .

[0031] The memory element 200a includes a top dielectric layer 204 overlying the memory cell 116. The memory cell 116 includes a conductive barrier layer 202 overlying the top electrode 112 and a data storage layer 110 disposed between the top electrode 112 and the bottom electrode 108. In some embodiments, the conductive barrier layer 202 is a portion of the top electrode 112, such that the conductive barrier layer 202 is the topmost layer in the top electrode 112. The conductive barrier layer 202 is configured to prevent material (e.g., silver) from migrating from the top electrode 112 to the bottom electrode 108 (and / or to an overlying metal layer), thereby mitigating electrical shorts between the top electrode 112 and the bottom electrode 108 and / or preventing non-ohmic contact with an overlying metal layer (e.g., via 122). In other embodiments, the top surface of the conductive barrier layer 202, the top surface of the top electrode 112, the top surface of the data storage layer 110, the top surface of the bottom electrode 108, and the top surface of the bottom dielectric layer 106 are aligned with the horizontal plane 203 (e.g., the xz plane). In other embodiments, the horizontal plane 203 is parallel to the top surface of the underlying semiconductor substrate (not shown). The bottom surface of the via 122 is lower than the horizontal plane 203. The upper surface 202u of the conductive barrier layer 202 is lower than the horizontal plane 203. The lower portion of the top dielectric layer 204 extends below the horizontal plane 203. In other embodiments, the top surface of the conductive barrier layer 202, the top surface of the top electrode 112, the top surface of the data storage layer 110, the top surface of the bottom electrode 108, and the top surface of the bottom dielectric layer 106 are directly in contact with the lower surface of the top dielectric layer 204, respectively. In some embodiments, the bottom surface of the bottom electrode 108 is recessed below the top surface of the bottom conductive line 104 by a distance d1, which may be, for example, in the range of about 1 angstrom to 130 angstroms. In other embodiments, the bottom surface of the bottom electrode 108 is aligned with the top surface of the bottom conductive line 104 so that the distance d1 is 0 angstroms (not shown).

[0032] In some embodiments, the bottom dielectric layer 106 may be one or more dielectric layers and may be, for example, silicon nitride, silicon carbide, etc., with a thickness in the range of approximately 300 angstroms to 1000 angstroms. In other embodiments, the bottom electrode 108 may be one or more conductive layers and may be, for example, silver, copper, aluminum, tellurium, etc., with a thickness in the range of approximately 75 angstroms to 300 angstroms. In still other embodiments, the data storage layer 110 may be one or more dielectric layers and may be, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, another metal oxide, etc., with a thickness in the range of approximately 20 angstroms to 100 angstroms. In some embodiments, the top electrode 112 may be one or more conductive layers and may be, for example, silver, copper, titanium nitride, tantalum nitride, etc., with a thickness in the range of approximately 100 angstroms to 600 angstroms. In some embodiments, the conductive barrier layer 202 may be, for example, titanium nitride, tantalum nitride, etc., with a thickness in the range of approximately 10 angstroms to 200 angstroms. In some embodiments, the top electrode 112 and the bottom electrode 108 include the same conductive material (e.g., silver), which is different from the material (e.g., titanium nitride) included in the conductive barrier layer 202. In some embodiments, the bottom conductive line 104, the via 122, and the upper conductive line 124 may be, for example, or may include aluminum, copper, etc. In other embodiments, the top dielectric layer 204 may be one or more dielectric layers and may be, for example, or may include silicon nitride, silicon carbide, etc., with a thickness in the range of 300 angstroms to 1500 angstroms. In some embodiments, the top dielectric layer 204 is the same material and / or material combination as the bottom dielectric layer 106. In other embodiments, the upper ILD structure 120 includes one or more dielectric layers and may be, for example, or may include silicon oxide, another oxide, a low-k dielectric, etc., with a thickness in the range of about 1250 angstroms to 2800 angstroms. As described herein, a low-k dielectric is a dielectric material with a dielectric constant less than 3.9.

[0033] Reference Figure 2B , provide the basis Figure 1A cross-sectional view of a memory element 200b of some alternative embodiments of the memory element 100 is shown, wherein the top surface of the top electrode 112 and the top surface of the bottom electrode 108 are recessed below the top surface of the data storage layer 110 by a distance d2. The upper section 110a of the data storage layer 110 is located above the top surfaces of the top electrode 112 and the bottom electrode 108 in the vertical direction. This partially increases the isolation between the top electrode 112 and the bottom electrode 108, and thereby alleviates the "leakage" (i.e., the flow of current) between the top electrode 112 and the bottom electrode 108. By increasing the isolation between the top electrode 112 and the bottom electrode 108, the initial "leakage" of the memory cell 116 is reduced, and the stability, durability of the memory cell 116 can be improved and / or the set / reset voltage margin of the memory cell 116 can be increased. In some embodiments, the top surface of the top electrode 112 is lower than the top surface of the bottom electrode 108, or the top surface of the bottom electrode 108 is lower than the top surface of the top electrode 112 (not shown). This may be partially due to over etching of the top electrode 112 or the bottom electrode 108 during the formation of the memory element 200b (eg, during an etching process for forming the recess).

[0034] In some embodiments, the distance d2 is in the range of 20 angstroms to 200 angstroms. In some embodiments, if the distance d2 is greater than 20 angstroms, the isolation between the top electrode 112 and the bottom electrode 108 is increased, thereby reducing the "leakage" between the top electrode 112 and the bottom electrode 108. In other embodiments, if the distance d2 is less than 200 angstroms, the top electrode 112 and / or the bottom electrode 108 are large enough to enable the memory cell 116 to have enhanced stability, durability, and / or switching time.

[0035] Reference Figure 3A , provide the basis Figure 1A cross-sectional view of a memory element 300a of some alternative embodiments of the memory element 100 is shown, wherein the top surface of the data storage layer 110 is recessed to be lower than the top surface of the top electrode 112 and the top surface of the bottom electrode 108 by a distance d3. This partially increases the isolation between the top electrode 112 and the bottom electrode 108, and thereby alleviates the "leakage" between the top electrode 112 and the bottom electrode 108. By increasing the isolation between the top electrode 112 and the bottom electrode 108, the initial "leakage" of the memory cell 116 is reduced, and the stability, durability and / or set / reset voltage margin of the memory cell 116 can be improved. The upper segment of the top electrode 112 and the upper segment of the bottom electrode 108 are respectively located above the top surface of the data storage layer 110. In some embodiments, the upper segment of the top electrode 112 and the upper segment of the bottom electrode 108 are separated from each other in the lateral direction by the top dielectric layer 204. In other embodiments, the protrusion of the top dielectric layer 204 extends from the top surface of the top electrode 112 to the top surface of the data storage layer 110 by a distance d3.

[0036] In some embodiments, the distance d3 is in the range of 20 angstroms to 200 angstroms. In some embodiments, if the distance d3 is greater than 20 angstroms, the isolation between the top electrode 112 and the bottom electrode 108 is increased, thereby reducing the "leakage" between the top electrode 112 and the bottom electrode 108. In other embodiments, if the distance d3 is less than 200 angstroms, the top electrode 112 and / or the bottom electrode 108 are large enough to enable the memory cell 116 to have enhanced stability, durability, and / or switching time.

[0037] Reference Figure 3B , provide the basis Figure 3A 300a, wherein the upper segment of the top electrode 112 and the upper segment of the bottom electrode 108 are laterally separated from each other by a filling dielectric layer 302. In some embodiments, the filling dielectric layer 302 may be, for example, or may include silicon nitride, silicon carbide, etc. In some embodiments, the filling dielectric layer 302 extends from the top surface of the top electrode 112 to the top surface of the data storage layer 110 by a distance d3. In still other embodiments, the filling dielectric layer 302 includes a different material than the bottom dielectric layer 106 and / or the top dielectric layer 204. In still other embodiments, the filling dielectric layer 302 is omitted, and the space occupied by the filling dielectric layer 302 is filled with an empty space (e.g., air) (not shown).

[0038] Reference Figure 4, a cross-sectional view of some embodiments of an integrated circuit 400 is provided, wherein the integrated circuit 400 includes a first memory cell 116a and a second memory cell 116b disposed in an interconnect structure 404 of the integrated circuit 400. The first memory cell 116a and the second memory cell 116b are respectively shown and described as Figure 1 Storage unit 116 is shown.

[0039] The integrated circuit 400 includes a substrate 406. The substrate 406 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment depicts one or more shallow trench isolation (STI) regions 408, which may include dielectric-filled trenches within the substrate 406. A scribe line is disposed directly above the top surface of the top electrode 112 of both the first memory cell 116a and the second memory cell 116b, the top surface of the data storage layer 110, and the top surface of the bottom electrode 108.

[0040] Two access transistors 410, 412 are disposed between the STI regions 408. The access transistors 410, 412 include access gate electrodes 414, 416, respectively; access gate dielectrics 418, 420, respectively; access sidewall spacers 422; and source / drain regions 424. The source / drain regions 424 are disposed within the substrate 406 between the access gate electrodes 414, 416 and the STI regions 408 and are doped to have a first conductivity type, respectively, which is opposite to a second conductivity type of a channel region below the access gate dielectrics 418, 420. The access gate electrodes 414, 416 may be, for example, doped polysilicon or a metal such as aluminum, copper, or a combination thereof. The access gate dielectrics 418, 420 may be, for example, an oxide such as silicon dioxide or a high-k dielectric material. As described herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than about 3.9. The access sidewall spacer 422 may be made of, for example, silicon nitride (e.g., Si3N4). In some embodiments, the access transistor 410 and / or the access transistor 412 may be, for example, electrically coupled to a word line (WL) so that an appropriate WL voltage may be applied to the access gate electrode 414 and / or the access gate electrode 416.

[0041] The interconnect structure 404 is arranged on the substrate 406 and electrically couples the components (e.g., the access transistors 410, 412) to each other. The interconnect structure 404 includes a plurality of inter-metal dielectric (IMD) layers 426, 428, 430 and a plurality of metallization layers 432, 434, 436 stacked on each other in an alternating manner. The IMD layers 426, 428, 430 may be made of, for example, a low-k dielectric layer or an oxide (e.g., silicon dioxide). The metallization layers 432, 434, 436 include metal lines 438, 440, 442, which are formed in trenches and may be made of metal (e.g., copper or aluminum). The contact 444 extends from the bottom metallization layer 432 to the source / drain region 424 and / or the access gate electrodes 414, 416; and the via 446 extends between the metallization layers 432, 434, 436. The via 446 extends through the dielectric protection layer 450 (the dielectric protection layer 450 can be made of a dielectric material and can act as an etch stop layer during manufacturing). For example, the dielectric protection layer 450 can be made of a very low dielectric constant dielectric material. For example, the contact 444 and the via 446 can be made of a metal (such as copper or tungsten). In some embodiments, the metal lines in the metal lines 438 can be electrically coupled to the source line (SL), for example, so that the output of the access transistors 410, 412 can be accessed at the SL.

[0042] The first memory cell 116a and the second memory cell 116b configured to store corresponding data states are arranged in the interconnect structure 404 between adjacent metal layers. The first memory cell 116a and the second memory cell 116b include a bottom electrode 108, a data storage layer 110, and a top electrode 112, respectively. The first memory cell 116a and the second memory cell 116b are electrically coupled to the first bit line BL1 and the second bit line BL2, respectively, via a metal line 442. In some embodiments, a via (not shown) is disposed between the bottom conductive line 104 and the metal line 440. In some other embodiments, a top electrode via (not shown) is disposed between the first memory cell 116a and the second memory cell 116b and the via 122, respectively.

[0043] Reference Figure 5 ,supply Figure 4 A top view of some embodiments of integrated circuit 400 is shown.

[0044] like Figure 5As shown, the first memory cell 116a and the second memory cell 116b have a circular / elliptical shape. In some embodiments, when viewed from a top view, the first memory cell 116a and the second memory cell 116b may have a square and / or rectangular shape. However, in other embodiments, for example due to the partialities of many etching processes, the corners of the square or rectangular shape may become rounded, so that the first memory cell 116a and the second memory cell 116b have a square or rectangular shape with rounded corners, or have a circular or elliptical shape. The first memory cell 116a and the second memory cell 116b are arranged on the metal lines ( Figure 4 440) and has an upper portion that is directly electrically connected to the via 122. In some embodiments, the upper portion of the top electrode 112 is directly electrically coupled to a top electrode via (not shown) disposed between the top electrode 112 and the metal line 442.

[0045] Figures 6 to 11 Cross-sectional views 600 to 1100 illustrate some embodiments of a method of forming a memory element including a programmable metallization unit according to the present disclosure. Although described with reference to a method Figures 6 to 10 600 to 1100, however, it should be understood that Figures 6 to 11 The structures shown are not limited to the described methods but can be used independently of the described methods. Figures 6 to 11 It is described as a series of actions, but it should be understood that these actions are not limited, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0046] like Figure 6 As shown in the cross-sectional view 600 of FIG. 600 , a bottom conductive line 104 is formed in an interlayer dielectric (ILD) layer 102. A dielectric film 602 is formed on the bottom conductive line 104. In some embodiments, the dielectric film 602 includes one or more dielectric layers and may be, for example, silicon nitride, silicon carbide, etc. formed to a thickness in the range of about 300 angstroms to 1000 angstroms. A mask layer 604 is formed on the dielectric film 602 so that the mask layer 604 covers the outer regions 606a, 606c of the dielectric film 602 and the central region 606b of the dielectric film 602 is not covered and exposed. In some embodiments, the mask layer 604 includes a photoresist mask. In other embodiments, the mask layer 604 includes a hard mask layer (for example, including a nitride layer). In some other embodiments, the mask layer 604 may include a multi-layer hard mask. In some embodiments, the bottom conductive line 104 may be, for example, or may include aluminum, copper, etc.

[0047] like Figure 7As shown in the cross-sectional view 700 of FIG. 7 , an etching process is performed to the dielectric film ( Figure 6 602) is etched and on the dielectric film ( Figure 6 602) to define the bottom dielectric layer 106. The etching process involves making the center region ( Figure 6 The dielectric film ( Figure 6 602) is exposed to one or more etchants, and then a removal process is performed to remove the mask layer ( Figure 6 604) (not shown). In some embodiments, the etching process may include one or more etchants, such as difluoromethane (e.g., CH2F2, CHF3), perfluorocyclobutane (C4F8), hydrofluoric acid and / or nitric acid. In other embodiments, the etching process may include a dry etching process using a first etchant (e.g., difluoromethane (e.g., CH2F2, CHF3) and / or perfluorocyclobutane (C4F8)) and a subsequent blanket etch back process using a second etchant different from the first etchant. In some embodiments, the etching process etches the bottom conductive line 104 so that the upper surface of the bottom conductive line 104 is lower than the bottom surface of the bottom dielectric layer 106 by a distance in the range of approximately 1 angstrom to 130 angstroms (not shown).

[0048] In some embodiments, the bottom dielectric layer 106 has a pair of opposite sidewalls 106s1, 106s2 through an etching process, and the pair of opposite sidewalls 106s1, 106s2 respectively include an inclined sidewall segment 106ss overlying the curved sidewall segment 106cs. For example, a dry etching process may form the inclined sidewall segment 106ss, and a blanket etch-back process may form the curved sidewall segment 106cs. In some embodiments, the curved sidewall segment 106cs is defined from a first point 704 (where an edge of the bottom dielectric layer 106 directly contacts the bottom conductive line 104) to a second point 706 (where the second point 706 is below the midpoint of the bottom dielectric layer 106 and above the first point 704 by a non-zero distance). In other embodiments, the slope of the curved surface of the bottom dielectric layer 106 continuously increases while moving along an incremental segment of the curved surface from the first point 704 to the second point 706. The angle α defined between the curved surface and the bottom conductive line 104 may be in the range of about 1 to 60 degrees. In other embodiments, the inclined sidewall segment 106ss is defined from the second point 706 to the third point 708 (defined at the edge of the top surface of the bottom dielectric layer 106). In some embodiments, the inclined sidewall segment 106ss is substantially straight and has an angle Φ from the top surface of the bottom conductive line 104 to the sidewall 106s2 of the bottom dielectric layer 106. The angle Φ may be, for example, in the range of about 30 to 75 degrees. In other embodiments, the sidewall 106s1 has an inclined sidewall segment 106ss that overlies the curved sidewall segment 106cs configured as described above.

[0049] like Figure 8 800, a bottom electrode layer 802 is formed on the bottom dielectric layer 106. A data storage film 804 is formed on the bottom electrode layer 802. A top electrode layer 806 is formed on the data storage film 804. A conductive barrier film 808 is formed on the top electrode layer 806. A top dielectric film 812 is formed on the conductive barrier film 808. A buffer layer 814 is formed on the top dielectric film 812. In some embodiments, the conductive barrier film 808 is a portion of the top electrode layer 806 (so that the top electrode layer 806 includes a top layer directly overlying the bottom layer). The substantially straight horizontal line 820 is aligned with the top surface of the bottom dielectric layer 106.

[0050] In some embodiments, the bottom electrode layer 802 may be, for example, or may include silver, copper, etc. formed to a thickness in the range of approximately 75 angstroms to 300 angstroms. In some embodiments, the data storage film 804 may be, for example, or may include a metal oxide (e.g., hafnium oxide, aluminum oxide, tantalum oxide, etc.) formed to a thickness in the range of approximately 20 angstroms to 100 angstroms. In some embodiments, the top electrode layer 806 may be, for example, or may include silver, titanium, nitride, copper, etc. formed to a thickness in the range of approximately 100 angstroms to 600 angstroms. In some embodiments, the conductive barrier film 808 may be, for example, or may include titanium nitride, nitride, tantalum nitride, etc. formed to a thickness in the range of approximately 25 angstroms to 250 angstroms. In some embodiments, the top dielectric film 812 may be, for example, or may include silicon nitride, silicon carbide, etc. formed to a thickness in the range of approximately 300 angstroms to 1500 angstroms. In yet other embodiments, the top dielectric film 812 may include the same material as the bottom dielectric layer 106. In some embodiments, buffer layer 814 may be, for example, or may include, an oxide (eg, silicon oxide) formed to a thickness in a range of approximately 1000 angstroms to 3000 angstroms.

[0051] like Fig. 9 900, a planarization process is performed until the top surface of the bottom dielectric layer 106 is reached, thereby defining the memory cell 116. The planarization process removes the buffer layer 814 and removes portions of the bottom electrode layer 802, the data storage film 804, the top electrode layer 806, the conductive barrier film 808, and the top dielectric film 812, thereby defining the bottom electrode 108, the data storage layer 110, the top electrode 112, the conductive barrier layer 202, and the dielectric segment 902, respectively. The memory cell 116 includes the bottom electrode 108, the data storage layer 110, the top electrode 112, and the conductive barrier layer 202. In some embodiments, the planarization process includes performing a chemical mechanical planarization (CMP) process along a substantially straight horizontal line 820. In some embodiments, the planarization process includes one or more slurries for non-selective CMP. Therefore, in some embodiments, the memory cell 116 is formed by, for example, a single CMP process to electrically isolate the top electrode 112 and the bottom electrode 108 from each other. In addition, in some embodiments, after the planarization process is performed, a cleaning process (e.g., a wet cleaning process using hydrofluoric acid) is performed. In other embodiments, the cleaning process can remove the conductive material extending over the top electrode 112 and the bottom electrode 108 and the data storage layer 110, thereby increasing the isolation between the top electrode 112 and the bottom electrode 108. In yet other embodiments, the top electrode 112, the data storage layer 110, and the bottom electrode 108, each having a U-shaped profile, mitigates the peeling between the above layers, thereby improving the stability and / or durability of the memory cell 116.

[0052] In some embodiments, after the planarization process and / or the cleaning process are performed, a pullback etch process is performed. In some embodiments, the pullback etch process is performed using a dry etch (e.g., an etchant containing methane (CH4) and / or hydrogen (H2)), and the dry etch is configured to remove a portion of the top electrode 112, the conductive barrier layer 202, and / or the bottom electrode 108 (e.g., see Figure 2B In some other embodiments, the etch-back process is performed using dry etching (eg, an etchant including carbon tetrafluoride (CF4)), wherein the dry etching is configured to remove a portion of the data storage layer 110 (eg, see Figure 3A In some other embodiments, the etch-back process is performed using a wet etch (e.g., including a hydrochloric acid etchant), wherein the wet etch is configured to remove a portion of the top electrode 112, the conductive barrier layer 202, and / or the bottom electrode 108 (e.g., see Figure 2B In other embodiments, the etch-back process is performed using a wet etchant (eg, containing a dihydrofolic acid etchant) configured to remove a portion of the data storage layer 110 (eg, see Figure 3A ).

[0053] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a top dielectric film 1002 is formed over the memory cell 116. In some embodiments, the top dielectric film 1002 may include the same material as the dielectric segment 902 and / or the bottom dielectric layer 106. In other embodiments, the top dielectric film 1002 may be, for example, or may include, a very low dielectric constant dielectric material, an oxide (e.g., silicon oxide), etc., formed to a thickness in the range of approximately 300 angstroms to 1500 angstroms.

[0054] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , an upper interlayer dielectric (ILD) structure 120 is formed on the top dielectric film 1002. In some embodiments, the upper ILD structure 120 may include one or more dielectric materials and / or include one or more dielectric layers. In other embodiments, the upper ILD structure 120 may be, for example, or may include an extremely low dielectric constant dielectric material, an oxide (e.g., silicon oxide), etc. formed to a thickness in the range of approximately 1250 angstroms to 2800 angstroms. A via 122 is formed on the memory cell 116 so that the via 122 electrically couples the conductive barrier layer 202 to the overlying conductive line. An upper conductive line 124 is formed on the via 122.

[0055] In some embodiments, the via 122 is formed by a single damascene process, and then the upper conductive line 124 is formed by a single damascene process. In other embodiments, the single damascene process includes depositing a dielectric layer, patterning the dielectric layer into an opening for obtaining a single-layer conductive feature (e.g., a layer of contact, via or conductive line), and filling the opening with a conductive material to form the single-layer conductive feature. In some embodiments, the via 122 and the upper conductive line 124 may be, for example, or may include copper, aluminum, etc. In yet other embodiments, the via 122, the upper conductive line 124, the top dielectric film 1002, and the upper ILD structure 120 are part of an interconnect structure.

[0056] Fig.12 A method 1200 for forming a memory element according to some embodiments is shown. Although method 1200 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may also be included.

[0057] At act 1202, a bottom dielectric layer is formed over the conductive lines. Figure 6 Cross-sectional view 600 corresponding to some embodiments of act 1202 is shown.

[0058] At act 1204 , a removal process is performed on the bottom dielectric layer to define an opening in the bottom dielectric layer. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1204 is shown.

[0059] At act 1206, a memory layer stack is formed over the conductive line and within the opening. The memory layer stack includes a top electrode overlying the bottom electrode. Figure 8 Cross-sectional view 800 corresponding to some embodiments of act 1206 is shown.

[0060] At act 1208, a planarization process is performed on the memory layer stack to align a top surface of the top electrode with a top surface of the bottom electrode to define a memory cell. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1208 is shown.

[0061] At act 1210, an interconnect structure is formed above the memory cell. Fig.10 and Fig.11Cross-sectional views 1000 and 1100 corresponding to some embodiments of act 1210 are shown.

[0062] Therefore, in some embodiments, the present disclosure relates to a method of forming a memory cell (the memory cell includes a top electrode overlying a bottom electrode) using a planarization process (e.g., a single CMP process) to align a top surface of the top electrode with a top surface of the bottom electrode.

[0063] In some embodiments, the present disclosure relates to a memory element comprising: a bottom electrode; a data storage layer overlying the bottom electrode, wherein the bottom electrode holds the underside of the data storage layer; and a top electrode overlying the data storage layer, wherein a top surface of the bottom electrode is aligned with a top surface of the top electrode.

[0064] In some embodiments, the sidewall of the top electrode includes an inclined segment overlying a curved segment so that the width of the top electrode increases continuously from the bottom surface of the top electrode to the top surface of the top electrode. In some embodiments, the data storage layer includes a conductive bridge region located above the central bottom electrode region, and wherein the conductive bridge region includes a conductive bridge, and the conductive bridge couples the bottom electrode to the top electrode to achieve a first data state. In some embodiments, the bottom electrode extends continuously along the sidewall of the data storage layer and the bottom surface of the data storage layer and directly contacts the sidewall of the data storage layer and the bottom surface of the data storage layer. In some embodiments, the top surface of the top electrode and the top surface of the bottom electrode are lower than the top surface of the data storage layer. In some embodiments, the top surface of the top electrode and the top surface of the bottom electrode are higher than the top surface of the data storage layer. In some embodiments, the top electrode includes an upper layer overlying a bottom layer so that the upper layer includes a first material and the bottom layer includes a second material, the second material is different from the first material, and wherein the bottom electrode includes the second material. In some embodiments, the first material is titanium nitride and the second material is silver. In some embodiments, the memory element further includes a dielectric segment disposed above the top electrode, wherein the top electrode cups an underside of the dielectric segment and has a top surface aligned with a top surface of the dielectric segment.

[0065] In other embodiments, the present disclosure relates to a programmable metallization unit, which includes: a bottom dielectric layer overlying a conductive line; a bottom electrode disposed in the bottom dielectric layer, wherein the bottom electrode is U-shaped and contacts the conductive line; a data storage layer overlying the bottom electrode, wherein the data storage layer is U-shaped so that the upper surface of the bottom electrode extends continuously along the lower surface of the data storage layer; and a top electrode overlying the data storage layer.

[0066] In some embodiments, the top electrode is U-shaped and the upper surface of the data storage layer extends continuously along the lower surface of the top electrode. In some embodiments, the bottom dielectric layer has a sidewall, and the sidewall has an inclined section overlying a curved section so that the sidewall of the bottom electrode directly contacts the inclined section and the curved section. In some embodiments, a dielectric section overlies the top electrode so that the top electrode extends continuously along the lower surface of the dielectric section and directly contacts the lower surface of the dielectric section, and the top surface of the dielectric section is aligned with the top surface of the top electrode. In some embodiments, the dielectric section includes a dielectric material different from that of the bottom dielectric layer. In some embodiments, the top electrode includes a titanium nitride layer, and the titanium nitride layer directly overlies the silver layer. In some embodiments, the bottommost surface of the bottom electrode is recessed to be lower than the topmost surface of the conductive line.

[0067] In other embodiments, the present disclosure relates to a method for manufacturing a memory element. The method includes: forming a bottom dielectric layer above a conductive line; patterning the bottom dielectric layer to form an opening above the conductive line, wherein the opening has a curved sidewall so that the width of the opening increases continuously from the bottom surface of the bottom dielectric layer to the top surface of the bottom dielectric layer; forming a memory layer stack above the conductive line and in the opening, wherein the memory layer stack includes a top electrode overlying a bottom electrode; and performing a planarization process on the memory layer stack to align the top surface of the top electrode with the top surface of the bottom electrode.

[0068] In some embodiments, the storage layer stack includes a central region, the central region overlying the opening and conformally lining the opening so that the storage layer stack includes an outer region, the outer region overlying the top surface of the bottom dielectric layer, wherein the outer region is located vertically above the central region. In some embodiments, the patterning includes performing an etching process and the planarization process includes performing a chemical mechanical planarization process. In some embodiments, the patterning removes a portion of the conductive line so that the storage layer stack extends below the bottom surface of the bottom dielectric layer.

[0069] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A memory element, comprising: A bottom electrode, comprising a central bottom electrode region and a peripheral bottom electrode region, wherein the peripheral bottom electrode region extends upward from the central bottom electrode region; a data storage layer overlying the bottom electrode, wherein the upper surface of the bottom electrode supports the lower side of the data storage layer; A top electrode overlying the data storage layer, wherein the upper surface of the data storage layer supports the lower side of the top electrode and the data storage layer separates the top electrode from the bottom electrode, wherein the top surface of the bottom electrode and the top surface of the top electrode are higher than the top surface of the data storage layer, and wherein the sidewall of the top electrode includes an inclined section at a height located on the curved section. 2 . The memory element of claim 1 , wherein a width of the top electrode increases continuously from a bottom surface of the top electrode to the top surface of the top electrode.

3. The memory element of claim 1, wherein the data storage layer comprises a conductive bridge region over the central bottom electrode region, and wherein the conductive bridge region comprises a conductive bridge that couples the bottom electrode to the top electrode to achieve a first data state. 4 . The memory element according to claim 1 , wherein the bottom electrode continuously extends along and directly contacts sidewalls of the data storage layer and a bottom surface of the data storage layer.

5. The memory element of claim 1 wherein the top electrode comprises an upper layer overlying a bottom layer such that the upper layer comprises a first material and the bottom layer comprises a second material, the second material being different than the first material, and wherein the bottom electrode comprises the second material.

6. The memory element of claim 5, wherein the first material is titanium nitride and the second material is silver.

7. The memory element according to claim 1, further comprising: A dielectric segment is disposed above the top electrode, wherein the top electrode holds the underside of the dielectric segment and has a top surface aligned with a top surface of the dielectric segment.

8. The memory element according to claim 1, further comprising: A via hole overlies the top electrode, wherein a bottom surface of the via hole is located below the top surface of the bottom electrode in a vertical direction.

9. A programmable metallization unit, comprising: a bottom dielectric layer overlying the conductive line, wherein a bottommost surface of the bottom dielectric layer directly contacts a top surface of the conductive line; a bottom electrode disposed within the bottom dielectric layer, wherein the bottom electrode is U-shaped and contacts the conductive line, wherein a bottommost surface of the bottom electrode is disposed at a height lower than the bottommost surface of the bottom dielectric layer; a data storage layer overlying the bottom electrode, wherein the data storage layer is U-shaped so that the upper surface of the bottom electrode extends continuously along the lower surface of the data storage layer; as well as A top electrode overlies the data storage layer, wherein the top electrode is U-shaped and an upper surface of the data storage layer continuously extends along a lower surface of the top electrode.

10. The programmable metallization cell of claim 9, wherein the bottom dielectric layer has a sidewall having an inclined section at a height above the curved section such that the sidewall of the bottom electrode directly contacts the inclined section and the curved section.

11. The programmable metallization cell of claim 9, wherein a dielectric segment overlies the top electrode such that the top electrode extends continuously along a lower surface of the dielectric segment, and wherein a top surface of the dielectric segment is aligned with a top surface of the top electrode.

12. The programmable metallization cell of claim 11, wherein the dielectric segments comprise a different dielectric material than the bottom dielectric layer.

13. The programmable metallization cell of claim 9, wherein the top electrode comprises a titanium nitride layer directly overlying a silver layer.

14. The programmable metallization cell of claim 9, wherein the bottommost surface of the bottom electrode is recessed below the top surface of the conductive line.

15. A method of manufacturing a memory element, comprising: forming a bottom dielectric layer over the conductive lines; patterning the bottom dielectric layer to form an opening over the conductive line, wherein the opening has curved sidewalls such that a width of the opening increases continuously from a bottom surface of the bottom dielectric layer to a top surface of the bottom dielectric layer; forming a memory layer stack above the conductive line and in the opening, wherein the memory layer stack includes a top electrode overlying a bottom electrode and a data storage layer between the top electrode and the bottom electrode; as well as performing a planarization process on the memory layer stack so that a top surface of the top electrode is flush with a top surface of the bottom electrode, wherein a bottommost surface of the bottom electrode is disposed at a height lower than the bottommost surface of the bottom dielectric layer.

16. A method for manufacturing a memory element according to claim 15, wherein the memory layer stack includes a central region, the central region overlying the opening and conformally lining the opening so that the memory layer stack includes an outer region, the outer region overlying the top surface of the bottom dielectric layer, wherein the outer region is located above the central region in a vertical direction. 17 . The method for manufacturing a memory device according to claim 15 , wherein the patterning comprises performing an etching process and the planarization process comprises performing a chemical mechanical planarization process. 18 . The method of manufacturing a memory device according to claim 15 , wherein the patterning removes a portion of the conductive line so that the memory layer stack extends below a bottom surface of the bottom dielectric layer.

19. A programmable metallization unit comprising: a bottom dielectric layer overlying the conductive line, wherein the bottom dielectric layer includes sidewalls defining a trench above the conductive line; a bottom electrode overlying the conductive line, wherein the bottom electrode is disposed within the trench and contacts the sidewall of the bottom dielectric layer, wherein the bottom electrode is U-shaped; a data storage layer overlying the bottom electrode and disposed in the trench, wherein the data storage layer is U-shaped; a top electrode overlying the data storage layer and disposed in the trench, wherein the top electrode is U-shaped and extends continuously along an upper surface of the data storage layer, wherein a top surface of the top electrode is aligned with a top surface of the bottom electrode; as well as a conductive barrier layer overlying the top electrode and disposed within the trench, wherein the conductive barrier layer is U-shaped, wherein a top surface of the conductive barrier layer is aligned with the top surface of the top electrode, The bottommost surface of the bottom electrode is vertically offset from the bottommost surface of the bottom dielectric layer by a non-zero distance in a direction away from the data storage layer.

20. The programmable metallization cell of claim 19, wherein the top electrode comprises a first material and the conductive barrier layer comprises a second material, the second material being different from the first material.

21. The programmable metallization cell of claim 19, further comprising: A via hole is overlying the conductive barrier layer, wherein a bottom surface of the via hole extends below the top surface of the top electrode to contact an upper surface of the conductive barrier layer.

22. The programmable metallization cell of claim 19, wherein the top surface of the top electrode is aligned with a top surface of the bottom dielectric layer.

23. The programmable metallization cell of claim 19, wherein a bottom surface of the bottom electrode is disposed vertically below a bottom surface of the bottom dielectric layer.

24. The programmable metallization cell of claim 19, wherein the bottom electrode, the data storage layer, the top electrode, and the conductive barrier layer each comprise a sidewall having an inclined sidewall segment at a height above a curved sidewall segment.

Images