Semiconductor Package

Abstract

The present invention provides a semiconductor package, which includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes: a first frame having a first through portion; a first semiconductor chip located in the first through portion and having a first surface on which a first connecting pad is arranged, a second surface on which a second connecting pad is arranged, and a through via connected to the second connecting pad; a first connection structure located on the first surface and including a first redistribution layer; and a backside redistribution layer located on the second surface, the second semiconductor package is located on the first semiconductor package and includes: a second connection structure including a second redistribution layer; a second frame located on the second connection structure and having a second through portion; and a second semiconductor chip located in the second through portion and having a third surface on which a third connecting pad is arranged.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0055468 filed on May 13, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package, for example, to a fan-out semiconductor package. Background Art

[0003] With the development of intelligent electronic devices in recent years, the specifications of components used in intelligent electronic devices have also been improved. For example, the specifications of application processors (APs), which are key components of intelligent electronic devices, have been rapidly improved. Various methods have been used to improve the performance of APs, and functional partitioning of APs is a recent method. For example, when the semiconductor chip of an AP is partitioned for each function, and then each semiconductor chip is designed and packaged to be optimized for its process and features, the AP can achieve higher performance than a traditional single AP. However, in this case, a high-level packaging method is required. Therefore, there is a need for a semiconductor packaging structure that can package multiple partitioned semiconductor chips to have optimal signal characteristics and power characteristics. Summary of the invention

[0004] An aspect of the present disclosure may provide a novel semiconductor package having a structure in which a plurality of semiconductor chips may be packaged to have optimal signal characteristics and power characteristics.

[0005] According to one aspect of the present disclosure, a semiconductor package having the following structure may be provided: a plurality of semiconductor chips may be arranged after being divided into an upper package and a lower package based on their specifications, and then the semiconductor chip of the lower package transmits power to the semiconductor chip of the upper package through a through via penetrating the semiconductor chip of the lower package.

[0006] According to one aspect of the present disclosure, a semiconductor package may include a first semiconductor package and a second semiconductor package, the first semiconductor package including: a first frame having a first through portion; a first semiconductor chip arranged in the first through portion of the first frame and having a first surface, a second surface and a through via, a first connection pad being arranged on the first surface, the second surface being opposite to the first surface and having a second connection pad being arranged on the second surface, and the through via being connected to the second connection pad; a first connection structure being arranged on the first surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pad of the first semiconductor chip; and a backside redistribution layer being arranged on the second surface of the first semiconductor chip and electrically connected to the second connection pad of the first semiconductor chip, the second semiconductor package being arranged on the first semiconductor package and including: a second connection structure including a second redistribution layer electrically connected to the first redistribution layer; a second frame being arranged on the second connection structure and having a second through portion; and a second semiconductor chip being arranged in the second through portion of the second frame and having a third surface, a third connection pad being arranged on the third surface, the third connection pad being electrically connected to the second redistribution layer.

[0007] According to another aspect of the present disclosure, a semiconductor package may include a first semiconductor package and a second semiconductor package, the first semiconductor package including: a first frame having a first through portion; a first semiconductor chip disposed in the first through portion of the first frame and having a first surface, a second surface and a through via, a first connection pad being disposed on the first surface, the second surface being opposite to the first surface and having a second connection pad being disposed on the second surface, and the through via being connected to the second connection pad; a first connection structure disposed on the first surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pad of the first semiconductor chip; and a backside redistribution layer disposed on the second surface of the first semiconductor chip and electrically connected to the second connection pad of the first semiconductor chip, the second semiconductor package being disposed on the first semiconductor package and including a second semiconductor chip, the second semiconductor chip having a third surface, a third connection pad being disposed on the third surface electrically connected to the first redistribution layer, wherein the first semiconductor chip includes a first semiconductor element having a first critical size, and the second semiconductor chip includes a second semiconductor element having a second critical size smaller than the first critical size. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0010] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0011] Figure 3A and Figure 3B is a schematic cross-sectional view showing states of a fan-in type semiconductor package before and after being packaged;

[0012] Figure 4 shows a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package;

[0013] Figure 5 is a schematic cross-sectional view showing a state where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device;

[0014] Figure 6 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device;

[0015] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package;

[0016] Figure 8 is a schematic cross-sectional view showing a state where a fan-out type semiconductor package is mounted on a main board of an electronic device;

[0017] Fig. 9 is a schematic cross-sectional view showing an example of a semiconductor package;

[0018] Fig. 10A and Fig. 10B It is along Fig. 9 A schematic plan view of a fan-out semiconductor package taken along line II′ and line II-II′;

[0019] Fig.11 is a schematic cross-sectional view showing another example of a semiconductor package;

[0020] Fig.12 is a schematic cross-sectional view showing another example of a semiconductor package;

[0021] Fig.13 is a schematic cross-sectional view showing another example of a semiconductor package;

[0022] Fig.14is a schematic cross-sectional view showing another example of a semiconductor package;

[0023] Fig.15 is a schematic cross-sectional view showing another example of a semiconductor package; and

[0024] Fig.16 is a schematic cross-sectional view showing another example of a semiconductor package. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the shapes, sizes, etc. of components may be exaggerated or reduced for clarity.

[0026] Here, "lower side", "lower part", "lower surface" and the like related to the cross section of the drawings are used to indicate a direction toward the mounting surface of the fan-out type semiconductor package, and "upper side", "upper part", "upper surface" and the like are used to indicate the opposite direction. However, these directions are defined for convenience of explanation, and the claims are not specifically limited to the directions defined as described above.

[0027] The meaning of a component "connected" to another component in the specification conceptually includes an indirect connection between two components through an adhesive layer and a direct connection between two components. In addition, "electrical connection" conceptually includes physical connection and physical disconnection. It will be understood that when referring to an element with terms such as "first" and "second", the element will not be limited thereby. They may only be used for the purpose of distinguishing the element from other elements, and may not limit the order or importance of the elements. In some cases, without departing from the scope of the claims set forth herein, the first element may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0028] The term "embodiment" as used herein does not refer to the same embodiment, and is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another embodiment. However, the embodiments provided herein are considered to be able to be implemented by combining with each other as a whole or in part with each other. For example, unless a contrary or opposing description is provided therein, an element described in a particular embodiment may be understood as a description related to another embodiment even if it is not described in another embodiment.

[0029] The terms used herein are only used to describe the embodiments and are not intended to limit the present disclosure. In this case, unless the context otherwise explains, the singular form includes the plural form.

[0030] Electronic Devices

[0031] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0032] Reference Figure 1 , the electronic device 1000 may contain a mainboard 1010 therein. In the mainboard 1010, chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to each other. These components may be connected to other components to be described below via various signal lines 1090.

[0033] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0034] The network-related components 1030 may include components designated to operate according to protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols designated after the above protocols. However, the network-related component 1030 is not limited thereto and may also include components designated to operate according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0035] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0036] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the main board 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited thereto, and other components for various purposes may also be included according to the type of the electronic device 1000, etc.

[0037] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0038] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0039] Reference Figure 2 , semiconductor packages can be used for various purposes in various electronic devices as described above. For example, a printed circuit board 1110 can be housed in a body 1101 of a smart phone 1100, and various electronic components 1120 can be physically and / or electrically connected to the printed circuit board 1110. In addition, other components (such as a camera module 1130) that may or may not be physically and / or electrically connected to the printed circuit board 1110 can be housed in the body 1101. A portion of the electronic components 1120 may be chip-related components (e.g., semiconductor packages 1121), and are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, and may be one of the other electronic devices as described above.

[0040] Semiconductor Package

[0041] Generally, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product and may be damaged by external physical impact or chemical impact. Therefore, the semiconductor chip itself may not be used but is packaged and used in an electronic device or the like in a packaged state.

[0042] The reason why semiconductor packaging is needed is that there is a difference in circuit width between a semiconductor chip and a mainboard of an electronic device in terms of electrical connection. In detail, the size of the connection pads of a semiconductor chip and the spacing between the connection pads of the semiconductor chip are very fine, while the size of the component mounting pads of a mainboard and the spacing between the component mounting pads of the mainboard used in an electronic device are significantly larger than the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip. Therefore, it is difficult to directly mount a semiconductor chip on a mainboard, and thus a packaging technology for alleviating this difference in circuit width between a semiconductor chip and a mainboard is needed.

[0043] Semiconductor packages manufactured by this packaging technology may be divided into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.

[0044] Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package are described in more detail with reference to the accompanying drawings.

[0045] Fan-in semiconductor package

[0046] Figure 3A and Figure 3B is a schematic cross-sectional view showing states of a fan-in type semiconductor package before and after being packaged, and Figure 4 A schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package is shown.

[0047] Reference FIG. 3A to FIG. 4 , the semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc.; a connection pad 2222 formed on one surface of the body 2221 and formed using a conductive material such as aluminum (Al), etc.; and a passivation layer 2223 such as an oxide film, a nitride film, etc., formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222. In this case, since the connection pad 2222 may be very small, it may be difficult to mount the integrated circuit (IC) on a printed circuit board (PCB) of a medium size class and a main board of an electronic device, etc.

[0048] Therefore, according to the size of the semiconductor chip 2220, a connection structure 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222. The connection structure 2240 may be formed by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) material, forming a via hole 2243h that opens the connection pads 2222, and then forming a wiring pattern 2242 and a via 2243. Thereafter, a passivation layer 2250, an opening 2251, and an under-bump metallization layer 2260 that protect the connection structure 2240 may be formed. That is, a fan-in semiconductor package 2200 including, for example, a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an under-bump metallization layer 2260 may be manufactured by a series of processes.

[0049] As described above, the fan-in semiconductor package may have a package form in which all the connection pads (e.g., input / output (I / O) terminals) of the semiconductor chip are arranged inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components installed in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to each achieve fast signal transmission while having a small size.

[0050] However, in a fan-in semiconductor package, since all the I / O terminals need to be arranged inside the semiconductor chip, the fan-in semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor chip with a large number of I / O terminals or a semiconductor chip with a small size. In addition, due to the above-mentioned shortcomings, it may not be possible to directly install and use the fan-in semiconductor package on the mainboard of an electronic device. The reason is that even when the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip are increased by a redistribution process, the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip may still be insufficient to directly install the fan-in semiconductor package on the mainboard of the electronic device.

[0051] Figure 5 is a schematic cross-sectional view showing a state where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device, and Figure 6 is a schematic cross-sectional view showing a state in which a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

[0052] Reference Figure 5In the fan-in semiconductor package 2200, the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 may be redistributed again through the interposer substrate 2301, and the fan-in semiconductor package 2200 may be mounted on the interposer substrate 2301. In this manner, the fan-in semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like may be fixed by the bottom filling resin 2280 and the like, and the outside of the semiconductor chip 2220 may be covered with the molding material 2290 and the like. Optionally, referring to Figure 6 , the fan-in type semiconductor package 2200 may be embedded in a separate interposer substrate 2302. In a state where the fan-in type semiconductor package 2200 is embedded in the separate interposer substrate 2302, the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 may be redistributed again through the interposer substrate 2302. In this manner, the fan-in type semiconductor package 2200 may be finally mounted on a main board 2500 of an electronic device.

[0053] As described above, it may be difficult to directly mount and use a fan-in type semiconductor package on a main board of an electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate interposer substrate and then mounted on the main board of the electronic device through a packaging process, or the fan-in type semiconductor package may be mounted and used on the main board of the electronic device in a state where the fan-in type semiconductor package is embedded in the interposer substrate.

[0054] Fan-out semiconductor packages

[0055] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

[0056] Reference Figure 7 In the fan-out type semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 may be protected by the encapsulant 2130, and the connection pads 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 through the connection structure 2140. In this case, a passivation layer 2150 may also be formed on the connection structure 2140, and an under bump metallization layer 2160 may also be formed in the opening of the passivation layer 2150. A solder ball 2170 may also be formed on the under bump metallization layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection structure 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a via 2143 to electrically connect the connection pad 2122 and the redistribution layer 2142 to each other.

[0057] As described above, the fan-out type semiconductor package may have a form in which the I / O terminals of the semiconductor chip are redistributed and arranged outside the semiconductor chip through a connection structure formed on the semiconductor chip. As described above, in the fan-in type semiconductor package, all the I / O terminals of the semiconductor chip need to be arranged inside the semiconductor chip. Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the ball need to be reduced, so that a standardized ball layout may not be used in the fan-in type semiconductor package. However, as described above, the fan-out type semiconductor package has a form in which the I / O terminals of the semiconductor chip are redistributed and arranged outside the semiconductor chip through a connection structure formed on the semiconductor chip. Therefore, even when the size of the semiconductor chip is reduced, the standardized ball layout can still be used as it is in the fan-out type semiconductor package, so that the fan-out type semiconductor package can be installed on the mainboard of the electronic device without using a separate printed circuit board or an intermediate substrate, as described below.

[0058] Figure 8 is a schematic cross-sectional view showing a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

[0059] Reference Figure 8 , the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device through the solder balls 2170 and the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection structure 2140 formed on the semiconductor chip 2120 and capable of redistributing the connection pads 2122 to the fan-out area outside the size of the semiconductor chip 2120, so that the standardized ball layout can be used as it is in the fan-out type semiconductor package 2100. As a result, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer substrate and the like.

[0060] As described above, since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the fan-out semiconductor package can be implemented in a thickness smaller than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, so the fan-out semiconductor package is particularly suitable for mobile products. In addition, the fan-out semiconductor package can be implemented in a more compact form than the ordinary package on package (POP) type using a printed circuit board (PCB), and the problem caused by the occurrence of the warping phenomenon can be solved.

[0061] In addition, the fan-out semiconductor package refers to a packaging technology for mounting a semiconductor chip on a mainboard of an electronic device, etc. and protecting the semiconductor chip from external impact as described above, and therefore the fan-out semiconductor package is a concept different from the concept of a printed circuit board (PCB) (such as an intermediate substrate having a size, use, etc. different from that of a fan-out semiconductor package and having a fan-in semiconductor package embedded therein).

[0062] Hereinafter, a semiconductor package having a structure in which a plurality of semiconductor chips can be packaged to have optimal signal characteristics and power characteristics will be described with reference to the accompanying drawings.

[0063] Fig. 9 is a schematic cross-sectional view showing an example of a semiconductor package, and Fig. 10A and Fig. 10B It is along Fig. 9 Schematic plan view of a fan-out semiconductor package taken along lines II' and II-II'.

[0064] Reference Figures 9 to 10BThe semiconductor package 100A has a package-on-package (POP) structure and includes a first semiconductor package P1 and a second semiconductor package P2 stacked in a vertical direction, wherein the second semiconductor package P2 is stacked on the first semiconductor package P1. The first semiconductor package P1 may include: a first frame 110 having a first through portion 110H; a first semiconductor chip 120, which is arranged in the first through portion 110H of the first frame 110 and has a first connecting pad 122 arranged on a first surface and a second connecting pad 123 arranged on a second surface opposite to the first surface; a first encapsulant 130, encapsulating at least a portion of the first frame 110 and at least a portion of the first semiconductor chip 120; a first connection structure 140, which is arranged on the first surface of the first frame 110 and the first semiconductor chip 120, and includes a first redistribution layer 142; a backside redistribution layer 132, which is arranged on the lower surface of the first encapsulant 130; a first passivation layer 150 and a second passivation layer 159, which are respectively arranged on the upper surface of the first connection structure 140 and on the lower surface of the backside redistribution layer 132; and a plurality of electrical connection metal parts 193, which are respectively arranged in a plurality of openings of the second passivation layer 159. The second semiconductor package P2 may include: a second connection structure 160, including a second redistribution layer 162; a second frame 170, arranged on the second connection structure 160 and having a second through-portion 170H; a second semiconductor chip 180, arranged in the second through-portion 170H of the second frame 170 and having a third connection pad 182 arranged on an effective surface of the second semiconductor chip 180; a second encapsulant 191, encapsulating at least a portion of the second frame 170 and at least a portion of the second semiconductor chip 180; a third passivation layer 155, arranged on the lower surface of the second connection structure 160; a plurality of connection terminals 195, respectively arranged in a plurality of openings of the third passivation layer 155; and a bottom filling layer 197, filling each space between the plurality of connection terminals 195.

[0065] The first semiconductor chip 120 may include a body 121, a first connection pad 122, a second connection pad 123, and a through-hole 125. The effective surface of the first semiconductor chip 120 may be a first surface on which the first connection pad 122 is disposed, and the ineffective surface of the first semiconductor chip 120 may be a second surface opposite to the first surface and on which the second connection pad 123 is disposed. However, the first semiconductor chip is not limited thereto. Specifically, the second connection pad 123 may be disposed on the second surface of the first semiconductor chip 120 in the form of a protrusion, and is not limited thereto. The through-hole 125 may be connected to the second connection pad 123 and extend from the second connection pad 123 to the effective surface of the first semiconductor chip 120 or a region adjacent to the effective surface of the first semiconductor chip 120 by penetrating at least a portion of the first semiconductor chip 120. For example, the through-hole 125 may extend to penetrate the entire first semiconductor chip 120, or extend from the second connection pad 123 to penetrate at least a portion of an effective layer disposed in contact with the effective surface of the first semiconductor chip 120 and having a semiconductor element disposed thereon. The through via 125 may be electrically connected to the semiconductor element inside the first semiconductor chip 120 .

[0066] In the first semiconductor chip 120, the first connection pad 122 may be electrically connected to the first redistribution layer 142 located above the first semiconductor chip 120. The through via 125 may be electrically connected to the backside redistribution layer 132 below the first semiconductor chip 120 through the second connection pad 123. Specifically, the first connection pad 122 may be connected to the signal pattern of the first redistribution layer 142, and the second connection pad 123 and the through via 125 may be connected to the power pattern and / or ground pattern of the backside redistribution layer 132. That is, in the first semiconductor chip 120, signals such as data signals may be transmitted and received through the first connection pad 122, and power may be supplied through the through via 125. In a plan view, the second connection pad 123 and the through via 125 may be disposed in a central region of the first semiconductor chip 120, and the first connection pad 122 may be disposed in an edge region surrounding the central region of the first semiconductor chip 120. However, the first semiconductor chip 120 is not limited thereto.

[0067] In addition, a functional partitioning method of an application processor (AP), a key component of an intelligent electronic device, has recently been used to achieve advanced performance of the AP. For example, when a semiconductor chip of the AP is partitioned for each function and then each semiconductor chip is designed and packaged to be optimized for its process and features, the AP can achieve advanced performance than a conventional single AP.

[0068] Therefore, in the semiconductor package 100A according to the embodiment, the first semiconductor chip 120 and the second semiconductor chip 180 that can perform different functions can be arranged so that: the first connection pad 122 and the third connection pad 182 face each other with the first connection structure 140 and the second connection structure 160 interposed therebetween. The first semiconductor chip 120 can be arranged below the first connection structure 140 so that the effective surface of the first semiconductor chip 120 on which the first connection pad 122 is arranged faces the lower surface of the first connection structure 140. The second semiconductor chip 180 can be arranged on the upper surface of the second connection structure 160 so that the effective surface of the second semiconductor chip 180 on which the third connection pad 182 is arranged faces the upper surface of the second connection structure 160. In a plan view, the second semiconductor chip 180 can be arranged so that at least a portion of the second semiconductor chip 180 overlaps with the first semiconductor chip 120 in a vertical direction. Each of the first semiconductor chip 120 and the second semiconductor chip 180 can be a chip having a partitioning function of the application processor AP. That is, the first semiconductor chip 120 and

[0069] The second semiconductor chips 180 may each implement a portion or all of the functions of an application processor, and are not limited thereto.

[0070] Specifically, Fig. 10A and Fig. 10B As shown, the first semiconductor chip 120 and the second semiconductor chip 180 may have a plurality of first regions FR1, FR2, FR3 and FR4 and a plurality of second regions SR1, SR2, SR3 and SR4; the two regions perform different functions respectively. The via region in which the through via 125 is arranged may also be arranged between the plurality of first regions FR1, FR2, FR3 and FR4 of the first semiconductor chip 120. Relatively more advanced functions may be performed in the plurality of second regions SR1, SR2, SR3 and SR4 of the second semiconductor chip 180 than in the plurality of first regions FR1, FR2, FR3 and FR4 of the first semiconductor chip 120. For example, the plurality of first regions FR1, FR2, FR3 and FR4 of the first semiconductor chip 120 may be logic regions for performing arithmetic functions of an application processor, and the plurality of second regions SR1, SR2, SR3 and SR4 of the second semiconductor chip 180 may be regions for performing power-related functions of an application processor. Optionally, in another embodiment, the second semiconductor chip 180 may be an application processor (AP) chip, and the first semiconductor chip 120 may be a power management integrated circuit (PMIC) chip. In the second semiconductor chip 180 and the first semiconductor chip 120, multiple first regions FR1, FR2, FR3 and FR4 and multiple second regions SR1, SR2, SR3 and SR4 may respectively perform corresponding functions.

[0071] In addition, the second semiconductor elements arranged in the plurality of second regions SR1, SR2, SR3 and SR4 of the second semiconductor chip 180 may have a relatively smaller size than the first semiconductor elements arranged in the plurality of first regions FR1, FR2, FR3 and FR4 of the first semiconductor chip 120. The size of the semiconductor element may refer to a characteristic size, specifically a value expressed as a critical size. When the semiconductor element is a transistor, the critical size may refer to, for example, the minimum length of the transistor channel and / or the minimum length of the gate electrode. Therefore, the first semiconductor element may have a first critical size, and the second semiconductor element may have a second critical size that is smaller than the first critical size. For example, the first critical size may be in the range of 0.05mm to 10mm, and the second critical size may be in the range of 1nm to 100nm. In this way, the first semiconductor chip 120 and the second semiconductor chip 180 with different specifications may be divided into different semiconductor packages P1 and P2, and then stacked vertically; therefore, each manufacturing process of the semiconductor chip and the semiconductor package can be optimized and streamlined, thereby reducing manufacturing costs.

[0072] In this case, a portion of the first connection pad 122 of the first semiconductor chip 120 may be electrically connected to a portion of the third connection pad 182 through a signal pattern in a region where the first semiconductor chip 120 and the second semiconductor chip 180 overlap each other in the vertical direction. Therefore, the signal pattern may be connected between the first semiconductor chip 120 and the second semiconductor chip 180 in the vertical direction. In addition, at least a portion of the second connection pad 123 of the first semiconductor chip 120 may be electrically connected to a power pattern and / or a ground pattern of a backside redistribution layer 132 disposed below the first semiconductor chip 120, may be electrically connected to a power pattern and / or a ground pattern of a first redistribution layer 142 of a first connection structure 140 located above the first semiconductor chip 120 through a through via 125, and may be electrically connected to a portion of the third connection pad 182. Therefore, the first semiconductor chip 120 and the second semiconductor chip 180 may be connected to each other at the shortest distance, thereby optimizing signal characteristics; and the first semiconductor chip 120 and the second semiconductor chip 180 may be connected to the electrical connection metal member 193 at the shortest distance through the through via 125, thereby also optimizing power characteristics.

[0073] Hereinafter, respective components included in the semiconductor package 100A according to an embodiment are described below in more detail.

[0074] The first frame 110 may have a first through portion 110H in the form of a through hole, and the first semiconductor chip 120 may be disposed in the first through portion 110H so that the surface on which the first connection pad 122 is disposed faces the lower surface of the first connection structure 140. The first frame 110 may be used as a supporting member. Here, the first connection pad 122 may be connected to the first connection via 143 of the first connection structure 140 without using a separate bump. In addition, the first frame 110 may include a first insulating layer 111a, and the first insulating layer 111a is in contact with the lower surface of the first connection structure 140.

[0075] The first wiring layer 112a may be recessed in the first insulating layer 111a. That is, the surface of the first insulating layer 111a in contact with the lower surface of the first connection structure 140 may have a step difference with the surface of the first wiring layer 112a in contact with the lower surface of the first connection structure 140. In this case, when the first semiconductor chip 120 and the first frame 110 are encapsulated by the first encapsulant 130, it is possible to prevent the encapsulant material from seeping out and contaminating the first wiring layer 112a. The thickness of each of the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be greater than the thickness of the first redistribution layer 142.

[0076] When forming a hole for forming the first wiring via layer 113a, part of the pads of the first wiring layer 112a can be used as a barrier, so it may be advantageous in the process to make each connection via of the first wiring via layer 113a have a tapered shape with a width of the upper surface less than the width of the lower surface. In this case, the wiring vias of the first wiring via layer 113a can be integrated with the pad pattern of the second wiring layer 112b. Similarly, when forming a hole for forming the second wiring via layer 113b, part of the pads of the second wiring layer 112b can be used as a barrier, so it may be advantageous in the process to make the wiring vias of the second via layer 113b have a tapered shape with a width of the upper surface less than the width of the lower surface. In this case, the wiring vias of the second via layer 113b can be integrated with the pad pattern of the third wiring layer 112c.

[0077] The first insulating layer 111a and the second insulating layer 111b may be formed using an insulating material. Here, the insulating material may be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), or an insulating material (such as a prepreg, ABF (Ajinomoto Build up Film), FR-4 (Frankel's function regulator-4), bismaleimide triazine (BT), etc.) impregnated with a thermosetting resin or a thermoplastic resin in an inorganic filler and / or a core material (such as glass fiber (or glass cloth or glass fabric)).

[0078] The first wiring layer 112a, the second wiring layer 112b and the third wiring layer 112c can be used to redistribute the first connection pad 122 of the first semiconductor chip 120, thereby providing a pad pattern for the wiring via layers 113a and 113b for connecting the upper and lower parts of the semiconductor package 100A to each other. The first wiring layer 112a, the second wiring layer 112b and the third wiring layer 112c can be formed using metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. The first wiring layer 112a, the second wiring layer 112b and the third wiring layer 112c can perform various functions according to the design of the corresponding layer. For example, the first wiring layer 112a, the second wiring layer 112b and the third wiring layer 112c can all include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern may be one of various signal patterns (eg, a data signal pattern, etc.) except for a ground (GND) pattern and a power (PWR) pattern related to power, etc.

[0079] The first wiring via layer 113a and the second wiring via layer 113b can electrically connect the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c formed on different layers to each other, thereby forming an electrical connection path in the first frame 110. In addition, the first wiring via layer 113a and the second wiring via layer 113b can form an electrical connection path between the first connection structure 140 and the electrical connection metal member 193. The first wiring via layer 113a and the second wiring via layer 113b can each be formed using a metal material. The first wiring via layer 113a and the second wiring via layer 113b can each be a filled via completely filled with a metal material, or a conformal via formed by a metal material along the wall of the via hole. In addition, the first wiring via layer 113a and the second wiring via layer 113b can each have a tapered shape. In addition, the first and second wiring via layers 113a and 113b may be integrated with at least a portion of the first wiring layer 112a, at least a portion of the second wiring layer 112b, and at least a portion of the third wiring layer 112c, without being limited thereto.

[0080] The second frame 170 may have a second through-portion 170H in the form of a through hole, and the second semiconductor chip 180 may be disposed in the second through-portion 170H so that the surface on which the third connection pad 182 is disposed faces the upper surface of the second connection structure 160. Here, the third connection pad 182 may be connected to the second connection via 163 of the second connection structure 160 without using a separate bump. Unlike the first frame 110, the second frame 170 may not include a wiring layer or a wiring via layer. However, the second frame 170 is not limited thereto.

[0081] The first semiconductor chip 120 and the second semiconductor chip 180 can each be an integrated circuit (IC) in which hundreds to millions or more components are integrated into a single chip. As a non-limiting example, the first semiconductor chip 120 and the second semiconductor chip 180 can be combined to form a single complete application processor (AP). In this case, each of the first semiconductor chip 120 and the second semiconductor chip 180 can be a chip with a partition function of an application processor (AP) (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor and / or a microcontroller, etc.); or it can be a partition chip with different functions that are not described. However, the first semiconductor chip 120 and the second semiconductor chip 180 are not limited thereto, and at least one of the first semiconductor chip 120 and the second semiconductor chip 180 can be a volatile memory (dynamic random access memory (DRAM)), a non-volatile memory (read-only memory (ROM)), a flash memory, etc. The first semiconductor chip 120 and the second semiconductor chip 180 can have different specifications, such as the functions and sizes described above, and the second semiconductor chip 180 can be a chip that is more advanced than the first semiconductor chip 120. In addition, the second semiconductor chip 180 may have a larger size than the first semiconductor chip 120 , and is not limited thereto.

[0082] The first semiconductor chip 120 and the second semiconductor chip 180 may be formed on the basis of an effective wafer; in this case, the base material of the main body 121 and the base material of the main body 181 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various semiconductor elements and circuits may be formed on the main bodies 121 and 181. The first connection pad 122, the second connection pad 123, the third connection pad 182, and the through-hole 125 may electrically connect the first semiconductor chip 120 and the second semiconductor chip 180 to other components. The first connection pad 122, the second connection pad 123, the third connection pad 182, and the through-hole 125 may be formed using conductive materials such as aluminum (Al), copper (Cu), etc., without any specific restrictions. A passivation film may also be formed on the main bodies 121 and 181 to expose the first connection pad 122, the second connection pad 123, and the third connection pad 182; in this case, the passivation film may be an oxide film, a nitride film, etc., or may be a double layer formed using an oxide film and a nitride film. The first semiconductor chip 120 and the second semiconductor chip 180 may be bare chips; however, if necessary, the first semiconductor chip 120 and the second semiconductor chip 180 may be packaged chips in which a separate redistribution layer is further formed on a surface (i.e., an effective surface) where the first connection pads 122 and the third connection pads 182 are respectively provided.

[0083] The first encapsulant 130 and the second encapsulant 191 may respectively protect the first frame 110 and the second frame 170 and the first semiconductor chip 120 and the second semiconductor chip 180, etc. There is no specific limitation on the encapsulation method of the first encapsulant 130 and the second encapsulant 191. For example, the first encapsulant 130 may cover the surface of the first frame 110 and the first semiconductor chip 120 on which the second connection pad 123 is disposed, and may fill at least a portion of the first through portion 110H. The second encapsulant 191 may cover the upper surface of the second frame 170 and the second semiconductor chip 180 opposite to the surface of the second semiconductor chip 180 on which the third connection pad 182 is disposed, and may fill at least a portion of the second through portion 170H. Since the first encapsulant 130 and the second encapsulant 191 may fill the first through portion 110H and the second through portion 170H, the adhesive function may be performed according to the specific material and buckling may also be reduced.

[0084] The materials of the first encapsulant 130 and the second encapsulant 191 may not be specifically limited. For example, the materials of the first encapsulant 130 and the second encapsulant 191 may be insulating materials; in this case, the insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide resin), a thermosetting resin or a thermoplastic resin mixed with an inorganic filler or a resin impregnated with an inorganic filler in a core material (such as glass fiber (or glass cloth or glass fabric)) (for example, prepreg, ABF (Ajinomoto Build up Film), FR-4 (Frankel's function regulator-4), bismaleimide triazine (BT), etc.). If necessary, a photosensitive encapsulant (PIE, photoimagableencapsulant) resin may also be used.

[0085] The first connection structure 140 may redistribute the first connection pads 122 of the first semiconductor chip 120. In addition, the first connection structure 140 may electrically connect the first connection pads 122 to the wiring layers 112a, 112b, and 112c of the first frame 110, respectively, according to the function. The second connection structure 160 may redistribute the third connection pads 182 of the second semiconductor chip 180. In addition, the first connection structure 140 and the second connection structure 160 may be electrically connected to each other and the first connection pads 122 may be electrically connected to the third connection pads 182. Tens to millions of first connection pads 122 and third connection pads 182 having various functions may be redistributed through the first connection structure 140 and the second connection structure 160, and may be physically connected and / or electrically connected to the outside through the electrical connection metal member 193 according to the function. The first connection structure 140 may include an insulating layer 141, a first redistribution layer 142 disposed on the insulating layer 141, and a first connection via 143 penetrating the insulating layer 141, and the second connection structure 160 may include an insulating layer 161, a second redistribution layer 162 disposed on the insulating layer 161, and a second connection via 163 penetrating the insulating layer 161. The insulating layer 141 of the first connection structure 140 and the insulating layer 161 of the second connection structure 160, the first redistribution layer 142 and the second redistribution layer 162, and the first connection via 143 and the second connection via 163 may each be formed to have a number of layers greater or less than that shown in the drawings.

[0086] The insulating layers 141 and 161 may each be formed using an insulating material. Here, as the insulating material, in addition to the insulating material described above, a photosensitive insulating material such as a photosensitive dielectric (PID) resin may also be used. That is, each of the insulating layers 141 and 161 may be a photosensitive insulating layer. When the insulating layers 141 and 161 have photosensitive properties, the insulating layers 141 and 161 may be formed to have a smaller thickness, and the fine pitch of the first connection via 143 and the second connection via 163 may be more easily realized. The insulating layers 141 and 161 may be photosensitive insulating layers formed using an insulating resin and an inorganic filler, respectively. When the insulating layers 141 and 161 each have a multilayer structure, the materials of the insulating layers 141 and 161 may be the same as each other, or may be different from each other when necessary. When the insulating layers 141 and 161 each have a multilayer structure, the insulating layers 141 may be integrated with each other according to the process so that the boundary between them may not be obvious, and the insulating layers 161 may be integrated with each other according to the process so that the boundary between them may not be obvious. However, the insulating layers 141 and 161 are not limited thereto.

[0087] The first redistribution layer 142 may substantially redistribute the first connection pad 122, and the second redistribution layer 162 may substantially redistribute the third connection pad 182, and may provide an electrical connection path as described above. The redistribution layers 142 and 162 may each be formed using a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first redistribution layer 142 and the second redistribution layer 162 may each perform various functions according to the design of the corresponding layer. For example, each of the redistribution layers 142 and 162 may include a ground pattern, a power pattern, a signal pattern, and the like. The signal pattern may be one of various signal patterns (e.g., a data signal pattern, etc.) other than a ground pattern, a power pattern, and the like. Here, a pattern is a concept including wiring and a pad. The first and second redistribution layers 142 and 162 may mainly include power patterns and / or ground patterns in a region where the first and second redistribution layers 142 and 162 overlap with the through vias 125 of the first semiconductor chip 120. The first and second redistribution layers 142 and 162 may mainly include signal patterns in a region where the first and second semiconductor chips 120 and 180 overlap with each other and are located near the through vias 125.

[0088] The first connection via 143 may be connected to the first redistribution layer 142, the first connection pad 122, the through via 125, and the uppermost first wiring layer 112a, and thus the first redistribution layer 142, the first connection pad 122, the through via 125, the wiring layers 112a, 112b, and 112c, etc., which are respectively formed on different layers, may be connected to each other. As a result, the first connection via 143 may form an electrical connection path in the first connection structure 140. The second connection via 163 may electrically connect the second redistribution layer 162, the third connection pad 182, etc., which are formed on different layers, to each other. As a result, the second connection via 163 may form an electrical connection path in the second connection structure 160. The first connection via 143 and the second connection via 163 may each be formed using a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first connection via 143 and the second connection via 163 may each be a filled via filled with a metal material or a conformal via formed by a metal material along the wall of the via hole. The first connection via 143 and the second connection via 163 may each have a tapered cross-sectional shape. The first connection via 143 and the second connection via 163 may have tapered directions opposite to each other, and the tapered direction of the first connection via 143 may be opposite to the tapered direction of the wiring via layers 113a and 113b of the first frame 110.

[0089] A backside redistribution layer 132 and a backside connection via 133 may be disposed under the first encapsulant 130. The backside connection via 133 may penetrate at least a portion of the first encapsulant 130, thereby electrically connecting the third wiring layer 112c and the backside redistribution layer 132 to each other.

[0090] The back side redistribution layer 132 can also be used to redistribute the first connection pad 122, the second connection pad 123 and the third connection pad 182, thereby providing the above-mentioned electrical connection path. The back side redistribution layer 132 can be formed using a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The back side redistribution layer 132 can perform various functions according to the design of the corresponding layer. For example, the back side redistribution layer 132 may include a ground pattern, a power pattern, a signal pattern, etc. The ground pattern and the signal pattern may be the same pattern. The signal pattern may be one of various signal patterns (e.g., a data signal pattern, etc.) other than the ground pattern, the power pattern, etc. Here, the pattern is a concept including wiring and pads.

[0091] The back side connection via 133 can electrically connect the third wiring layer 112c and the back side redistribution layer 132 to each other. The back side connection via 133 can also be formed using a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The back side connection via 133 can be a filled via filled with a metal material or a conformal via formed along the wall of the via hole by a metal material. The back side connection via 133 can have a tapered cross-sectional shape. The back side connection via 133 can have the same tapered direction as each wiring via of the first wiring via layer 113a and the second wiring via layer 113b. In another embodiment, the number of the back side redistribution layer 132 and the back side connection via 133 can be changed.

[0092] The first passivation layer 150 and the second passivation layer 159 may be used to protect the first connection structure 140 and the back redistribution layer 132 from external physical damage or chemical damage, etc. The third passivation layer 155 may be used to protect the second connection structure 160 from external physical damage or chemical damage. The first passivation layer 150, the second passivation layer 159 and the third passivation layer 155 may include a thermosetting resin. For example, the passivation layers 150, 155 and 159 may be formed using ABF, but are not limited thereto. The first passivation layer 150, the second passivation layer 159 and the third passivation layer 155 may have a plurality of openings that expose at least a portion of the first redistribution layer 142, at least a portion of the second redistribution layer 162, and at least a portion of the back redistribution layer 132, respectively. The openings may be provided in an amount of tens to tens of thousands or more or less. Each opening may include a plurality of holes.

[0093] The electrically connected metal piece 193 may be further used to physically connect and / or electrically connect the semiconductor package 100A to the outside. For example, the semiconductor package 100A may be mounted on a mainboard of an electronic device through the electrically connected metal piece 193. The electrically connected metal piece 193 may be respectively disposed on a plurality of openings of the second passivation layer 159. Therefore, the electrically connected metal piece 193 may be electrically connected to the exposed backside redistribution layer 132. When necessary, a metal piece under the bump may be formed in a plurality of openings of the second passivation layer 159; in this case, the metal piece under the bump may be electrically connected to the exposed backside redistribution layer 132. The electrically connected metal piece 193 may be formed using a low melting point metal such as tin (Sn) or an alloy including tin (Sn). In more detail, the electrically connected metal piece 193 may be solder or the like; however, the material is only an example, and the material of the electrically connected metal piece 193 is not specifically limited thereto.

[0094] The electrically connected metal part 193 may have the shape of a pad, a solder ball, a pin, etc. The electrically connected metal part 193 may be formed as a multilayer or a single layer. When formed as a multilayer, the electrically connected metal part 193 may include a copper (Cu) column and a solder; when formed as a single layer, the electrically connected metal part 193 may include a tin-silver solder or copper (Cu). However, this material is only an example, and the material of the electrically connected metal part 193 is not limited thereto. There is no specific restriction on the number, spacing, arrangement form, etc. of the electrically connected metal parts 193, and those skilled in the art can make full modifications according to the design details. For example, according to the number of the first connection pad 122, the second connection pad 123, and the third connection pad 182, the electrically connected metal part 193 can be set in an amount of tens to tens of thousands or more or less.

[0095] At least one of the electrical connection metal parts 193 may be arranged in the fan-out region. The fan-out region refers to an area other than the area where the first semiconductor chip 120 is arranged. That is, the semiconductor package 100A according to the embodiment may be a fan-out semiconductor package. The fan-out package may have higher reliability than the fan-in package, may realize multiple input / output (I / O) terminals, and may facilitate three-dimensional (3D) interconnection. In addition, when compared with a ball grid array (BGA) package, a grid array (LGA) package, etc., the fan-out package may be manufactured to have a smaller thickness and may be price competitive.

[0096] The connection terminal 195 may be disposed between the first connection structure 140 and the second connection structure 160 to electrically and physically connect the first redistribution layer 142 and the second redistribution layer 162 to each other. The connection terminal 195 may be formed using copper (Cu), tin (Sn), or an alloy thereof, for example, may be formed using a low melting point metal such as solder. In another embodiment, the number and shape of the connection terminal 195 may be changed.

[0097] The bottom filling layer 197 may be disposed between the first connection structure 140 and the second connection structure 160 to cover at least a portion of the connection terminal 195. The bottom filling layer 197 may be used to fix the first semiconductor package P1 and the second semiconductor package P2. The bottom filling layer 197 may be formed using, for example, epoxy resin, etc., and is not limited thereto. In another embodiment, the bottom filling layer 197 may be omitted.

[0098] Fig.11 is a schematic cross-sectional view showing another example of a semiconductor package.

[0099] Reference Fig.11 , the semiconductor package 100B according to another example may further include one or more passive components 200 disposed on the first connection structure 140. The first connection pad 122, the second connection pad 123, and the third connection pad 182 may be electrically connected to the passive component 200 according to the function. The passive component 200 may be disposed on the first connection structure 140 in a surface mounting form by a low melting point metal member 200s such as solder.

[0100] The passive component 200 may be a chip capacitor (such as a multilayer ceramic capacitor (MLCC) or a low inductance chip capacitor (LICC)) or a chip inductor (such as a power inductor). However, the type of the passive component 200 is not limited thereto and may be other known passive components. That is, the passive component 200 may be a known chip passive component. Here, a chip component refers to an independent chip component having, for example, a main body, an inner electrode formed inside the main body, and an outer electrode formed on the main body. Multiple passive components 200 may be components of the same or different types. The number of passive components 200 is not specifically limited, and may be more or less than the number of passive components 200 shown in the drawings according to the design.

[0101] The other structures are substantially the same as those of the semiconductor package 100A and the like described above, and thus detailed descriptions thereof are omitted.

[0102] Fig.12 is a schematic cross-sectional view showing another example of a semiconductor package.

[0103] Reference Fig.12, the semiconductor package 100C according to another example may further include one or more passive components 205 disposed on the lower surface of the backside redistribution layer 132. Each of the passive components 205 may be disposed under a portion of at least one of the through vias 125, and may be disposed between the electrical connection metal pieces 193. According to the function, the first connection pad 122, the second connection pad 123, and the third connection pad 182 may be electrically connected to the passive component 205. The passive component 205 may be disposed in a surface mounting form by a low melting point metal piece 205s such as solder.

[0104] The passive component 205 may be a chip capacitor (such as a pad side capacitor (LSC), a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC)) or a chip inductor (such as a power inductor). The passive component 205 may be components of the same or different types. The number of passive components 205 is not specifically limited, and may be more or less than the number of passive components 205 shown in the drawings according to the design.

[0105] The other structures are substantially the same as those of the semiconductor package 100A and the like described above, and thus detailed description thereof is omitted. In addition, the specific structure of the semiconductor package 100C described above may also be applied to a semiconductor package 100B according to another embodiment.

[0106] Fig.13 is a schematic cross-sectional view showing another example of a semiconductor package.

[0107] Reference Fig.13 ,and Fig. 9 Unlike the semiconductor package 100A in the embodiment of the present invention, in a semiconductor package 100D according to another example, the first semiconductor package P1 may include a plurality of first semiconductor chips 120A and 120B, and the second semiconductor package P2 may include a plurality of second semiconductor chips 180A and 180B. To this end, the first frame 110 may have a plurality of first penetrations 110H1 and 110H2 spaced apart from each other, and the second frame 170 may have a plurality of second penetrations 170H1 and 170H2 spaced apart from each other. The plurality of first semiconductor chips 120A and 120B and the plurality of second semiconductor chips 180A and 180B may be respectively arranged so that each pair of the first semiconductor chips and the second semiconductor chips at least partially overlap each other in the vertical direction. The plurality of second semiconductor chips 180A and 180B may each perform a function that is more advanced than the plurality of first semiconductor chips 120A and 120B, and may each include a semiconductor element having a size smaller than that of the semiconductor elements of the plurality of first semiconductor chips 120A and 120B.

[0108] The other structures are substantially the same as those of the semiconductor package 100A and the like described above, and thus detailed description thereof is omitted. In addition, the specific structure of the semiconductor package 100D described above may also be applied to the semiconductor packages 100B and 100C according to another embodiment.

[0109] Fig.14 is a schematic cross-sectional view showing another example of a semiconductor package.

[0110] Reference Fig.14 According to another example, the semiconductor package 100E may further include a third semiconductor package P3, which is arranged side by side with the second semiconductor package P2 including the second semiconductor chip 180 and includes the second semiconductor chip 180'. In addition, the first semiconductor package P1 may include a plurality of first semiconductor chips 120A and 120B, and thus, the first frame 110 may have a plurality of first penetration portions 110H1 and 110H2 arranged to be spaced apart from each other. In addition, Fig.11 Similar to the semiconductor package 100B in FIG. 1 , the semiconductor package 100E may further include one or more passive components 200 disposed on the first connection structure 140 .

[0111] The third semiconductor package P3 may have a structure substantially the same as that of the second semiconductor package P2. The third semiconductor package P3 may include a second connection structure 160, a second frame 170, a second semiconductor chip 180', a second encapsulant 191, a third passivation layer 155, a connection terminal 195, and a bottom filling layer 197. The second semiconductor package P2 and the third semiconductor package P3 may be respectively arranged to vertically overlap at least a portion of the plurality of first semiconductor chips 120A and 120B. The second semiconductor chips 180 and 180' may each perform a relatively higher-level function than the plurality of first semiconductor chips 120A and 120B, and may include semiconductor elements each having a size smaller than that of the semiconductor elements of the plurality of first semiconductor chips 120A and 120B.

[0112] The passive component 200 may be disposed between the second semiconductor package P2 and the third semiconductor package P3, specifically, the passive component 200 may be disposed between the second semiconductor package P2 and the third semiconductor package P3 through a low-melting-point metal member 200s and located on the first connection structure 140. In another embodiment, the passive component 200 may be additionally disposed outside each of the second semiconductor package P2 and the third semiconductor package P3.

[0113] The other structures are substantially the same as those of the semiconductor packages 100A, 100B, 100D, etc. described above, and thus a detailed description thereof is omitted.

[0114] Fig.15 is a schematic cross-sectional view showing another example of a semiconductor package.

[0115] Reference Fig.15 ,and Fig. 9 Unlike the semiconductor package 100A in FIG. 1 , a semiconductor package 100F according to another example may further include a third semiconductor package P3 stacked on top of the second semiconductor package P2 in a vertical direction. Fig. 9 Unlike the semiconductor package 100A in FIG. 1 , the second semiconductor package P2 may have a structure partially symmetrical with the first semiconductor package P1 in the vertical direction.

[0116] In the second semiconductor package P2, the second frame 170 may have a plurality of insulating layers 171a and 171b, and may further include wiring layers 172a, 172b and 172c and wiring via layers 173a and 173b. In addition, the second semiconductor package P2 may further include a backside wiring layer 132' and a backside connection via 133' located on the second semiconductor chip 180, and may further include a passivation layer 159' covering the backside wiring layer 132'. In addition to the body 181 and the third connection pad 182, the second semiconductor chip 180 may further include a backside wiring layer 132' and a backside connection via 133'.

[0117] Fourth connection pads 183 on the ineffective surface of the second semiconductor chip 180 and through vias 185 connected to the fourth connection pads 183. The through vias 185 may be provided in a region of the second semiconductor chip 180 overlapping with the through vias 125, and the through vias 125 and the through vias 185 may be electrically connected to a power pattern or a ground pattern of the backside redistribution layer 132.

[0118] The third semiconductor package P3 may include a wiring board 210 , a plurality of third semiconductor chips 220A and 220B disposed on the wiring board 210 , a third encapsulant 230 encapsulating the third semiconductor chips 220A and 220B, and upper connection terminals 260 disposed under the wiring board 210 .

[0119] The wiring board 210 may be a known printed circuit board (PCB) such as an interposer. The wiring board 210 may include an insulating layer and a conductive wiring layer formed in the insulating layer. A passivation layer or the like may be formed on both sides of the wiring board 210. In another embodiment, the structure and shape of the wiring board 210 may be changed. In addition, in another embodiment, an interposer may also be provided between the wiring board 210 and the second semiconductor package P2.

[0120] The third semiconductor chips 220A and 220B may be stacked vertically. The third semiconductor chip 220A is attached to the wiring board 210 by an adhesive member 225, and the third semiconductor chip 220B is attached to the third semiconductor chip 220A by an adhesive member 225. The third semiconductor chips 220A and 220B may be electrically connected to the wiring layer of the wiring board 210 by a wire 240 connected to the connection pad 221P and a wire 240 connected to the connection pad 222P, respectively. However, in another embodiment, the third semiconductor chip 220A at the bottom may be combined on the wiring board 210 in a flip chip manner.

[0121] The third semiconductor chips 220A and 220B can each be an integrated circuit (IC) in which hundreds to millions or more components are integrated in a single chip. The IC can be a memory chip such as a volatile memory (such as a dynamic random access memory (DRAM)), a non-volatile memory (such as a read-only memory (ROM) and a flash memory), etc., and is not limited thereto. In the third semiconductor chips 220A and 220B, each effective surface can be a surface on which each of the connection pads 221P and 222P is provided, and each invalid surface can be a surface opposite to the effective surface. However, in another embodiment, the third semiconductor chips 220A and 220B can be arranged in a face-down form. Each of the third semiconductor chips 220A and 220B can be formed on the basis of an effective wafer; in this case, the base material of each of the semiconductor chips can be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits can be formed in the third semiconductor chips 220A and 220B. The connection pads 221P and 222P may be used to electrically connect the third semiconductor chips 220A and 220B to other components, respectively; the connection pads 221P and 222P may each be formed using a conductive material such as aluminum (Al) without any particular limitation.

[0122] The adhesive member 225 can make the ineffective surface of the third semiconductor chip 220A easily attached to the upper surface of the wiring board 210, and can make the ineffective surface of the third semiconductor chip 220B easily attached to the upper surface of the third semiconductor chip 220A. For example, the adhesive member 225 can be a film such as a chip attachment film (DAF). The material of the adhesive member 225 is not specifically limited. The adhesive member 225 can be formed using, for example, an epoxy resin component, and is not limited thereto. The third semiconductor chips 220A and 220B can be more stably mounted by the adhesive member 225, respectively, and have improved reliability.

[0123] The third encapsulant 230 can protect the third semiconductor chips 220A and 220B. The encapsulation form of the third encapsulant 230 is not specifically limited, and can be a form in which the third encapsulant 230 encapsulates at least a portion of the third semiconductor chips 220A and 220B. For example, the third encapsulant 230 can cover at least a portion of the effective surface of the third semiconductor chips 220A and 220B, and can also cover at least a portion of the side surface of the third semiconductor chips 220A and 220B. The third encapsulant 230 can be formed using an insulating material. The insulating material can be a photosensitive epoxy resin (PIE, photoimagable epoxy), a photosensitive dielectric (PID) material, etc. However, the insulating material is not limited thereto. That is, the insulating material can be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin having a reinforcing material such as an inorganic filler, more specifically, ABF, etc. In addition, any known molding material (such as epoxy molding compound (EMC)), etc.) can also be used. Where necessary, a material in which a thermosetting resin or a thermoplastic resin is impregnated in an inorganic filler and / or a core material such as glass fiber (or glass cloth or glass fabric) may also be used as the insulating material.

[0124] The upper connection terminal 260 can electrically connect the wiring board 210 and the second connection structure 160 to each other. The upper connection terminal 260 can be interposed between the wiring layer of the wiring board 210 and the second redistribution layer 162 of the second connection structure 160, specifically, the upper connection terminal 260 can be interposed between the wiring layer of the wiring board 210 and the backside wiring layer 132'. The upper connection terminal 260 can be formed using a conductive material such as solder. However, the material is only an example, and the material of the upper connection terminal 260 is not specifically limited. The upper connection terminal 260 may have a shape of a pad, a solder ball, a pin, etc.

[0125] The other structures are substantially the same as those of the semiconductor packages 100A, 100B, 100D, etc. described above, and thus detailed description thereof is omitted. In addition, the specific structure of the semiconductor package 100F described above may also be used for the semiconductor packages 100B, 100C, 100D, and 100E according to another embodiment.

[0126] Fig.16 is a schematic cross-sectional view showing another example of a semiconductor package.

[0127] Reference Fig.16In a semiconductor package 100G according to another example, the first frame 110 may have a different shape. In detail, the first frame 110 may include: a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, which are respectively disposed on opposite surfaces of the first insulating layer 111a; a second insulating layer 111b and a third insulating layer 111c, which are respectively disposed on opposite surfaces of the first insulating layer 111a and cover the first wiring layer 112a and the second wiring layer 112b; a third wiring layer 112c, which is disposed on another surface of the second insulating layer 111b opposite to one surface of the second insulating layer 111b in which the first wiring layer 112a is embedded; a fourth wiring layer 112d, which is disposed on the second insulating layer 111b; The first frame 110 may include a larger number of wiring layers 112a, 112b, 112c, and 112d, so that the connection structure 140 can be further simplified.

[0128] The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may have a greater thickness to substantially maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be used to form a greater number of wiring layers 112c and 112d. Similarly, the height and / or average diameter of the wiring vias of the first wiring via layer 113a that passes through the first insulating layer 111a may be greater than the height and / or average diameter of the second wiring via layer 113b that passes through the second insulating layer 111b and greater than the height and / or average diameter of the third wiring via layer 113c that passes through the third insulating layer 111c, respectively. In addition, the wiring vias of the first wiring via layer 113a may have an hourglass shape or a cylindrical shape, while the wiring vias of the second wiring via layer 113b and the wiring vias of the third wiring via layer 113c may have a tapered shape with tapered directions opposite to each other. The thickness of the first wiring layer 112 a , the second wiring layer 112 b , the third wiring layer 112 c , and the fourth wiring layer 112 d may be greater than the thickness of the first redistribution layer 142 .

[0129] If necessary, the metal layer 115 may also be provided on the wall surface of the first penetration portion 110H of the first frame 110, and the metal layer 115 may cover the entire wall surface. The metal layer 115 may include a metal material such as copper (Cu), etc. Due to the metal layer 115, the first semiconductor chip 120 may have an improved electromagnetic wave shielding effect and a heat dissipation effect.

[0130] The other structures are substantially the same as those of the semiconductor package 100A, etc., and thus detailed description thereof is omitted. In addition, the specific structure of the semiconductor package 100G described above may also be used for semiconductor packages 100B, 100C, 100D, 100E, and 100F according to another embodiment.

[0131] As set forth above, according to the embodiments in the present disclosure, a package structure is provided that can package a plurality of semiconductor chips to have optimal signal characteristics and power characteristics.

[0132] While embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor package, comprising a first semiconductor package and a second semiconductor package, The first semiconductor package comprises: A first frame having a first penetration portion; a first semiconductor chip disposed in the first penetration portion of the first frame and having a first surface, a second surface, and a first through-via, a first connection pad being disposed on the first surface, the second surface being opposite to the first surface and a second connection pad being disposed on the second surface, and the first through-via penetrating the first surface and the second surface and connected to the second connection pad; a first connection structure disposed on the first surface of the first semiconductor chip and comprising a first redistribution layer electrically connected to the first connection pads of the first semiconductor chip; as well as a backside redistribution layer disposed on the second surface of the first semiconductor chip and electrically connected to the second connection pads of the first semiconductor chip, The second semiconductor package is disposed on the first semiconductor package and includes: a second connection structure comprising a second redistribution layer electrically connected to the first redistribution layer; a second frame, disposed on the second connecting structure and having a second penetrating portion; and a second semiconductor chip disposed in the second through portion of the second frame and having a third surface on which a third connection pad is disposed, the third connection pad being electrically connected to the second redistribution layer, The first semiconductor chip includes a plurality of first semiconductor elements, the plurality of first semiconductor elements are distributed in a plurality of first regions, and the first through vias are provided in plurality, and the via regions where the plurality of first through vias are arranged are provided between the plurality of first regions, and The first connection pad is connected to the signal pattern of the first redistribution layer, and the second connection pad and the first through vias are connected to at least one of the power pattern and the ground pattern of the backside redistribution layer.

2. The semiconductor package according to claim 1, wherein: The via region is disposed in a central region of the first semiconductor chip, and the plurality of first regions are arranged around the central region.

3. The semiconductor package according to claim 2, wherein: The first frame includes a wiring structure electrically connecting the first redistribution layer and the backside redistribution layer to each other.

4. The semiconductor package according to claim 3, wherein: The signal pattern of the first redistribution layer is electrically connected to the backside redistribution layer through the wiring structure. 5 . The semiconductor package of claim 1 , further comprising a plurality of connection terminals connecting the first redistribution layer and the second redistribution layer to each other.

6. The semiconductor package according to claim 1, wherein: The first connection pad and the third connection pad face each other.

7. The semiconductor package according to claim 1, wherein: The first connection structure further includes a first connection via connected to the first redistribution layer, and The first through via is electrically connected to the first redistribution layer through the first connection via at one end of the first through via, the one end of the first through via being opposite to the other end of the first through via connecting the first through via to the second connection pad.

8. The semiconductor package according to claim 1, wherein: The first through via of the first semiconductor chip extends from the second connection pad to the first surface or a region adjacent to the first surface by penetrating the first semiconductor chip.

9. The semiconductor package according to claim 1, wherein: The first semiconductor chip and the second semiconductor chip each implement a part of or all of the functions of an application processor.

10. The semiconductor package according to claim 1, wherein Each of the plurality of first semiconductor elements has a first critical dimension, and The second semiconductor chip includes a second semiconductor element having a second critical dimension that is smaller than the first critical dimension. 11 . The semiconductor package of claim 1 , further comprising a passive component disposed on the first connection structure together with the second semiconductor package. 12 . The semiconductor package of claim 1 , further comprising a passive component disposed under the first through via and on a lower surface of the backside redistribution layer.

13. The semiconductor package according to claim 1, wherein: The first frame has a plurality of the first penetration portions, and A plurality of the first semiconductor chips are respectively disposed in a plurality of the first penetration portions.

14. The semiconductor package according to claim 13, wherein: The second frame has a plurality of the second penetration portions, and The plurality of second semiconductor chips are respectively disposed in the plurality of second penetration portions. 15 . The semiconductor package of claim 1 , further comprising a third semiconductor package disposed on the first semiconductor package together with the second semiconductor package and having substantially the same structure as the second semiconductor package. 16 . The semiconductor package of claim 15 , further comprising a passive component disposed between the second semiconductor package and the third semiconductor package and located on the first connection structure.

17. The semiconductor package according to claim 1, wherein: The second semiconductor chip further includes: a fourth connection pad provided on a fourth surface opposite to the third surface on which the third connection pad is provided; and a second through via connected to the fourth connection pad.

18. The semiconductor package according to claim 17, wherein: The second through via is provided in a region of the second semiconductor chip overlapping with the first through via, and The first through via and the second through via are electrically connected to a power pattern or a ground pattern of the backside redistribution layer.

19. The semiconductor package according to claim 1, further comprising a third semiconductor package, wherein the third semiconductor package is disposed on the second semiconductor package, and the third semiconductor package comprises a wiring board and at least one third semiconductor chip, wherein the wiring board is electrically connected to the second redistribution layer through an upper connection terminal, and the at least one third semiconductor chip is disposed on the wiring board.

20. A semiconductor package comprising a first semiconductor package and a second semiconductor package, The first semiconductor package comprises: A first frame having a first penetration portion; a first semiconductor chip disposed in the first through portion of the first frame and having a first surface, a second surface and a through via, wherein a first connection pad is disposed on the first surface, the second surface is opposite to the first surface and a second connection pad is disposed on the second surface, and the through via penetrates the first surface and the second surface and is connected to the second connection pad; a first connection structure disposed on the first surface of the first semiconductor chip and comprising a first redistribution layer electrically connected to the first connection pads of the first semiconductor chip; as well as a backside redistribution layer disposed on the second surface of the first semiconductor chip and electrically connected to the second connection pads of the first semiconductor chip, The second semiconductor package is disposed on the first semiconductor package and includes a second semiconductor chip, the second semiconductor chip having a third surface on which a third connection pad electrically connected to the first redistribution layer is disposed, The first semiconductor chip includes a plurality of first semiconductor elements having a first critical dimension, and the second semiconductor chip includes a second semiconductor element having a second critical dimension smaller than the first critical dimension, There are multiple through vias, and the multiple first semiconductor elements are distributed in multiple first regions, and the via region where the multiple through vias are arranged is arranged between the multiple first regions, and The first connection pad is connected to the signal pattern of the first redistribution layer, and the second connection pad and the plurality of through vias are connected to at least one of the power pattern and the ground pattern of the backside redistribution layer.

21. The semiconductor package according to claim 20, wherein: The first critical dimension is in the range of 0.05 mm to 10 mm, and the second critical dimension is in the range of 1 nm to 100 nm.

22. The semiconductor package according to claim 20, wherein: The via region is disposed in a central region of the first semiconductor chip, and the plurality of first regions are arranged around the central region.

23. The semiconductor package according to claim 20, wherein: The second semiconductor chip includes a plurality of the second semiconductor elements, the plurality of the second semiconductor elements are distributed in a plurality of second regions, and The plurality of first regions and the plurality of second regions perform different functions.

24. The semiconductor package according to claim 23, wherein: The plurality of first regions are logic regions for executing arithmetic functions of the application processor, and the plurality of second regions are regions for executing power-related functions of the application processor.

25. The semiconductor package according to claim 20, wherein: The first semiconductor chip is a power management integrated circuit chip, and the second semiconductor chip is an application processor chip.

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