Semiconductor Devices

Abstract

The present disclosure provides a semiconductor device, the semiconductor device comprising: a semiconductor layer having a first surface and a second surface opposite to the first surface; an active pattern on the first surface, the active pattern comprising a source / drain region; a power rail electrically connected to the source / drain region; and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer comprises an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application No. 10-2019-0057543 filed on May 16, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices including field effect transistors and methods of manufacturing the semiconductor devices. Background Art

[0004] Semiconductor devices are widely used in the electronics industry due to their small size, multifunctional characteristics and / or low manufacturing cost. Semiconductor devices can be classified as any of semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that have both the functions of semiconductor memory devices and the functions of semiconductor logic devices. With the development of the electronics industry, the demand for semiconductor devices with excellent characteristics is increasing. For example, the demand for high reliability, high speed and / or multifunctional semiconductor devices continues to increase. In order to meet these demands, semiconductor devices have been highly integrated, and the structure of semiconductor devices has become more and more complex. Summary of the invention

[0005] Some example embodiments of the inventive concepts may provide a semiconductor device capable of improving integration density and reliability.

[0006] According to some example embodiments, a semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface; an active pattern on the first surface, the active pattern including source / drain regions; a power rail electrically connected to the source / drain regions; and a power delivery network on the second surface, the power delivery network electrically connected to the power rail, wherein the semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

[0007] According to some example embodiments, a semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a transistor on the first surface, an upper insulating layer on the transistor, an upper interconnection line in the upper insulating layer, a lower insulating layer on the second surface, and a lower interconnection line in the lower insulating layer, wherein the semiconductor layer includes an etch stop dopant, and a concentration of the etch stop dopant decreases from the second surface to the first surface.

[0008] According to some example embodiments, a semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a transistor on the first surface, a lower insulating layer on the second surface, and a lower interconnection line in the lower insulating layer, wherein the semiconductor layer includes an etch stop dopant, and a concentration of the etch stop dopant increases from the first surface to the second surface, has a maximum value at the second surface, and may be sharply reduced in the lower insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The inventive concept will become more apparent in view of the accompanying drawings and the associated detailed description.

[0010] Figure 1 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept.

[0011] Figure 2A , Figure 2B and Figure 2C Along Figure 1 Cross-sectional views taken along lines II', II-II' and III-III'.

[0012] Figure 3 is based on Figure 2A A graph schematically illustrating the dopant concentration at depth in a semiconductor layer.

[0013] FIG. 4A to FIG. 4J According to some exemplary embodiments of the present invention, Figure 1 A cross-sectional view taken along line II-II' of FIG. 1 is shown to illustrate a method of manufacturing a semiconductor device.

[0014] Figure 5 is based on Figure 4C A graph schematically illustrating the dopant concentration at depth in a semiconductor layer.

[0015] Figure 6 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept.

[0016] Fig. 7A and Figure 7B Along Figure 6 Cross-sectional views taken along lines II' and II-II'. DETAILED DESCRIPTION

[0017] Figure 1 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept. Figure 2A , Figure 2B and Figure 2C Along Figure 1Cross-sectional views taken along lines II', II-II' and III-III'. Figure 3 is based on Figure 2A A graph schematically illustrating the dopant concentration at depth in a semiconductor layer.

[0018] refer to Figure 1 and FIG. 2A to FIG. 2C , a semiconductor layer SL may be provided. The semiconductor layer SL may have a first surface SLa and a second surface SLb opposite to the first surface SLa. The semiconductor layer SL may include a first active region PR and a second active region NR. For example, the semiconductor layer SL may include silicon, germanium, or a combination thereof.

[0019] A device isolation layer ST may be provided on the first surface SLa of the semiconductor layer SL. The device isolation layer ST may define a first active region PR and / or a second active region NR. For example, the first active region PR may be a P-type metal oxide semiconductor field effect transistor (PMOSFET) region, and the second active region NR may be an N-type metal oxide semiconductor field effect transistor (NMOSFET) region. Each of the first active region PR and the second active region NR may be defined by a second trench TR2 formed in the first surface SLa of the semiconductor layer SL, and the device isolation layer ST may fill the second trench TR2. For example, the device isolation layer ST may include a silicon oxide layer.

[0020] The first active region PR and / or the second active region NR may be arranged along the first direction D1. For example, the first active region PR and the second active region NR may be spaced apart from each other in the first direction D1 with a device isolation layer ST interposed therebetween.

[0021] The first power rail POR1 may be provided in the second trench TR2 between a pair of first active regions PR adjacent to each other. The second power rail POR2 may be provided in the second trench TR2 between a pair of second active regions NR adjacent to each other. The first power rail POR1 and / or the second power rail POR2 may be buried in the device isolation layer ST. The first power rail POR1 and / or the second power rail POR2 may have a line shape extending in the second direction D2.

[0022] A through-via TVI extending from the second surface SLb of the semiconductor layer SL to the first surface SLa may be provided. The through-via TVI may partially penetrate the semiconductor layer SL. In other words, the top surface of the through-via TVI may be lower than the first surface SLa. The bottom surface of the through-via TVI may be coplanar with the second surface SLb. The through-via TVI may be connected to the first power rail POR1 and / or the second power rail POR2, respectively.

[0023] A plurality of first active patterns FN1 extending in the second direction D2 may be provided on each of the first active regions PR. A plurality of second active patterns FN2 extending in the second direction D2 may be provided on each of the second active regions NR. The first active pattern FN1 and / or the second active pattern FN2 may be a vertically protruding portion of the semiconductor layer SL. The first active pattern FN1 and / or the second active pattern FN2 may protrude vertically from the first surface SLa. The first active pattern FN1 and / or the second active pattern FN2 may be arranged along the first direction D1.

[0024] For example, three first active patterns FN1 may extend in parallel with each other in the second direction D2 on the first active region PR. For example, three second active patterns FN2 may extend in parallel with each other in the second direction D2 on the second active region NR. However, the number and shape of the first active patterns FN1 on the first active region PR and the number and shape of the second active patterns FN2 on the second active region NR are illustrated as examples and are not limited to the illustration.

[0025] The first trench TR1 may be defined between a pair of active patterns FN1 adjacent to each other along the first direction D1 and between a pair of active patterns FN2 adjacent to each other along the first direction D1. A device isolation layer ST may also fill the first trench TR1.

[0026] The upper portion of the first active pattern FN1 and / or the second active pattern FN2 may be higher than the top surface of the device isolation layer ST. The upper portion of the first active pattern FN1 and / or the second active pattern FN2 may protrude vertically from the device isolation layer ST. The upper portion of the first active pattern FN1 and / or the second active pattern FN2 may have a fin shape protruding from the device isolation layer ST.

[0027] The upper portion of each of the first active patterns FN1 may include a first channel region CH1 and / or a first source / drain region SD1. The first source / drain region SD1 may be a P-type dopant region. Each of the first channel regions CH1 may be disposed between a pair of first source / drain regions SD1 adjacent to each other. The upper portion of each of the second active patterns FN2 may include a second channel region CH2 and / or a second source / drain region SD2. The second source / drain region SD2 may be an N-type dopant region. Each of the second channel regions CH2 may be disposed between a pair of second source / drain regions SD2 adjacent to each other.

[0028] The first source / drain region SD1 and / or the second source / drain region SD2 may include an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The top surface of the first source / drain region SD1 and / or the second source / drain region SD2 may be higher than the top surface of the first channel region CH1 and / or the second channel region CH2.

[0029] In some example embodiments, the first source / drain region SD1 may include a semiconductor element having a lattice constant greater than a lattice constant of a semiconductor element of the semiconductor layer SL. Therefore, the first source / drain region SD1 may provide compressive stress to the first channel region CH1. In some example embodiments, the second source / drain region SD2 may include the same semiconductor element as the semiconductor layer SL. For example, the first source / drain region SD1 may include silicon-germanium (SiGe), and / or the second source / drain region SD2 may include silicon.

[0030] When viewed in a cross-sectional view taken along the first direction D1 (see Figure 2B ), a cross-sectional shape of each of the first source / drain regions SD1 may be different from a cross-sectional shape of each of the second source / drain regions SD2.

[0031] The gate electrode GE may extend in the first direction D1 to intersect the first active pattern FN1 and / or the second active pattern FN2. The gate electrodes GE may be spaced apart from each other in the second direction D2. The gate electrode GE may vertically overlap the first channel region CH1 and / or the second channel region CH2. Each of the gate electrodes GE may be provided on a top surface and both sidewalls of each of the first channel region CH1 and the second channel region CH2 (see FIG. 2 ). Figure 2C For example, the gate electrode GE may include at least one of a conductive metal nitride (eg, titanium nitride and / or tantalum nitride) and / or a metal material (eg, titanium, tantalum, tungsten, copper, and / or aluminum).

[0032] A pair of gate spacers GS may be provided on both side walls of each of the gate electrodes GE, respectively. The gate spacer GS may extend along the gate electrode GE in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the gate cap layer CP to be described later. For example, the gate spacer GS may include at least one of SiCN, SiCON and / or SiN. In some example embodiments, each of the gate spacers GS may have a multilayer structure formed of at least two of SiCN, SiCON and / or SiN.

[0033] The gate dielectric layer GI may be arranged between each of the gate electrodes GE and the channel regions CH1 and CH2. The gate dielectric layer GI may extend along the bottom surface of the gate electrode GE. The gate dielectric layer GI may cover the top surface and both sidewalls of each of the first channel region CH1 and the second channel region CH2. The gate dielectric layer GI may include a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium-silicon oxide, lanthanum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, lithium oxide, aluminum oxide, lead-scandium-tantalum oxide, and / or lead-zinc niobate.

[0034] A gate cover layer CP may be provided on each of the gate electrodes GE. The gate cover layer CP may extend along the gate electrode GE in the first direction D1. The gate cover layer CP may include a material having an etching selectivity with respect to a first upper insulating layer UIL1 and a second upper insulating layer UIL2 to be described later. For example, the gate cover layer CP may include at least one of SiON, SiCN, SiCON, and / or SiN.

[0035] The first upper insulating layer UIL1, the second upper insulating layer UIL2, the third upper insulating layer UIL3 and / or the fourth upper insulating layer UIL4 may be sequentially stacked on the first surface SLa of the semiconductor layer SL. Each of the first to fourth upper insulating layers UIL1 to UIL4 may include a silicon oxide layer and / or a silicon oxynitride layer. The first upper insulating layer UIL1 may cover the first active pattern FN1 and / or the second active pattern FN2.

[0036] The active contact AC may penetrate the first upper insulating layer UIL1 and the second upper insulating layer UIL2 between the pair of gate electrodes GE so as to be electrically connected to the first source / drain region SD1 and / or the second source / drain region SD2. The active contact AC may have a strip shape extending in the first direction D1. For example, the active contact AC may be connected to a plurality of first source / drain regions SD1 and / or a plurality of second source / drain regions SD2.

[0037] The at least one active contact AC may be electrically connected to the first power rail POR1 and / or the second power rail POR2. The at least one active contact AC may include a body portion BP and / or an extension portion EP.

[0038] The body portion BP may be provided on the first source / drain region SD1 and / or the second source / drain region SD2 and may be electrically connected to the first source / drain region SD1 and / or the second source / drain region SD2. At least a portion of the extension portion EP may vertically overlap the first power rail POR1 and / or the second power rail POR2. The extension portion EP may vertically extend from the body portion BP to the first power rail POR1 and / or the second power rail POR2. Therefore, the extension portion EP may contact the first power rail POR1 and / or the second power rail POR2. The lower portion of the extension portion EP may penetrate the upper portion of the device isolation layer ST so as to be connected to the first power rail POR1 and / or the second power rail POR2.

[0039] A power supply voltage (VDD) and / or a ground voltage (VSS) may be applied to the first power rail POR1 and / or the second power rail POR2, respectively. The power supply voltage (VDD) may be applied to the first source / drain region SD1 through the extension portion EP and / or the body portion BP of the active contact AC. The ground voltage (VSS) may be applied to the second source / drain region SD2 through the extension portion EP and / or the body portion BP of the active contact AC.

[0040] A gate contact GC may be provided on at least one gate electrode GE. The gate contact GC may penetrate the second upper insulating layer UIL2 and / or the gate capping layer CP so as to be electrically connected to the gate electrode GE. When viewed in a plan view, the gate contact GC may be arranged between the first active region PR and the second active region NR. The gate contact GC may vertically overlap with the device isolation layer ST filling the second trench TR2 between the first active region PR and the second active region NR.

[0041] The active contact AC and the gate contact GC may include the same conductive material. The active contact AC and the gate contact GC may include a metal material, such as at least one of aluminum, copper, tungsten, molybdenum and / or cobalt.

[0042] The first active pattern FN1 and / or the second active pattern FN2 , the first channel region CH1 and / or the second channel region CH2 , the first source / drain region SD1 and / or the second source / drain region SD2 , the gate electrode GE, the gate contact GC and / or the active contact AC may be collectively referred to as a transistor.

[0043] The first upper interconnection line UML1 may be provided in the third upper insulating layer UIL3, and / or the second upper interconnection line UML2 may be provided in the fourth upper insulating layer UIL4. An upper via UVI may be provided under each of the first upper interconnection line UML1 and / or the second upper interconnection line UML2.

[0044] For example, the first upper interconnection line UML1 and / or the upper via UVI connected thereto may constitute a first metal layer. The second upper interconnection line UML2 and / or the upper via UVI connected thereto may constitute a second metal layer. Even though not shown in the drawings, a plurality of metal layers may be additionally stacked on the second metal layer.

[0045] A power delivery network PON may be provided on the second surface SLb of the semiconductor layer SL. The power delivery network PON may include a first lower insulating layer LIL1 and / or a second lower insulating layer LIL2 sequentially stacked on the second surface SLb of the semiconductor layer SL.

[0046] The power delivery network PON may further include a first lower interconnect line LML1 and / or a second lower interconnect line LML2. The first lower interconnect line LML1 may be provided in the first lower insulating layer LIL1, and / or the second lower interconnect line LML2 may be provided in the second lower insulating layer LIL2. A lower via LVI may be provided on each of the first lower interconnect line LML1 and the second lower interconnect line LML2.

[0047] At least one of the first lower interconnect lines LML1 may be electrically connected to the through-hole TVI through the lower via LVI. In other words, the first power rail POR1 and / or the second power rail POR2 may be electrically connected to the first lower interconnect line LML1. The first lower interconnect line LML1 and / or the second lower interconnect line LML2 may constitute an interconnection network for applying a power supply voltage (VDD) and / or a ground voltage (VSS) to the first power rail POR1 and / or the second power rail POR2, respectively. Even though not shown in the drawings, a plurality of interconnection layers may be additionally provided on the first lower interconnect line LML1 and / or the second lower interconnect line LML2.

[0048] Will refer to Figure 3 A concentration profile of a dopant according to a depth in the semiconductor layer SL is described in detail. The semiconductor layer SL may include various dopants. In some example embodiments, the semiconductor layer SL may include a well dopant WD, an etch stop dopant ESD, and / or a counter dopant CD.

[0049] The well dopant WD may be a dopant for forming a well in the semiconductor layer SL. The well dopant WD may include phosphorus (P), arsenic (As), or a combination thereof. From the first surface SLa to the second surface SLb of the semiconductor layer SL, the concentration of the well dopant WD may increase and then decrease. In other words, the well dopant WD may have the highest concentration at the middle point of the semiconductor layer SL. The concentration of the well dopant WD may be sharply reduced in the first lower insulating layer LIL1, so that the well dopant WD cannot be detected in the first lower insulating layer LIL1. In other words, the well dopant WD may not be present in the first lower insulating layer LIL1. The maximum concentration of the well dopant WD may be 1E18 / cm 3 To 1E19 / cm 3 in the range of 1E18 / cm 3 To about 1E19 / cm 3 As used herein, the term "about" refers to an increase of 10% or a decrease of 10% in a value.

[0050] According to some example embodiments, the etch stop dopant ESD may be a dopant for forming an etch stop region used in a process for manufacturing the semiconductor layer SL. The etch stop dopant ESD may include boron (B), carbon (C), or a combination thereof. The concentration of the etch stop dopant ESD may increase from the first surface SLa to the second surface SLb. The etch stop dopant ESD may have a highest concentration (e.g., a maximum concentration) at the second surface SLb. The concentration of the etch stop dopant ESD may be sharply reduced in the first lower insulating layer LIL1, so that the etch stop dopant ESD is not detected in the first lower insulating layer LIL1. In other words, the etch stop dopant ESD may not be present in the first lower insulating layer LIL1. The maximum concentration of the etch stop dopant ESD may be 1E16 / cm 3 To 5E21 / cm 3 In the range of 1E16 / cm 3 Up to about 5E21 / cm 3 In particular, the maximum concentration of the etch stop dopant ESD may be in the range of 1E18 / cm 3 To 5E20 / cm 3 in the range of 1E18 / cm 3 Up to about 5E20 / cm 3 within the range.

[0051] The anti-dopant CD may be a dopant for reducing or preventing the etching stop dopant ESD from penetrating into the well of the semiconductor layer SL. The anti-dopant CD may include phosphorus (P), arsenic (As), or a combination thereof. The concentration of the anti-dopant CD may increase from the first surface SLa to the second surface SLb. The anti-dopant CD may have a highest concentration (e.g., a maximum concentration) at the second surface SLb. The concentration of the anti-dopant CD may be sharply reduced in the first lower insulating layer LIL1, so that the anti-dopant CD cannot be detected in the first lower insulating layer LIL1. In other words, the anti-dopant CD may not be present in the first lower insulating layer LIL1. The maximum concentration of the anti-dopant CD may be 1E18 / cm 3 To 5E20 / cm 3 in the range of 1E18 / cm 3 Up to about 5E20 / cm 3 In some example embodiments, the counter dopant CD may be omitted.

[0052] In the semiconductor device according to some example embodiments of the inventive concept, by using the etching stop dopant ESD, the power delivery network PON can be stably formed on the second surface SLb of the semiconductor layer SL. Specifically, the etching stop dopant ESD can reduce, inhibit or prevent the semiconductor layer SL from being etched during the formation of the power delivery network PON. Therefore, the power delivery network PON can be formed without damaging the first active region PR and / or the second active region NR. As a result, the reliability and integration density of the semiconductor device can be improved.

[0053] FIG. 4A to FIG. 4J According to some exemplary embodiments of the present invention, Figure 1 A cross-sectional view taken along line II-II' of FIG. 1 is shown to illustrate a method of manufacturing a semiconductor device. Figure 5 is based on Figure 4C A graph schematically illustrating the dopant concentration at depth in a semiconductor layer.

[0054] refer to Figure 1 and Figure 4A , a substrate SUB may be provided. The substrate SUB may be a silicon substrate. A first ion implantation process IIP1 may be performed on an upper portion of the substrate SUB to form an etch stop region ESR. The formation of the etch stop region ESR may include doping an upper portion of the substrate SUB with an etch stop dopant ESD and performing a first annealing process.

[0055] The etch stop region ESR may include an etch stop dopant ESD. The etch stop dopant ESD may include boron (B), carbon (C), or a combination thereof. For example, the formation of the etch stop region ESR may include a 2E15 / cm2 Boron (B) is ion implanted with an energy of 10 KeV at a dose of 10 KeV.

[0056] refer to Figure 1 and Figure 4B , the first semiconductor layer SL1 may be formed on the etch stop region ESR of the substrate SUB. The formation of the first semiconductor layer SL1 may include performing a selective epitaxial growth (SEG) process on the substrate SUB. For example, the first semiconductor layer SL1 may include silicon.

[0057] A second ion implantation process IIP2 may be performed on the first semiconductor layer SL1. Subsequently, a second annealing process may be performed. Anti-dopants CD may be implanted into the first semiconductor layer SL1 through the second ion implantation process IIP2. Anti-dopants CD may reduce, suppress, or prevent the etching stop dopant ESD from diffusing into a well of the second semiconductor layer SL2 to be described later.

[0058] The counter dopant CD may include phosphorus (P), arsenic (As), or a combination thereof. For example, in the second ion implantation process IIP2, 1E13 / cm 2 As another example, in the second ion implantation process IIP2, arsenic (AS) may be implanted at a dose of 3E13 / cm 2 Phosphorus (P) is ion implanted with an energy of 400 KeV at a dose of 1.5 keV.

[0059] refer to Figure 1 and Figure 4C , the second semiconductor layer SL2 may be formed on the first semiconductor layer SL1. The formation of the second semiconductor layer SL2 may include performing a selective epitaxial growth (SEG) process on the first semiconductor layer SL1. For example, the second semiconductor layer SL2 may include silicon. By doping the second semiconductor layer SL2 with a well dopant WD, a well may be formed in the second semiconductor layer SL2. The first semiconductor layer SL1 and / or the second semiconductor layer SL2 may constitute the semiconductor layer SL.

[0060] refer to Figure 5 , the well dopant WD may have a maximum concentration in the second semiconductor layer SL2. In other words, the well dopant WD may form a well in the second semiconductor layer SL2. The anti-dopant CD may have a maximum concentration in the first semiconductor layer SL1. The etch stop dopant ESD may have a maximum concentration in the etch stop region ESR. The maximum concentration of the etch stop dopant ESD may be 1E19 / cm 3 To 5E21 / cm 3 in the range of 1E19 / cm 3 Up to about 5E21 / cm 3The maximum concentration of the anti-dopant CD can be 1E18 / cm 3 To 5E20 / cm 3 in the range of 1E18 / cm 3 Up to about 5E20 / cm 3 The maximum concentration of the counter dopant CD may be less than the maximum concentration of the etch stop dopant ESD.

[0061] refer to Figure 1 and Figure 4D , an upper portion of the second semiconductor layer SL2 may be patterned to form a first trench TR1 extending in the second direction D2. The first trench TR1 may define a first active pattern FN1 and / or a second active pattern FN2 in an upper portion of the second semiconductor layer SL2. The first active pattern FN1 and / or the second active pattern FN2 may be arranged along the first direction D1.

[0062] The upper portion of the second semiconductor layer SL2 may be patterned to form a second trench TR2 defining the first active region PR and the second active region NR. While the second trench TR2 is formed, the active pattern FN1 and / or FN2 may be removed in the region where the second trench TR2 is formed. The second trench TR2 may be deeper than the first trench TR1.

[0063] A device isolation layer ST may be formed to fill the first trench TR1 and / or the second trench TR2. The device isolation layer ST may be formed using silicon oxide.

[0064] refer to Figure 1 and Figure 4E , the device isolation layer ST may be patterned to form a first hole HO1 between a pair of first active regions PR adjacent to each other. The device isolation layer ST may be patterned to form a second hole HO2 between a pair of second active regions NR adjacent to each other. The first hole HO1 and / or the second hole HO2 may be simultaneously formed by using the same photolithography process.

[0065] Each of the first hole HO1 and / or the second hole HO2 may expose the bottom surface of the second trench TR2. When the first hole HO1 and / or the second hole HO2 are formed, the exposed bottom surface of the second trench TR2 may be recessed by over-etching. The first hole HO1 and / or the second hole HO2 may extend parallel to each other in the second direction D2.

[0066] The first power rail POR1 and / or the second power rail POR2 may be formed in the first hole HO1 and / or the second hole HO2, respectively. The formation of the first power rail POR1 and / or the second power rail POR2 may include forming a conductive layer filling the first hole HO1 and / or the second hole HO2 and recessing the conductive layer.

[0067] refer to Figure 1 and Figure 4F , an insulating layer may be deposited on the device isolation layer ST to completely fill the first hole HO1 and / or the second hole HO2. The insulating layer and / or the device isolation layer ST may be recessed until upper portions of the first active pattern FN1 and the second active pattern FN2 are exposed.

[0068] The first source / drain region SD1 may be formed at an upper portion of the first active pattern FN1. The second source / drain region SD2 may be formed at an upper portion of the second active pattern FN2. The first source / drain region SD1 may be doped with a P-type dopant, and the second source / drain region SD2 may be doped with an N-type dopant.

[0069] The first source / drain region SD1 and / or the second source / drain region SD2 may include an epitaxial pattern formed by a selective epitaxial growth (SEG) process. In detail, portions of the first active pattern FN1 and / or the second active pattern FN2 may be recessed, and then, a SEG process may be performed on the recessed regions of the first active pattern FN1 and / or the second active pattern FN2 to form the epitaxial pattern. A first upper insulating layer UIL1 may be formed to cover the first source / drain region SD1 and / or the second source / drain region SD2.

[0070] refer to Figure 1 , Figure 2A and Figure 2C , a gate electrode GE extending in the first direction D1 may be formed to intersect the first active pattern FN1 and / or the second active pattern FN2. A gate dielectric layer GI may be formed under the gate electrodes GE, respectively. A gate spacer GS may be formed on both sidewalls of each of the gate electrodes GE. A gate capping layer CP may be formed on the gate electrodes GE, respectively.

[0071] refer to Figure 1 and Figure 4G , the second upper insulating layer UIL2 may be formed on the first upper insulating layer UIL1. The active contact AC may be formed to penetrate the first upper insulating layer UIL1 and / or the second upper insulating layer UIL2. The active contact AC may be formed on the first source / drain region SD1 and / or the second source / drain region SD2.

[0072] At least one active contact AC may be formed to be electrically connected to the first power rail POR1 and / or the second power rail POR2. For example, the formation of the at least one active contact AC may include forming a first contact hole exposing the first power rail POR1 and / or the second power rail POR2, forming a second contact hole exposing the first source / drain region SD1 and / or the second source / drain region SD2, and forming an extension portion EP and / or a body portion BP in the first contact hole and / or the second contact hole, respectively.

[0073] The third upper insulating layer UIL3 and / or the fourth upper insulating layer UIL4 may be formed on the second upper insulating layer UIL2. The first upper interconnection line UML1 may be formed in the third upper insulating layer UIL3, and / or the second upper interconnection line UML2 may be formed in the fourth upper insulating layer UIL4. Even though not shown in the figure, a plurality of metal layers stacked on the fourth upper insulating layer UIL4 may be additionally formed.

[0074] refer to Figure 1 and Figure 4H , the substrate SUB may be turned over in such a manner that the bottom surface of the substrate SUB is exposed. In other words, the substrate SUB may be turned over in such a manner that the second surface SLb of the semiconductor layer SL faces upward.

[0075] A wet etching process may be performed on the substrate SUB to etch the substrate SUB. The wet etching process may be performed until the etching stop region ESR of the substrate SUB is exposed. In detail, the etching stop region ESR may have an etching selectivity with respect to the substrate SUB formed of silicon. Therefore, in the wet etching process, the substrate SUB formed of silicon may be selectively etched, but the etching stop region ESR including the etching stop dopant ESD may not be etched but may remain.

[0076] In the method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept, the wet etching process can be easily controlled by the etching stop region ESR. In other words, the etching dispersion of the substrate SUB can be reduced. Therefore, the process defects (damage) of the first active region PR and the second active region NR can be reduced or prevented, and the power delivery network PON to be described later can be stably formed on the second surface SLb of the semiconductor layer SL.

[0077] refer to Figure 1 and Fig. 4I , a planarization process may be performed on the etch stop region ESR until the second surface SLb of the semiconductor layer SL is exposed. The etch stop region ESR may be removed by the planarization process. A portion of the first semiconductor layer SL1 may also be removed by the planarization process.

[0078] refer to Figure 1 and Figure 4J , a through-hole TVI extending from the second surface SLb of the semiconductor layer SL to the first surface SLa may be formed. For example, the formation of the through-hole TVI may include performing an etching process on the second surface SLb of the semiconductor layer SL to form a through-hole exposing the first power rail POR1 and / or the second power rail POR2, and forming the through-hole TVI in the through-holes, respectively.

[0079] The first lower insulating layer LIL1 and / or the second lower insulating layer LIL2 may be formed on the second surface SLb of the semiconductor layer SL. The first lower interconnection line LML1 may be formed in the first lower insulating layer LIL1 and / or the second lower interconnection line LML2 may be formed in the second lower insulating layer LIL2.

[0080] The first lower interconnect line LML1 and / or the second lower interconnect line LML2 may constitute a power delivery network PON. The power delivery network PON may be electrically connected to the first power rail POR1 and / or the second power rail POR2 through a through-hole TVI. The power delivery network PON may apply a power supply voltage (VDD) and / or a ground voltage (VSS) to the first power rail POR1 and / or the second power rail POR2, respectively.

[0081] Figure 6 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept. Fig. 7A and Figure 7B Along Figure 6 In this example embodiment, for the purpose of ease and convenience of explanation, the cross-sectional view taken along the lines II-I' and II-II' will be omitted or briefly mentioned. Figures 1 to 3 In other words, the following will mainly describe the present exemplary embodiment and Figures 1 to 3 The differences between the example embodiments of FIG.

[0082] refer to Figure 6 , Fig. 7A and Figure 7B , the first power rail POR1 and / or the second power rail POR2 may be provided in the third upper insulating layer UIL3. In other words, the first power rail POR1 and / or the second power rail POR2 and / or the first upper interconnection line UML1 may constitute a first metal layer. The first power rail POR1 and / or the second power rail POR2 may extend parallel to each other in the second direction D2.

[0083] At least one active contact AC may be electrically connected to the first power rail POR1 and / or the second power rail POR2. The at least one active contact AC may be electrically connected to the first power rail POR1 and / or the second power rail POR2 through an upper via UVI thereon.

[0084] The through-hole TVI may extend vertically from the second surface SLb of the semiconductor layer SL to the third upper insulating layer UIL3. The through-hole TVI may sequentially penetrate the semiconductor layer SL, the device isolation layer ST, the first upper insulating layer UIL1, and / or the second upper insulating layer UIL2. The through-hole TVI may be electrically connected to the first power rail POR1 and / or the second power rail POR2, respectively. For example, the through-hole TVI may be in direct contact with the first power rail POR1 and / or the second power rail POR2, respectively.

[0085] The through-hole TVI can vertically connect the first power rail POR1 and / or the second power rail POR2 of the first metal layer to the power delivery network PON below the semiconductor layer SL. The power supply voltage (VDD) and / or the ground voltage (VSS) can be applied to the first power rail POR1 and / or the second power rail POR2 respectively through the through-hole TVI.

[0086] In the semiconductor device according to some example embodiments of the inventive concepts, the power delivery network PON may be stably formed on the second surface SLb of the semiconductor layer SL. As a result, the reliability and / or integration density of the semiconductor device may be improved.

[0087] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above-described example embodiments are not restrictive, but illustrative. Therefore, the scope of the inventive concept will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be constrained or limited by the foregoing description.

Claims

1. A semiconductor device, comprising: a semiconductor layer having a first surface and a second surface opposite to the first surface; an active pattern on the first surface, the active pattern comprising a source / drain region; a power rail electrically connected to the source / drain region; and a power delivery network on the second surface, the power delivery network being electrically connected to the power rail, wherein the semiconductor layer includes an etch stop dopant, and the etch stop dopant having a maximum concentration at the second surface, wherein the semiconductor layer further comprises an anti-dopant, and The antidopant has a maximum concentration at the second surface.

2. The semiconductor device according to claim 1, further comprising: a through hole extending from the second surface to the first surface, Wherein, the through-hole electrically connects the power rail to the power delivery network. 3 . The semiconductor device of claim 1 , wherein the etch stop dopant comprises boron (B), carbon (C), or a combination thereof.

4. The semiconductor device of claim 1 , wherein the maximum concentration of the etch stop dopant has a value from 1E18 / cm 3 To 5E20 / cm 3 range. 5 . The semiconductor device of claim 1 , wherein the counterdopant comprises phosphorus (P), arsenic (As), or a combination thereof.

6. The semiconductor device of claim 1, wherein the power delivery network comprises: a lower insulating layer on the second surface; and A lower interconnection line in the lower insulating layer.

7. The semiconductor device according to claim 1, further comprising: a device isolation layer on the first surface, the device isolation layer defining the active pattern, Wherein, the power rail is in the device isolation layer.

8. The semiconductor device according to claim 1, further comprising: an upper insulating layer on the first surface, the upper insulating layer covering the active pattern; and An upper interconnection line in the upper insulating layer.

9. The semiconductor device of claim 8, wherein the power rail is in the upper insulating layer.

10. The semiconductor device of claim 1, wherein the source / drain region comprises: a first source / drain region; and a second source / drain region, wherein The first source / drain region has a first lattice constant greater than a second lattice constant of the semiconductor layer, and The second source / drain region has the second lattice constant equal to the second lattice constant of the semiconductor layer.

11. The semiconductor device of claim 1 , wherein the source / drain region comprises: a first source / drain region; and a second source / drain region, wherein A first cross-sectional shape of the first source / drain region is different from a second cross-sectional shape of the second source / drain region.

12. A semiconductor device comprising: a semiconductor layer having a first surface and a second surface opposite to the first surface; transistors on the first surface; an upper insulating layer on the transistor; an upper interconnection line in the upper insulating layer; a lower insulating layer on the second surface; and a lower interconnection line in the lower insulating layer, wherein the semiconductor layer includes an etch stop dopant, and a concentration of the etch stop dopant decreases from the second surface to the first surface, wherein the semiconductor layer further comprises an anti-dopant, and The concentration of the antidopant decreases from the second surface to the first surface.

13. The semiconductor device of claim 12, wherein the etch stop dopant comprises boron (B), carbon (C), or a combination thereof.

14. The semiconductor device according to claim 12, wherein The etch stop dopant has a maximum concentration at the second surface, and The maximum concentration has a value from 1E18 / cm 3 To 5E20 / cm 3 range.

15. A semiconductor device comprising: a semiconductor layer having a first surface and a second surface opposite to the first surface; transistors on the first surface; a lower insulating layer on the second surface; and a lower interconnection line in the lower insulating layer, wherein the semiconductor layer includes an etch stop dopant, and The concentration of the etch stop dopant increases from the first surface to the second surface, has a maximum value at the second surface, and decreases sharply in the lower insulating layer, wherein the semiconductor layer further comprises an anti-dopant, and The concentration of the antidopant increases from the first surface to the second surface and has a maximum value at the second surface.

16. The semiconductor device according to claim 15, further comprising: a power rail electrically connected to the transistor; and a through hole extending from the second surface to the first surface, wherein the through via electrically connects the power rail to the lower interconnect line.

17. The semiconductor device of claim 15, wherein the etch stop dopant comprises boron (B), carbon (C), or a combination thereof.

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