Storage device and method for writing data

Abstract

A storage device and a data writing method. The storage device can be applied to a neural network. The storage device includes a memristor unit, a current limiting circuit and a write circuit. The memristor unit is a one-transistor one-resistance memory 1T1R structure. The current limiting circuit is used to limit the current passing through the memristor unit to a target current, wherein the target current is determined according to the target conductance of the memristor unit and the gate voltage of the transistor, and the target conductance is used to indicate the target data to be written into the memristor unit. The write circuit is used to load a write voltage to the memristor unit in cooperation with the current limiting circuit to write the target data into the memristor unit.

Description

Technical Field

[0001] The present application relates to the field of storage, and more specifically, to a storage device and a method for writing data. Background Art

[0002] Memristor, whose full name is memory resistor (Memristor), is a circuit device that represents the relationship between magnetic flux and charge. The memristor unit has the dimension of conductance, but unlike conductance, the resistance of the memristor is determined by the charge flowing through the memristor. When the memristor loses power, the conductance of the memristor will not change, that is, the memristor has a memory function. If the high resistance state of the memristor is defined as "1" and the low resistance state is defined as "0", the memristor can realize the data storage function through its own resistance. At present, in the process of use, a one-transistor and one-resistive random access memory (1T1R) structure is usually used. 1T1R can be called a memristor unit.

[0003] In writing data, due to the device-to-device variation and the cycle-to-cycle variation of the same memristor in different programming cycles, when the same pulse voltage is used to adjust the conductance of different memristor units, the change in conductance of each memristor unit is usually different. For a memristor unit, when the same pulse voltage is used to adjust the conductance of the memristor unit in different programming cycles, the change in conductance of the memristor unit adjusted in each programming cycle is also different.

[0004] In order to improve the accuracy and speed of conductance adjustment, the incremental step pulse programming (ISPP) technology provides a "read verification-correction" method to adjust the conductance of the target memristor unit. That is, after each pulse (set pulse or reset pulse) is loaded to the target memristor unit to adjust the conductance of the target memristor unit, the adjusted conductance is read by a read pulse, and this cycle is repeated until the conductance of the target memristor unit is adjusted to the target conductance, and the adjustment process ends. However, using the above-mentioned ISPP technology, each adjustment of the conductance of a memristor unit requires a large number of "read verification-correction" processes, resulting in a very long time to adjust the conductance. Summary of the invention

[0005] The present application provides a storage device and a programming method based on the storage device, which is beneficial to reducing the time occupied by adjusting the conductance of a memristor unit and improving the speed of writing data to the memristor unit.

[0006] In a first aspect, a storage device is provided, comprising: a memristor unit, wherein the memristor unit is a one-transistor one-resistance variable memory 1T1R structure; a current limiting circuit, used to limit the current passing through the memristor unit to a target current, wherein the target current is determined according to a target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit; and a write circuit, used to load a write voltage to the memristor unit in cooperation with the current limiting circuit to write the target data into the memristor unit.

[0007] In the embodiment of the present application, the current flowing through the memristor unit is limited to the target current by the current limiting circuit, wherein the target current is the current that can make the conductance of the memristor unit the target conductance, and then the write voltage is applied to the memristor unit through the write circuit to adjust the conductance of the memristor unit to the target conductance. Therefore, in the process of writing data, due to the existence of the current limiting circuit, when the memristor unit writes data according to the write pulse, the conductance of the memristor unit will not exceed the target conductance and need to be constantly corrected. This avoids the "read verification-correction" method used in the prior art and reduces the time taken to write data to the memristor unit.

[0008] In a possible implementation, the target current I, the write voltage V b , the target conductance G and the drain voltage V of the transistor d Satisfy the formula

[0009] In the embodiment of the present application, the target conductance G and the write voltage V b Under certain circumstances, the target current is determined according to the target conductance, so that the current limiting circuit limits the current flowing through the memristor unit to the target current, that is, the conductance of the memristor unit can be adjusted to the current of the target conductance.

[0010] In one possible implementation, the current limiting circuit includes a current mirror, which includes a first branch and a second branch connected in parallel, the second branch is connected to the memristor unit, the current passing through the first branch is the target current, and the current mirror is used to copy the target current from the first branch to the second branch to limit the current flowing through the memristor unit to the target current.

[0011] In the embodiment of the present application, a current limiting circuit including a current mirror is used to limit the current flowing through the memristor unit, which is helpful to simplify the structure of the current limiting circuit.

[0012] Optionally, the current limiting circuit further includes a current source, wherein the current source is used to provide a plurality of currents, wherein the plurality of currents include the target current.

[0013] In a possible implementation, the current limiting circuit provides a plurality of currents for the memristor unit, different currents in the plurality of currents correspond to different conductances of the memristor unit, and the plurality of currents include the target current.

[0014] In an embodiment of the present application, the current limiting circuit can provide multiple currents for the memristor unit. Under different current conditions, the conductance of the memristor unit can have different conductance values, representing different data, which is helpful in assisting the memristor unit to store different data.

[0015] In a possible implementation, the first conductance G of the plurality of conductances max The conductance value is the largest, and the write voltage is less than the preset first write voltage threshold V bmax , wherein the first write voltage threshold V bmax Satisfy the formula I max represents modulating the conductance of the memristor unit to the first conductance G max Required current.

[0016] Optionally, the write voltage is greater than or equal to an estimated mutation voltage of the resistive memory, wherein the estimated mutation voltage is higher than a real mutation voltage of the memristor unit.

[0017] In the embodiment of the present application, the write voltage is limited to be greater than or equal to the estimated mutation voltage of the resistive memory, so as to ensure that a voltage mutation occurs in the resistive memory.

[0018] In a possible implementation, the second conductance G′ among the multiple conductances of the memristor unit corresponding to the multiple currents max The conductance value is the largest, and the second write voltage threshold V' b max Satisfy the formula Indicates that the conductance of the memristor unit is modulated to the second conductance The required current, if the second write voltage threshold is less than the estimated mutation voltage of the resistive memory, then the write voltage is the estimated mutation voltage, and the estimated mutation voltage is higher than the actual mutation voltage of the memristor unit.

[0019] In the embodiment of the present application, if the second write voltage threshold is less than the estimated mutation voltage of the resistive memory, the write voltage may be equal to the estimated mutation voltage to ensure that a voltage mutation occurs in the resistive memory.

[0020] It should be noted that the estimated mutation voltage may be based on the sum of the statistical results of the voltages of a plurality of resistive memory devices and a voltage threshold, wherein the voltage threshold may be any value, such as 0.2V.

[0021] In a second aspect, a storage device is provided, comprising: a storage array, the storage array comprising a plurality of memristor units, the plurality of memristor units being a one-transistor one-resistive memory 1T1R structure; a current limiting circuit, used to limit the current passing through a target memristor unit among the plurality of memristor units to a target current, wherein the target current is determined according to a target conductance of the target memristor unit and a gate voltage of the transistor, the target conductance being used to indicate target data to be written into the memristor unit; and a write circuit, used to load a write voltage to the target memristor unit in cooperation with the current limiting circuit to write the target data into the target memristor unit.

[0022] In a possible implementation, the target current I, the write voltage V b , the target conductance G and the drain voltage V of the transistor d Satisfy the formula

[0023] In a possible implementation, the storage device further includes: a gating circuit, wherein the gating circuit is used to gating the target memristor unit from the storage array.

[0024] In one possible implementation, the current limiting circuit includes a current mirror, which includes a first branch and multiple second branches, each of the multiple second branches is connected to a memristor unit in the storage array, the current passing through the first branch is the target current, and the current mirror is used to copy the target current from the first branch to a target second branch among the multiple second branches to limit the current flowing through the target memristor unit in the target second branch to the target current.

[0025] In a third aspect, a method for writing data is provided, the method being used to write data to a memristor unit, the memristor unit being a one-transistor one-resistive memory 1T1R structure, the method comprising: limiting a current passing through the memristor unit to a target current through a current limiting circuit, wherein the target current is determined based on a target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit; and, in cooperation with the current limiting circuit, applying a write voltage to the memristor unit through a write circuit to write the target data into the memristor unit.

[0026] In a possible implementation, the target current I, the write voltage V b , the target conductance G and the drain voltage V of the transistor d Satisfy the formula BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the mapping relationship between the neural network and the cross array.

[0028] Figure 2 It is a schematic diagram of the process of writing target data to the target memristor based on the ISPP strategy.

[0029] FIG3( a ) is a schematic diagram of a memristor unit of a 1T1R structure.

[0030] FIG3( b ) is a schematic diagram of another memristor unit with a 1T1R structure.

[0031] Figure 4 It is a schematic diagram of the current-voltage characteristic curve of a transistor.

[0032] Figure 5 is a schematic diagram of the current-voltage characteristic curve of RRAM.

[0033] Figure 6 Schematic diagram of the current-voltage characteristic curve of the 1T1R memristor unit.

[0034] Figure 7 It is a schematic diagram of a storage device according to an embodiment of the present application.

[0035] Figure 8 It is a schematic diagram of a storage device provided in an embodiment of the present application.

[0036] Fig. 9 It is a schematic diagram of a storage device provided in an embodiment of the present application.

[0037] Fig.10 It is a schematic diagram of a storage device according to an embodiment of the present application.

[0038] Fig.11 A schematic diagram of a storage device according to an embodiment of the present application is shown.

[0039] Fig.12 A schematic diagram of a storage device according to an embodiment of the present application is shown.

[0040] Fig.13 A schematic diagram of a storage device according to another embodiment of the present application is shown.

[0041] Fig.14 It is a schematic flow chart of a programming method for a storage device according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will describe the technical solution in this application in conjunction with the accompanying drawings. Figure 1, taking the implementation of the function of a neural network through a crossbar array as an example, the application scenario of the embodiment of the present application is introduced. It should be noted that the embodiment of the present application is also applicable to other neural networks, such as convolutional neural networks, etc. The embodiment of the present application can also be applied to the scenario of using a memristor unit alone to store data.

[0043] Figure 1 It is a schematic diagram of the mapping relationship between the neural network and the cross array. The neural network 110 includes multiple neural network layers. In the embodiment of the present invention, the neural network layer is a logical layer concept, and a neural network layer refers to a neural network operation to be performed. Each layer of neural network calculation is implemented by a computing node (also called a neuron). In practical applications, the neural network layer may include a convolution layer, a pooling layer, etc.

[0044] Those skilled in the art know that when performing neural network calculations (e.g., convolution calculations), the computing nodes in the neural network system can calculate the input data and the weights of the corresponding neural network layer. In a neural network system, weights are usually represented by a real number matrix, and each element in the weight matrix represents a weight value. Since the computing nodes of the neural network system can use a resistive random access memory (ReRAM) composed of a resistive random access memory crossbar (ReRAM crossbar) for calculation, and since ReRAM has the advantage of integrated storage and calculation, the weights can be configured on the ReRAM cells of the ReRAM crossbar before calculation. In practical applications, computing nodes that perform calculations on the same neural network layer can share weights, and the weights of computing nodes that perform calculations on different neural network layers may be different. In an embodiment of the present invention, the weights of each computing node can be completed by prior configuration.

[0045] For the sake of convenience, the data processing process is introduced by taking the first neural network layer in the neural network 110 as an example. In the neural network system, the first neural network layer can be any layer in the neural network system. For the sake of convenience, the first neural network layer can be referred to as the "first layer".

[0046] Figure 1 Take a ReRAM crossbar in a computing node as an example. The computing node can be used to perform calculations on the first neural network layer. Figure 1 The crossbar array 120 shown is an m×n crossbar array, wherein the bit lines of each column of the memristor unit are i (bit line i , B.L. i ) are connected together, and the word lines of each row of memristor cells j(word line j , W.L. j ) are connected together. In the process of executing neural network calculations, n input data V i Can be loaded into BL i The pulse or input voltage is represented by, for example Figure 1 In: V1, V2, V3, ... Vn. The weights in the weight matrix can be obtained by i With WL j The conductance of the memristor unit at the intersection is represented. Different conductances of memristor units can indicate different weights stored in the memristor units. The computing node calculates the received input data V1, V2, V3, ... Vn with the weights configured in the computing node, and obtains Figure 1 The m output data shown in 112 in FIG. The m output data can be obtained through the source line i (source line i , SL i ) represents the current on the Figure 1 In: I1,I2,…Im.

[0047] The following takes writing target data to the target memristor cell located at the intersection of BL1 and WL1 as an example to introduce the set operation and the reset operation. The set operation is used to adjust the conductance of the memristor cell from low conductance to high conductance, and the reset operation is used to adjust the conductance of the memristor cell from high conductance to low conductance.

[0048] Assume that the target memristor unit R 11 The target conductance range can be expressed as the target weight W 11 When writing W to the target memristor cell 11 In the process of adjusting the current conductance of the target memristor unit, if the current conductance of the target memristor unit is lower than the lower limit of the target conductance range, the conductance of the target memristor unit can be increased by the set operation. At this time, the gate voltage of the transistor in the target memristor unit to be adjusted can be applied to turn on the transistor through WL1, so that the target memristor unit is in the gated state. At the same time, the SL1 connected to the target memristor unit and other BLs in the cross array are also grounded, and then a set pulse is applied to the BL1 where the target memristor unit is located to adjust the conductance of the target memristor unit.

[0049] On the contrary, if the current conductance of the target memristor unit is higher than the upper limit of the target conductance range, the conductance of the target memristor unit can be reduced by a reset operation. At this time, a voltage can be applied to the gate of the transistor in the target memristor unit that needs to be adjusted through WL1, so that the target memristor unit is in a gated state. At the same time, BL1 connected to the target memristor unit and other WLs in the cross array are grounded. Then, a reset pulse is applied to SL1 where the target memristor unit is located to adjust the conductance of the target memristor unit.

[0050] The following is based on Figure 1 The cross array and set and reset operations introduced are combined with Figure 2 The process of writing target data to a target memristor unit based on the incremental step programming pulse (ISPP) strategy is introduced. The target memristor unit is any memristor unit in the above cross array. In the process of writing target data to the target memristor unit, the ISPP strategy usually uses a "read verification-correction" method to adjust the conductance of the target memristor unit, so that the conductance of the target memristor unit is finally adjusted to the target conductance corresponding to the target data.

[0051] First, a read pulse is applied to the target memristor unit to read out the current conductance of the target memristor unit and compare it with the target conductance. If the current conductance is less than the target conductance, a first set pulse can be loaded to the target memristor unit to increase the conductance of the target memristor unit so that the conductance of the target memristor unit is adjusted to the target conductance, and then the adjusted conductance, i.e., the first conductance, is read through the read pulse. If the first conductance is still less than the target conductance, a second set pulse can be loaded to the target memristor unit, the pulse width of the second set pulse is the same as the pulse width of the first set pulse, but the amplitude of the second set pulse is greater than the amplitude of the first set pulse, and an enhanced set operation is performed, and the conductance of the target memristor unit, i.e., the second conductance, is continued to be read through the read pulse. If the second conductance is greater than the target conductance, a first reset pulse can be loaded to the target memristor unit to increase the second conductance so that the second conductance is adjusted to the target conductance. The above process of adjusting the conductance by “read verification-correction” is completed until the conductance of the target memristor unit read out by the read pulse is within a certain error range of the target conductance.

[0052] Based on the above introduction, the ISPP technology aims to adjust the conductance of the target memristor unit to the target conductance through such a large number of "read verification-correction" processes. However, each time the conductance of a memristor unit is adjusted, a large number of "read verification-correction" processes are required, resulting in a very long time to adjust the conductance.

[0053] In order to reduce the time taken to adjust the conductance of a target memristor unit, the present application provides a storage device that utilizes the electrical characteristics of a memristor unit with a 1T1R structure to limit the current flowing through the memristor unit through a current limiting circuit so that the conductance value of the memristor unit reaches the target conductance value without the need for read verification.

[0054] For ease of understanding, the following first introduces the 1T1R structure memristor unit and the process of applying the set voltage to the memristor unit in conjunction with FIG. 3(a), and then Figures 4 to 6 The electrical characteristics of the memristor unit of the 1T1R structure are introduced. FIG3(a) is a schematic diagram of the memristor unit of the 1T1R structure. The memristor unit 300 shown in FIG3(a) includes a resistive random access memory (RRAM) 310 and a transistor (T) 320. Among them, the RRAM 310 is connected in series with the transistor 320, and the drain (drain, D) of the transistor 320 is connected to the bottom electrode (bottom electrode, BE) of the RRAM 310. In the set operation, the source (source, S) of the transistor is grounded, that is, the source voltage V S =0. V b Indicates the pulse voltage used in the set operation.

[0055] For transistor 320, a voltage V is applied to the memristor unit. b After that, the current-voltage characteristic curve of the transistor satisfies the formula:

[0056] I D =f(V GS ,V DS ) (1)

[0057] Among them, I D represents the current flowing through the drain of the transistor, V GS Represents the gate-source voltage of the transistor, V DS represents the drain-source voltage applied to the transistor, and f() represents the functional relationship. The specific current-voltage characteristic curve of the transistor can be found in Figure 4 .

[0058] from Figure 4 It can be seen that the working area of ​​the transistor can be divided into two regions, namely the triode region (TriodeRegion), also known as the "linear region", and the saturation region (Saturation Region). Figure 4 The dashed line in the figure indicates the boundary between the linear region and the saturation region. DS <V GS -V TWhen V DS >V GS -V T When the transistor works in the saturation region, V T Indicates the turn-on voltage of the transistor. GS When the value of is different, the current range of the linear region of the transistor is different.

[0059] For RRAM 310, V is loaded to the RRAM. b After that, the current-voltage characteristic curve of RRAM satisfies the formula:

[0060] I d,M =G(V b -V d )=-G(V d -V b ) (2)

[0061] Where G represents the conductance of RRAM. The specific current-voltage characteristic curve of RRAM can be found in Figure 5 .

[0062] For formula (1), since V S =0, and V DS =V d -V S , then V DS =V d Furthermore, the transistor 320 and the RRAM 310 are connected in series, and the current I flowing through the transistor D The current I flowing through the RRAM d,M Equal, that is, I D =I d,M =I d .therefore, Figure 4 The performance curves and Figure 5 The performance curves in the d and V d The coordinate system represented by Figure 6 Similarly, V S =0, and V GS =V g -V S , then V GS =V g .from Figure 6 It can be seen that when the set pulse voltage is given by V b , the gate voltage of the transistor is V g If during the set process, I d The current is limited to I1, I2, and I3 respectively. Based on the characteristics of the linear region, the voltage of the transistor corresponding to I1, I2, and I3 can be determined as Vd1 ,V d2 ,V d3 The initial state of RRAM is a low conductance state. In the process of adding set pulses to modulate the conductance, its conductance gradually increases, and I gradually increases. The final current values ​​that can be reached are I1, I2, and I3 respectively. The conductance of RRAM is G1, G2, and G3 respectively, which is Figure 6 The absolute values ​​of the slopes of the three straight lines shown are: Therefore, the RRAM conductance value can be determined according to formula (3).

[0063]

[0064] The embodiments of this application are based on Figure 6 The current-voltage characteristics of the 1T1R memristor unit shown in Figure 1 are given by V b and V g After that, different currents flowing through the memristor unit correspond to different conductance values ​​of the memristor unit. Based on the above characteristics, an embodiment of the present application provides a storage device, which limits the current flowing through the memristor unit to a target current through a current limiting circuit in the storage device, and then applies a write voltage to the memristor unit to adjust the conductance of the memristor unit to the target conductance corresponding to the target current, thereby avoiding the "read verification" process introduced above, so as to reduce the time occupied by adjusting the conductance of the memristor unit.

[0065] It should be noted that the current-voltage characteristic curves introduced above based on formulas (1) to (3) are also applicable to the 1T1R structure memristor unit 350 shown in Figure 3(b). The same numbering is used for the same components in Figure 3(b) as in Figure 3(a). The drain (drain, D) of the transistor 320 in Figure 3(b) is connected to the top electrode (top electrode, TE) of the RRAM 310. Accordingly, the write voltage can be loaded from the BE of the RRAM 310 to the memristor, and the source of the transistor is still grounded. Therefore, the transistor still satisfies V S =0, V DS =V d And, the current I flowing through the transistor D The current I flowing through the RRAM d,M Based on this, the current-voltage characteristic curve of the transistor and the current-voltage characteristic curve of the RRAM can be obtained by using I d and V d The constructed coordinate system is represented and satisfies the above formula (3).

[0066] The following is combined Figures 7 to 14When introducing the storage device of the embodiment of the present application, only the memristor unit shown in FIG. 3( a ) is used as an example for description, and the memristor unit in the above storage device may also be the memristor unit 350 shown in FIG. 3( b ). For the sake of brevity, no further description is given.

[0067] Figure 7 It is a schematic diagram of a storage device according to an embodiment of the present application. Figure 7 The illustrated memory device 700 includes a memristor cell 710 , a current limiting circuit 720 , and a write circuit 730 .

[0068] A memristor unit 710, wherein the memristor unit is a one-transistor one-resistive memory 1T1R structure;

[0069] a current limiting circuit 720, configured to limit the current passing through the memristor unit to a target current, wherein the target current is determined according to a target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit;

[0070] The write circuit 730 is used to apply a write voltage to the memristor unit in cooperation with the current limiting circuit to write the target data into the memristor unit.

[0071] The transistor may be an N-channel Metal Oxide Semiconductor (NMOS) transistor, or a P-channel Metal Oxide Semiconductor (PMOS) transistor.

[0072] The above-mentioned target current is determined according to the target conductance of the memristor unit and the gate voltage of the transistor. It can also be understood that when the write voltage and the gate voltage of the transistor are determined, the target current is the current corresponding to the target conductance, wherein the current corresponding to the target conductance is the intersection of the current-voltage characteristic curve of the transistor and the current-voltage characteristic curve of the RRAM.

[0073] When the above transistor operates in the linear region, the target current and the drain-source voltage of the transistor are approximately linearly related. When the write voltage is constant, the target current, the target conductance and the drain voltage of the transistor correspond one to one. In this way, the current flowing through the memristor unit can be controlled by the current limiting circuit, so that the memristor unit can be adjusted to the target conductance. For the structure of the memristor unit shown in Figure 3 (a), the conductance of the memristor unit can be adjusted by the set operation. For the structure of the memristor unit shown in Figure 3 (b), the conductance of the memristor unit can be adjusted by the reset operation.

[0074] For example, in the process of writing data to the memristor unit 300 shown in Figure 3(a), the initial state of the memristor unit is first adjusted to a high-resistance state (i.e., low conductance) through a reset operation, and then a write voltage, i.e., a set pulse, can be loaded to the memristor unit through a write circuit to adjust the memristor unit from a high-resistance state to a low-resistance state. At this time, as the number of set pulses loaded to the memristor unit increases, the resistance of the memristor unit continues to decrease, the conductance increases, and the current flowing through the memristor unit increases. However, due to the existence of the current limiting circuit, the maximum value of the current flowing through the memristor unit is the target current. Based on the correspondence between current and conductance, after the conductance of the memristor unit is adjusted to the target conductance corresponding to the target current, the conductance of the memristor unit will no longer change even if the set pulse continues to be loaded.

[0075] It should be noted that, in the above process of adjusting the conductance of the memristor unit by loading a set pulse, the process of adjusting the memristor unit from the initial conductance to the target conductance may include a process of loading a plurality of set pulses to the memristor unit. The number and pulse width of the loaded set pulses may be pre-configured based on the model of the memristor unit to ensure that the memristor unit can be adjusted from the initial conductance to the target conductance after a preset number of set pulses are loaded.

[0076] For another example, in the process of programming the memristor unit 350 shown in FIG3(b), the initial state of the memristor unit is adjusted to a low resistance state (i.e., high conductance), and a write voltage, i.e., a reset pulse, can be loaded to the memristor unit through a write circuit to adjust the memristor unit from a low resistance state to a high resistance state. At this time, as the number of reset pulses loaded to the memristor unit increases, the resistance of the memristor unit continues to increase, the conductance decreases, and the current flowing through the memristor unit decreases. However, due to the existence of the current limiting circuit, the minimum value of the current flowing through the memristor unit is the target current. Based on the correspondence between current and conductance, after the conductance of the memristor unit is adjusted to the target conductance corresponding to the target current, the conductance of the memristor unit will no longer change even if the reset pulse continues to be loaded.

[0077] It should be noted that, in the above process of adjusting the conductance of the memristor unit by loading a reset pulse, the process of adjusting the memristor unit from the initial conductance to the target conductance may include a process of loading a plurality of reset pulses to the memristor unit. The number and pulse width of the loaded reset pulses may be pre-configured based on the model of the memristor unit to ensure that the memristor unit can be adjusted from the initial conductance to the target conductance after loading a preset number of reset pulses.

[0078] It should be noted that the target conductance G is one of the multiple conductances that the memristor unit can provide, and the current required to modulate the conductance of the memristor unit to different conductances among the multiple conductances is different. In other words, the current flowing through the memristor unit limited by the current limiting circuit may include multiple target currents, each target current corresponds to a target conductance, and the conductance of the memristor unit may be multiple target conductances corresponding to the above multiple target currents, so as to achieve storage of multiple target data.

[0079] For example, Figure 6 In the example, the set pulse voltage is given as V b , the gate voltage of the transistor is V g When the current flowing through the memristor unit is limited to I1 by the current limiting circuit, the adjusted target conductance of the RRAM is G1, which is used to record the first target data. When the current flowing through the memristor unit is limited to I2 by the current limiting circuit, the adjusted target conductance of the RRAM is G2, which is used to record the second target data. When the current flowing through the memristor unit is limited to I3 by the current limiting circuit, the adjusted target conductance of the RRAM is G3, which is used to record the third target data.

[0080] There are many ways to implement the above current limiting circuit, and a current limiting circuit based on a current source and a current mirror can be used. The current mirror can be a MOS tube basic current mirror, a bipolar basic current mirror, a cascade current mirror, etc.

[0081] Figure 8 This is a schematic diagram of another storage device provided in an embodiment of the present application. Figure 8 The storage device 800 and Figure 7 Circuits with the same functions in the storage device 700 are numbered the same and will not be described again for brevity.

[0082] The current limiting circuit 720 includes a current mirror, which includes a first branch 810 (also called an input branch) and a second branch 820 (also called an output branch) connected in parallel. The second branch 820 is connected to the memristor unit 710. The current passing through the first branch 810 is the target current. The current mirror is used to limit the maximum current flowing through the memristor unit to the target current according to the target current.

[0083] The above-mentioned current mirror can be a MOS transistor basic current mirror, including a first MOS transistor 811 and a second MOS transistor 821. The first MOS transistor is located in the first branch 810, and the second MOS transistor is located in the second branch 820. Since the first branch and the second branch are connected in parallel, the first MOS transistor (see Figure 8 The source voltage of the second MOS tube (represented by P1) is Figure 8In the embodiment of the present invention, the source voltages of the first MOS tube and the second MOS tube are the same, and the gate of the first MOS tube is connected to the gate of the second MOS tube and short-circuited. In this way, when the gate voltage and the source voltage of the two MOS tubes are the same, based on the characteristics of the MOS tubes, it can be considered that the currents flowing through the two MOS tubes are the same, that is, the target current of the first direct current is the same as the current flowing through the second MOS tube.

[0084] Optionally, the current mirror can be connected to multiple second branches 820 through a gating circuit, each second branch is connected to multiple memristor units, so that multiple memristor units can be connected through multiple second branches to provide current limiting effect for multiple memristor units to adjust the conductance of multiple memristor units. For specific connection methods, please refer to the following introduction.

[0085] Because in the process of writing data, before the conductance of the memristor unit reaches the target conductance, the conductance of the memristor unit changes with the number of times the write voltage is applied, resulting in a slight difference between the current of the second branch and the current of the first branch, but when the conductance of the memristor unit changes to the target conductance, the current flowing through the second branch is the target current. The following takes the process of adjusting the conductance of the memristor unit 300 through the set operation as an example to introduce the working principle of the current mirror.

[0086] After the reset operation, the memristor unit is in a high-resistance state, and the current conductance of the memristor unit is less than the target conductance. It is necessary to adjust the memristor unit to a low-resistance state by loading a set pulse to the memristor unit. As the number of set pulses loaded increases, the resistance of the memristor unit decreases, the conductance increases, and the current flowing through the second branch increases. However, due to the limitation of the "reference current" (i.e., target current) provided by the first branch of the current mirror, the maximum value of the current on the second branch is the target current.

[0087] Accordingly, in the process of adjusting the conductance of the memristor unit 350 by the reset operation, the initial state of the memristor unit is a low-resistance state, and the current conductance of the memristor unit is greater than the target conductance, and it is necessary to adjust the memristor unit to a high-resistance state by loading a reset pulse to the memristor unit. As the number of reset pulses loaded increases, the resistance of the memristor unit increases, the conductance decreases, and the current flowing through the second branch decreases, but due to the limitation of the "reference current" (i.e., the target current) provided by the first branch of the current mirror, the minimum value of the current on the second branch is the target current.

[0088] It should be noted that Figure 8 Only some components in the current limiting circuit are shown. The current limiting circuit may also include other components, which is not limited in the embodiments of the present application.

[0089] Optionally, the storage device 700 may further include a programming control circuit 910 and a gate voltage generating circuit 920. The specific structure may be found in Fig. 9 It should be noted that Fig. 9 The storage devices shown are Figure 7 Storage devices shown have the same functions and are numbered the same.

[0090] The programming control module 910 is used to control the operation sequence of the entire programming process and the working mode of each circuit module. For example, the writing circuit is controlled to generate a voltage with an amplitude of V b The set pulse is controlled; the current limiting circuit is controlled to limit the current flowing through the memristor unit to the target current; and the gate voltage generating circuit is controlled to provide a voltage for the gate of the transistor.

[0091] It should be noted that, in the embodiment of the present application, the above-mentioned programming process includes the data writing process mentioned above.

[0092] Optionally, the programming control module 910 may also control the initialization circuit ( Fig. 9 (not shown) performs initialization (Forming) operation on the RRAM and controls the reset circuit ( Fig. 9 (not shown) performs a reset operation on the RRAM, etc.

[0093] The gate voltage generating module 920 is used to provide a variable gate voltage for the entire programming process, so as to be applied to the initialization operation, the set operation, and the reset operation, wherein the gate voltages required for the initialization operation, the set operation, and the reset operation are different.

[0094] For different memristor units, the current limiting range of the current limiting circuit, the setting conditions of the gate voltage of the transistor, and the write voltage V b The setting conditions need to be set based on the actual circuit conditions. The following article focuses on the setting conditions of the above three parameters.

[0095] 1. Current limiting range of current limiting circuit

[0096] Assume that the minimum value of the programmed target conductance is G min and the maximum value of the target conductance is G max , according to the formula Combining the RRAM and CMOS manufacturing processes, it can be roughly estimated that at a given gate voltage V g Linear region (V b -V d ) is (V b -V d ) forecast , and the above G min and G max , the predicted minimum current limit can be calculated as Therefore, the actual current limiting range that can be achieved by the current limiting circuit can be designed [I min ,I max ] can be greater than the predicted current range This leaves enough margin to ensure that the actual programmed conductivity limit value meets the requirements.

[0097] 2. Setting conditions of transistor gate voltage

[0098] based on Figure 4 It can be seen that the gate voltage V g The selection of is closely related to the size of the linear region of the transistor. Therefore, the setting condition of the gate voltage is mainly to ensure that the transistor is g Under the working conditions, the current range of the linear region of the IV characteristic curve can be divided into multiple current limiting values ​​to represent multiple target data through multiple target conductances. For example, if the data to be represented is 4 bits, there may be 2 4 = 16 different data need to be represented, and accordingly 16 different data need to correspond to 16 different target currents. Therefore, the linear region of the transistor needs to be able to divide 16 target currents, or it can be understood that a gate voltage V with a saturation current (i.e., the current corresponding to the transistor in the saturation region) large enough needs to be selected. g .

[0099] by Fig. 9 Taking the 1T1R structure shown in the figure as an example, the RRAM is connected to the drain of the transistor. When performing the set operation, the source of the transistor is grounded. Because the maximum current value of the actual writing data is limited by the current limiting circuit, even if the V g is the power supply voltage V of the corresponding transistor process DD , the saturation current that can be achieved is very large, but the programming power consumption is determined by the pulse voltage amplitude V b and current limiting value.

[0100] Considering that as the process feature size decreases, the operating voltage is also decreasing, and the maximum saturation current that the transistor can achieve is also decreasing, so in order to ensure that there is still enough current range, transistors with a power supply voltage below 3.3V can directly take V g =V DD , the power supply voltage of the transistor is above 3.3V, and V can be selected according to the actual application g ≤V DD , to ensure that the saturation current under the gate voltage is greater than the required maximum current limit value.

[0101] Assume that the maximum programming current limit value is I max , so that the saturation current I 饱和 =I max The gate voltage is V g th,V gThe value range is: V g th<V g ≤V DD .

[0102] 3. V b Setting conditions

[0103] The voltage amplitude of the set pulse is V b Mainly meet two requirements: 1) ensure that the RRAM resistance can be changed; 2) after loading into the memristor unit, the conductance of the memristor unit can reach the maximum conductance value G that needs to be programmed max .

[0104] 1) Ensure that RRAM can resist switching

[0105] First, ensure that the voltage amplitude of the set pulse V b Higher than the set operation mutation voltage V during the direct current (DC) scanning process of the RRAM device c (V change , V c ) to make the RRAM resistive.

[0106] Specifically, the V of RRAM can be determined by the following method: c :From the same batch of RRAM devices, randomly select different silicon wafers and 1T1R arrays on different wafers (die) for DC scanning test, and count the mutation voltages of enough devices. The maximum value of the mutation voltage is V c,max , then V b The minimum value needs to be greater than V c,max Generally, in order to ensure that the voltage mutation of RRAM occurs, a voltage greater than the maximum value of the mutation voltage (also called "estimated mutation voltage") can be taken based on the maximum value of the mutation voltage. For example, (V c,max +0.2)V to increase the probability of triggering RRAM voltage mutation. On the other hand, when V b The larger the value, the greater the power consumption of the storage device during programming. Usually, V b The maximum value is the transistor supply voltage V DD , that is (V c,max +0.2)V≤V b ≤V DD .

[0107] 2) After loading into the memristor unit, the conductance of the memristor unit can reach the maximum conductance value G that needs to be programmed max .

[0108] Theoretically, the minimum value of G can be close to 0, that is, RRAM is in a very high resistance state. The maximum value of G is usually related to V b Assume that V g =V DD , and the target conductivity It can be seen that G is an increasing function of current I, and G is V b Since I needs to be less than V g =V DD The maximum value of I is limited by V g , cannot increase infinitely. Therefore, the maximum value of G is related to V b related.

[0109] Assume that the maximum value of the target conductance is G max , then according to the formula V b,max =I max / G max +V d The V b The maximum value V b,max , when V b,max =V DD When V b The value range is: (V c,max +0.2)V≤V b ≤V b,max .

[0110] The V introduced above b The setting conditions of V are usually ideal. However, in the actual configuration process, the actual parameter setting of the memristor unit may affect V b The following mainly introduces V in three situations. b Assume that the current limiting range of the current limiting circuit is [I min ,I max ].

[0111] Case 1: When V b,max <(V c,max +0.2)V, V b =(V c,max +0.2)V.

[0112] It should be noted that if the current limit I max The maximum value of G that can be achieved is less than the maximum value of the target conductance G max In this case, if it is still required to achieve G max , it is necessary to increase the I max .

[0113] Case 2: When (V c,max +0.2)V≤V b,max ≤VDD When (V c,max +0.2)V≤V b ≤V b,max .

[0114] Case 3: When V b,max >V DD When V b =V DD .

[0115] The method of the embodiment of the present application can be applied to a storage array. Fig.10 The solution of the embodiment of the present application is introduced in a scenario where the solution is applied to a storage array. Fig.10 It is a schematic diagram of a storage device according to an embodiment of the present application. Fig.10 The storage device shown includes a storage array 1010, a current limiting circuit 720, and a write circuit 730. It should be noted that: Fig.10 The storage devices shown are Figure 7 Modules implementing the same functions in the storage device shown are numbered the same. For a detailed introduction, please refer to the above description, which will not be repeated here for the sake of brevity.

[0116] A memory array 1010, wherein the memory array includes a plurality of memristor units, and the plurality of memristor units are a one-transistor one-resistive memory 1T1R structure;

[0117] a current limiting circuit 720, configured to limit a current passing through a target memristor unit among the plurality of memristor units to a target current, wherein the target current is determined according to a target conductance of the target memristor unit and a gate voltage of a transistor in the target memristor unit, and the target conductance is used to indicate target data to be written into the memristor unit;

[0118] The write circuit 730 is used to apply a write voltage to the target memristor unit in cooperation with the current limiting circuit to write the target data into the target memristor unit.

[0119] The above-mentioned storage array can be a storage array in a memory, or a cross array that integrates storage and computing in a neural network processor, which is not limited in the embodiments of the present application.

[0120] Optionally, the storage device 1000 further includes a gating circuit, and the gating circuit is used to select the target memristor unit from the storage array.

[0121] Optionally, the gating circuit can gating multiple memristor units at one time, or the gating circuit can gating one memristor unit at one time. When the gating circuit gating multiple memristor units at the same time, the same target data can be written into the multiple memristor units at the same time by cooperating with the current limiting circuit.

[0122] Fig.11 It is a schematic diagram of a storage device according to an embodiment of the present application. Fig.11 The storage devices shown are Fig.10 The storage devices shown have the same functions and are numbered the same. Fig.11 The illustrated memory device 1100 includes a memory array 1010 , a current limiting circuit 720 , a write circuit 730 , and a gating circuit 1110 .

[0123] The gating circuit 1110 is used to gating the memristor unit to which data is to be written, so that the write circuit 730 can load a write voltage to the memristor unit, and the current limiting circuit 720 can limit the current flowing through the memristor unit.

[0124] Optionally, the current limiting circuit includes a current mirror, which includes a first branch and multiple second branches, each of the multiple second branches is connected to a memristor unit in the storage array, and the current passing through the first branch is the target current. The current mirror is used to copy the target current from the first branch to a target second branch among the multiple second branches to limit the current flowing through the target memristor unit connected to the target second branch to the target current.

[0125] Fig.12 A schematic diagram of a storage device according to an embodiment of the present application is shown. Fig.12 The storage devices shown are Fig.11 The storage devices shown have the same functions and are numbered the same. Fig.12 Only the Fig.11 The following is a description of the different components of the storage device shown. Fig.12 The focus is on introducing the functions of the gating circuit and the current limiting circuit.

[0126] Fig.12 The current limiting circuit in the storage device 1200 shown includes a current mirror 1210. The current mirror 1210 includes a first branch (also called an input branch) and a plurality of second branches (also called output branches) BL1, BL2, . . . , BL n The gate of the MOS transistor P1 in the first branch is short-circuited with the gates of the MOS transistors P2 in the second branches. According to the characteristics of the current mirror, the current flowing through the MOS transistors in the second branches can be limited to be equal to the current flowing through the MOS transistor in the first branch.

[0127] For example, taking the memristor unit 300 shown in Figure 3(a) as an example, by loading a set pulse voltage to the memristor unit 300 and adjusting the conductance of the memristor unit, the above-mentioned current mirror can limit the maximum current flowing through the MOS tubes of multiple second branches to be equal to the current flowing through the MOS tube of the first branch.

[0128] For another example, taking the memristor unit 350 shown in FIG3(b) as an example, by loading a reset pulse voltage to the memristor unit 350 and adjusting the conductance of the memristor unit, the above-mentioned current mirror can limit the minimum current flowing through the MOS tubes of the multiple second branches to be equal to the current flowing through the MOS tube of the first branch.

[0129] A gating circuit 1110, configured to select a target second branch from a plurality of second branches, wherein the target second branch is connected to a target memristor unit;

[0130] The first branch of the current mirror is used to limit the current of the target second branch to a target current.

[0131] Correspondingly, an embodiment of the present application also provides a connection method between a current mirror and a gating circuit, that is, the current mirror includes a first branch and a second branch, the drain of the MOS tube in the second branch is connected to multiple memristor units through the gating circuit 1110, the current of the first branch is the target current, and the current mirror is used to copy the target current from the first branch to the second branch to limit the maximum current flowing through the target memristor unit in the second branch to the target current.

[0132] Fig.13 A schematic diagram of a storage device according to another embodiment of the present application is shown. Fig.13 The storage devices shown are Fig.12 The storage devices shown have the same functions and are numbered the same. Fig.13 The focus is on introducing another way of connecting the gating circuit and the current limiting circuit.

[0133] Fig.13 The current limiting circuit 1210 in the storage device 1300 shown includes a current mirror. The current mirror 1210 includes a first branch (also called an input branch) and a second branch (also called an output branch). The second branch is connected to a plurality of memristor units through a gating circuit 1110. The connection between each memristor unit and the gating circuit is BL1, BL2, ..., BL n The gate of the MOS tube P1 in the first branch is short-circuited with the gate of the MOS tube P2 in the second branch. According to the characteristics of the current mirror, the maximum current flowing through the MOS tubes in the second branches is equal to the current flowing through the MOS tube in the first branch.

[0134] A gating circuit 1110, configured to select a target memristor unit from a plurality of memristor units connected to the second branch;

[0135] The first branch of the current mirror is used to limit the maximum value of the current flowing through the target memristor unit to a target current.

[0136] In the embodiment of the present application, a plurality of memristor units can share the MOS tube located in the second branch of the current mirror, which is helpful to reduce the number of components in the storage device.

[0137] Combination of the above Figures 1 to 13 The storage device of the embodiment of the present application is introduced. Fig.14 The method of the embodiment of the present application is introduced. It should be noted that: Fig.14 The method shown can be executed by the storage device introduced above. The principles on which the execution process is based and the selection of parameters have been introduced in detail above. For the sake of brevity, they will not be repeated below.

[0138] Fig.14 It is a schematic flow chart of a programming method for a storage device according to an embodiment of the present application. Fig.14 The method shown can be executed by a device having a control function, for example, Fig. 9 The programming controller circuit 910 in. Fig.14 The method shown includes steps 1410 to 1420 .

[0139] 1410. Limit the current passing through the memristor to a target current through a current limiting circuit, wherein the target current is determined based on a target conductance of the memristor and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor.

[0140] 1420 , in cooperation with the current limiting circuit, applying a write voltage to the memristor through a write circuit to write the target data into the memristor.

[0141] Optionally, as an embodiment, the target current I, the write voltage V, the target conductance G and the drain voltage V of the transistor are d Satisfy the formula

[0142] Optionally, as an embodiment, the current limiting circuit includes a current mirror, the current mirror includes a first branch and a second branch connected in parallel, the second branch is connected to the memristor unit, the current passing through the first branch is the target current, and the current mirror is used to copy the target current from the first branch to the second branch to limit the maximum current flowing through the memristor unit to the target current.

[0143] Optionally, as an embodiment, the current limiting circuit provides a plurality of currents for the memristor unit, different currents in the plurality of currents correspond to different conductances of the memristor unit, and the plurality of currents include the target current.

[0144] Optionally, as an embodiment, the first conductance G of the plurality of conductancesmax The conductance value is the largest, and the write voltage is less than the preset first write voltage threshold V bmax , wherein the first write voltage threshold V b max Satisfy the formula I max represents modulating the conductance of the memristor unit to the first conductance G max Required current.

[0145] Optionally, as an embodiment, the second conductance of the multiple conductances of the memristor unit corresponding to the multiple currents is The conductance value is the largest, and the second write voltage threshold Satisfy the formula Indicates that the conductance of the memristor unit is modulated to the second conductance The required current, if the second write voltage threshold is less than the estimated mutation voltage of the resistive memory, then the write voltage is the estimated mutation voltage, and the estimated mutation voltage is higher than the actual mutation voltage of the memristor unit.

[0146] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0147] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0148] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0151] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0152] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A storage device, characterized in that: include: A memristor unit, wherein the memristor unit is a one-transistor one-resistive memory 1T1R structure; a current limiting circuit, used to limit the current passing through the memristor unit to a target current, wherein the target current is determined according to a target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit; A write circuit, used for applying a write voltage to the memristor unit in cooperation with the current limiting circuit to write the target data into the memristor unit; The current limiting circuit includes a current mirror, the current mirror includes a first branch and a second branch connected in parallel, the second branch is connected to the memristor unit, the current passing through the first branch is the target current, and the current mirror is used to copy the target current from the first branch to the second branch to limit the current flowing through the memristor unit to the target current. The current limiting circuit provides a plurality of currents for the memristor unit, different currents among the plurality of currents correspond to different conductances of the memristor unit, the plurality of currents include the target current, and the plurality of currents correspond to a second conductance G′ among the plurality of conductances of the memristor unit. max The conductance value is the largest, and the second write voltage threshold V' b max Satisfy the formula I' max Indicates that the conductance of the memristor unit is modulated to the second conductance G' max Required current, V' max represents the drain voltage of the transistor. If the second write voltage threshold is less than the estimated mutation voltage of the memristor unit, the write voltage is the estimated mutation voltage, and the estimated mutation voltage is higher than the actual mutation voltage of the memristor unit.

2. The storage device according to claim 1, wherein: The target current I, the write voltage V b , the target conductance G and the drain voltage V of the transistor d Satisfy the formula 3. A storage device, characterized in that: include: A memory array, the memory array comprising a plurality of memristor units, wherein each memristor unit is a one-transistor one-resistive memory 1T1R structure; a current limiting circuit, configured to limit a current passing through a target memristor cell among the plurality of memristor cells to a target current, wherein the target current is determined according to a target conductance of the target memristor cell and a gate voltage of a transistor in the target memristor cell, and the target conductance is used to indicate target data to be written into the memristor cell; A write circuit, used for applying a write voltage to the target memristor unit in cooperation with the current limiting circuit to write the target data into the target memristor unit; The current limiting circuit includes a current mirror, the current mirror includes a first branch and a plurality of second branches, each of the plurality of second branches is connected to a memristor unit in the storage array, the current passing through the first branch is the target current, and the current mirror is used to copy the target current from the first branch to a target second branch in the plurality of second branches, so as to limit the current flowing through the target memristor unit connected to the target second branch to the target current, The current limiting circuit provides a plurality of currents for the memristor unit, different currents among the plurality of currents correspond to different conductances of the memristor unit, the plurality of currents include the target current, and the plurality of currents correspond to a second conductance G′ among the plurality of conductances of the memristor unit. max The conductance value is the largest, and the second write voltage threshold V' b max Satisfy the formula I' max Indicates that the conductance of the memristor unit is modulated to the second conductance G' max Required current, V' max represents the drain voltage of the transistor. If the second write voltage threshold is less than the estimated mutation voltage of the memristor unit, the write voltage is the estimated mutation voltage, and the estimated mutation voltage is higher than the actual mutation voltage of the memristor unit.

4. The storage device according to claim 3, characterized in that: The target current I, the write voltage V b , the target conductance G and the drain voltage V of the transistor d Satisfy the formula 5. The storage device according to claim 3 or 4, characterized in that: The storage device further includes a gating circuit configured to select the target memristor unit from the storage array.

6. A method for writing data, characterized in that: The method is used to write data into a memristor unit, wherein the memristor unit is a one-transistor one-resistive memory 1T1R structure, and the method comprises: The current passing through the memristor unit is limited to a target current by a current limiting circuit, wherein the target current is determined according to a target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The current limiting circuit includes a current mirror, and the current mirror includes a first branch and a second branch connected in parallel, and the second branch is connected to the memristor unit. The current passing through the first branch is the target current. The current limiting circuit provides a plurality of currents for the memristor unit, and different currents among the plurality of currents correspond to different conductances of the memristor unit. The plurality of currents include the target current, and the plurality of currents correspond to a second conductance G' among the plurality of conductances of the memristor unit. max The conductance value is the largest, and the second write voltage threshold V' b max Satisfy the formula I' max Indicates that the conductance of the memristor unit is modulated to the second conductance G' max Required current, V' max represents the drain voltage of the transistor, if the second write voltage threshold is less than the estimated mutation voltage of the memristor unit, then the write voltage is the estimated mutation voltage, and the estimated mutation voltage is higher than the actual mutation voltage of the memristor unit; In cooperation with the current limiting circuit, applying a write voltage to the memristor unit through a write circuit to write the target data into the memristor unit; The method of limiting the current passing through the memristor unit to a target current by using a current limiting circuit includes: The target current is copied from the first branch to the second branch through the current mirror, so as to limit the current flowing through the memristor unit to the target current.

7. The method according to claim 6, characterized in that The target current I, the write voltage V b , the target conductance G and the drain voltage V of the transistor d Satisfy the formula

Images