Semiconductor device and method of forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same, including: providing a substrate, the substrate including a pull-up transistor region, forming a first core layer on the substrate; forming discrete second core layers on the first core layer; forming a first sacrificial sidewall on the sidewalls of the second core layers; there is a gap formed between the adjacent first sacrificial sidewalls in the pull-up transistor region; removing the second core layer, and etching the first core layer using the first sacrificial sidewall as a mask until the substrate is exposed; filling the gap with a dielectric layer; the semiconductor device formed by the method of the present invention has stable use performance, can ensure the accuracy of forming a pattern, and the process is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] A fin field-effect transistor (Fin FET) is a common multi-gate device. The structure of the fin field-effect transistor includes: a fin portion located on the surface of a semiconductor substrate and an isolation structure, the isolation structure covering sidewalls of a part of the fin portion, a gate structure located on the substrate and spanning across; source regions and drain regions within the fin portions on both sides of the gate structure.

[0003] With the increasing demand for high-capacity semiconductor storage devices, the integration density of semiconductor devices has attracted people's attention. In order to increase the integration density of semiconductor devices, the self-aligned double patterning technique (SADP) has been widely applied to the manufacturing process of fin field-effect transistor devices, and using the self-aligned quadruple patterning (SAQP) lithography technique to fabricate semiconductor devices with smaller nodes has been proven to provide smaller process fluctuations.

[0004] However, as the size of semiconductor devices shrinks and the device density increases, the performance of the formed fin field-effect transistors is unstable. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same, such that the performance of the formed semiconductor device is stable.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, the substrate including a pull-up transistor region, forming a first core layer on the substrate; forming discrete second core layers on the first core layer; forming a first sacrificial sidewall on sidewalls of the second core layers; there is a gap between adjacent first sacrificial sidewalls in the pull-up transistor region; after removing the second core layers, using the first sacrificial sidewall as a mask to etch the first core layer until the substrate is exposed; filling the gap with a dielectric layer.

[0007] Optionally, before filling the dielectric layer, it further includes: removing the first sacrificial sidewall.

[0008] Optionally, after filling the dielectric layer, it further includes: forming a second sacrificial sidewall on sidewalls of the etched first core layer; removing the etched first core layer and the dielectric layer; using the second sacrificial sidewall as a mask to etch a part of the thickness of the substrate to form a plurality of discrete fin portions on the substrate; removing the second sacrificial sidewall.

[0009] Optionally, before forming the first core layer, it further includes forming a first barrier layer on the surface of the substrate.

[0010] Optionally, before forming the second core layer, it further includes forming a second barrier layer on the surface of the first core layer.

[0011] Optionally, the material of the first core layer includes one or more of amorphous silicon, amorphous carbon, silicon nitride, and silicon oxide.

[0012] Optionally, the material of the second core layer includes one or more of amorphous silicon, amorphous carbon, silicon nitride, and silicon oxide.

[0013] Optionally, the material of the first barrier layer includes one or more combinations of silicon nitride, silicon oxide, and silicon carbide.

[0014] Optionally, the material of the second barrier layer includes one or more of silicon nitride, silicon oxide, and silicon carbide.

[0015] Optionally, the step of filling the gap with a dielectric layer includes atomic layer deposition of the dielectric layer material and back-etching of the dielectric layer material.

[0016] Optionally, the material of the first sacrificial sidewall includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0017] Optionally, the material of the second sacrificial sidewall includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0018] A semiconductor device formed by the above method includes: a substrate, the substrate includes a pull-up transistor region; a first core layer, discretely located on the substrate; a gap, located between the adjacent first core layers in the pull-up transistor region; a dielectric layer, filling the gap.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] By forming a gap between adjacent first sacrificial sidewalls in the pull-up transistor region, when fins are subsequently formed in the pull-up transistor region, the distance between adjacent fins is increased, ensuring that when an epitaxial layer is subsequently formed, the adjacent epitaxial layers in the pull-up transistor region do not grow together, playing a good isolation role, so that the formed semiconductor device does not exhibit leakage, improving the service life of the semiconductor device; at the same time, since a gap is formed between adjacent first sacrificial sidewalls in the pull-up transistor region, a dielectric layer needs to be filled in the gap. Subsequently, with the second sacrificial sidewall as a mask, a part of the thickness of the substrate is etched. When a plurality of discretely arranged fins are formed on the substrate, since the gap is filled with the dielectric layer, no second sacrificial sidewall will be formed in the gap, and no extra fins will be formed on the substrate corresponding to the gap, making the structural diagram of the formed fins meet the actual requirements. Brief Description of the Drawings

[0021] Figures 1 to 6 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment;

[0022] Figures 7 to 11 is a schematic structural diagram of the formation process of a semiconductor device in the first embodiment of the present invention;

[0023] Figures 12 to 22 is a schematic structural diagram of the formation process of a semiconductor device in the second embodiment of the present invention. Detailed Description of the Embodiments

[0024] Currently, self-aligned quadruple patterning lithography technology is used to fabricate semiconductor devices with smaller nodes. The formed semiconductor devices have poor performance stability and are prone to problems such as leakage, unable to meet the actual usage requirements.

[0025] The specific formation method of the semiconductor device is as follows:

[0026] Refer to Figure 1 , provide a substrate 1, on which a transfer transistor region 101, a pull-up transistor region 102, and a pull-down transistor region 103 are provided.

[0027] Refer to Figure 2 , a first core layer 2 is formed on the substrate 1, and discrete second core layers 3 are formed on the first core layer 2.

[0028] Refer to Figure 3 , a first sacrificial sidewall 4 is formed on the sidewalls of the second core layer 3.

[0029] Refer to Figure 4 , the second core layer 3 is removed, the first core layer 2 is etched with the first sacrificial sidewall 4 as a mask, and the first sacrificial sidewall 4 is removed.

[0030] Refer to Figure 5, a second sacrificial sidewall 5 is formed on the sidewall of the etched first core layer 2.

[0031] Reference Figure 6 , the first core layer 2 is removed, the substrate 1 with a partial thickness is etched using the second sacrificial sidewall 5 as a mask, a plurality of fin portions 6 arranged separately are formed on the substrate 1, and the second sacrificial sidewall 5 is removed.

[0032] The inventors found that the stability of the performance of semiconductor devices formed by this method is poor, and phenomena such as leakage and short - circuit are likely to occur, which limits the use of semiconductor devices. This is because the first sacrificial sidewall is just filled in the pull - up transistor region. When fins are formed in the pull - up transistor region subsequently, the distance between adjacent fins is small. When the epitaxial layer is formed, adjacent epitaxial layers are likely to grow together, and the isolation effect between adjacent epitaxial layers is very poor. In this way, leakage phenomena will occur during the use of semiconductor devices; at the same time, if gaps are formed between the first sacrificial sidewalls to increase the distance between adjacent fins in the pull - up transistor region, it will lead to the formation of redundant fins on the substrate corresponding to the gaps subsequently, resulting in inaccurate pattern formation. The formed redundant fins need to be removed again, the process is complex, and it is easy to damage the formed fins, which is not conducive to improving the quality of the formed semiconductor devices.

[0033] The inventors' research found that forming gaps between adjacent first sacrificial sidewalls in the pull - up transistor region to increase the distance between adjacent fins in the pull - up transistor region can eliminate the leakage phenomenon of the formed semiconductor devices. This is because the distance between adjacent fins in the pull - up transistor region increases, and when the epitaxial layer is formed, the distance between epitaxial layers is large enough, and adjacent epitaxial layers will not grow together. At this time, there is a good isolation effect between adjacent epitaxial layers; at the same time, because it is necessary to increase the distance between adjacent fins in the pull - up transistor region and ensure the accuracy of pattern conversion, before forming the fins, the gap needs to be filled with a dielectric layer. In this way, when the second sacrificial sidewall is formed subsequently, the second sacrificial sidewall will not be formed in the gap. When etching the substrate with a partial thickness using the second sacrificial sidewall as a mask, redundant fins will not be formed on the substrate corresponding to the gap, making the pattern of the finally formed fins meet the actual requirements, improving the accuracy of pattern conversion, simplifying the process, and improving the quality of the formed semiconductor devices.

[0034] To make the above - mentioned objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the drawings.

[0035] The First Embodiment

[0036] Figures 7 to 11 is a schematic structural diagram of the formation process of a semiconductor device in the first embodiment of the present invention.

[0037] First, refer toFigure 7 , a substrate 100 is provided, and the upper pull transistor region 110, the transfer transistor region 120, and the lower pull transistor region 130 are included on the substrate 100.

[0038] In this embodiment, the material of the substrate 100 is single crystal silicon; in other embodiments, the substrate 100 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate 100 may also be a semiconductor material such as silicon, germanium, germanium silicon, gallium arsenide, etc.

[0039] Reference Figure 8 , a first core layer 200 is formed on the substrate 100, and a second core layer 300 arranged discretely is formed on the first core layer 200.

[0040] In this embodiment, the material of the first core layer 200 is amorphous silicon; in other embodiments, the material of the first core layer 200 may also be any one of amorphous silicon, amorphous carbon, silicon nitride, silicon oxide, or a combination of amorphous silicon and amorphous carbon, or a combination of amorphous carbon and silicon nitride, etc.

[0041] In this embodiment, the first core layer 200 is formed on the substrate 100 by atomic layer chemical vapor deposition; in other embodiments, the first core layer 200 may also be formed by chemical vapor deposition or physical vapor deposition.

[0042] In this embodiment, the material of the second core layer 300 is the same as that of the first core layer 200, both being amorphous silicon; in other embodiments, the material of the second core layer 300 may be different from that of the first core layer 200.

[0043] In this embodiment, the material of the second core layer 300 is amorphous silicon; in other embodiments, the material of the second core layer 300 may also be a combination of amorphous silicon and amorphous carbon, or a combination of silicon nitride and silicon oxide.

[0044] In this embodiment, the material of the second core layer 300 is first deposited on the first core layer 200, and then the material of the second core layer 300 is etched back, so as to form the second core layer 300 arranged discretely on the first core layer 200.

[0045] Reference Figure 9 , a first sacrificial sidewall 301 is formed on the sidewall of the second core layer 300, and a gap 140 is formed between adjacent first sacrificial sidewalls 301 of the upper pull transistor region 110.

[0046] In this embodiment, the first sacrificial sidewall 301 is made of silicon nitride; in other embodiments, the first sacrificial sidewall 301 can also be made of a combination of silicon nitride and silicon oxynitride, or a combination of silicon oxide and silicon oxynitride, or a combination of silicon carbide and silicon oxynitride, or a combination of metal oxides of silicon, etc.

[0047] In this embodiment, first, the material of the first sacrificial sidewall 301 is chemically vapor deposited on the first core layer 200 and the second core layer 300, and then the material of the first sacrificial sidewall 301 is etched back to form the first sacrificial sidewall 301 on the sidewall of the second core layer 300.

[0048] In this embodiment, the material of the first sacrificial sidewall 301 is etched by dry etching. The specific dry etching process parameters include that the gases used include CF 4 gas, CH 3 F gas and O 2 , the flow rate of CF 4 gas is 5 sccm to 100 sccm, the flow rate of CH 3 F gas is 8 sccm to 50 sccm, the flow rate of O 2 is 10 sccm to 100 sccm, the chamber pressure is 10 mtorr to 2000 mtorr, the radio frequency power is 50 W to 300 W, the bias voltage is 30 V to 100 V, and the time is 4 seconds to 50 seconds.

[0049] In this embodiment, since a gap 140 is formed between adjacent first sacrificial sidewalls 301 in the pull-up transistor region 110, it is ensured that when fins are formed in the pull-up transistor region 110 subsequently, the distance between adjacent fins is increased. In this way, when an epitaxial layer is formed, there is a sufficiently large spacing between adjacent epitaxial layers in the pull-up transistor region 110, which can play a good isolation role to prevent adjacent epitaxial layers from growing together, reducing the probability of leakage in the semiconductor device during use and improving the performance of the semiconductor device.

[0050] Refer to Figure 10 , remove the second core layer 300, and use the first sacrificial sidewall 301 as a mask to etch the first core layer 200 until the substrate 100 is exposed.

[0051] In this embodiment, the second core layer 300 is removed by dry etching; in other embodiments, the second core layer 300 can also be removed by ashing.

[0052] In this embodiment, dry etching is used for the first core layer 200. The specific process parameters of the dry etching include that the etching gases used are HBr and Ar. Among them, the flow rate of HBr is 10 sccm to 1000 sccm, and the flow rate of Ar is 10 sccm to 1000 sccm.

[0053] Reference Figure 11 , the first sacrificial sidewall 301 is removed, and the dielectric layer 400 is filled in the gap 140. The gap 140 is transferred between the adjacent etched first core layers 200 in the pull-up transistor region 110.

[0054] In this embodiment, the material of the dielectric layer 400 is silicon oxide; in other embodiments, the dielectric layer 400 can also be other silicon oxides.

[0055] In this embodiment, first, an atomic layer deposition method is used to form a dielectric layer material on the exposed substrate 100 and the etched first core layer 200; the dielectric layer material is etched back so that only the dielectric layer 400 in the gap 140 remains.

[0056] In this embodiment, the specific parameters of the atomic layer deposition method include using an organic gas containing Si and O, a temperature of 80 degrees Celsius to 300 degrees Celsius, a pressure of 5 mtorr to 20 torr, and a process number of 5 to 100 times.

[0057] In this embodiment, the reason for using the atomic layer deposition method to form the dielectric layer material is that the dielectric layer material formed by the atomic layer deposition method has good compactness and uniformity, which is convenient for improving the performance of the formed semiconductor device.

[0058] In this embodiment, the process of etching back the dielectric layer material uses wet etching; in other embodiments, dry etching back of the dielectric layer material can also be used.

[0059] In this embodiment, the process parameters of the wet etching include a temperature of 25 degrees Celsius to 300 degrees Celsius and HCl gas with a volume percentage of 20% to 90%.

[0060] In this embodiment, a gap 140 is formed between adjacent first sacrificial sidewalls 301 of the pull-up transistor region 110. When fins are formed by subsequent etching, the distance between adjacent fins of the pull-up transistor region 110 can be increased. In this way, when the epitaxial layer is formed, the epitaxial layers adjacent to the pull-up transistor region 110 will not grow together due to too small a distance, thereby ensuring that the formed semiconductor device will not have leakage or short-circuit phenomena, and improving the service life of the formed semiconductor device. However, since the gap 140 is formed between adjacent first sacrificial sidewalls 301 of the pull-up transistor region 110, it is necessary to fill the gap 140 with the dielectric layer 400 to ensure that when the second sacrificial sidewall is formed subsequently, the second sacrificial sidewall will not be formed in the gap 140. In this way, when etching a part of the thickness of the substrate using the second sacrificial sidewall as a mask, fins will not be formed on the substrate corresponding to the gap 140, so that the finally formed fin pattern meets the actual requirements, simplifies the manufacturing process, and at the same time ensures the accuracy of the formed pattern.

[0061] A semiconductor device formed by using the above method includes a substrate 100, which includes a pull-up transistor region 110, a transfer transistor region 120, and a pull-down transistor region 130; a first core layer 200, separately located on the substrate 100; a gap 140, located between adjacent first core layers 200 of the pull-up transistor region 110; and a dielectric layer 400, filling the gap 140.

[0062] Second Embodiment

[0063] Figures 12 to 22 It is a schematic structural diagram of the formation process of a semiconductor device in the second embodiment of the present invention.

[0064] Reference Figure 12 , first, a substrate 100 is provided, and the substrate 100 includes a pull-up transistor region 110, a transfer transistor region 120, and a pull-down transistor region 130.

[0065] In this embodiment, the substrate 100 is made of single-crystalline silicon material; in other embodiments, the substrate 100 can also be a semiconductor material such as silicon, germanium, germanium-silicon, or gallium arsenide.

[0066] Reference Figure 13 , a first barrier layer 500 is formed on the substrate 100.

[0067] In this embodiment, the material of the first barrier layer 500 is silicon nitride; in other embodiments, the material of the first barrier layer 500 includes one or a combination of silicon nitride, silicon oxide, and silicon carbide.

[0068] In this embodiment, the first barrier layer 500 is formed on the substrate 100 by atomic layer deposition; in other embodiments, the first barrier layer 500 can also be formed on the substrate 100 by chemical vapor deposition or plasma vapor deposition.

[0069] In this embodiment, the purpose of forming the first barrier layer 500 on the substrate 100 is to protect the surface of the substrate 100 from being damaged during subsequent etching processes, ensure that the surface of the fin has high quality when the fin is formed subsequently, and ensure the accuracy of patterning.

[0070] Reference Figure 14 , the first core layer 200 is formed on the first barrier layer 500.

[0071] In this embodiment, the material and formation method of the first core layer 200 are the same as those in the first embodiment, and will not be elaborated here.

[0072] Reference Figure 15 , the second barrier layer 600 is formed on the first core layer 200.

[0073] In this embodiment, the material of the second barrier layer 600 is silicon nitride; in other embodiments, the material of the second barrier layer 600 includes a stacked structure of a combination of silicon nitride and silicon oxide or a stacked structure of a combination of silicon oxide and silicon carbide, etc., or a single layer of silicon oxide or silicon carbide, etc.

[0074] In this embodiment, the second barrier layer 600 is formed on the first core layer 200 by atomic layer deposition; in other embodiments, the second barrier layer 600 can also be formed on the first core layer 200 by chemical vapor deposition or plasma vapor deposition.

[0075] In this embodiment, the purpose of forming the second barrier layer 600 on the first core layer 200 is to protect the surface quality of the first core layer 200, ensure that the formed pattern can be accurately transferred during the transfer process, and prevent the pattern from deviating during the transfer process due to the surface quality problem of the first core layer 200, which affects the performance of the formed semiconductor device.

[0076] Reference Figure 16 , discrete second core layers 300 are formed on the second barrier layer 600.

[0077] In this embodiment, the material and formation method of the second core layer 300 are the same as those in the first embodiment, and will not be elaborated here.

[0078] Reference Figure 17, the first sacrificial sidewall 301 is formed on the sidewall of the second core layer 300, and the gap 140 is formed between the adjacent first sacrificial sidewalls 301 in the pull-up transistor region 110.

[0079] In this embodiment, the material and formation method of the first sacrificial sidewall 301 are the same as those in the first embodiment, and will not be elaborated here.

[0080] Reference Figure 18 , after removing the second core layer 300, using the first sacrificial sidewall 301 as a mask, the second barrier layer 600 and the first core layer 200 are etched in sequence until the first barrier layer 500 is exposed.

[0081] In this embodiment, the second barrier layer 600 and the first core layer 200 are etched by dry etching. The specific process parameters of the dry etching include that the total gas used includes etching gas and dilution gas. The etching gas includes HCl, and the dilution gas includes N 2 , the molar percentage of the etching gas in the total gas is 20% - 90%, and the temperature is 100 °C - 200 °C, such as 150 °C.

[0082] Reference Figure 19 , the first sacrificial sidewall 301 and the second barrier layer 600 are removed, and the gap 140 is filled with the dielectric layer 400, and the gap 140 is transferred between the adjacent etched first core layers 200 in the pull-up transistor region 110.

[0083] In this embodiment, the first sacrificial sidewall 301 and the second barrier layer 600 are removed by dry etching; in other embodiments, the first sacrificial sidewall 301 and the second barrier layer 600 can also be removed by processes such as chemical mechanical polishing or ashing.

[0084] A semiconductor device formed by the above method includes a substrate 100, which includes a pull-up transistor region 110, a transfer transistor region 120, and a pull-down transistor region 130; a first barrier layer 500, located on the substrate 100; a first core layer 200, separately located on the first barrier layer 500; a gap 140, located between the adjacent first core layers 200 in the pull-up transistor region 110; and a dielectric layer 400, filling the gap 140.

[0085] Reference Figure 20 , a second sacrificial sidewall 201 is formed on the sidewall of the etched first core layer 200.

[0086] In this embodiment, the second sacrificial sidewall 201 is made of a combination of silicon nitride and silicon oxide; in other embodiments, the second sacrificial sidewall 201 can also be made of a combination of silicon nitride and silicon oxynitride or a combination of silicon oxide and silicon oxynitride or a combination of silicon carbide and silicon oxynitride or a combination between metal oxides of silicon, etc., or a single layer of silicon nitride or silicon oxide or silicon carbide, etc.

[0087] Reference Figure 21 , remove the etched first core layer 200 and the dielectric layer 400.

[0088] In this embodiment, the first core layer 200 and the dielectric layer 400 are removed by dry etching or by using a TMAH etchant.

[0089] Reference Figure 22 , using the second sacrificial sidewall 201 as a mask, sequentially etch the first barrier layer 500 and a part of the thickness of the substrate 100 to form a plurality of discretely arranged fin portions 700 on the substrate 100, and remove the second sacrificial sidewall 201 and the first barrier layer 500.

[0090] In this embodiment, since the gap 140 is filled with the dielectric layer 400, when the second sacrificial sidewall 201 is formed, the second sacrificial sidewall 201 cannot be formed in the gap 140. Thus, when using the second sacrificial sidewall 201 as a mask to etch the first barrier layer 500 and a part of the thickness of the substrate 100 to form a plurality of discretely arranged fin portions 700 on the substrate 100, no redundant fin structures will be formed on the substrate 100 corresponding to the gap 140, ensuring the accuracy of the formed pattern and simplifying the process flow.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, comprising: providing a substrate, the substrate including a pull-up transistor region, and forming a first core layer on the substrate; forming discrete second core layers on the first core layer; forming a first sacrificial sidewall on the sidewalls of the second core layers, the width of the second core layers being greater than the width of the first sacrificial sidewall; there is a gap formed between adjacent ones of the first sacrificial sidewalls in the pull-up transistor region; after removing the second core layers, using the first sacrificial sidewall as a mask to etch the first core layer until the substrate is exposed, and the gap is transferred between adjacent ones of the etched first core layers in the pull-up transistor region; removing the first sacrificial sidewall; filling the gap between adjacent ones of the etched first core layers in the pull-up transistor region with a dielectric layer; after filling the dielectric layer, further comprising: forming a second sacrificial sidewall on the sidewalls of the etched first core layer; removing the etched first core layer and the dielectric layer; using the second sacrificial sidewall as a mask to etch a part of the thickness of the substrate to form a plurality of discrete fins on the substrate; removing the second sacrificial sidewall.

2. The method for forming a semiconductor device according to claim 1, characterized in that, before forming the first core layer, further comprising forming a first barrier layer on the surface of the substrate.

3. The method for forming a semiconductor device according to claim 1, characterized in that, before forming the second core layer, further comprising forming a second barrier layer on the surface of the first core layer.

4. The method for forming a semiconductor device according to claim 1, characterized in that, the material of the first core layer includes one or more of amorphous silicon, amorphous carbon, silicon nitride, and silicon oxide.

5. The method for forming a semiconductor device according to claim 1, characterized in that, the material of the second core layer includes one or more of amorphous silicon, amorphous carbon, silicon nitride, and silicon oxide.

6. The method for forming a semiconductor device according to claim 2, characterized in that, the material of the first barrier layer includes one or more of silicon nitride, silicon oxide, and silicon carbide.

7. The method for forming a semiconductor device according to claim 3, characterized in that, the material of the second barrier layer includes one or more of silicon nitride, silicon oxide, and silicon carbide.

8. The method for forming a semiconductor device according to claim 1, characterized in that, the step of filling the gap with a dielectric layer includes atomic layer depositing a dielectric layer material and back-etching the dielectric layer material.

9. The method for forming a semiconductor device according to claim 1, characterized in that, the material of the first sacrificial sidewall includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

10. The method for forming a semiconductor device according to claim 1, characterized in that, the material of the second sacrificial sidewall includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

11. A semiconductor device formed by using the method according to any one of claims 1 to 10.

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