Electronic component modules

Abstract

The present invention provides an electronic component module, which includes: a semiconductor package, having a first surface set as a mounting surface and a second surface opposite to the first surface, and including a semiconductor chip; a component package, having a first surface facing the second surface of the semiconductor package and a second surface opposite to the first surface of the component package, the component package including a passive component; and a connector, which is arranged on the second surface of the component package and has a connecting surface constructed to be mechanically coupled to an external device, the connector including a plurality of connecting wires arranged on the connecting surface.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0059710 filed on May 21, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The inventive concept relates to an electronic component module including a semiconductor chip. Background Art

[0003] As mobile displays become larger and larger, the demand for increasing battery capacity is growing. As the battery capacity increases, the area occupied by the battery increases. Therefore, it is necessary to reduce the size of a printed circuit board (PCB) provided as a main board. On the other hand, in response to this demand for size reduction, modularization is required in consideration of the mounting area of ​​various components (e.g., passive components) and semiconductor packages. Summary of the invention

[0004] An aspect of the inventive concept is to provide an electronic component module that can reduce a mounting space of a main board.

[0005] According to one aspect of the present invention, an electronic component module includes: a semiconductor package having a first surface set as a mounting surface and a second surface opposite to the first surface, and including a semiconductor chip; a component package having a first surface facing the second surface of the semiconductor package and a second surface opposite to the first surface of the component package, the component package including a passive component; and a connector disposed on the second surface of the component package and having a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface.

[0006] According to one aspect of the inventive concept, an electronic component module includes: a connection structure having a first surface and a second surface opposite to each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a first wiring structure connected to the redistribution layer and extending in a direction substantially perpendicular to the first surface; a passive component disposed on the second surface of the connection structure and connected to the redistribution layer; a frame having a first surface in contact with the second surface of the connection structure and a second surface opposite to the first surface of the frame, the frame having through holes penetrating the first and second surfaces of the frame and accommodating the passive components; a second wiring structure connected to the redistribution layer and penetrating the first and second surfaces of the frame; and a connector disposed on the second surface of the frame and having a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface and electrically connected to the second wiring structure.

[0007] According to one aspect of the present invention, an electronic component module includes: a first frame having a through hole and including a first wiring structure having a wiring layer arranged on a surface of the first frame; a passive component arranged in the through hole; a connecting member on which the first frame is arranged, the connecting member including a redistribution layer, the passive component and the first wiring structure being connected to the redistribution layer; a semiconductor chip connected to the redistribution layer, the semiconductor chip and the passive component being arranged on opposite sides of the connecting member; a connector arranged above the through hole and having a connecting terminal extending to the wiring layer of the first wiring structure; and an electrically connecting metal body connecting the connecting terminal to the wiring layer, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0010] Figure 2 is a schematic perspective view of an example of an electronic device;

[0011] Figure 3A and Figure 3B are cross-sectional views schematically showing a fan-in type semiconductor package before and after packaging, respectively;

[0012] Figure 4 is a schematic cross-sectional view of a packaging process for a fan-in semiconductor package;

[0013] Figure 5 is a cross-sectional view schematically showing a state where a fan-in type semiconductor package is mounted on an interposer substrate to be finally mounted on a main board of an electronic device;

[0014] Figure 6 is a cross-sectional view schematically showing a state in which a fan-in type semiconductor package is embedded in an interposer substrate to be finally mounted on a main board of an electronic device;

[0015] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package;

[0016] Figure 8 is a schematic cross-sectional view showing a fan-out type semiconductor package mounted on a main board of an electronic device;

[0017] Fig. 9 is a schematic cross-sectional view of an electronic component module according to an example embodiment of the inventive concept;

[0018] Fig.10 yes Fig. 9 The electronic components of the module are along Fig. 9 A cross-sectional view taken along line I1-I1';

[0019] Fig.11 It is shown that it can be applied to Fig. 9 A perspective view of an example of a connector of an electronic component module shown in FIG.

[0020] Fig. 12A is a diagram showing a display assembly as an example embodiment of the present invention. Fig. 9 A plan view of an application example of an electronic assembly module, and Fig. 12B is along Fig. 12A A cross-sectional view of the display assembly taken along line II1-II1';

[0021] Fig.13 is along Fig. 12A A cross-sectional view taken along line II2-II2'; and

[0022] Figures 14 to 17 is a schematic cross-sectional view of an electronic component module according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. The shapes and sizes of constituent elements in the drawings may be exaggerated or reduced for clarity.

[0024] Electronic Devices

[0025] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0026] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected to the mainboard 1010. These components may be connected to other components to be described below through various signal lines 1090.

[0027] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0028] The network-related components 1030 may include components implementing protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components implementing a variety of other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 .

[0029] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or the network-related components 1030.

[0030] The electronic device 1000 may include other components that may or may not be physically or electrically connected to the main board 1010, depending on the type of the electronic device 1000. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000, etc.

[0031] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0032] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0033] Reference Figure 2 , the semiconductor package can be used for various purposes in various electronic devices 1000 as described above. For example, the motherboard 1110 can be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 can be physically connected or electrically connected to the motherboard 1110. In addition, other components (such as a camera module 1130) that may be physically connected or electrically connected to the motherboard 1110 or may not be physically connected or electrically connected to the motherboard 1110 can be accommodated in the body 1101. Some of the electronic components 1120 may be chip-related components, and the semiconductor package 100 may be, for example, an application processor in a chip-related component, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0034] Semiconductor Package

[0035] Generally, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product and may be damaged by external physical or chemical impact. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device or the like in a packaged state.

[0036] The reason why semiconductor packaging is generally used is that there is generally a difference in circuit width between a semiconductor chip and a mainboard of an electronic device in terms of electrical connection. Specifically, the size of the connection pads of a semiconductor chip and the spacing between the connection pads of the semiconductor chip are very small, while the size of the component mounting pads of a mainboard used in an electronic device and the spacing between the component mounting pads of the mainboard are significantly larger than the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip. Therefore, it may be difficult to mount the semiconductor chip directly on the mainboard, so the use of a packaging technology for alleviating the difference in circuit width between the semiconductor chip and the mainboard is advantageous.

[0037] Semiconductor packages manufactured by the packaging technology may be divided into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.

[0038] Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.

[0039] Fan-in semiconductor package

[0040] Figure 3A and Figure 3B is a schematic cross-sectional view showing a fan-in type semiconductor package before and after being packaged, and Figure 4 A series of schematic cross-sectional views illustrating a packaging process for a fan-in semiconductor package are shown.

[0041] Reference FIG. 3A to FIG. 4 , the semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc.; a connection pad 2222 formed on one surface of the body 2221 and including a conductive material such as aluminum (Al), etc.; and a passivation layer 2223 such as an oxide film, a nitride film, etc. formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222. In this case, since the connection pad 2222 is very small, it may be difficult to mount the integrated circuit (IC) on a printed circuit board (PCB) of a medium size class and a main board of an electronic device, etc.

[0042] Therefore, according to the size of the semiconductor chip 2220, the connection member 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222. The connection member 2240 may be formed by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, forming a via hole 2243h that opens the connection pad 2222, and then forming a wiring pattern 2242 and a via 2243. Then, a passivation layer 2250 that protects the connection member 2240 may be formed, and an opening 2251 may be formed to have an under bump metallization layer 2260 extending through the opening 2251, etc. For example, a fan-in type semiconductor package 2200 including, for example, a semiconductor chip 2220, a connection member 2240, a passivation layer 2250, and an under bump metallization layer 2260 may be manufactured by a series of processes.

[0043] As described above, the fan-in type semiconductor package may have a package form in which all connection pads (e.g., input / output (I / O) terminals) of a semiconductor chip are disposed inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components installed in smart phones have been manufactured in the form of fan-in type semiconductor packages. In detail, many components installed in smart phones have been developed to achieve fast signal transmission while having a compact size.

[0044] However, in a fan-in semiconductor package, since all the I / O terminals generally need to be arranged inside the semiconductor chip, the fan-in semiconductor package has a large space limitation. Therefore, it may be difficult to apply this structure to a semiconductor chip with a large number of I / O terminals or a semiconductor chip with a small size. In addition, due to the above-mentioned shortcomings, it may not be possible to directly install and use the fan-in semiconductor package on the mainboard of an electronic device. The reason is that even if the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip are increased by a redistribution process, the size of the I / O terminals of the semiconductor chip and the spacing between the I / O terminals of the semiconductor chip may still be insufficient to directly install the fan-in semiconductor package on the mainboard of the electronic device.

[0045] Figure 5 is a schematic cross-sectional view showing a fan-in type semiconductor package mounted on an interposer substrate that is ultimately mounted on, for example, a main board of an electronic device, and Figure 6 is a schematic cross-sectional view showing a fan-in type semiconductor package embedded in an interposer substrate that is ultimately mounted on, for example, a main board of an electronic device.

[0046] Reference Figure 5In the fan-in semiconductor package 2200, the connection pads 2222 (e.g., I / O terminals) of the semiconductor chip 2220 may be redistributed again through the interposer substrate 2301, and the fan-in semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device in a state where the fan-in semiconductor package 2200 is mounted on the interposer substrate 2301. In this case, the solder balls 2270 and the like may be fixed by the bottom filling resin 2280 and the like, and the outer surface of the semiconductor chip 2220 may be covered with the encapsulant 2290 and the like. Optionally, referring to Figure 6 The fan-in semiconductor package 2200 can be embedded in a separate intermediate substrate 2302. In a state where the fan-in semiconductor package 2200 is embedded in the intermediate substrate 2302, the connection pads 2222 (e.g., I / O terminals) of the semiconductor chip 2220 can be redistributed again through the intermediate substrate 2302, and the fan-in semiconductor package 2200 can be finally mounted on a mainboard 2500 of the electronic device.

[0047] As described above, it may be difficult to directly mount and use a fan-in type semiconductor package on a main board (e.g., 2500) of an electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate interposer substrate (e.g., 2301 or 2302) and then mounted on the main board of the electronic device through a packaging process, or the fan-in type semiconductor package may be mounted and used on the main board of the electronic device in a state where the fan-in type semiconductor package is embedded in the interposer substrate.

[0048] Fan-out semiconductor packages

[0049] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

[0050] Reference Figure 7 In the fan-out type semiconductor package 2100, for example, the outer surface of the semiconductor chip 2120 may be protected by the encapsulant 2130, and the connection pads 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 by the connection member 2140. In this case, the passivation layer 2150 may also be formed on the connection member 2140, and the under bump metallization layer 2160 may also be formed in the opening of the passivation layer 2150. The solder ball 2170 may also be formed on the under bump metallization layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), etc. The connection member 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a via 2143 to electrically connect the connection pad 2122 and the redistribution layer 2142 to each other.

[0051] In the present manufacturing process, the connection member 2140 may be formed after the encapsulant 2130 is formed outside the semiconductor chip 2120. In this case, the process of forming the connection member 2140 is performed to form a via hole that connects the connection pad 2122 of the semiconductor chip 2120 and the redistribution layer to each other, and the via hole 2143 may therefore have a width that decreases toward the semiconductor chip 2120.

[0052] As described above, the fan-out type semiconductor package may have a form in which the I / O terminals of the semiconductor chip are redistributed and arranged outside the semiconductor chip 2120 through the connection member 2140 formed on the semiconductor chip 2120. As described above, in the fan-in type semiconductor package, all the I / O terminals of the semiconductor chip generally need to be arranged inside the semiconductor chip (for example, within the occupied area of ​​the semiconductor chip on the package). Therefore, when the size of the semiconductor chip is reduced, the size and pitch of the ball generally need to be reduced, so that a standardized ball layout may not be used in the fan-in type semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has a form in which the I / O terminals of the semiconductor chip 2120 are redistributed and arranged outside the semiconductor chip 2120 (for example, outside the occupied area of ​​the semiconductor chip) through the connection member 2140 formed on the semiconductor chip. Therefore, even if the size of the semiconductor chip 2120 is reduced, the standardized ball layout can still be used as it is in the fan-out type semiconductor package, so that the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, as described below.

[0053] Figure 8 is a schematic cross-sectional view showing a fan-out type semiconductor package mounted on a main board of an electronic device.

[0054] Reference Figure 8 , the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device through the solder balls 2170, etc. For example, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140, which is formed on the semiconductor chip 2120 and enables the connection pads 2122 to be redistributed to, for example, a fan-out area located outside the area / occupied area of ​​the semiconductor chip 2120, so that a standardized ball layout can be used as is in the fan-out type semiconductor package 2100. As a result, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer substrate, etc.

[0055] As described above, since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate intermediate substrate, the fan-out semiconductor package can be implemented in a thickness smaller than that of the fan-in semiconductor package using the intermediate substrate. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, making it particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a more compact form than a common package-on-package (POP) type using a printed circuit board (PCB), and the problem caused by the occurrence of the warpage phenomenon can be solved.

[0056] In addition, the fan-out semiconductor package refers to a packaging technology for mounting a semiconductor chip on a main board of an electronic device or the like and protecting the semiconductor chip from external impact as described above. The fan-out semiconductor package is a concept different from the concept of a printed circuit board (PCB) or the like such as an intermediate substrate (having specifications, uses, etc. different from those of the fan-out semiconductor package and having a fan-in semiconductor package embedded therein).

[0057] Fig. 9 is a schematic cross-sectional view of an electronic component module according to an example embodiment, and Fig.10 is along Fig. 9 sectional view of the electronic component module taken along line I1 - I1 ′ in FIG.

[0058] Reference Fig. 9 and Fig.10 According to an example embodiment, an electronic component module 300 includes: a semiconductor package 100 having a first surface 100A set as a mounting surface and a second surface 100B opposite to the first surface 100A; a component package 200 having a first surface 200A facing the second surface 100B of the semiconductor package 100 and a second surface 200B opposite to the first surface 200A; and a connector 350 disposed on the second surface 200B of the component package 200.

[0059] The semiconductor package 100 employed in this embodiment includes: a first connection structure 140 having a first surface 140A and a second surface 140B opposite to each other and including a first redistribution layer 142; a semiconductor chip 120 disposed on the first surface 140A of the first connection structure 140 and including a connection pad 120P connected to the first redistribution layer 142; and a first encapsulant 130 disposed on the first surface 140A of the first connection structure 140 and encapsulating the semiconductor chip 120. The second surface 140B of the first connection structure 140 may be provided as the second surface 100B of the semiconductor package 100.

[0060] The first redistribution layer 142 of the first connection structure 140 may be implemented at two heights of a plurality of (e.g., two) insulating layers 141, but example embodiments thereof are not limited thereto. In some embodiments, the first redistribution layer 142 may be formed of a single layer or a plurality of different layers. The first redistribution layer 142 may be connected to the connection pads 120P of the semiconductor chip 120 through the first redistribution vias 143 penetrating the insulating layer 141.

[0061] The semiconductor package 100 used in this embodiment may further include a first frame 110 having a first surface 110A and a second surface 110B opposite to each other and including a first wiring structure 115 connecting the first surface 110A and the second surface 110B. The first frame 110 may have a through hole 110H for accommodating the semiconductor chip 120. In another embodiment, the structure of the accommodating portion of the semiconductor chip 120 may be changed to another structure (see Fig.14 ). The second surface 110B of the first frame 110 may be in contact with the first surface 140A of the first connection structure 140 .

[0062] In an example embodiment, the first frame 110 includes a first insulating layer 111a and a second insulating layer 111b, and the first wiring structure 115 includes three wiring layers 112a, 112b, and 112c and may include first wiring vias 113a and second wiring vias 113b connecting the three wiring layers 112a, 112b, and 112c to each other, but example embodiments thereof are not limited thereto. In some embodiments, the first wiring structure 115 may be formed to have a different number of layers and structure therefrom. The first wiring structure 115 (in detail, the first wiring layer 112a) of the first frame 110 may be electrically connected to the first redistribution layer 142 of the first connection structure 140 through the first redistribution vias 143.

[0063] The semiconductor package 100 employed in this embodiment further includes a third redistribution layer 152 disposed on the first surface 110A of the first frame 110 and the first encapsulant 130 .

[0064] The third connection structure 155 may include a third redistribution layer 152 and a third redistribution via 153. The third redistribution layer 152 may be connected to the first wiring structure 115 (in detail, the third wiring layer 112c) through the third redistribution via 153 penetrating the first encapsulant 130. In this embodiment, one side on which the third redistribution layer 152 is formed may be provided as the first surface 100A of the semiconductor package 100, for example, a mounting surface. In another embodiment, the third redistribution layer 152 is shown as a single layer, but in some embodiments, an insulating layer (not shown) is further included and may be implemented at two or more heights.

[0065] The component package 200 used in this embodiment includes: a second connection structure 240, having a first surface 240A and a second surface 240B opposite to each other and having a second redistribution layer 242; a passive component 220, which is arranged on the second surface 240B of the second connection structure 240 and is electrically connected to the second redistribution layer 242; and a second encapsulant 230, which is arranged on the second surface 240B of the second connection structure 240 and encapsulates the passive component 220.

[0066] The first surface 200A of the component package 200 (in detail, the first surface 240A of the second connection structure 240 ) may be in contact with the second surface 100B of the semiconductor package 100 (in detail, the second surface 140B of the first connection structure 140 ).

[0067] The second connection structure 240 includes a plurality of insulating layers 241, and the second redistribution layer 242 may be implemented at two heights of the plurality of (e.g., two) insulating layers 241, similar to the first redistribution layer 142. The structure of the second connection structure 240 is not limited thereto. In some embodiments, the insulating layer 241 and the second redistribution layer 242 may be implemented as a single layer or a double layer or more. The passive component 220 disposed on the first surface 240A of the second connection structure 240 may be connected to the second redistribution layer 242 through the second redistribution via 243 penetrating the insulating layer 241.

[0068] The component package 200 employed in this embodiment may include a second frame 210 having a through hole 210H accommodating a passive component 220. The second frame 210 has a first surface 210A and a second surface 210B opposite to each other, and the first surface 210A of the second frame 210 may contact the second surface 240B of the second connection structure 240.

[0069] The second frame 210 may include an insulating member 211 and a second wiring structure 215 penetrating the insulating member 211. The second wiring structure 215 may be connected to the second redistribution layer 242 of the second connection structure 240 through a second redistribution via 243 penetrating the insulating layer 241.

[0070] The connector 350 employed in this embodiment may be disposed on the component package 200 , for example, on the second surface 210B of the second frame 210 . Fig.11 It shows that Fig. 9 1 is a perspective view of an example of a connector 350 employed in an electronic component module 300.

[0071] Reference Fig.11, the connector 350 may have a connection surface 351 configured to be mechanically coupled to the connector 650 of the external device 600. A plurality of connection lines 355 may be arranged on the connection surface 351 to be connected to corresponding connection lines (not shown) of the external device (e.g., a rigid-flexible printed circuit board (PCB) 600). The plurality of connection lines 355 may include a signal line 355a and a power line 355b.

[0072] The connector 350 may be detachably coupled to the connector 650 of the external device 600. For example, the connector 350 may have a coupling portion 352 that is detachable from the connector 650 of the external device 600 on a connection surface 351, for example. In some embodiments, the plurality of connection wires 355 may be implemented as protruding pins or recessed slots, respectively, and may be removably coupled to corresponding connection wires (not shown) of the external device 600 that are configured as recessed slots or protruding pins to ensure electrical and mechanical connection. In another embodiment, the connector 350 may be configured to be detachably coupled by a separate fixing unit, and in the coupled state, the plurality of connection wires 355 may be electrically connected to the external device 600.

[0073] The connector 350 may include a plurality of external connection terminals 319 electrically connected to the second wiring structure 215. The plurality of external connection terminals 319 may be respectively associated with a plurality of connection lines 355. For example, the plurality of external connection terminals 319 may be provided as a plurality of pins. The plurality of external connection terminals 319 may be connected to the second wiring structure 215 (specifically, the second wiring layer 212b) through a third electrical connection metal body 320 such as a low melting point metal.

[0074] In this structure, each connection line 355 of the connector 350 may be electrically connected to the passive component 220 and the semiconductor chip 120 through the circuit structure of the component package 200 (such as the second wiring structure 215 and the second redistribution layer 242) and the circuit structure of the semiconductor package 100 (such as the first wiring structure 115, the first redistribution layer 142, and the third redistribution layer 152). In addition, each connection line 355 of the connector 350 may be connected to another external device (e.g., a main board) through the first electrical connection metal body 170 connected to the third redistribution layer 152 located on the mounting surface of the semiconductor package 100.

[0075] The electronic component module 300 according to example embodiments may reduce a mounting space of the passive component 220 by disposing the component package 200 having the passive component 220 on an upper portion of the semiconductor package 100 , and may also reduce noise by shortening an electrical connection path between the passive component 220 and the semiconductor chip 120 .

[0076] In addition, the electronic component module 300 according to the example embodiment may be configured to have an uppermost structure, for example, an upper structure of the component package 200, in which the connector 350 is introduced in such a manner that the area of ​​the connector 350 overlaps with the installation space of the electronic component module 300. In this case, since the area of ​​the connector 350 is not required on the main board, the area of ​​the main board can be reduced. Fig. 12A and Fig. 12B A detailed description thereof is given.

[0077] As described above, according to example embodiments, since the passive components 220 and the connector area occupying a considerable space of the main board may be omitted, the area of ​​the electronic device may be significantly reduced.

[0078] Hereinafter, a main configuration of the electronic component module 300 according to example embodiments will be described in more detail.

[0079] The first frame 110 and the second frame 210 can improve the rigidity of the semiconductor package 100 and the assembly package 200 according to a specific material, and can ensure the uniformity of the thickness of the first encapsulant 130 and the second encapsulant 230. As described above, the first frame 110 and the second frame 210 have the first wiring structure 115 and the second wiring structure 215, and thus can be used as a package structure of a package on package (POP) type. Therefore, the exemplary embodiment thereof can be modified in other forms, and other functions can be performed according to the form.

[0080] As described above, the first frame 110 includes: a first insulating layer 111a, which contacts the first connection structure 140; a first wiring layer 112a, which contacts the first connection structure 140 and is embedded in the first insulating layer 111a; a second wiring layer 112b, which is disposed on the side of the first insulating layer 111a opposite to the side on which the first wiring layer 112a is embedded; a second insulating layer 111b, which is disposed on the first insulating layer 111a and covers the second wiring layer 112b; and a third wiring layer 112c, which is disposed on the second insulating layer 111b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c are electrically connected to the connection pad 120P. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c are electrically connected to each other through the first wiring via 113a penetrating the first insulating layer 111a and the second wiring via 113b penetrating the second insulating layer 111b, respectively.

[0081] In the case of the first frame adopted in this embodiment, since the first wiring layer 112a is embedded in the first insulating layer 111a, the step generated by the thickness of the first wiring layer 112a can be significantly reduced, and the insulation distance of the first connection structure 140 can be more constant. Since the first wiring layer 112a is recessed in the first insulating layer 111a, the first insulating layer 111a may have a step between the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a. In this case, the material of the first encapsulant 130 can be prevented from seeping out to contaminate the first wiring layer 112a.

[0082] The second frame 210 includes an insulating member 211 disposed on the second connection structure 240, a first wiring layer 212a and a second wiring layer 212b disposed on both surfaces of the insulating member 211, and wiring vias 213 penetrating the insulating member 211 to electrically connect the first wiring layer 212a and the second wiring layer 212b. The first wiring layer 212a can be connected to the second redistribution layer 242 through the second redistribution vias 243.

[0083] The first frame 110 and the second frame 210 may be manufactured by a process of manufacturing a printed circuit board to have a sufficient thickness, and the first connection structure 140 and the second connection structure 240 may be manufactured by a semiconductor process, etc. to have a relatively reduced thickness. Therefore, the thickness of each of the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c of the first frame 110 and the first wiring layer 212a and the second wiring layer 212b of the second frame 210 may be greater than the thickness of each of the first redistribution layer 142 of the first connection structure 140 and the second redistribution layer 242 of the second connection structure 240.

[0084] In some other embodiments, the first connection structure 140 and / or the second connection structure 240 may also be manufactured by a printed circuit board manufacturing process similar to that of the first frame 110 and the second frame 210. In this case, the thickness of each of the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c of the first frame 110 and the thickness of each of the first wiring layer 212a and the second wiring layer 212b of the second frame 210 may be similar to the thickness of each of the first redistribution layer 142 and the second redistribution layer 242.

[0085] In some embodiments, the first insulating layer 111a and the second insulating layer 111b and the insulating member 211 may be formed using a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins and an inorganic filler, or a resin (e.g., a prepreg resin, an ABF (Ajinomoto Build-up Film) resin, a FR-4 resin, a bismaleimide triazine (BT) resin, etc.) impregnated with these resins together with a core material (e.g., glass fiber, glass cloth, glass fabric, etc.) and an inorganic filler. In some embodiments, a photosensitive dielectric (PID) resin may be used. In terms of maintaining rigidity, a prepreg may be used.

[0086] The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c are used to redistribute the connection pads 120P of the semiconductor chip 120. The first wiring layer 212a and the second wiring layer 212b can be used to redistribute passive components. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c and the first wiring layer 212a and the second wiring layer 212b may contain conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c and the first wiring layer 212a and the second wiring layer 212b may perform various functions according to the design of the corresponding layers, and may include, for example, a ground (GND) pattern, a power supply (PoWeR: PWR) pattern, a signal (S) pattern, etc. In this case, the signal S pattern includes various signals other than a ground (GND) pattern, a power supply (PWR) pattern, etc., for example, including a data signal, etc. At least one of the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c and / or at least one of the first wiring layer 212a and the second wiring layer 212b may further include a via pad, a wiring pad, a ball pad, etc.

[0087] The first wiring via 113a, the second wiring via 113b, and the wiring via 213 are respectively arranged in the first frame 110 and the second frame 210 in an interlayer connection structure. The first wiring via 113a, the second wiring via 113b, and the wiring via 213 may also use the above-mentioned conductive material. The first wiring via 113a, the second wiring via 113b, and the wiring via 213 may be a filled via filled with a conductive material, or may be a conformal via formed when a conductive material is formed along the wall surface of the through hole. On the other hand, according to the process, the first wiring via 113a and the second wiring via 113b may have a tapered shape that tapers in the same direction, for example, a tapered shape with a width of the upper portion less than the width of the lower portion relative to the cross section. The first wiring via 113a and the second wiring via 113b may be integrated with the second wiring layer 112b and the third wiring layer 112c, respectively, by the same plating process.

[0088] The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. In this case, the integrated circuit may be, but is not limited to, a processor chip such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. Specifically, it may be an application processor (AP) or a memory chip (e.g., a volatile memory such as a dynamic random access memory (DRAM), a non-volatile memory such as a read-only memory (ROM), a flash memory, etc.), or a logic chip such as an analog-to-digital converter, or other types of chips such as a power management integrated circuit (PMIC), or a combination of some of them.

[0089] The semiconductor chip 120 may be formed based on an active wafer. In this case, the base material of the main body may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed in the main body. A connection pad 120P is provided to electrically connect the semiconductor chip 120 to other components, and a conductive material such as aluminum (Al), copper (Cu), etc. may be used as a forming material of the connection pad 120P without any particular restrictions. A passivation film 121 may be formed on the effective surface of the main body to expose the connection pad 120P. The passivation film 121 may be an oxide film, a nitride film, etc., or may be a double layer of an oxide film and a nitride film. The lower surface of the connection pad 120P may form a step with the lower surface of the first encapsulant 130 through the passivation film 121, and therefore, the first encapsulant 130 may fill at least a portion of the space between the passivation film 121 and the first connection structure 140. In this case, the first encapsulant 130 may be prevented from leaking to the lower surface of the connection pad 120P to a certain extent. An insulating film (not shown) or the like may be further provided at other desired locations. The semiconductor chip 120 may be a bare chip so that the connection pads 120P may physically contact the first redistribution vias 143 of the first connection structure 140. Depending on the type of the semiconductor chip 120, a separate redistribution layer (not shown) may be further formed on an effective surface of the semiconductor chip 120, and bumps (not shown) or the like may be connected to the connection pads 120P.

[0090] The first encapsulant 130 can protect the first frame 110, the first semiconductor chip 120, etc. Similarly, the second encapsulant 230 can protect the second frame 210, the passive component 220, etc. The encapsulation form thereof is not particularly limited, and may be in the form of wrapping at least a portion of the object to be protected. The first encapsulant 130 and the second encapsulant 230 fill the through holes 110H and 210H to act as an adhesive and reduce bending according to the specific materials of the first encapsulant 130 and the second encapsulant 230.

[0091] The materials of the first encapsulant 130 and the second encapsulant 230 are not limited thereto. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin obtained by mixing these resins with an inorganic filler, or a resin obtained by impregnating these resins with a core material such as glass fiber and an inorganic filler may be used. In some embodiments, a curable resin such as a prepreg resin, an ABF resin, an FR-4 resin, a BT resin, or a photosensitive encapsulant (PIE) resin may be used as the first encapsulant 130 and the second encapsulant 230.

[0092] The third redistribution layer 152 may be disposed on the first encapsulant 130 as described above to be connected to the wiring structure of the first frame 110, specifically, to the third wiring layer 112c. The third redistribution via 153 passes through at least a portion of the first encapsulant 130 and electrically connects the third wiring layer 112c, which is the lowest wiring layer of the first frame 110, and the third redistribution layer 152. The forming material of the third redistribution layer 152 and the third redistribution via 153 may include a conductive material as described above, and may also include a metal such as copper (Cu) in some embodiments. Each of the third redistribution layer 152 and the third redistribution via 153 may be a plurality of conductor layers each consisting of a seed layer and a plating layer. The third redistribution layer 152 may perform various functions according to the design. For example, the third redistribution layer 152 may include, for example, a ground pattern, a power pattern, a signal pattern, etc. The third redistribution via 153 may also have a tapered shape in which the width of the upper surface relative to the cross section is smaller than the width of the lower surface.

[0093] The first connection structure 140 may redistribute the connection pads 120P of the semiconductor chip 120. Tens to hundreds of connection pads 120P of the semiconductor chip 120 having various functions may be redistributed through the first connection structure 140, and may be physically and / or electrically connected to the outside through the first electrical connection metal body 170 according to their functions.

[0094] In addition to the above-mentioned insulating materials, a photosensitive dielectric material such as a PID resin may be used as the material of the insulating layer 141 of the first connection structure 140. When the insulating layer 141 has a photosensitive property, the insulating layer 141 may be formed to have a relatively reduced thickness, and a fine pitch of the first redistribution via 143 may be more easily obtained using a photolithography process. In some embodiments, the insulating layer 141 may be a photosensitive dielectric layer containing an insulating resin and an inorganic filler. For example, when the insulating layer 141 is composed of multiple layers, the materials of the multiple layers may be the same as each other, and may also be different from each other as needed. Although the insulating layer 141 is composed of a plurality of layers, the boundaries between the layers may be unclear depending on the process.

[0095] The first redistribution layer 142 may substantially redistribute the connection pads 120P, and the above-mentioned conductive material may be used as the material of the first redistribution layer 142. The first redistribution layer 142 may perform various functions according to the design of the corresponding layer, for example, may include a ground pattern, a power pattern, a signal pattern, etc. In this case, the signal pattern includes various signals other than the ground pattern, the power pattern, etc., for example, including a data signal, etc., and may include pad patterns of various shapes as required. The above-mentioned conductive material may also be used as the material of the first redistribution via 143. The first redistribution via 143 may be completely filled with a conductive material, or may be formed as a conductive material formed along the via wall. Each configuration of the second connection structure 240 may also be manufactured with materials and processes similar to those of the first connection structure 140.

[0096] The first redistribution via 143 of the first connection structure 140 may have a shape that tapers in a direction opposite to the direction in which the first and second wiring vias 113a and 113b of the first frame 110 taper. For example, the first redistribution via 143 may have a tapered shape in which a width of an upper surface relative to a cross section is greater than a width of a lower surface.

[0097] The first passivation layer 181 and the second passivation layer 182 of the semiconductor package 100 and the first passivation layer 281 of the component package 200 may include, for example, a prepreg, ABF, FR-4, BT, a solder resist, or a PID. The first passivation layer 181 and the second passivation layer 182 of the semiconductor package 100 and the first passivation layer 281 of the component package 200 may include a plurality of openings 181H, 182H, and 281H for electrical connection.

[0098] In detail, a plurality of openings 181H are formed in the first passivation layer 181 of the semiconductor package 100 to expose a portion of the third redistribution layer 152, and a first under bump metallization layer 160 is formed to be connected to a portion of the third redistribution layer 152 through the plurality of openings 181H, and a first electrical connection metal body 170 may be formed.

[0099] Similarly, a plurality of openings 281H are formed in the first passivation layer 281 of the component package 200 to expose a portion of the second redistribution layer 242, and the second under bump metallization layer 260 is formed to be connected to a portion of the second redistribution layer 242 through the plurality of openings 281H, and a second electrical connection metal body 270 may be formed. A plurality of openings 182H are formed in the second passivation layer 182 of the semiconductor package 100 to expose a portion of the first redistribution layer 142, and the second electrical connection metal body 270 may be connected to a portion of the first redistribution layer 142 through the plurality of openings 182H.

[0100] The underfill 380 surrounding the second electrical connection metal body 270 fills a gap between the second surface 140B of the first connection structure 140 and the first surface 240A of the second connection structure 240 , so that the semiconductor package 100 and the component package 200 may be firmly combined with each other.

[0101] The first under-bump metallization layer 160 and the second under-bump metallization layer 260 may be formed in the openings of the first passivation layer 181 and the first passivation layer 281 by a known metallization method using a known conductive material such as a metal, but the exemplary embodiments thereof are not limited thereto. The number, spacing, arrangement type, etc. of the first electrical connection metal bodies 170 and the second electrical connection metal bodies 270 are not particularly limited and may be fully modified according to the design specifications of those skilled in the art. For example, the number of the first electrical connection metal bodies 170 may be from tens to thousands, and may be a greater or lesser number, depending on the number of the connection pads 120P.

[0102] The first electrically connected metal body 170 and the second electrically connected metal body 270 are used to physically and / or electrically connect the semiconductor package 100 to an external device such as a main board of an electronic device. The first electrically connected metal body 170 and the second electrically connected metal body 270 may include a low melting point metal, for example, a solder of tin (Sn)-aluminum (Al)-copper (Cu), etc. The first electrically connected metal body 170 may be a multi-layer or a single layer. For example, the multi-layer may include a copper column and a solder, and the single layer may include a tin-silver solder or copper.

[0103] The first electrical connection metal body 170 and the second electrical connection metal body 270 are shown in a spherical shape, but may have another structure with a constant height (such as a structure in the form of a pad or a pin). Therefore, a specific installation space can be ensured on the upper surface of the insulating layer 141 by adjusting the height of the first electrical connection metal body 170.

[0104] The electronic component module 300 according to the exemplary embodiment adopts the connector as the uppermost structure, thereby significantly reducing the size of the main board. Fig. 12A and Fig. 12B , a miniaturization effect of a main board of an electronic component module according to example embodiments will be described.

[0105] Fig. 12A is a diagram showing an exemplary embodiment according to the present invention. Fig. 9 An example of an application of an electronic component module is a plan view showing the components, and Fig. 12B is along Fig. 12A A cross-sectional view of the display assembly taken along line II1-II1'. Fig.13 It is taken along line II2-II2' Fig. 12A A cross-sectional view of a display assembly.

[0106] Reference Fig. 12A and Fig. 12B , the electronic device may include a main board 400 , a display panel 500 , and a rigid-flexible printed circuit board (RF-PCB) 600 connecting the main board 400 and the display panel 500 .

[0107] The connector 650 of the rigid-flexible PCB 600 may be coupled to the connector 350 for the main board 400 to ensure power / signal connection between the display panel 500 and the main board 400. Such an electronic device may be a mobile device.

[0108] like Fig.13 As shown in FIG. 4 , the electronic component module 300 mounted on the main board 400 includes a semiconductor package 100 having a semiconductor chip such as a power management IC (PMIC) chip, and a component package 200 disposed on the semiconductor package 100 and including passive components. Figures 9 to 11 The detailed construction of the electronic component module 300 can be understood.

[0109] The electronic component module 300 according to the example embodiment adopts the connector 350 for the main board 400 as its uppermost structure, and the connector 650 of the rigid-flexible PCB 600 may be connected to the connector 350 of the electronic component module 300. Therefore, the power / signal connection between the display panel 500 and the main board 400 may be ensured through the electronic component module 300.

[0110] As described above, the connector 350 can be provided by utilizing the installation space of the electronic component module 300, and additional space consumption of the main board 400 due to the connector 350 can be prevented. In addition, since various passive components can be provided in the component package 200 of the electronic component module 300, space consumption of the main board 400 due to the passive components can be reduced.

[0111] As a result, the main board 400 employed in the mobile device can be reduced in size, and sufficient space for other configurations such as a battery can be ensured, or the mobile device can be further miniaturized.

[0112] The electronic component module according to the example embodiment may be implemented in various forms. The component package structure and the semiconductor package structure may be variously changed (for example, see Fig.14 , Fig.16 and Fig.17 ), and the area of ​​the semiconductor package can be partially used to set the passive components without configuring a separate component package (for example, see Figures 15 to 17 ).

[0113] Fig.14 is a schematic cross-sectional view of an electronic component module according to example embodiments.

[0114] Reference Fig.14 It can be understood that, in addition to using the semiconductor package 100-A having a different structure, the electronic component module 300A according to the example embodiment has the same Figures 9 to 11 Unless otherwise specifically described, the description of the components of the example embodiments may refer to Figures 9 to 11 . Description of the same or similar components of the electronic component module 300 shown in FIG.

[0115] The semiconductor package 100-A employed in the example embodiment includes a first frame 110', which is disposed on a first surface 140A of a connection structure 140 and includes a cavity 110H' having a concave shape, only a second surface 110B of which is open. The semiconductor chip 120 may be accommodated in the cavity 110H' in such a manner that an inactive surface of the semiconductor chip 120 faces the bottom surface of the cavity 110H'. The bottom surface of the cavity 110H' may include a stopper layer 112M formed using a material such as a metal and used as a stopper when the cavity 110H' is formed. The inactive surface of the first semiconductor chip 120 and the bottom surface of the cavity 110H' may be attached to each other by an adhesive layer 125.

[0116] The conductive bump 120B may be disposed on the connection pad 120P of the semiconductor chip 120. The conductive bump 120B has a predetermined height and may have a substantially flat upper surface that is level with the surface of the first encapsulant 130. The connection pad 120P of the semiconductor chip 120 may be connected to the first redistribution layer 142 (in detail, the first redistribution via 143 of the first connection structure 140) through the conductive bump 120B.

[0117] The first frame 110' adopted in the exemplary embodiment includes: a core insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, which are respectively arranged on the lower surface and the upper surface of the core insulating layer 111a; a first reinforced insulating layer 111b, which is arranged under the core insulating layer 111a to cover the first wiring layer 112a; a third wiring layer 112c, which is arranged on the first reinforced insulating layer 111b; a second reinforced insulating layer 111c, which is arranged on the upper side of the core insulating layer 111a to cover the second wiring layer 112b; and a fourth wiring layer 112d, which is arranged on the second reinforced insulating layer 111c.

[0118] The first frame 110' includes: a first wiring via 113a, which penetrates the core insulating layer 111a and connects the first wiring layer 112a and the second wiring layer 112b; a second wiring via 113b, which penetrates the first reinforced insulating layer 111b and connects the first wiring layer 112a and the third wiring layer 112c; and a third wiring via 113c, which penetrates the second reinforced insulating layer 111c and connects the second wiring layer 112b and the fourth wiring layer 112d.

[0119] Similar to the aforementioned embodiment, the component package 200 is disposed on the semiconductor package 100-A, and the first redistribution layer 142 of the first connection structure 140 and the second redistribution layer 242 of the second connection structure 240 may be electrically connected to each other. The connector 350 is disposed on the component package 200, and the external connection terminal 319 of the connector 350 may be electrically connected to the second wiring structure 215 (specifically, the second wiring layer 212b).

[0120] The connector 350 used in the example embodiment can be electrically connected to the first redistribution layer 142 and the third redistribution layer 152 of the semiconductor package 100-A and the first wiring structure 115, and is electrically connected to the second wiring structure 215 and the second redistribution layer 242, and therefore, can also be electrically connected to the passive component 220 and the semiconductor chip 120.

[0121] Fig.15 is a schematic cross-sectional view of an electronic component module according to example embodiments.

[0122] Reference Fig.15 , except that a separate component package is not formed, the electronic component module 300B according to the example embodiment may be understood to be similar to Figures 9 to 11 Unless otherwise specifically described, the description of the components of the example embodiments may refer to Figures 9 to 11 . Description of the same or similar components of the electronic component module 300 shown in FIG.

[0123] Although the electronic component module 300B according to the example embodiment includes Fig. 9 The semiconductor package 100 of the example embodiment shown in FIG. 1 is similar to the semiconductor package 100 , but instead of separate component packages (see FIG. 1 ), the semiconductor package 100 of FIG. 1 is similar to the semiconductor package 100 of the example embodiment shown in FIG. Fig. 9 200 in FIG), the passive component 220 may be directly disposed on the second surface 100B of the semiconductor package 100, for example, disposed on the second surface 140B of the first connection structure 140. The passive component 220 may be connected to a portion of the first redistribution layer 142 through the low melting point metal body 275. The connection region of the first redistribution layer 142 may be defined by the opening of the second passivation layer 182.

[0124] The second frame 210 is used as an intermediary for interconnecting the connector 350 and the semiconductor package 100. The second frame 210 may include a first wiring layer 212a and a second wiring layer 212b respectively disposed on both surfaces of an insulating member 211, and a wiring via 213 penetrating the insulating member 211 to connect the first wiring layer 212a and the second wiring layer 212b, but example embodiments thereof are not limited thereto, and therefore, may also have another wiring structure providing a vertical connection path form.

[0125] The second frame 210 may include a first passivation layer 281 and a second passivation layer 282 disposed on the first surface 210A and the second surface 210B thereof, respectively. The first passivation layer 281 and the second passivation layer 282 may each have an opening that exposes a portion of the first wiring layer 212a and the second wiring layer 212b. The external connection terminal 319 of the connector 350 is connected to the second wiring structure 215 (specifically, the second wiring layer 212b) through a third electrical connection metal body 320 such as a low melting point metal, and the second wiring structure 215 (specifically, the first wiring layer 212a) may be connected to the first redistribution layer 142 of the semiconductor package 100 through the second electrical connection metal body 270.

[0126] Fig.16 is a cross-sectional view schematically illustrating an electronic component module according to example embodiments.

[0127] Reference Fig.16 , except that a semiconductor package 100-B having another structure is adopted and a separate component package is not configured, an electronic component module 300C according to an example embodiment may be understood as being similar to Figures 9 to 11 Unless otherwise specifically described, the description of the components of the example embodiments may refer to Figures 9 to 11 . Description of the same or similar components of the electronic component module 300 shown in FIG.

[0128] The semiconductor package 100-B according to the example embodiment may not have a frame structure, but may have a metal column 115' that penetrates the encapsulant 130 as a wiring structure (vertical connection structure). The metal column 115' may include, for example, copper (Cu). One end of the metal column 115' is connected to the first redistribution layer 142 of the first connection structure 140, and the other end of the metal column 115' is connected to the third redistribution layer 152. The third redistribution layer 152 may be provided on the surface of the first encapsulant 130.

[0129] Although only the semiconductor package 100-B is illustrated as having a wiring structure using the metal pillars 115' without adopting a frame structure in this embodiment, similarly, in Fig. 9 and Fig.14In the case of a wiring structure of the component package 200 , the second frame 210 may be replaced by a metal post penetrating the second encapsulant 230 .

[0130] The electronic component module 300C according to the example embodiment may be configured in such a manner that the passive component 220 is directly disposed on the second surface 100B of the semiconductor package 100-B (e.g., disposed on the second surface 140B of the first connection structure 140). In addition, the second frame 210 may have a second wiring structure 215 interconnecting the connector 350 and the semiconductor package 100-B.

[0131] The second wiring structure 215 may include a first wiring layer 212a and a second wiring layer 212b and a wiring via 213 penetrating the insulating member 211. The external connection terminal 319 of the connector 350 may be connected to the second wiring structure 215 (specifically, the second wiring layer 212b) through a third electrical connection metal body 320 such as a low melting point metal. The second wiring structure 215 (specifically, the first wiring layer 212a) may be connected to the first redistribution layer 142 of the semiconductor package 100-B through a second electrical connection metal body 270.

[0132] Fig.17 is a cross-sectional view schematically illustrating an electronic component module according to example embodiments.

[0133] Reference Fig.17 , except that a semiconductor package 100C having another structure is adopted and a separate component package is not configured, an electronic component module 300D according to example embodiments may be understood to be similar to Fig. 9 and Fig.10 Unless otherwise specifically described, the description of the components of the example embodiments may refer to Fig. 9 and Fig.10 1. Description of the same or similar components of the electronic component package 100 shown in FIG.

[0134] Similar to reference Fig.16 According to the semiconductor package 100-B of the example embodiment, the semiconductor package 100C according to the example embodiment may not have a frame structure, but may have a low-melting-point metal body 115" that penetrates the encapsulant 130 as a wiring structure (vertical connection structure). The low-melting-point metal body 115" may include, for example, a solder ball. The low-melting-point metal body 115" may be connected to the first redistribution layer 142 of the first connection structure 140 and extend to the mounting surface of the semiconductor package to be exposed outside the first encapsulant 130.

[0135] In the case of the electronic component module 300D according to the example embodiment, similar to Fig.15 and Fig.16In the electronic component modules 300B and 300C shown in FIG, the passive component 220 may be directly disposed on the second surface 100B of the semiconductor package 100C (eg, disposed on the second surface 140B of the first connection structure 140). In addition, the second frame 210 may have a second wiring structure 215 interconnecting the connector 350 and the semiconductor package 100C.

[0136] Similar to the first connection structure 140 of the aforementioned embodiment, the first connection structure 190 used in this embodiment may include a redistribution layer 192 for redistributing the connection pads 120P of the semiconductor chip 120 and a redistribution via 193, and may also be implemented as a structure having, for example, Fig.17 The thickness of the first connection structure 140 of the aforementioned embodiment shown in FIG. In detail, similar to the case of the second frame 210, the first connection structure 190 may be understood to have a form manufactured by a general printed circuit board manufacturing process.

[0137] The thickness of the redistribution layer 192 of the first connection structure 190 may be similar to the thickness of the wiring layer of another frame (such as the wiring layer in the second frame 210), and the thickness of the redistribution layer 192 of the first connection structure 190 may be greater than the thickness of the redistribution layer of the connection structure manufactured by using a photosensitive dielectric material as an insulating layer. The insulating layer 191 constituting the first connection structure 190 may be formed using a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins and an inorganic filler, or a resin impregnated with these resins using a core material such as glass fiber, glass cloth, glass fabric, etc. and an inorganic filler (for example, prepreg resin, ABF (Ajinomoto Build-up Film) resin, FR-4 resin, bismaleimide triazine (BT) resin, etc.).

[0138] As described above, by using the uppermost structure of the electronic component module as a connector and installing passive components in a single module, the size of the main board can be significantly reduced. As a result, sufficient space for other structures such as a battery can be ensured, or the mobile device can be further miniaturized.

[0139] As described above, according to example embodiments, an electronic component module in which a mounting space of a main board can be significantly reduced by modularizing various components such as passive components together with a semiconductor chip into one body to be coupled to a connector can be provided.

[0140] In the present invention, for the sake of convenience, the lower side, lower part, lower surface, etc. refer to the downward direction relative to the cross section of the drawings, and the upper side, upper part, and upper surface are used in the opposite direction. However, it should be noted that this is a definition of direction for the purpose of convenience of explanation, and the scope of rights of the claims is not particularly limited by the description of such direction.

[0141] In the present invention, the meaning of connection includes not only direct connection, but also indirect connection. In addition, the term "electrical connection" represents a concept including physical connection and physical disconnection. In addition, the expressions "first", "second", etc. are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

[0142] The expression "example" used in the present inventive concept does not mean the same embodiment, but is provided to emphasize and explain different unique features. However, the above examples or embodiments do not exclude implementation in the form of a combination of features with other examples. For example, although the description in a specific example is not described in another example, it can be understood as an explanation related to another example unless otherwise described or contradicted with another example.

[0143] The terms used in the inventive concept are only for illustrative examples and are not intended to limit the inventive concept. Unless the context clearly dictates otherwise, a singular expression includes a plural expression.

[0144] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. An electronic component module, comprising: A semiconductor package having a first surface provided as a mounting surface and a second surface opposite to the first surface, and including a semiconductor chip; a component package having a first surface facing the second surface of the semiconductor package and a second surface opposite the first surface of the component package, the component package including a passive component; as well as A connector is provided on the second surface of the component package and has a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface.

2. The electronic component module according to claim 1, wherein: The semiconductor package further comprises: a first connection structure having a first surface and a second surface opposite to each other, the second surface of the first connection structure providing the second surface of the semiconductor package, the first connection structure having a first redistribution layer, a first encapsulant disposed on the first surface of the first connection structure and encapsulating the semiconductor chip; and a first wiring structure connected to the first redistribution layer and extending to the mounting surface of the semiconductor package, The semiconductor chip is disposed on the first surface of the first connection structure and includes a connection pad connected to the first redistribution layer.

3. The electronic component module according to claim 2, wherein: The semiconductor package further comprises: a first frame having a first surface and a second surface opposite to each other, the second surface of the first frame being in contact with the first surface of the first connection structure, the first frame having a cavity for accommodating the semiconductor chip, and The first wiring structure penetrates the first surface and the second surface of the first frame.

4. The electronic component module according to claim 3, wherein: The cavity has a through hole penetrating the first surface and the second surface of the first frame.

5. The electronic component module according to claim 3, wherein: The cavity is a recess in which the second surface of the first frame is open.

6. The electronic component module according to claim 3, wherein: The semiconductor package further comprises: An additional redistribution layer is disposed on the first surface of the first frame and on the first encapsulant and is connected to the first wiring structure on the first surface of the first frame.

7. The electronic component module according to claim 2, wherein: The first wiring structure includes a first metal pillar penetrating the first encapsulant.

8. The electronic component module according to claim 2, wherein: The semiconductor package further comprises: An electrical connection metal body is disposed on the mounting surface and is electrically connected to the first redistribution layer through the first wiring structure.

9. The electronic component module according to claim 2, wherein: The component package comprises: a second connection structure having a first surface facing the second surface of the first connection structure and a second surface opposite to the first surface of the second connection structure, the second connection structure comprising a second redistribution layer electrically connected to the first redistribution layer; the passive component being disposed on the second surface of the second connection structure and connected to the second redistribution layer; a second encapsulant disposed on the second surface of the second connection structure and encapsulating the passive component; and a second wiring structure connected to the second redistribution layer and extending to the second surface of the component package, and The connector is electrically connected to the second wiring structure.

10. The electronic component module according to claim 9, wherein: The component package further comprises: a second frame having a first surface in contact with the second surface of the second connection structure and a second surface opposite to the first surface of the second frame, the second frame including a through hole penetrating the first surface and the second surface of the second frame and accommodating the passive component, and The second wiring structure penetrates the first surface and the second surface of the second frame.

11. The electronic component module according to claim 9, wherein: The second wiring structure includes a metal pillar penetrating the second encapsulant.

12. An electronic component module, comprising: a connection structure having a first surface and a second surface opposite to each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a first wiring structure connected to the redistribution layer and extending in a direction substantially perpendicular to the first surface; a passive component disposed on the second surface of the connection structure and connected to the redistribution layer; a frame having a first surface in contact with the second surface of the connection structure and a second surface opposite to the first surface of the frame, the frame having a through hole penetrating the first surface and the second surface of the frame and accommodating the passive component; a second wiring structure connected to the redistribution layer and penetrating the first surface and the second surface of the frame; as well as A connector is provided on the second surface of the frame and has a connection surface configured to be mechanically coupled to an external device, the connector including a plurality of connection lines arranged on the connection surface and electrically connected to the second wiring structure.

13. The electronic component module according to claim 12, further comprising: an additional frame having a second surface in contact with the first surface of the connection structure and a first surface opposite to the second surface of the additional frame, the additional frame comprising a through hole for accommodating the semiconductor chip, The first wiring structure passes through the first surface and the second surface of the additional frame.

14. The electronic component module according to claim 13, further comprising: An additional redistribution layer is disposed on the first surface of the additional frame and on the encapsulant and is connected to the first wiring structure on the first surface of the additional frame.

15. The electronic component module according to claim 14, further comprising: a passivation layer disposed on the first surface of the additional frame and on the encapsulant and having a plurality of openings exposing a portion of the additional redistribution layer; as well as An electrical connection metal body is disposed on the passivation layer and is electrically connected to the additional redistribution layer.

16. The electronic component module according to claim 12, wherein: The first wiring structure includes a metal pillar penetrating the encapsulant.

17. An electronic component module, comprising: a first frame having a through hole and including a first wiring structure having a wiring layer disposed on a surface of the first frame; A passive component is disposed in the through hole; a connecting member on which the first frame is disposed, the connecting member comprising a redistribution layer, the passive components and the first wiring structure being connected to the redistribution layer; a semiconductor chip connected to the redistribution layer, the semiconductor chip and the passive components being disposed on opposite sides of the connection member; a connector disposed above the through hole and having a connection terminal extending to the wiring layer of the first wiring structure; as well as The metal bodies are electrically connected to connect the connection terminals to the wiring layers, respectively.

18. The electronic component module according to claim 17, further comprising: The second frame has a cavity or a through hole for accommodating the semiconductor chip and includes a second wiring structure connected to the redistribution layer.

19. The electronic component module according to claim 17, wherein: The connection member includes an upper portion and a lower portion, each including a redistribution layer; and an electrical connection metal body connecting the redistribution layer of the upper portion and the redistribution layer of the lower portion to each other.

20. The electronic component module according to claim 17, wherein: The connector includes connection wires that are arranged on a connection surface of the connector and are respectively connected to the connection terminals.

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