Semiconductor device

Abstract

A semiconductor device includes an active pattern including channel regions. The channel regions are arranged between first source / drain patterns spaced apart from each other in a first direction and second source / drain patterns spaced apart from each other in the first direction. The channel regions are configured to connect the first source / drain patterns to each other and the second source / drain patterns to each other. A gate electrode is arranged on a bottom surface of the active pattern and between the first source / drain patterns and the second source / drain patterns. An upper interconnection line is arranged on a top surface of the active pattern opposite the bottom surface of the active pattern and connected to the first source / drain patterns.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0059390, filed on May 21, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Background Technology

[0004] The demand for highly reliable, high-performance, and / or multifunctional semiconductor devices is increasing. The structural complexity and / or integration density of semiconductor devices have increased to meet these technical requirements. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor device with high integration density and improved reliability.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes an active pattern comprising a channel region. The channel region is disposed between a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction. The channel region is configured to connect the first source / drain pattern and the second source / drain pattern to each other. A gate electrode is disposed on the bottom surface of the active pattern and is disposed between the first source / drain pattern and between the second source / drain pattern. An upper interconnect is disposed on the top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source / drain pattern.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction. An active pattern is disposed between opposing sidewalls of the first and second source / drain patterns. A gate electrode is disposed on the bottom surface of the active pattern. An insulating layer is disposed on the top surface of the active pattern. An upper interconnect is disposed on the insulating layer and electrically connected to the first source / drain pattern. The first source / drain pattern includes a first portion adjacent to a side surface of the active pattern and a second portion extending from the first portion into the insulating layer. The maximum width of the first portion in the first direction is smaller than the maximum width of the second portion in the first direction.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor device includes a substrate including a PMOS region and an NMOS region. A plurality of first active regions is disposed on the PMOS region. The plurality of first active regions extends in a first direction. A plurality of second active regions is disposed on the NMOS region. The plurality of second active regions extends in the first direction. A gate electrode crosses the plurality of first active regions and the plurality of second active regions and extends in a second direction crossing the first direction. A portion of the gate electrode is located between a bottom surface of the first active region and a top surface of the substrate. First source / drain patterns are spaced apart from each other in the first direction with the gate electrode interposed therebetween. The first source / drain patterns are connected to the plurality of first active regions. An upper interconnection line is disposed on a top surface of the first active region opposite the bottom surface of the first active region. The upper interconnection line is connected to at least a portion of the first source / drain patterns. BRIEF DESCRIPTION OF DRAWINGS

[0009] Exemplary embodiments will be more fully understood from the following brief description, taken in connection with the accompanying drawings, which are described with reference to non-limiting exemplary embodiments as described herein.

[0010] Figure 1 is a top plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0011] Figures 2A-2C is a cross-sectional view taken along line A-A', B-B', and C-C' of Figure 1 , respectively, according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 is a cross-sectional view taken along line A-A' of Figure 1 , illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0013] Figure 4A and Figure 4B is a cross-sectional view taken along line A-A' of Figure 1 , illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0014] Figure 5 is a cross-sectional view taken along line A-A' of Figure 1 , illustrating a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 are top plan views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept;

[0016] Figure 7A 、 Figure 9A 、 Figure 11A 、 Figure 13A 、 Figure 15A and Figure 17A are cross-sectional views taken along lines Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 16 of the exemplary embodiments according to the inventive concept, respectively;

[0017] Figure 7B 、 Figure 9B 、 Figure 11B 、 Figure 13B 、 Figure 15B and Figure 17B are cross-sectional views taken along lines Figure 6 、 Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 16 of the exemplary embodiments according to the inventive concept, respectively.

[0018] It should be noted that the figures are intended to show the general features of the methods, structures and / or materials utilized in particular example embodiments and to supplement the written specification that is provided below. However, the figures are not necessarily drawn to scale and can not accurately reflect the exact structural or performance characteristics of any given embodiment, and should not be interpreted as limiting or restricting the scope or range of values or properties encompassed by the exemplary embodiments. For example, relative thicknesses and positioning of molecules, layers, regions and / or structural elements can be reduced or exaggerated for clarity. The use of similar or identical reference numerals in various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings in which exemplary embodiments are shown.

[0020] Figure 1 is a top plan view showing a semiconductor device according to an exemplary embodiment of the inventive concept. Figures 2A-2C are cross-sectional views taken along lines Figure 1 A-A', B-B' and C-C' of

[0021] Reference is made to Figure 1 and Figures 2A-2CThe lower substrate 102 can include a p-channel metal-oxide field-effect transistor ("PMOSFET") region PR and an n-channel metal-oxide field-effect transistor ("NMOSFET") region NR. The lower substrate 102 can be a semiconductor substrate formed of or including silicon, germanium, or silicon-germanium, or a compound semiconductor substrate. For example, the lower substrate 102 can be a silicon wafer. However, exemplary embodiments of the inventive concept are not limited thereto.

[0022] In exemplary embodiments, the PMOSFET region PR and the NMOSFET region NR can be logic cell regions on which logic transistors constituting logic circuits of a semiconductor device are formed. For example, logic transistors constituting a processor core or an I / O terminal can be arranged on the logic cell regions of the lower substrate 102. The PMOSFET region PR and the NMOSFET region NR can include some of the logic transistors. The PMOSFET region PR and the NMOSFET region NR can be spaced apart from each other in a first direction D1. Each of the PMOSFET region PR and the NMOSFET region NR can extend in a second direction D2 perpendicular to the first direction D1.

[0023] A plurality of active patterns AP1 and AP2 extending in the second direction D2 can be disposed on the PMOSFET region PR and the NMOSFET region NR. For example, as shown in exemplary embodiments of FIGS. 1A and 1B, the active patterns AP1 and AP2 can include first active patterns AP1 on the PMOSFET region PR and second active patterns AP2 on the NMOSFET region NR. Figure 1 The first active patterns AP1 and the second active patterns AP2 can be disposed (e.g., in a third direction D3) on a top surface of the lower substrate 102 and can have a fin structure protruding in the third direction D3 perpendicular to the top surface of the lower substrate 102. Each of the first active patterns AP1 and the second active patterns AP2 can include a bottom surface APb facing the top surface of the lower substrate 102 and a top surface APa opposite to the bottom surface APb in the third direction D3.

[0024] In this specification, spatial relative terms, such as "beneath", "below", "lower", "bottom", "top", "on", "above", and the like, can be used to describe one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. The device can be oriented in any direction, and the spatially relative terms are intended to Figures 6-11BAs shown, if the devices in the figures are upside down, elements described as "beneath" or "below" other elements or features would then be oriented "above" the other elements or features. Therefore, the exemplary term "below" can encompass both an orientation of above and below. Likewise, a semiconductor extending in a first direction D1 can be rotated to change the direction of the semiconductor to a second direction D2, a third direction D3, etc. The semiconductor devices according to exemplary embodiments of the inventive concept can be oriented in other directions, and the spatial relative descriptions used herein are interpreted accordingly.

[0025] The gate electrodes GE can cross the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrodes GE can be spaced apart from each other in the second direction D2. When viewed in a plan view, the gate electrodes GE can overlap the channel regions CH1. Each of the gate electrodes GE can be arranged to face a bottom surface of each of the channel regions CH and two side surfaces of each of the channel regions CH, which are opposite to each other and extend in the third direction D3 and are spaced apart in the first direction D1 (see Figure 2C ). For example, the gate electrodes GE can be formed of or include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum). However, exemplary embodiments of the inventive concept are not limited thereto. A portion of the gate electrodes GE can be located between (e.g., spaced apart in the third direction D3 between) the bottom surfaces APb of the first active pattern AP1 and the second active pattern AP2 and the top surface of the lower substrate 102, as shown in Figure 2A . Further, an uppermost surface of the gate electrodes GE can be located at a level height not higher than that of the top surfaces APa of the first active pattern AP1 and the second active pattern AP2. For example, a distance between the top surface of the lower substrate 102 and the uppermost surface of the gate electrodes (e.g., in the third direction D3) can be less than or equal to a distance between the top surface of the lower substrate 102 and the top surfaces APa of the first active pattern AP1 and the second active pattern AP2 (e.g., in the third direction D3).

[0026] A pair of gate spacers GS can be disposed on two opposite sidewalls of each of the gate electrodes GE, respectively. The gate spacers GS can extend along the gate electrodes GE in the first direction D1. A bottom surface of the gate spacers GS can be located at a level lower than a bottom surface of the gate electrodes GE. For example, a distance between a top surface of the lower substrate 102 and a bottom surface of the gate spacers GS (e.g., in the third direction D3) can be less than a distance between the top surface of the lower substrate 102 and a bottom surface of the gate electrodes GE (e.g., in the third direction D3). The bottom surface of the gate spacers GS can be coplanar with a bottom surface of the first lower insulating layer 112, which will be described below. The gate spacers GS can be formed of or include at least one of SiCN, SiCON, and SiN. In an exemplary embodiment, the gate spacers GS can have a multi-layer structure including at least two layers, each layer being made of SiCN, SiCON, or SiN. However, exemplary embodiments of the inventive concept are not limited thereto.

[0027] The gate dielectric patterns GI can be interposed between the gate electrodes GE and the first and second active patterns AP1 and AP2. Each of the gate dielectric patterns GI can extend along a top surface (e.g., in the third direction D3) of a corresponding one of the gate electrodes GE. Each of the gate dielectric patterns GI can cover (e.g., in the third direction D3) a bottom surface and two side surfaces of each of the channel regions CH1, which extend in the third direction D3 and are spaced apart in the first direction D1. The gate dielectric patterns GI can be formed of or include at least one high-k dielectric material. Examples of the high-k dielectric material can include at least one selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, exemplary embodiments of the inventive concept are not limited thereto.

[0028] The gate capping patterns GP can be disposed (e.g., in the third direction D3) on a bottom surface of each of the gate electrodes GE. The gate capping patterns GP can extend along the gate electrodes GE in the first direction D1. The gate capping patterns GP can include a material having etch selectivity with respect to the first and second lower insulating layers 112 and 114, which will be described below. For example, the gate capping patterns GP can be formed of or include at least one of SiON, SiCN, SiCON, and SiN. However, exemplary embodiments of the inventive concept are not limited thereto.

[0029] A first source / drain pattern SD1 can be disposed on a side surface of the first active pattern AP1. The first source / drain pattern SD1 can include impurities of a first conductivity type (e.g., p-type). A first channel region CH1 can be interposed between a pair of the first source / drain patterns SD1. A second source / drain pattern SD2 can be disposed on a side surface of the second active pattern AP2. The second source / drain pattern SD2 can include impurities of a second conductivity type (e.g., n-type). A second channel region CH2 can be interposed between a pair of the second source / drain patterns SD2.

[0030] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. A bottom surface of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be disposed at a level lower than a bottom surface of the first channel region CH1 and the second channel region CH2. For example, a distance between a top surface of the lower substrate 102 and a bottom surface of the first source / drain pattern SD1 and the second source / drain pattern SD2 (e.g., in the third direction D3) can be less than a distance between the top surface of the lower substrate 102 and a bottom surface of the first channel region CH1 and the second channel region CH2 (e.g., in the third direction D3). The first source / drain pattern SD1 and the second source / drain pattern SD2 can have a top surface disposed at a level higher than a top surface of the first channel region CH1 and the second channel region CH2. For example, a distance between the top surface of the lower substrate 102 and a top surface of the first source / drain pattern SD1 and the second source / drain pattern SD2 (e.g., in the third direction D3) can be greater than a distance between the top surface of the lower substrate 102 and a top surface of the first channel region CH1 and the second channel region CH2 (e.g., in the third direction D3). The first source / drain pattern SD1 can include a semiconductor material (e.g., SiGe) having a lattice constant greater than a lattice constant of the lower substrate 102. In this example embodiment, the first source / drain pattern SD1 can exert compressive stress on the first channel region CH1. In an example embodiment, the second source / drain pattern SD2 can include a semiconductor material (e.g., Si) identical to a material of the lower substrate 102.

[0031] The first source / drain patterns SD1 can pass through the first upper insulating layer 120, which will be described below, and can extend to cover a portion of a top surface of the first upper insulating layer 120. Each of the first source / drain patterns SD1 can include a first portion SDB and a second portion SDE extending (e.g., in the third direction D3) from the first portion SDB. The first portion SDB of the first source / drain pattern SD1 can be arranged between opposite sidewalls of the first active pattern AP1 (e.g., in the second direction D2). The second portion SDE of the first source / drain pattern SD1 can be located at a higher vertical level than the top surface APa of the first active pattern AP1. For example, a distance between the top surface of the lower substrate 102 and the second portion SDE of the first source / drain pattern SD1 (e.g., in the third direction D3) can be greater than a distance between the top surface of the lower substrate 102 and the top surface APa of the first active pattern AP1 (e.g., in the third direction D3). As shown, a maximum width W2 (e.g., a length in the second direction D2) of the second portion SDE of the first source / drain pattern SD1 can be greater than a maximum width W1 (e.g., a length in the second direction D2) of the first portion SDB of the first source / drain pattern SD1. For example, the first source / drain pattern SD1 can have the maximum width at a higher level (e.g., in the third direction D3) than the top surface APa of the first active pattern AP1. Figure 2A

[0032] The first upper insulating layer 120, the second upper insulating layer 122, and the third upper insulating layer 124 can be stacked in order on the top surface APa of the first active pattern AP1. For example, as shown, the second upper insulating layer 122 (e.g., in the third direction D3) can be directly arranged on a top surface of the first upper insulating layer 120. The third upper insulating layer 124 (e.g., in the third direction D3) can be directly arranged on a top surface of the second upper insulating layer 122. Figure 2A

[0033] Each of the first upper insulating layer to the third upper insulating layer 120, 122, and 124 can include a silicon oxide layer or a silicon oxynitride layer. However, example embodiments of the inventive concept are not limited thereto.

[0034] The upper contact UAC can pass through the second upper insulating layer 122 and can be electrically connected to the first source / drain patterns SD1 and the second source / drain patterns SD2. The upper contact UAC can have a strip pattern extending in the first direction D1. For example, as shown in the example embodiment of FIG. 1A, the upper contact UAC (e.g., in the third direction D3) can be directly arranged on top surfaces of the second portions SDE of the first source / drain patterns SD1 and the second source / drain patterns SD2. Figure 2A

[0035] ​​​The first upper interconnect POR1, the second upper interconnect POR2, and the upper via UV can be disposed in the third upper insulating layer 124. For example, as Figure 2A As shown, the bottom surface of the upper via UV (e.g., on third-direction D3) can directly contact the top surface of the upper contact UAC (e.g., on third-direction D3). The bottom surface of the first upper interconnect POR1 can contact the top surface of the upper via UV. The upper via UV can connect the first upper interconnect POR1 and the second upper interconnect POR2 to the upper contact UAC. The first upper interconnect POR1 and the second upper interconnect POR2 can be power rails, such as embedded power rails. For example, the first upper interconnect POR1 and the second upper interconnect POR2 can be supplied with a power supply voltage or a ground voltage. The first upper interconnect POR1 can be connected to at least one of the first source / drain patterns SD1 through the upper via UV. The second upper interconnect POR2 can be connected to at least one of the second source / drain patterns SD2 through the upper via UV. The first upper interconnect POR1 can be used to apply a power supply voltage to the first source / drain pattern SD1, and the second upper interconnect POR2 can be used to apply a ground voltage to the second source / drain pattern SD2.

[0036] First upper interconnect POR1 and second upper interconnect POR2 may extend in the second direction D2. The width of the first upper interconnect POR1 (e.g., its length in the first direction D1) may be greater than the width of the first active pattern AP1 (e.g., its length in the first direction D1). When viewed in plan view, the first upper interconnect POR1 (e.g., in the third direction D3) may at least partially overlap with each of the first source / drain patterns SD1 disposed thereunder. Similarly, the width of the second upper interconnect POR2 (e.g., its length in the first direction D1) may be greater than the width of the second active pattern AP2 (e.g., its length in the first direction D1). When viewed in plan view, the second upper interconnect POR2 (e.g., in the third direction D3) may at least partially overlap with each of the second source / drain patterns SD2 disposed thereunder.

[0037] The first lower insulating layer 112, the second lower insulating layer 114, and the third lower insulating layer 116 can be arranged between the first active pattern AP1 and the second active pattern AP2 and the lower substrate 102.

[0038] A first lower insulating layer 112 may be disposed on the bottom surface APb of the first active pattern AP1 and the second active pattern AP2. For example, the top surface of the first lower insulating layer 112 (e.g., on the third direction D3) may be directly disposed on the bottom surface APb of the first active pattern AP1 and the second active pattern AP2. The first lower insulating layer 112 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The bottom surface of the first lower insulating layer 112 (e.g., on the third direction D3) may be substantially coplanar with the bottom surface of the gate cap pattern GP and the bottom surface of the gate spacer GS. A second lower insulating layer 114 may be formed on the bottom surface of the first lower insulating layer 112 and may cover the gate cap pattern GP. For example, the top surface of the second lower insulating layer 114 (e.g., on the third direction D3) may be directly disposed on the bottom surface of the first lower insulating layer 112. For example, the first lower insulating layer 112 and the second lower insulating layer 114 may include silicon oxide layers. However, exemplary embodiments of the inventive concept are not limited thereto.

[0039] The lower contact LAC may be arranged to pass through the first lower insulating layer 112 and the second lower insulating layer 114, and may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, a contact hole may be formed in the first lower insulating layer 112 and the second lower insulating layer 114 to pass through the first lower insulating layer 112 and the second lower insulating layer 114 and expose the first source / drain pattern SD1 or the second source / drain pattern SD2. The lower contact LAC may be disposed in the contact hole. The lower contact LAC may be arranged between a pair of gate electrodes GE. The lower contact LAC may extend from a first portion SDB of the first source / drain pattern SD1 (e.g., on a third direction D3) to the bottom surface of the second lower insulating layer 114.

[0040] The lower interconnect LML and lower via LV can be disposed in the third lower insulating layer 116. For example, as Figure 2A In the exemplary embodiment shown, the bottom surface of the lower contact LAC (e.g., on the third direction D3) may be disposed on the top surface of the third lower insulating layer 116 and may directly contact the top surface of the third lower insulating layer 116. However, the exemplary embodiments of the inventive concept are not limited thereto. A lower via LV can connect the lower contact LAC to the lower interconnect LML. For example, as Figure 2A As shown, the top surface of the lower via LV (e.g., on third-party D3) may contact the bottom surface of the lower contact LAC (e.g., on third-party D3). The top surface of the lower interconnect LML (e.g., on third-party D3) may contact the bottom surface of the lower via LV (e.g., on third-party D3).

[0041] like Figure 2CAs shown, the gate contact GC can be disposed through the second lower insulating layer 114 and the gate cap pattern GP, and can be electrically connected to the gate electrode GE. In example embodiments, the gate contact GC can be disposed between the PMOSFET region PR and the NMOS region NR when viewed in plan view. For example, the gate contact GC can be spaced apart from the PMOSFET region PR and the NMOS region NR in the first direction D1. The gate contact GC can pass through the gate cap pattern GP, and can be in contact with a bottom surface of the gate electrode GE. A bottom surface of the gate contact GC (e.g., in the third direction D3) can be coplanar with a bottom surface of the second lower insulating layer 114 (e.g., in the third direction D3). In contrast to the direction of the upper contact UAC extending upward to the first upper interconnect line POR1 and the second upper interconnect line POR2, the gate contact GC extends in a downward direction to the lower interconnect line LML.

[0042] Figure 3 is a cross-sectional view taken along line A-A' of Figure 1 , according to example embodiments of the inventive concepts.

[0043] Referring to Figure 3 , unlike Figure 2A , example embodiments in Figure 3 include a first active pattern AP1 having a top surface at a level higher than an interface between a first portion SDB and a second portion SDE of the first source / drain pattern SD1. For example, a distance between a top surface (e.g., in the third direction D3) of the lower substrate 102 to a top surface (e.g., in the third direction D3) of the first active pattern AP1 is greater than a distance between the top surface of the lower substrate to the interface between the first portion SDB and the second portion SDE of the first source / drain pattern SD1.

[0044] Figure 4A and Figure 4B is a cross-sectional view taken along line A-A' of Figure 1 , according to example embodiments of the inventive concepts.

[0045] Referring to Figure 4AThe second portion SDE of the first source / drain pattern SD1 can include a first member SDE-1 and a second member SDE-2 spaced apart from each other in the first direction D1. Each of the first member SDE-1 and the second member SDE-2 can pass through the first upper insulating layer 120 and can be connected to the first portion SDB of the first source / drain pattern SD1. Some portions of the first member SDE-1 and the second member SDE-2 of the second portion SDE passing through the first upper insulating layer 120 can have a narrower width (e.g., a length in the first direction D1) than that of the portion of the first member SDE-1 and the second member SDE-2 disposed above the first upper insulating layer 120.

[0046] Referring to Figure 4B In the illustrated example embodiment, the second portion SDE of the first source / drain pattern SD1 can be connected to the first portion SDB of the first source / drain pattern SD1 through an opening formed in the first upper insulating layer 120. Accordingly, the first portion SDB and the second portion SDE of the first source / drain pattern SD1 can be seamlessly connected to each other without the first upper insulating layer 120 or the first lower insulating layer 112 interposed therebetween.

[0047] Figure 5 FIG. 16 is a cross-sectional view taken along line A-A' of FIG. 15, illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 1

[0048] Referring to Figure 5 A semiconductor device according to an example embodiment of the inventive concept can have a wrap-around gate structure. For example, the first active pattern AP1 can include a plurality of channel regions CHP interposed between adjacent first source / drain patterns SD1. The channel regions CHP can be stacked and vertically spaced apart from each other. An insulating pattern ILL can be interposed between the first source / drain patterns SD1 and the gate electrode GE. The insulating pattern ILL can be interposed between the channel regions CHP. The insulating pattern ILL can electrically isolate the gate electrode GE from the first source / drain patterns SD1.

[0049] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 FIGS. 18A through 18E are top plan views illustrating a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept. Figure 7A , Figure 9A , Figure 11A , Figure 13A , Figure 15A and Figure 17A are cross-sectional views taken along lines A-A' of FIGS. 18A through 18E, respectively. Figure 6 , Figure 8 , Figure 10 ,​Figure 12 , Figure 14 and Figure 16 a cross-sectional view taken along line A-A' of Figure 7B , Figure 9B , Figure 11B , Figure 13B , Figure 15B and Figure 17B a cross-sectional view taken along line B-B' of Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 a cross-sectional view taken along line B-B' of

[0050] For the convenience of explanation of a method of manufacturing a semiconductor device according to exemplary embodiments of the present inventive concept, Figures 6-11B a capsized shape of a semiconductor device is illustrated. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0051] Referring to Figure 6 , Figure 7A and Figure 7B , a substrate 100 including a first active pattern AP1 and a second active pattern AP2 can be formed. The substrate 100 can include an etch stop layer ESL.

[0052] In exemplary embodiments, an ion implantation process and / or an epitaxial growth process can be performed on a semiconductor layer to form the etch stop layer ESL. Then, the substrate 100 including the etch stop layer ESL can be formed by growing a semiconductor layer on the etch stop layer ESL. In exemplary embodiments, the substrate 100 can be formed of or include silicon and silicon germanium. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0053] The substrate 100 including the etch stop layer ESL can be patterned to form the first active pattern AP1 and the second active pattern AP2. The etch stop layer ESL can be located under the first active pattern AP1 and the second active pattern AP2.

[0054] A device isolation layer ST can be formed on the substrate 100 to fill a gap region between the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be formed of or include an insulating material such as silicon oxide. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0055] Referring to Figure 8 , Figure 9A and Figure 9B , a first source / drain pattern SD1 and a second source / drain pattern SD2 and a gate structure GST can be formed on the first active pattern AP1.

[0056] For example, a first portion SDB of the first source / drain pattern SD1 can be formed on the first active pattern API. As Figure 9A In the exemplary embodiment shown, the first portion SDB of the first source / drain pattern SD1 can be formed directly on the first active pattern API. The first portion SDB of the second source / drain pattern SD2 can be formed on the second active pattern AP2. For example, the first portion SDB of the second source / drain pattern SD2 can be formed directly on the second active pattern AP2. The first portion SDB of the first source / drain pattern SD1 can be doped with p-type impurities, and the first portion SDB of the second source / drain pattern SD2 can be doped with n-type impurities. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the first portion SDB of the first source / drain pattern SD1 can be doped with n-type impurities, and the first portion SDB of the second source / drain pattern SD2 can be doped with p-type impurities.

[0057] The first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. For example, the first active pattern API and the second active pattern AP2 can be partially recessed. An epitaxial growth process can then be performed on the recessed portions of the first active pattern API and the second active pattern AP2. The first lower insulating layer 112 can be formed to cover the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0058] Then, gate electrodes GE can be formed to cross the first active pattern API and the second active pattern AP2, and to extend in the first direction D1. Gate dielectric patterns GI can be formed between the gate electrodes GE and the first active pattern API and the second active pattern AP2, respectively. Gate spacers GS can be formed on both side surfaces of each of the gate electrodes GE. Gate capping patterns GP can be formed on the gate electrodes GE, respectively.

[0059] Referring to Figure 10 , Figure 11A and Figure 11B A lower interconnection line LML can be formed to be electrically connected to the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, a second lower insulating layer 114 can be formed on the first lower insulating layer 112. A lower contact LAC can be formed to pass through the first lower insulating layer 112 and the second lower insulating layer 114, and can be coupled to the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0060] A third lower insulating layer 116 can be formed on the second lower insulating layer 114. For example, a bottom surface of the third lower insulating layer 116 can be formed directly on a top surface of the second lower insulating layer 114. Lower interconnect lines LML and lower vias LV connecting the lower interconnect lines LML to lower contacts LAC can be formed in the third lower insulating layer 116.

[0061] Referring to Figure 12 , Figure 13A and Figure 13B , the lower substrate 102 can be formed. A wafer bonding process can be performed such that the bottom surface (e.g., in the third direction D3) of the third lower insulating layer 116 faces a top surface of the lower substrate 102. The lower substrate 102 can be a carrier substrate or an interconnect substrate. In exemplary embodiments in which the lower substrate 102 is an interconnect substrate, interconnect lines in the lower substrate 102 can be electrically connected to the lower interconnect lines LML.

[0062] Referring to Figure 14 , Figure 15A and Figure 15B , a portion of the substrate 100 can be removed to expose a first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0063] For example, the partial removal of the substrate 100 can include performing an etching process to expose the etch stop layer ESL and performing a CMP process to expose a top surface of the first portion SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0064] In exemplary embodiments, as a result of the partial removal of the substrate 100, the first active pattern AP1 can be divided into a plurality of patterns arranged in the second direction D2. For example, as shown in Figure 15A , one first active pattern AP1 including one channel region CH1 can be disposed between opposing sidewalls of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0065] Referring to Figure 16 , Figure 17A and Figure 17BThe second portions SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed on the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, a bottom surface (e.g., in the third direction D3) of the second portions SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be directly formed on a top surface (e.g., in the third direction D3) of the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. The second portions SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns grown from the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0066] For example, the first upper insulating layer 120 can be formed on the first active pattern AP1 and the second active pattern AP2 and the first source / drain pattern SD1 and the second source / drain pattern SD2. Then, a patterning process can be performed on the first upper insulating layer 120 to form an opening exposing a top surface of the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2. Next, an epitaxial growth process can be performed to form the second portions SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2. The epitaxial growth process can be performed such that a width W2 of the second portions SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2 is greater than a width W1 of the first portions SDB of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0067] Referring back to Figure 1 , Figure 2A and Figure 2B , the second upper insulating layer 122 can be formed on the first upper insulating layer 120. For example, a bottom surface (e.g., in the third direction D3) of the second upper insulating layer 122 can be directly disposed on a top surface of the first upper insulating layer 120. The upper contact UAC can be formed through the second upper insulating layer 122. The upper contact UAC can be coupled to the second portions SDE of the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively.

[0068] The third upper insulating layer 124 can be formed on the second upper insulating layer 122 to cover the upper contact UAC. The first upper interconnect line POR1 and the second upper interconnect line POR2 and the upper via UV can be formed in the third upper insulating layer 124. The upper via UV can be formed to electrically connect the first upper interconnect line POR1 and the second upper interconnect line POR2 to the at least one upper contact UAC.

[0069] In the semiconductor device according to the example embodiment of the present inventive concept, the power transmission network is stably formed on the second surface of the semiconductor substrate. As a result, the reliability and the integration density of the semiconductor device can be increased.

[0070] While the example embodiments of the present inventive concept have been particularly shown and described, one of ordinary skill in the art will understand that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: an active pattern including a channel region arranged between a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction, the channel region configured to connect the first and second source / drain patterns to each other; a gate electrode on a bottom surface of the active pattern and arranged between the first and second source / drain patterns; and an upper interconnect line arranged on a top surface of the active pattern opposite the bottom surface and connected to the first source / drain pattern, wherein the first source / drain pattern includes: a first portion adjacent to a side surface of the active pattern; and a second portion extending from the first portion and protruding above the top surface of the active pattern, wherein a width of the second portion in the first direction is greater than a width of the first portion in the first direction. The first and second source / drain patterns have a maximum width in the first direction at a level higher than a level of the top surface of the active pattern.

2. The apparatus of claim 1, wherein, 3. The device of claim 1, further comprising: an upper contact coupled to a top surface of the first source / drain pattern; and a lower contact coupled to a bottom surface of the second source / drain pattern. A width of a bottom surface of the upper contact adjacent to a top surface of the first source / drain pattern in the first direction is greater than a width of a top surface of the lower contact adjacent to a bottom surface of the second source / drain pattern in the first direction.

5. The device of claim 1, further comprising:

4. The apparatus of claim 3, wherein, a gate spacer on a sidewall of the gate electrode, wherein the first and second source / drain patterns overlap the gate spacer when viewed in plan. The upper interconnect line includes a power rail. The upper interconnect line extends in the first direction.

6. The apparatus of claim 1, wherein, The upper interconnect line overlaps the first and second source / drain patterns when viewed in plan.

7. The apparatus of claim 1, wherein, 9. The device of claim 1, further comprising:

8. The apparatus of claim 1, wherein, a semiconductor substrate disposed below the gate electrode; an interlayer insulating layer between the gate electrode and the semiconductor substrate; and a lower interconnect line arranged in the interlayer insulating layer and connected to at least one of the first and second source / drain patterns. The active pattern includes a plurality of stacked semiconductor patterns vertically spaced apart from each other.

11. A semiconductor device comprising: a first source / drain pattern and a second source / drain pattern spaced apart from each other in a first direction; 10. The apparatus of claim 1, wherein, an active pattern arranged between opposing sidewalls of the first and second source / drain patterns; a gate electrode on a bottom surface of the active pattern; an insulating layer on a top surface of the active pattern; and an upper interconnect line arranged on the insulating layer and electrically connected to the first source / drain pattern. ​ ​ ​ ​ wherein the first source / drain pattern includes a first portion adjacent to a side surface of the active pattern and a second portion extending from the first portion into the insulating layer, and a maximum width of the first portion in the first direction is smaller than a maximum width of the second portion in the first direction.

12. The apparatus of claim 11, wherein, the upper interconnect line extends in the first direction and at least partially overlaps each of the first source / drain pattern and the second source / drain pattern.

13. The device of claim 11, further comprising: gate spacers on side walls of the gate electrode, wherein the first source / drain pattern and the second source / drain pattern overlap the gate spacers when viewed in plan view.

14. The apparatus of claim 11, wherein, the upper interconnect line includes a power rail.

15. A semiconductor device, comprising: a substrate including a PMOS region and an NMOS region; a plurality of first active regions disposed on the PMOS region, the plurality of first active regions extending in a first direction; a plurality of second active regions disposed on the NMOS region, the plurality of second active regions extending in the first direction; a gate electrode crossing the plurality of first active regions and the plurality of second active regions and extending in a second direction crossing the first direction, a portion of the gate electrode being located between a bottom surface of the first active regions and a top surface of the substrate; first source / drain patterns spaced apart from each other in the first direction with the gate electrode interposed therebetween, the first source / drain patterns being connected to the plurality of first active regions; and an upper interconnect line disposed on a top surface of the first active regions opposite the bottom surface of the first active regions, wherein the upper interconnect line is connected to at least a portion of the first source / drain patterns, wherein the first source / drain pattern includes: a first portion adjacent to a side surface of the first active regions; and a second portion extending from the first portion and protruding above the top surface of the first active regions, a maximum width of the first portion in the first direction is smaller than a maximum width of the second portion in the first direction. the upper interconnect line extends in the first direction and 16. The apparatus of claim 15, wherein, each of the first source / drain patterns at least partially overlaps the upper interconnect line when viewed in plan view.

17. The device of claim 15, further comprising: an interlayer insulating layer interposed between the gate electrode and the substrate; and a lower interconnect line disposed in the interlayer insulating layer and connected to at least a portion of the first source / drain patterns.

18. The device of claim 15, further comprising: gate spacers on side surfaces of the gate electrode; and a gate cap pattern between the gate spacers, the gate cap pattern being disposed on a bottom surface of the gate electrode. the plurality of first active regions have a fin shape protruding in a third direction crossing the first direction and the second direction, and 19. The apparatus of claim 15, wherein, the gate electrode is disposed on a top surface of the fin shape. The length of the plurality of first active regions in the third direction is less than the length of the first source / drain pattern in the third direction.

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