Capacitor array and method for forming capacitor array and integrated circuit

Abstract

The present application relates to arrays of capacitors, methods for forming integrated circuits, and methods for forming arrays of capacitors. A method for forming an integrated circuit includes forming an array of structures that vertically penetrate a stack of a first material and a second material. The structure is vertically projected relative to an outermost portion of the first material. Energy is directed onto the vertically projected portion of the structure and onto the second material in a direction that is angled to the vertical and along a straight line between the immediately adjacent structures to form an opening into the second material, the opening being individually between the immediately adjacent structures along the straight line. Other embodiments that include structures that are independent of the method are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to arrays of capacitors, methods for forming integrated circuits, and methods for forming arrays of capacitors. Background Art

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Digit lines interconnect memory cells in a conductive manner along the columns of the array, and word lines interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and word lines.

[0003] Memory cells can be volatile, semi-volatile or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is generally designated as memory with a retention time of at least about 10 years. Volatile memory is dissipative and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different optional states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information of more than two levels or states.

[0004] Capacitors are another type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy such as an electric field can be stored in such a material in an electrostatic manner. Depending on the composition of the insulator material, the stored field will be volatile or non-volatile. For example, a capacitor insulator material that only contains SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states and can thus include programmable materials for capacitors and / or memory cells. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and maintained (at least for a certain period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from each other, which is ideally usable for writing (i.e., storing) and reading a memory state without reversing the polarization state until it is desired to reverse such a polarization state. Less desirable, in a memory having a ferroelectric capacitor, the act of reading a memory state can reverse the polarization. Therefore, after determining the polarization state, the memory cell is rewritten to place the memory cell into the pre-read state immediately after the determination of the polarization state. In any case, due to the bistable nature of the ferroelectric material that forms part of the capacitor, the memory cell incorporating the ferroelectric capacitor is ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile. In any case, a typical goal in the manufacture of capacitors is to maximize the surface area of ​​the capacitor electrodes to maximize the capacitance of the individual capacitors.

[0005] Of course capacitors and transistors may be used in integrated circuits other than memory circuits. Furthermore, arrays of structures other than capacitors and / or transistors (circuit operational or non-operational) may be part of the integration. Summary of the invention

[0006] Some embodiments of the present invention provide a method for forming an integrated circuit, the method comprising forming an array of structures vertically penetrating a stack comprising a first material and a second material, the structures being vertically projected relative to an outermost portion of the first material; and directing energy onto the vertically projected portions of the structures and onto the second material in a direction angled to the vertical and along a straight line between adjacent structures to form openings into the second material, the openings being individually between the adjacent structures along the straight line.

[0007] Some embodiments of the present invention provide methods for forming an array of capacitors, the method comprising forming an array of vertically elongated first capacitor electrodes through a stack including a first material and a second material, the first capacitor electrode projecting vertically relative to an outermost portion of the first material; directing energy onto the vertically projected portions of the first capacitor electrodes and onto the second material in a direction angled to vertical and along a straight line between immediately adjacent first capacitor electrodes to form openings through the second material, the openings being individually between the immediately adjacent first capacitor electrodes along the straight line, the directing of energy removing all of the second material from respective first sides of the vertically projected portions in a vertical cross section along the straight line, the directing of energy leaving the second material laterally above respective second sides of the vertically projected portions in the vertical cross section; after the directing of energy, removing at least some of the first material to expose sidewalls of the first capacitor electrode; forming a capacitor insulator above the exposed sidewalls of the first capacitor electrode; and forming at least one second capacitor electrode above the container insulator.

[0008] Some embodiments of the present invention provide an array of capacitors comprising: a two-dimensional (2D) array of vertically elongated first capacitor electrodes; a horizontal layer of insulating support material directly abutting and supporting the first capacitor electrodes, the horizontal layer of insulating support material being horizontally and vertically discontinuous in the two dimensions in the 2D array; a capacitor insulator directly abutting the horizontally and vertically discontinuous horizontal layer of insulating support material and directly abutting the vertically elongated first capacitor electrodes; and at least one second capacitor electrode directly abutting the capacitor insulator.

[0009] Some embodiments of the present invention provide an array of capacitors comprising: a two-dimensional (2D) array of vertically elongated first capacitor electrodes; an uppermost horizontal layer of insulating support material that directly abuts and supports the first capacitor electrodes; openings extending vertically through the uppermost horizontal layer of the insulating support material in the 2D array, the openings having a total number within the array equal to the total number of the vertically elongated first capacitor electrodes in the 2D array; a capacitor insulator that directly abuts the uppermost horizontal layer of the insulating support material and directly abuts the vertically elongated first capacitor electrodes; and at least one second capacitor electrode that directly abuts the capacitor insulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate construction in process according to an embodiment of the present invention and is a cross-sectional view through Figure 3Intercepted by line 1-1 in.

[0011] Figure 2 It passes through Figure 1 and 2 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0012] Figure 3 It passes through Figure 3 A diagrammatic cross-sectional view taken along line 3-3 in FIG.

[0013] Figure 4 , 5 and 7 to 14 are in the process according to some embodiments of the present invention Figure 1 Diagram of the construction in sequential cross-sectional views.

[0014] Figure 6 is a diagrammatic cross-sectional view of a portion of a substrate construction in process according to an embodiment of the present invention.

[0015] Fig.15 is a diagrammatic cross-sectional view of a portion of a substrate construction in process according to an embodiment of the present invention.

[0016] Fig.16 is through Fig.15 The processing steps after the steps shown are Fig.15 Constructed view. DETAILED DESCRIPTION

[0017] Embodiments of the present invention encompass methods for the manufacture of integrated circuits and arrays of capacitors independent of the method of manufacture. An integrated circuit manufactured according to a method embodiment may have any of the properties described herein in the structural embodiments. A first example method embodiment is a reference to Figures 1 to 14 Described in the fabrication of an integrated circuit including an array of capacitors.

[0018] refer to Figures 1 to 3 , which shows a portion of a construction 10 including an array or array region 12 in which capacitors are to be fabricated. Construction 10 includes a base substrate 13 having any one or more of a conductive / conductor / conductive, semiconductive / semiconducting / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) material. Various materials have been vertically formed over base substrate 13. The materials may be Figures 1 to 313. For example, other partially fabricated or fully fabricated components of the integrated circuit may be provided somewhere above, around, or within the base substrate 13. Control circuits and / or other peripheral circuits for operating components within an array (e.g., a memory array) may also be fabricated, and may or may not be completely or partially within the array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently of one another, sequentially, or otherwise. In this document, a "sub-array" may also be considered an array.

[0019] The access device 15 is Figure 3 1 and may be formed as part of a base substrate 13. By way of example only, it may include a field effect transistor for controlling access to individual capacitors, such as in a DRAM circuit where the access device 15 and the capacitor comprise components of a single memory cell (e.g., a one transistor, one capacitor [1T / 1C] memory cell). However, other memory circuits and non-memory circuits are contemplated and whether the circuits are existing or yet to be developed. The example base substrate 13 is shown as including an insulating material 16 (e.g., doped and / or undoped silicon dioxide) having conductive vias 18 extending therethrough for electrically coupling the individual access devices 15 to the individual capacitors.

[0020] Stack 22 has been formed vertically outward from base substrate 13 (e.g., above) and includes a first material 24 and a second material 26, which in one embodiment and as shown is directly against first material 24. Example first material 24 includes insulating material 20 (e.g., silicon nitride and / or silicon oxynitride), which may have served and / or will serve as an etch stop. Example first material 24 is also shown to include material 28 (e.g., doped or undoped silicon dioxide and which may be completely sacrificial), intermediate material 30 (e.g., silicon nitride) as a horizontal layer within material 28, and material 32 (e.g., silicon nitride) vertically outward from an upper portion of material 28. Example second material 26 includes silicon dioxide, spin-on carbon, silicon oxynitride, and hard mask materials now or in future development. In the embodiment described in the first example, second material 26 may be sacrificial (e.g., all of it is eventually removed at least within the array, so it does not comprise part of the completed integrated circuit construction).

[0021] An array of vertically elongated first capacitor electrodes 34 has been formed through stack 22. It may include a solid pillar configuration as shown or may include any other suitable configuration, for example, in the form of an upwardly open container shape (not shown), which may or may not be filled with a sacrificial material during processing. An example first capacitor electrode material is titanium nitride. First capacitor electrodes 34 are vertically projected relative to the outermost portion of first material 24 (e.g., from at least the uppermost portion of example material 32), for example, so that a portion 29 so projected has an example vertical projection distance of portion 29 of 10 to 15 nanometers.

[0022] The array 12 of first capacitor electrodes 34 can be viewed as having corresponding straight lines 38 (one so designated) between immediately adjacent first capacitor electrodes 34, with the construction 10 having corresponding vertical cross-sections along the lines 38 (e.g., Figure 3 38). It should be noted that the corresponding straight line 38 is not necessarily between the first capacitor electrodes 34 that are in close proximity within the array 12. In any case, the first capacitor electrodes 34 can be considered to have a corresponding first side 40 and a corresponding second side 42 in the vertical cross section.

[0023] refer to Figure 4 and 5 , energy is directed (e.g., as indicated by arrow 44) onto vertically projected portions 29 of first capacitor electrodes 34 and onto second material 26 at an angle to vertical (e.g., angle 36) and in a direction along line 38 between immediately adjacent first capacitor electrodes 34 to form openings 50 into second material 26, said openings being individually between immediately adjacent first capacitor electrodes 34 along line 38. In one embodiment and as shown, such directing of energy forms openings 50 through second material 26, and in one such embodiment where second material 26 is directly against first material 24, such directing of energy forms openings 50 into first material 24. Alternatively, in one embodiment, at least at this point in the process, openings 50 may be only partially formed into second material 26 (not shown). Regardless, in one embodiment and as shown, the total number of openings 50 within array 12 is equal to the total number of first capacitor electrodes 34 in array 12.

[0024] Figures 1 to 5 An example embodiment is shown in which the second material 26 does not cover the vertically outermost surface 35 of the first capacitor electrode 34 at the beginning of said directing of energy onto the second material 26 in a direction angled from vertical. Figure 6An alternative example embodiment configuration 10a is shown in which the second material 26a of the stack 22a covers the vertically outermost surface 35 of the first capacitor electrode 34. Like reference numerals from the first described embodiment have been used where appropriate, with the suffix "a" indicating certain construction differences. Thus, as indicated by Figure 4 and 5 Shown relative to Figure 6 The configuration 10a directs energy initially onto the second material 26a to expose the vertically outermost surface 35 of the first capacitor electrode 34. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0025] The first capacitor electrode 34 can be viewed as an array of structures 34 formed vertically through the stack 22 including the first material 24 and the second material 26. However, embodiments of the method for forming an integrated circuit can form any other existing or future developed structures, and regardless of whether those structures are sacrificial or remain in the completed circuit configuration and regardless of which material such structures are made of and regardless of whether such structures are circuit operational in the completed configuration of the integrated circuit. In any case, in one embodiment and as shown, the first capacitor electrodes / structures 34 are arranged in a two-dimensional (2D) hexagonal lattice. In another embodiment, the structures are arranged in a two-dimensional (2D) lattice with parallelogram unit cells, with the angled directions being vertical along the diagonals of the parallelogram unit cells. Other 2D arrays can be used, and they can have a Bravais lattice (i.e., no gaps or overlaps within the lattice) or have a non-Bravais lattice.

[0026] In one embodiment and as Figure 4 and 5 As shown in , the directing of energy removes all of second material 26 from respective first sides 40 of vertically projected portions 29 in vertical cross-section along line 38 and leaves second material 26 laterally above respective second sides 42 of vertically projected portions 29 in vertical cross-section.

[0027] In one embodiment, such directing of energy removes the second material 26 by chemical etching of the second material 26 to at least predominantly form the opening 50 (i.e., up to and including 100%) and in one such embodiment is performed selectively with respect to the vertically projected portion 29 of the first capacitor electrode / structure 34 (e.g., using a directed chemical etching tool using an etch chemistry to selectively anisotropically etch the second material 26 with respect to the projected portions 29 of different compositions of the first capacitor electrode / structure 34, e.g., using a Raptor). TM (Raptor TM) and other etching tools available from Applied Materials of Santa Clara, California). In another example, such directing of energy removes the second material 26 to at least primarily form the opening 50 (i.e., up to and including 100%) by non-chemical, physical removal of the second material 26, with one such example using an ion beam etcher that physically directs a bombarding ion beam onto the vertically projected portion 29 of the first capacitor electrode / structure 34 and at such an angle to the vertical onto the second material 26. Regardless, a skilled artisan may select any suitable angle to the vertical and the angle may affect the size of the opening 50 (e.g., the maximum length along the line 38).

[0028] In one embodiment, material 32 of first material 24 comprises an insulating support material that supports the vertically elongated first capacitor electrode / structure 34 in the completed construction. In another example embodiment described below, the second material may comprise an insulating support material in the form of material 32 that provides such a function, and it may be without the use of any additional second material 26 above it. Alternatively, embodiments of the present invention may not use material 32 as an insulating support material that supports the vertically elongated first capacitor electrode / structure in the completed construction.

[0029] In one embodiment and following the directing of energy as described above, at least some of first material 24 is removed to expose sidewalls of first capacitor electrode / structure 34 (e.g., a majority of which is below material 32). In one such embodiment, the directing of energy has formed second material 26 having openings 50 through which is mask 56 (e.g., second material 26 in combination with the material of first capacitor electrode / structure 34, as initially described in Figure 5 In one such embodiment, and with reference to Figure 7 and 8 , mask 56 has been used to simultaneously etch insulating support material 32 through openings 50 in mask 56 so that openings 50 extend into and through insulating support material 32 .

[0030] In one such embodiment, and with reference to Fig. 9 and 10, removing at least some of the first material 24 to expose the sidewalls of the first capacitor electrode / structure 34 includes selectively etching the first material 24 below the insulating support material 32 (e.g., material 28) relative to the insulating support material 32 and the first capacitor electrode / structure 34. This can be done isotropically or anisotropically. In addition, and as shown, this can be ideally done anisotropically to the intermediate material 30 initially, and then the chemistry changes to anisotropically etch through the intermediate material 30. In the case where the second material 26 (not shown) has the same composition as the composition of the material 28, such etching can remove all of the remaining second material 26 as shown. Regardless, and in one embodiment, all of the remaining second material 26 is removed when sacrificial.

[0031] In one embodiment, the second material 26 initially includes a horizontal layer 58 that is horizontally and vertically continuous within the array 12 ( Figure 2 In one such embodiment, such horizontal layer 58 is formed to be horizontally and vertically discontinuous by or after the directing of the energy, wherein Figures 1 to 5 , 7 and 8 illustrate the behavior of directing such energy to form such a horizontal layer 58 as in Figures 7 to 10 Horizontally and vertically discontinuous.

[0032] Fig.11 and 12 An example post-processing is shown where an isotropic etch has been performed to remove all remaining material 28 (not shown) to expose more of the sidewalls of the first capacitor electrode / structure 34. The intermediate material 30, when present, may also serve as an insulating support material to support the vertically elongated first capacitor electrode / structure 34 in the finished construction.

[0033] refer to Fig.13 and 14 , a capacitor insulator 60 has been formed over the exposed sidewalls of the first capacitor electrode / structure 34 (and over the insulating support materials 32 and 30 when present), and at least one second capacitor electrode 62 has been formed over the capacitor insulator 60, thereby forming an individual capacitor 65. In one embodiment and as shown, a single second capacitor electrode 62 may be formed that is common to all capacitors 65 within the array 12.

[0034] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] Relative to Fig.15 and 16An example alternative embodiment is described with respect to the manufacture of an alternative embodiment construction 10b. The same reference numerals from the embodiments described above have been used where appropriate, with the suffix "b" indicating certain construction differences. The alternative example method embodiment does not use the example second material 26 of the first described embodiment vertically outward of the material 32. In fact, in Fig.15 and 16 , the first material 24 can be considered as all of the material below material 32, wherein material 32 is considered as a second material and in one embodiment it is directly against the sidewalls of the first capacitor electrode / structure 34 and in one embodiment material 32 is insulating and supports the first capacitor electrode 34 in the completed construction of the array of capacitors. Fig.15 In the processing sequence corresponding to Figure 3 of the processing sequence (before directing energy at an angle to the vertical) and Fig.16 In the processing sequence corresponding to Figure 5 of the processing sequence (after directing the energy at an angle to vertical). Fig.16 The material 32b forming the horizontal layer 58b of the mask 56b is shown. Figures 7 to 14 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0036] Embodiments of the present invention encompass arrays of capacitors independent of the method of manufacture. However, such an array may have any of the properties described in the method embodiments as herein. Similarly, the method embodiments described above may incorporate and form any of the properties described with respect to the device embodiments.

[0037] In one embodiment, the array of capacitors (e.g., 65) includes a two-dimensional (2D) array (e.g., 12) of vertically extended first capacitor electrodes (e.g., 34). A horizontal layer (e.g., 58, 58b) of insulating support material (e.g., 32) directly abuts against and supports the first capacitor electrode. The horizontal layer of insulating support material is horizontally and vertically discontinuous in two dimensions in the 2D array (e.g., in contrast to the horizontally and vertically continuous capacitor insulator 60). The capacitor insulator (e.g., 60) directly abuts against the horizontally and vertically discontinuous horizontal layer of insulating support material and directly abuts against the vertically extended first capacitor electrode. At least one second capacitor electrode (e.g., 62) directly abuts against the capacitor insulator. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0038] In one embodiment, an array of capacitors (e.g., 65) includes a 2D array (e.g., 12) of vertically extended first capacitor electrodes (e.g., 34). The uppermost horizontal layer (e.g., 58, 58b) of insulating support material (e.g., 32) directly abuts against and supports the first capacitor electrodes. An opening (e.g., 50) extends vertically through the uppermost horizontal layer of insulating support material in the 2D array. The openings have a total number within the array equal to the total number of vertically extended first capacitor electrodes in the 2D array. A capacitor insulator (e.g., 60) directly abuts against the uppermost horizontal layer of insulating support material and directly abuts against the vertically extended first capacitor electrode. At least one second capacitor electrode (e.g., 62) directly abuts against the capacitor insulator. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0039] The above processing or construction can be viewed as an array relative to components that are formed as a single stack or a single stack of such components or within a single stack or a single stack, which is above or as part of the underlying base substrate (but a single stack / stack may have multiple layers). Control and / or other peripheral circuits for operating or accessing such components within the array may also be formed anywhere as part of the completed construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown in the figure or described above. In addition, the arrays of components may be the same or different relative to each other in different stacks / stacks. Intervening structures may be provided between stacks / stacks that are adjacent vertically (e.g., additional circuits and / or dielectric layers). And, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more than two stacks / stacks may be manufactured substantially at the same time.

[0040] The assemblies and structures discussed above can be used in integrated circuits / circuits and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0041] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "on top", "bottom", "above", "below", "below", "under", "upward", and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees) and relative to which the substrate can be processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to a direction along the surface of the main substrate (i.e., not forming a degree with the surface) and relative to which the substrate can be processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that deviates from just horizontal by at least 45°. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending" and similar terms relative to a field effect transistor are references to the orientation of the channel length of the transistor, along which the current flows between the source / drain regions in operation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and similar terms are referenced to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any components, features, and / or regions that extend vertically extend vertically or within 10° of vertical.

[0042] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to each other. Also, the use of "above" without a preceding "directly" requires only that some portion of the stated region / material / component that is above another stated region / material / component is vertically outward of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated region / material / component that is below / beneath another stated region / material / component is vertically inward of the other stated region / material / component (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components).

[0043] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. Where one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0044] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions are not directly against each other, then in the case of such materials or regions being non-uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when there is at least one physical touch contact of the stated materials, regions or structures relative to each other, a material, region or structure "directly abuts" another material, region or structure. In contrast, “over,” “on,” “adjacent,” “along,” and “against” without being preceded by “directly” encompass “directly against” as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical touching contact with each other.

[0045] As used herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0046] The composition of any of the conductive / conductor / conductive materials herein can be a metallic material and / or a conductive doped semiconductive / semiconductive / semiconductive material. "Metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0047] As used herein, "selectivity" with respect to etching, etching, removing, removal, deposition, forming, and / or formation is such action that one stated material acts relative to another stated material in a ratio of at least 2: 1 by volume. Additionally, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials for at least the first 75 angstroms in a ratio of at least 2: 1 by volume.

[0048] Unless otherwise indicated, the use of "or" herein includes either or both.

[0049] in conclusion

[0050] In some embodiments, a method for forming an integrated circuit includes forming an array of structures vertically through a stack including a first material and a second material. The structures are vertically projected relative to an outermost portion of the first material. Energy is directed onto the vertically projected portion of the structures and onto the second material in a direction angled to the vertical and along a straight line between immediately adjacent structures to form openings into the second material, the openings being individually between immediately adjacent structures along the straight line.

[0051] In some embodiments, a method for forming an array of capacitors includes forming an array of vertically elongated first capacitor electrodes through a stack including a first material and a second material. The first capacitor electrode is vertically projected relative to the outermost portion of the first material. Energy is directed onto the vertically projected portion of the first capacitor electrode and onto the second material in a direction that is angled to the vertical and between the immediately adjacent first capacitor electrodes along a straight line to form an opening through the second material, the opening being individually between the immediately adjacent first capacitor electrodes along the straight line. The directing of energy removes all of the second material from the respective first sides of the vertically projected portion in a vertical cross section along the straight line. The directing of energy leaves the second material laterally above the respective second sides of the vertically projected portion in the vertical cross section. After the directing of energy, at least some of the first material is removed to expose the sidewalls of the first capacitor electrode. A capacitor insulator is formed above the exposed sidewalls of the first capacitor electrode. At least one second capacitor electrode is formed above the container insulator.

[0052] In some embodiments, the array of capacitors includes a two-dimensional (2D) array of vertically elongated first capacitor electrodes. A horizontal layer of insulating support material directly abuts against and supports the first capacitor electrode. The horizontal layer of insulating support material is horizontally and vertically discontinuous in two dimensions in the 2D array. The capacitor insulator directly abuts against the horizontally and vertically discontinuous horizontal layer of insulating support material and directly abuts against the vertically elongated first capacitor electrode. At least one second capacitor electrode directly abuts against the capacitor insulator.

[0053] In some embodiments, the array of capacitors comprises a two-dimensional (2D) array of vertically extended first capacitor electrodes. The uppermost horizontal layer of insulating support material directly abuts against and supports the first capacitor electrodes. The openings extend vertically through the uppermost horizontal layer of insulating support material in the 2D array. The openings have a total number within the array equal to the total number of vertically extended first capacitor electrodes in the 2D array. The capacitor insulator directly abuts against the uppermost horizontal layer of insulating support material and directly abuts against the vertically extended first capacitor electrodes. At least one second capacitor electrode directly abuts against the capacitor insulator.

[0054] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming an integrated circuit, comprising: forming an array vertically through a structure comprising a stack of a first material and a second material, the structure projecting vertically relative to an outermost portion of the first material; as well as Energy is directed onto a vertically projected portion of the structure and onto the second material in a direction angled to vertical and along a straight line between adjacent structures to form openings into the second material, wherein the openings in the second material are individually between the adjacent structures along the straight line. 2 . The method of claim 1 , wherein the directing of energy forms an opening in the second material through the second material.

3. The method of claim 2, wherein the second material is directly against the first material, the directing of energy forming an opening to the first material.

4. The method of claim 1 wherein the second material does not cover a vertically outermost surface of the structure at a commencement of the directing of energy onto the second material in the direction at an angle to vertical.

5. The method according to claim 1, wherein: the second material covers the vertically outermost surface of the structure; and The directing of energy is initially onto the second material to expose a vertically outermost surface of the structure.

6. The method of claim 1, wherein the directing of energy removes the second material by chemical etching of the second material to at least primarily form openings in the second material.

7. The method of claim 6, wherein the chemical etching is performed selectively with respect to the vertically projected protrusion.

8. The method of claim 1, wherein the directing of energy removes the second material by non-chemical, physical removal of the second material to at least primarily form openings in the second material.

9. The method of claim 8, wherein the directing of energy comprises directing an ion beam onto the vertically projected portion of the structure and onto the second material at the angle.

10. The method of claim 1, wherein the openings in the second material have a total number equal to the total number of structures.

11. The method according to claim 1, wherein: The second material initially comprises a horizontal layer that is continuous horizontally and vertically within the array; and The horizontal layers are formed by or after the directing of energy to be horizontally and vertically discontinuous.

12. The method of claim 11, wherein the openings in the second material have a total number equal to the total number of structures.

13. The method of claim 1, wherein the structures are arranged in a two-dimensional (2D) hexagonal lattice.

14. The method of claim 1, wherein the structures are arranged in a two-dimensional (2D) lattice having parallelogram unit cells, and the directions are along diagonals of the parallelogram unit cells.

15. A method for forming an array of capacitors, comprising: forming an array of vertically elongated first capacitor electrodes through a stack comprising a first material and a second material, the first capacitor electrodes projecting vertically relative to an outermost portion of the first material; directing energy onto a vertically projected portion of the first capacitor electrode and onto the second material in a direction angled to vertical and along a straight line between immediately adjacent first capacitor electrodes to form openings through the second material, wherein the openings in the second material are individually between the immediately adjacent first capacitor electrodes along the straight line, the directing of energy removing all of the second material from a respective first side of the vertically projected portion in a vertical cross section along the straight line, the directing of energy leaving the second material laterally above a respective second side of the vertically projected portion in the vertical cross section; after said directing of energy, removing at least some of said first material to expose a sidewall of said first capacitor electrode; forming a capacitor insulator over the exposed sidewall of the first capacitor electrode; as well as At least one second capacitor electrode is formed over the container insulator.

16. The method of claim 15, wherein the second material is sacrificial and is removed prior to forming the capacitor insulator.

17. The method of claim 16, wherein the first material comprises an insulating support material that supports the vertically elongated first capacitor electrodes in a completed configuration of the array of capacitors.

18. The method of claim 17, wherein the second material having openings therethrough forms a mask, and the method further comprises: The insulating support material is simultaneously etched through the openings in the mask using the mask to extend the openings in the mask into and through the insulating support material.

19. The method of claim 18, wherein the removing at least some of the first material to expose sidewalls of the first capacitor electrode comprises etching the first material through an opening in the insulating support material selectively relative to the insulating support material and the vertically elongated first capacitor electrode.

20. The method of claim 15, wherein the first material comprises an insulating support material that supports the vertically elongated first capacitor electrodes in a completed configuration of the array of capacitors, the second material having openings therethrough forms a mask, and the method further comprises: The insulating support material is simultaneously etched through the openings in the mask using the mask to extend the openings into and through the insulating support material.

21. The method according to claim 15, wherein: the second material comprising an insulating support material directly against a sidewall of the vertically elongated first capacitor electrode and supporting the vertically elongated first capacitor electrode in a completed configuration of the array of capacitors; as well as The opening in the second material is ultimately formed through the insulating support material to the first material.

22. The method of claim 21 wherein the removing at least some of the first material to expose sidewalls of the first capacitor electrode comprises etching the first material through an opening to the first material selectively relative to the insulating support material and the vertically elongated first capacitor electrode.

23. An array of capacitors, comprising: a two-dimensional 2D array of vertically elongated first capacitor electrodes; a horizontal layer of insulating support material directly against and supporting the first capacitor electrode, the horizontal layer of insulating support material being discontinuous horizontally and vertically in the two dimensions in the 2D array; a capacitor insulator directly against the horizontally and vertically discontinuous horizontal layer of the insulating support material and directly against the vertically elongated first capacitor electrode; as well as At least one second capacitor electrode is directly against the capacitor insulator.

24. An array of capacitors, comprising: a two-dimensional 2D array of vertically elongated first capacitor electrodes; an uppermost horizontal layer of insulating support material directly against and supporting said first capacitor electrode; openings extending vertically through the uppermost horizontal layer of the insulating support material in the 2D array, the openings having a total number within the array equal to a total number of the vertically elongated first capacitor electrodes in the 2D array; a capacitor insulator directly against the uppermost horizontal layer of the insulating support material and directly against the vertically elongated first capacitor electrode; as well as At least one second capacitor electrode is directly against the capacitor insulator.

25. The array of claim 24, wherein the uppermost horizontal layer of insulating support material is discontinuous horizontally and vertically in the two dimensions in the 2D array.

Images