Display device

Abstract

A display device is provided, the display device comprising: a substrate including a display area, a non-display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; a pixel located in the display area; a packaging film located on the pixel; a sensing electrode located on the packaging film; a pad located in the second additional area; a sensing wiring connecting the sensing electrode and the pad; a first sensing insulating film located on the packaging film; and a second sensing insulating film located on the first sensing insulating film. The substrate comprises a curved first side in the first additional area and the first additional area decreases in width from the first boundary to the second boundary, and a boundary of the first sensing insulating film is closer to the first side than a boundary of the second sensing insulating film.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0061147 filed on May 24, 2019, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device. Background Art

[0003] As the field of information technology develops, the importance of display devices as a connection medium between users and information increases. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices has been increasing.

[0004] In particular, user demands for bendable displays have been increasing. However, large stress is applied to a bending region of a bendable display compared to other regions of the display, and thus measures for preventing or substantially preventing cracks from forming due to the stress are desired. Summary of the invention

[0005] Aspects of example embodiments are directed to a display device capable of reducing stress applied to a bending region.

[0006] A display device according to a disclosed embodiment includes: a substrate including a display area, a non-display area surrounding the periphery of the display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; a pixel located in the display area; a packaging film located on the pixel; a sensing electrode located on the packaging film; a pad located in the second additional area; a sensing wiring connecting the sensing electrode and the pad; a first sensing insulating film located on the packaging film; and a second sensing insulating film located on the first sensing insulating film, the sensing electrode, and the sensing wiring. The substrate includes a curved first side in the first additional area and the first additional area decreases in width from the first boundary to the second boundary, and a boundary of the first sensing insulating film is closer to the first side than a boundary of the second sensing insulating film.

[0007] A boundary of the first sensing insulating film may not be covered by the second sensing insulating film.

[0008] The substrate may include a first bent region extending from the first side to overlap the non-display region.

[0009] A boundary of the first sensing insulating film and a boundary of the second sensing insulating film may be located in the first bending region.

[0010] The second additional region may include a second bending region, and the first bending region and the second bending region do not overlap.

[0011] The encapsulation film may include an organic film, the display device may further include a dam located at a boundary of the organic film, and a boundary of the second sensing insulating film may be closer to the first side than the dam.

[0012] The encapsulation film may include an organic film, the display device may further include a dam located at a boundary of the organic film, and a boundary of the second sensing insulating film may be farther from the first side than the dam.

[0013] A boundary of the second sensing insulating film may be closer to the first side than the sensing wiring.

[0014] The first sensing insulating film may be located between the packaging film and the sensing wiring.

[0015] The sensing electrode may be located on the first sensing insulating film, the display device may further include a bridge electrode located below the first sensing insulating film, and the sensing electrode may be connected to the bridge electrode through a contact hole of the first sensing insulating film.

[0016] The sensing electrode may be located under the first sensing insulating film, the display device may further include a bridging electrode located on the first sensing insulating film, and the bridging electrode may be connected to the sensing electrode through a contact hole of the first sensing insulating film.

[0017] The first sensing insulating film may be located between the sensing wiring and the second sensing insulating film.

[0018] The sensing electrode may be located on the first sensing insulating film, the display device may further include a bridge electrode located below the first sensing insulating film, and the sensing electrode may be connected to the bridge electrode through a contact hole of the first sensing insulating film.

[0019] The sensing electrode may be located under the first sensing insulating film, the display device may further include a bridging electrode located on the first sensing insulating film, and the bridging electrode may be connected to the sensing electrode through a contact hole of the first sensing insulating film.

[0020] A display device according to a disclosed embodiment includes: a substrate including a display area, a non-display area surrounding the periphery of the display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; a pixel located in the display area; a packaging film located on the pixel; a sensing electrode located on the packaging film; a pad located in the second additional area; a sensing wiring connecting the sensing electrode and the pad; a first sensing insulating film located on the packaging film; and a second sensing insulating film located on the first sensing insulating film, the sensing electrode, and the sensing wiring. The substrate includes a curved first side in the first additional area and the first additional area decreases in width from the first boundary to the second boundary, and a boundary of the second sensing insulating film is spaced apart from the first side by 200 μm or more.

[0021] The first side of the first additional area and the non-display area may commonly include a first bending area, the second additional area may include a second bending area, and the first bending area and the second bending area do not overlap.

[0022] The encapsulation film may include an organic film, the display device may further include a dam located at a boundary of the organic film, and a boundary of the second sensing insulating film may be closer to the first side than the dam.

[0023] The encapsulation film may include an organic film, the display device may further include a dam located at a boundary of the organic film, and a boundary of the second sensing insulating film may be farther from the first side than the dam.

[0024] A boundary of the second sensing insulating film may be closer to the first side than the sensing wiring.

[0025] A display device according to a disclosed embodiment includes: a substrate including a display area, a non-display area surrounding the periphery of the display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; a pixel located in the display area; a packaging film located on the pixel; a sensing electrode located on the packaging film; a pad located in the second additional area; a sensing wiring connecting the sensing electrode and the pad; and a sensing insulating film located on the sensing electrode and the sensing wiring. The substrate includes a curved first side in the first additional area and the first additional area decreases in width from the first boundary to the second boundary, the substrate includes a first curved area extending from the first side to overlap with the non-display area, and in the first curved area, a boundary of the sensing insulating film is closer to a first point of the first side intersecting (e.g., intersecting) with the first boundary than a second point of the first side intersecting (e.g., intersecting) with the second boundary.

[0026] Aspects according to example embodiments of the disclosed display device are directed to reducing stress applied to a bending region. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the invention will become more apparent by further describing in detail exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0028] Figure 1 is a diagram for describing a substrate according to a disclosed embodiment;

[0029] Figure 2 is a diagram for describing a display device according to a disclosed embodiment;

[0030] Figure 3 yes Figure 2 an enlarged view of a portion of a first additional region;

[0031] Figure 4is a diagram for describing the effect of increasing the separation distance between the second sensing insulating film and the first side;

[0032] Figure 5 It is along Figure 2 An embodiment of a cross section taken along line II';

[0033] Figures 6 to 8 Shown along Figure 2 A section taken along line II-II';

[0034] Fig. 9 It is along Figure 2 An embodiment of a cross section taken along line II';

[0035] Figures 10 to 12 It is along Figure 2 An embodiment of a cross section taken along line II-II';

[0036] Figures 13 to 16 It is along Figure 2 An embodiment of a cross section taken along line II';

[0037] Fig.17 and Fig.18 is a diagram for describing a sensing electrode and a bridging electrode according to a disclosed embodiment;

[0038] Fig.19 is a diagram for describing a sensing electrode and a bridging electrode according to a disclosed embodiment;

[0039] Fig. 20 is based on a different Figure 3 an enlarged view of a portion of a first additional region of an embodiment of;

[0040] Fig.21 is based on Fig. 20 Along the lines of Figure 2 An embodiment of a cross section taken along line II';

[0041] Figure 22 to Figure 24 is based on Fig. 20 Along the lines of Figure 2 An embodiment of a cross section taken along line II-II';

[0042] Fig.25 and Fig.26 is based on Fig. 20 Embodiments of sensing electrodes and sensing wirings of embodiments of; and

[0043] Figure 27 to Figure 29 is a diagram for describing a pixel according to a disclosed embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, various embodiments of the disclosure will be described in more detail with reference to the accompanying drawings so that those skilled in the art can easily perform the disclosure. The disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0045] In order to clearly describe the disclosure, parts not related to the description are omitted, and the same or similar elements are represented by the same reference numerals throughout the specification. Therefore, the reference numerals described above may be used in other drawings.

[0046] In addition, for the convenience of description, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore, the disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly indicate various layers and regions.

[0047] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, first component, first region, first layer or first part discussed below may be referred to as the second element, second component, second region, second layer or second part without departing from the spirit and scope of the inventive concept.

[0048] For ease of description, spatial relative terms such as "under ...", "below ...", "below ...", "below ...", "above ...", "on ...", etc. may be used here to describe the relationship between an element or feature and another (other) element or feature as shown in the figure. It will be understood that the spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below" or "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "below ..." and "below ..." can include both above and below orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used here should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, the layer can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0049] The terms used here are only for the purpose of describing specific embodiments, and are not intended to be limitations of the inventive concept. Unless the context clearly indicates otherwise, the singular forms "one (kind / person)" and "the (the)" as used here are also intended to include plural forms. It will also be understood that when the term "include" and / or its variations are used in this specification, it is explained that there are stated features, wholes, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, wholes, steps, operations, elements, components and / or their groups. As used here, the term "and / or" includes any combination and all combinations of one or more of the related listed items. When a statement such as "at least one (kind / person) in ... " is located after a column of elements, the entire column of elements is modified without modifying the individual elements in the column. In addition, when describing the embodiment of the inventive concept, the use of "may" represents "one or more embodiments of the inventive concept".

[0050] It will be understood that when an element or layer is referred to as being "on," "connected to," "bound to," or "adjacent to" another element or layer, the element or layer may be directly on, directly connected to, directly bound to, or directly adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly bound to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0051] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent variations in measurements or calculations that those of ordinary skill in the art would recognize.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which this disclosure is a part. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0053] Figure 1 is a diagram for describing a substrate according to a disclosed embodiment, Figure 2 is a diagram for describing a display device according to a disclosed embodiment.

[0054] In the following embodiments, the plane may be defined in the first direction DR1 and the second direction DR2, and the height may be defined in the third direction DR3 (refer to Figure 5 The first direction DR1, the second direction DR2, and the third direction DR3 may be directions orthogonal to each other.

[0055] The substrate SUB may include a display area DA, a non-display area NDA, a first additional area ADA1, and a second additional area ADA2.

[0056] The display area DA may have a quadrilateral shape (e.g., a rectangular shape). Each corner of the display area DA may be angled or curved. In addition, in the case of a circular display, the display area DA may have a circular shape (e.g., a perfect circle or an ellipse). In addition, the display area DA may be another shape such as a polygon other than a quadrilateral, an ellipse, etc. As described above, the shape of the display area DA may be set differently depending on the product.

[0057] The pixels may be located in the display area DA. Depending on the type of the display device DP, each pixel may include a light emitting diode or may include a liquid crystal layer.

[0058] The non-display area NDA may surround the circumference of the display area DA. For example, the non-display area NDA may have a rectangular shape. Each corner of the non-display area NDA may be angled or curved. Figure 2 The case where each corner of the non-display area NDA has a curved shape is shown. The non-display area NDA may have a circular shape. Since minimizing or reducing the non-display area NDA is conducive to creating a narrow frame structure, the shape of the non-display area NDA may be similar to that of the display area DA.

[0059] The first additional area ADA1 may be located between the non-display area NDA and the second additional area ADA2. The first additional area ADA1 may be connected to the non-display area NDA at a first boundary ED1. The first additional area ADA1 may be connected to the second additional area ADA2 at a second boundary ED2. Each of the first boundary ED1 and the second boundary ED2 may extend in a first direction DR1.

[0060] The width of the first additional area ADA1 may be narrowed or reduced from the first boundary ED1 to the second boundary ED2. That is, the width of the first additional area ADA1 in the first direction DR1 may be narrowed or reduced toward the second direction DR2. Therefore, the first additional area ADA1 may include a curved first side RC1 and a curved second side RC2. The sides RC1 and RC2 may bulge toward the inside of the substrate SUB (e.g., the center of the substrate SUB).

[0061] Figure 2It is shown that the first additional area ADA1 includes two sides (e.g., two opposite sides) RC1 and RC2 in a first direction DR1 and a direction opposite to the first direction DR1. In other words, the first side RC1 and the second side RC2 are relatively aligned and define the left and right sides of the first additional area ADA1. In an embodiment, the boundary arranged along the first direction DR1 may coincide with the boundary of the non-display area NDA, so the first additional area ADA1 may include only the first side RC1. In an embodiment, the boundary arranged in a direction opposite to the first direction DR1 may coincide with the boundary of the non-display area NDA, so the first additional area ADA1 may include only the second side RC2.

[0062] The second additional area ADA2 may have a rectangular shape. Each corner of the second additional area ADA2 arranged along the second direction DR2 may be angled or curved. Figure 2 Each corner of the second additional area ADA2 arranged in the second direction DR2 is an example embodiment in which the corners are angled.

[0063] The encapsulation film TFE may be located on the pixel. For example, the encapsulation film TFE may cover the pixel in the display area DA, and the boundary of the encapsulation film TFE may be located in the non-display area NDA. The encapsulation film TFE may cover the light emitting elements and circuit elements of the pixel in the display area DA to prevent or reduce exposure to external moisture and / or prevent or substantially prevent cracking caused by impact.

[0064] The sensing electrodes SC1 and SC2 may be located on the packaging film TFE. The sensing electrodes SC1 and SC2 may sense a user's touch, hovering, gesture, proximity, etc. The sensing electrodes SC1 and SC2 may be constructed in different shapes according to various methods such as a resistive type (or method), a capacitive type (or method), an electromagnetic type (or method), and / or an optical type (or method). For example, when the sensing electrodes SC1 and SC2 are constructed as a capacitive type, the sensing electrodes SC1 and SC2 may be constructed as a self-capacitive type, a mutual-capacitive type, etc.

[0065] When the sensing electrodes SC1 and SC2 are configured as a self-capacitive type, each of the sensing electrodes SC1 and SC2 may be independently driven, and a sensing signal corresponding to a capacitance formed by each of the sensing electrodes SC1 and SC2 and a user's body may be provided to corresponding sensing wirings IST1 and IST2 .

[0066] When the sensing electrodes SC1 and SC2 are configured as a mutual capacitance type, the drive signal can be sent through the sensing wiring corresponding to the first sensing electrode SC1, and the sensing signal can be received through the sensing wiring corresponding to the second sensing electrode SC2 that forms a mutual capacitance with the first sensing electrode SC1. When the user approaches the sensing electrodes sufficiently closely, the mutual capacitance between the first sensing electrode SC1 and the second sensing electrode SC2 changes, so the user's touch can be detected based on the difference in the mutual capacitance change according to the sensing signal. In an embodiment, the drive signal can be sent through the sensing wiring corresponding to the second sensing electrode SC2, and the sensing signal can be received through the sensing wiring corresponding to the first sensing electrode SC1 used to form a mutual capacitance with the second sensing electrode SC2.

[0067] Pads (or "pads") PDE1, PDE2, and PDE3 may be located in the second additional area ADA2. Pads PDE1 and PDE3 may be connected to sensing electrodes SC1 and SC2 located above the encapsulation film TFE through sensing wirings IST1 and IST2. Pads PDE1 and PDE3 may be connected to an external touch integrated chip ("IC"). In addition, pad PDE2 may be connected to a pixel or a driver of a pixel located below the encapsulation film TFE through display wiring DST. The driver may include a scan driver, a light emitting driver, a data driver, and the like. The driver may be located below the encapsulation film TFE, or may be located in an external display IC connected through pad PDE2.

[0068] When the display device DP includes a mutual capacitance sensor, the touch IC can send a drive signal through the first sensing wiring IST1, and can receive a sensing signal through the second sensing wiring IST2. In an embodiment, the drive signal can be sent through the second sensing wiring IST2, and the sensing signal can be received through the first sensing wiring IST1. When the display device DP includes a self-capacitance sensor, the driving method of the first sensing wiring IST1 and the second sensing wiring IST2 can be the same. The display wiring DST may include a control line, a data line, a power line, etc., and may provide a signal so that the pixel can display an image. The signal can be provided from a driver connected to the display wiring DST.

[0069] Figure 1 shows a state in which the substrate SUB is bent, Figure 2 1 and 2 show a state in which the substrate SUB is not bent. Figure 2 After being stacked on the substrate SUB as shown in FIG. Figure 1 Bend as shown in FIG.

[0070] The substrate SUB may include a first curved area BA1 extending from a first side RC1 of the first additional area ADA1 to overlap with the non-display area NDA. In addition, the first curved area BA1 may be extended to overlap with the display area DA. That is, each of the display area DA, the non-display area NDA, and the first additional area ADA1 may partially overlap with the first curved area BA1. The first curved area BA1 may have a width extending in the first direction DR1 and a length extending in the second direction DR2. The first bending axis BX1 may be defined as a folding line extending through the center of the first curved area BA1 in the second direction DR2. According to an embodiment, the first curved area BA1 may be a portion where stress is reduced due to the removal of a portion of an insulating film or the like. Therefore, unlike other portions around the first curved area BA1, the first curved area BA1 may have a portion of an insulating film or the like removed. According to an embodiment, the first curved area BA1 may have the same configuration as other portions around the first curved area BA1. In other words, the first curved area BA1 may not have a portion of an insulating film removed.

[0071] The substrate SUB may include a third curved area BA3 extending from the second side RC2 of the first additional area ADA1 to overlap the non-display area NDA. In addition, the third curved area BA3 may be extended to overlap the display area DA. That is, each of the display area DA, the non-display area NDA, and the first additional area ADA1 may partially overlap the third curved area BA3. The third curved area BA3 may have a width extending in the first direction DR1 and a length extending in the second direction DR2. The third bending axis BX3 may be defined as a folding line extending through the center of the third curved area BA3 in the second direction DR2. According to an embodiment, the third curved area BA3 may be a portion where stress is reduced by removing a portion of an insulating film or the like. Therefore, compared with other portions around the third curved area BA3, the third curved area BA3 may have a portion of an insulating film or the like removed. According to an embodiment, the third curved area BA3 may have the same configuration as other portions around the third curved area BA3. In other words, the third curved area BA3 may not have a portion of an insulating film removed.

[0072] The second additional area ADA2 may include a second bending area BA2. The second bending area BA2 may have a width extending in the second direction DR2 and a length extending in the first direction DR1. The second bending axis BX2 may be defined as a folding line extending through the center of the second bending area BA2 in the first direction DR1. According to an embodiment, the second bending area BA2 may be a portion where stress is reduced due to the removal of a portion of an insulating film or the like. Therefore, the second bending area BA2 may have a portion of an insulating film or the like removed compared to other portions around the second bending area BA2. According to an embodiment, the second bending area BA2 may have the same configuration as other portions around the second bending area BA2. In other words, the second bending area BA2 may not have a portion of the insulating film removed.

[0073] In one or more embodiments, the first bending area BA1, the second bending area BA2, and the third bending area BA3 do not overlap each other.

[0074] Here, the term "folding" is intended to refer to a shape that is not fixed and can be modified from its original form to another form, and can refer to folding, bending, or rolling along one or more bending axes. The side frame width of the display device DP in the first direction DR1 and the direction opposite to the first direction DR1 can be reduced by the first bending area BA1 and the third bending area BA3. In addition, the side frame width of the display device DP in the second direction DR2 can be reduced by the second bending area BA2.

[0075] Figure 3 yes Figure 2 an enlarged view of a portion of the first additional region, Figure 4 is a diagram for describing the effect of increasing the separation distance between the second sensing insulating film and the first side.

[0076] Specifically, Figure 3 FIG. 4 shows an enlarged view of the non-display area NDA, the first additional area ADA1, and the second additional area ADA2 near the first side RC1. However, in one or more embodiments, Figure 3 The description of the embodiment in FIG. 1 can be applied to the second side RC2 in addition to the first side RC1.

[0077] The first sensing insulating film ISI1 may be located on the packaging film TFE. The first sensing insulating film ISI1 may cover the sensing electrodes SC1 and SC2, the sensing wirings IST1 and IST2, and the bridge electrode CP1 and the connection pattern CP2 (refer to Fig.18 and Fig.19 ) at least some of ).

[0078] The second sensing insulating film ISI2 may be located on the first sensing insulating film ISI1, the sensing electrodes SC1 and SC2, and the sensing wirings IST1 and IST2. The second sensing insulating film ISI2 may cover the sensing electrodes SC1 and SC2 and the sensing wirings IST1 and IST2 in the display area DA, the non-display area NDA, and the first additional area ADA1. According to an embodiment, the second sensing insulating film ISI2 may additionally cover the sensing wirings IST1 and IST2 in the second additional area ADA2.

[0079] According to an embodiment, the second sensing insulating film ISI2 may cover at least a portion of the second wiring protection film LPL2. The second wiring protection film LPL2 may cover the sensing wirings IST1 and IST2 passing through the second bending area BA2 and the display wiring DST.

[0080] The first side RC1 can be bent with a curvature radius CR. As the curvature radius CR increases, the space where the sensing wiring IST1 and IST2 or the display wiring DST is to be set is reduced and insufficient. Therefore, it is desirable to reduce the curvature radius CR to match the sensing wiring IST1 and IST2 or the display wiring DST. However, the stress applied to the first curved area BA1 increases as the curvature radius CR becomes smaller or decreases. In this case, cracks may appear in the second sensing insulating film ISI2.

[0081] The first additional area ADA1 can be referred to as a stress relaxation area. When the radius of curvature CR is large, the length of the first additional area ADA1 in the second direction DR2 will increase, and the width of the first additional area ADA1 in the first direction DR1 will decrease. In this case, as described above, the stress applied to the first bending area BA1 can be reduced, but the space where the wiring IST1, IST2 and DST are to be set will be insufficient. On the other hand, as the radius of curvature CR decreases, the length of the first additional area ADA1 in the second direction DR2 will decrease, and the width of the first additional area ADA1 in the first direction DR1 will increase. In this case, as described above, the stress applied to the first bending area BA1 will increase, but the available space where the wiring IST1, IST2 and DST are to be set will increase.

[0082] Reference Figure 4 , it can be seen that as the distance from the first side RC1 increases, the stress applied to the first sensing insulating film ISI1 and the second sensing insulating film ISI2 decreases.

[0083] The first sensing insulating film ISI1 may be constructed of an inorganic film, and cracks may occur when a stress of 500 MPa or more is applied. Figure 4It can be seen that since the stress applied to the first sensing insulating film ISI1 is about 43 MPa, even if the first side RC1 is close to the first sensing insulating film ISI1, the possibility of cracks occurring in the first sensing insulating film ISI1 is low.

[0084] The second sensing insulating film ISI2 may be constructed of an organic film and may crack when a stress of 6 MPa or more is applied. When the second sensing insulating film ISI2 is close to the first side RC1, since a stress of about 5.5 MPa may occur in the second sensing insulating film ISI2, a possibility of cracks occurring in the second sensing insulating film ISI2 is high.

[0085] Therefore, it is desirable that the second sensing insulating film ISI2 is sufficiently spaced apart from the first side RC1. According to experimental results, it is confirmed that when the boundary of the second sensing insulating film ISI2 is spaced apart from the first side RC1 by 200 μm or more, the possibility of cracks occurring in the second sensing insulating film ISI2 is significantly reduced.

[0086] Therefore, when the boundary of the second sensing insulating film ISI2 is sufficiently spaced apart from the first side RC1, the stress applied to the second sensing insulating film ISI2 can be reduced, thereby having the advantage that the curvature radius CR of the first side RC1 can be further reduced without undesirably increasing the possibility of cracks occurring in the second sensing insulating film ISI2.

[0087] In an embodiment, at least some boundaries of the first sensing insulating film ISI1 may be closer to the first side RC1 than at least some boundaries of the second sensing insulating film ISI2. That is, a first distance DI1 between at least some boundaries of the first sensing insulating film ISI1 and the first side RC1 may be smaller than a second distance DI2 between at least some boundaries of the second sensing insulating film ISI2 and the first side RC1. For example, the first distance DI1 and the second distance DI2 may be distances on the first bending axis BX1.

[0088] According to such an embodiment, at least some boundaries of the first sensing insulating film ISI1 may not be covered by the second sensing insulating film ISI2. For example, at least some boundaries of the first sensing insulating film ISI1 may be exposed by the second sensing insulating film ISI2. That is, near the first side RC1, a non-covered area ("NCA") may exist in the first sensing insulating film ISI1.

[0089] At least some of the boundaries of the first sensing insulating film ISI1 and at least some of the boundaries of the second sensing insulating film ISI2 described above may be located in the first bending area BA1.

[0090] Figure 5 It is along Figure 2 Example of a cross section taken along line II'. Assuming Figure 2 The line II′ passes through the first pad PDE1 and the first sensing wiring IST1.

[0091] First, the display area DA will be described.

[0092] In the disclosed embodiment, the pixels PX are disposed in the display area DA. Each pixel PX may include a transistor connected to a corresponding wiring in the display wiring DST, a light emitting element connected to the transistor, and a capacitor Cst. Figure 5 In the figure, for the convenience of description, one transistor, one light emitting element, and one capacitor Cst are shown for one pixel PX as an example.

[0093] The substrate SUB may be formed of an insulating material such as glass and / or resin. In addition, the substrate SUB may be formed of a material having flexibility to be bent or folded, and may have a single-layer structure or a multi-layer structure.

[0094] For example, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material constituting the substrate SUB may be variously changed and may be formed of fiber reinforced plastic ("FRP") or the like.

[0095] For example, when the substrate SUB has a multi-layer structure, an inorganic material such as silicon nitride, silicon oxide, and / or silicon oxynitride may be interposed between a plurality of layers as a single layer or as a multi-layer.

[0096] The buffer film BF may cover the substrate SUB. The buffer film BF may prevent or substantially prevent impurities from diffusing into the channel of the transistor. The buffer film BF may be an inorganic insulating film formed of an inorganic material. For example, the buffer film BF may be formed of silicon nitride, silicon oxide, silicon oxynitride, etc., and in one or more embodiments, the buffer film BF may be omitted according to the material and process conditions of the substrate SUB. According to an embodiment, a barrier layer may be further provided.

[0097] The active film ACT may be located on the buffer film BF. The active film ACT may be patterned to construct a channel, a source electrode, and a drain electrode of a transistor, or may be patterned to construct wiring. The active film ACT may be formed of a semiconductor material. The active film ACT may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The channel of the transistor is a semiconductor pattern that is not doped with impurities, and may be an intrinsic semiconductor. The source electrode, the drain electrode, and the wiring may be a semiconductor pattern doped with impurities. Impurities such as n-type impurities (e.g., impurities for providing n-type doping), p-type impurities (e.g., impurities for providing p-type doping), and / or other metals may be used.

[0098] The first gate insulating film GI1 may cover the active film ACT. The first gate insulating film GI1 may be an inorganic insulating film formed of an inorganic material. As the inorganic material, an inorganic insulating material such as polysiloxane, silicon nitride, silicon oxide, or silicon oxynitride may be used.

[0099] The gate electrode GE of the transistor and the lower electrode LE of the capacitor Cst may be located on the first gate insulating film GI1. The gate electrode GE may overlap a region corresponding to a channel.

[0100] The gate electrode GE and the lower electrode LE may be formed of a metal. For example, the gate electrode GE may be formed of at least one of a metal such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium, or copper (Cu) and an alloy of the metal. In addition, the gate electrode GE may be formed of a single film, but is not limited thereto, and may be formed of a plurality of films in which two or more materials of the metal and the alloy are stacked.

[0101] The second gate insulating film GI2 may cover the gate electrode GE and the lower electrode LE. The second gate insulating film GI2 may be an inorganic insulating film formed of an inorganic material. As the inorganic material, polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. may be used.

[0102] The upper electrode UE of the capacitor Cst may be located on the second gate insulating film GI2. The upper electrode UE of the capacitor Cst may be formed of a metal. For example, the upper electrode UE may be formed of at least one of a metal such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium or copper (Cu) and an alloy of the metal. In addition, the upper electrode UE may be formed of a single film, but is not limited thereto, and may be formed of a plurality of films in which two or more materials in the metal and the alloy are stacked.

[0103] The lower electrode LE and the upper electrode UE may form a capacitor Cst with the second gate insulating film GI2 interposed therebetween. Figure 5, the capacitor Cst is shown as a two-layer electrode structure of a lower electrode LE and an upper electrode UE. However, in one or more embodiments, the capacitor Cst may be constructed as a three-layer electrode structure using an active film ACT or a three-layer electrode structure using electrodes of the same layer as the first connection pattern CNP1, or may be constructed as a four-layer electrode structure or more.

[0104] The interlayer insulating film ILD may cover the upper electrode UE. The interlayer insulating film ILD may be an inorganic insulating film formed of an inorganic material. As the inorganic material, polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. may be used.

[0105] In this embodiment, for ease of description, the first gate insulating film GI1, the second gate insulating film GI2 and the interlayer insulating film ILD may be referred to as a first insulating film group ING1. The first insulating film group ING1 may cover a portion of the transistor. According to an embodiment, the first insulating film group ING1 may further include a buffer film BF.

[0106] The first connection pattern CNP1 may be located on the interlayer insulating film ILD and may contact one of the source electrode and the drain electrode of the active film ACT through a contact hole formed through the interlayer insulating film ILD, the second gate insulating film GI2, and the first gate insulating film GI1.

[0107] The first connection pattern CNP1 may be formed of a metal. For example, the first connection pattern CNP1 may be formed of at least one of a metal such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium or copper (Cu) and an alloy of the metal.

[0108] According to an embodiment, a passivation film may cover the first connection pattern CNP1. The passivation film may be an inorganic insulating film formed of an inorganic material. Inorganic materials such as polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. may be used for the passivation film.

[0109] The first via film VIA1 may cover a passivation film or a transistor. The first via film VIA1 may be an organic insulating film formed of an organic material. As the organic material, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorocarbon compound (such as Teflon) and / or a benzocyclobutene compound may be used. The organic film may be deposited by a method such as evaporation.

[0110] The second connection pattern CNP2 may be connected to the first connection pattern CNP1 through the opening portion of the first via film VIA1. The second connection pattern CNP2 may be formed of at least one of a metal and an alloy of the metal such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium or copper (Cu).

[0111] The second via film VIA2 may cover the first via film VIA1 and the second connection pattern CNP2. The second via film VIA2 may be an organic insulating film formed of an organic material. As the organic material, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorocarbon compound (such as Teflon) and / or a benzocyclobutene compound may be used.

[0112] The first light emitting element electrode LDE1 may be connected to the second connection pattern CNP2 through an opening portion of the second via film VIA2. Here, the first light emitting element electrode LDE1 may be an anode of the light emitting element according to the embodiment.

[0113] According to an embodiment, the configuration of the second via film VIA2 and the second connection pattern CNP2 may be omitted, and the first light emitting element electrode LDE1 may be directly connected to the first connection pattern CNP1 through the opening portion of the first via film VIA1 .

[0114] The first light emitting element electrode LDE1 may be formed of at least one of a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr, an alloy of the metal, indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide ("ZnO"), indium tin zinc oxide ("ITZO"), etc. The first light emitting element electrode LDE1 may be formed of one metal, but is not limited thereto, and may be formed of two or more metals, for example, an alloy of Ag and Mg.

[0115] When an image is to be provided in a downward direction of the substrate SUB, the first light emitting element electrode LDE1 may be formed of a transparent conductive film, and when an image is to be provided in an upward direction of the substrate SUB, the first light emitting element electrode LDE1 may be formed of a metal reflective film and a transparent conductive film.

[0116] A pixel defining layer PDL for dividing the light emitting area of ​​each pixel PX is disposed on the substrate SUB on which the first light emitting element electrode LDE1 and the like are formed. The pixel defining layer PDL may be an organic insulating layer formed of an organic material. An organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorocarbon compound (such as Teflon), or a benzocyclobutene compound may be used for the pixel defining layer PDL.

[0117] The pixel defining layer PDL may expose the upper surface of the first light emitting element electrode LDE1 and may protrude from the substrate SUB along the periphery of the pixel PX. The light emitting film EML may be disposed in a region of the pixel PX surrounded by the pixel defining layer PDL.

[0118] The light-emitting film EML may include a low molecular weight material or a high molecular weight material. Examples of low molecular weight materials may include copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (Alq 3 ) etc. These materials can be formed by a vacuum deposition method. Examples of polymer materials may include PEDOT, polyphenylene vinylene ("PPV"), polyfluorene, etc.

[0119] The light-emitting film EML may be provided as a single layer, but may also be provided as a multilayer including various functional layers. When the light-emitting film EML is multilayer, the light-emitting film EML may have a structure in which a hole injection layer ("HIL"), a hole transport layer ("HTL"), an emission layer ("EML"), an electron transport layer ("ETL"), an electron injection layer ("EIL"), etc. are stacked in a single structure or a composite structure. The light-emitting film EML may be formed by screen printing, inkjet printing, laser induced thermal imaging ("LITI"), etc.

[0120] According to an embodiment, at least a portion of the light emitting film EML may be integrally formed over the plurality of first light emitting element electrodes LDE1 , and may also be individually disposed to correspond to the plurality of first light emitting element electrodes LDE1 , respectively.

[0121] The second light emitting element electrode LDE2 may be disposed on the light emitting film EML. The second light emitting element electrode LDE2 may be disposed for each pixel PX, but may also be disposed to cover most of the display area DA and may be shared by a plurality of pixels PX.

[0122] The second light emitting element electrode LDE2 may be used as a cathode or an anode according to the embodiment. When the first light emitting element electrode LDE1 is an anode, the second light emitting element electrode LDE2 may be used as a cathode. When the first light emitting element electrode LDE1 is a cathode, the second light emitting element electrode LDE2 may be used as an anode.

[0123] The second light emitting element electrode LDE2 may be formed of a metal film (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir or Cr), a transparent conductive film (such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide ("ZnO"), indium tin zinc oxide ("ITZO"), etc. In the disclosed embodiment, the second light emitting element electrode LDE2 may be formed of a plurality of films including two or more films of a metal thin film, for example, the second light emitting element electrode LDE2 may be formed of three films of ITO / Ag / ITO.

[0124] When an image is to be provided in a downward direction of the substrate SUB, the second light emitting element electrode LDE2 may be formed of a metal reflective film and a transparent conductive film, and when an image is to be provided in an upward direction of the substrate SUB, the second light emitting element electrode LDE2 may be formed of a transparent conductive film.

[0125] A set of the first light emitting element electrode LDE1 , the light emitting film EML, and the second light emitting element electrode LDE2 may be referred to as a light emitting element.

[0126] The encapsulation film TFE may be disposed on the second light emitting element electrode LDE2. The encapsulation film TFE may be formed of a single layer, but may also be formed of multiple layers. In the present embodiment, the encapsulation film TFE may include a first encapsulation film ENC1, a second encapsulation film ENC2, and a third encapsulation film ENC3. The first encapsulation film ENC1, the second encapsulation film ENC2, and the third encapsulation film ENC3 may be formed of an organic material and / or an inorganic material. The third encapsulation film ENC3 located at the outermost periphery may be formed of an inorganic material. For example, the first encapsulation film ENC1 may be an inorganic film constructed of an inorganic material, the second encapsulation film ENC2 may be an organic film constructed of an organic material, and the third encapsulation film ENC3 may be an inorganic film constructed of an inorganic material. The penetration of moisture or oxygen into an inorganic material is less than that of an organic material. However, because the elasticity or flexibility of an inorganic material may be low, the inorganic material is susceptible to cracks. The propagation of cracks may be prevented or reduced by forming the first encapsulation film ENC1 and the third encapsulation film ENC3 with an inorganic material and forming the second encapsulation film ENC2 with an organic material. Here, the layer formed by the organic material (i.e., the second encapsulation film ENC2) can be completely covered by the third encapsulation film ENC3 so that the end is not exposed to the outside. As the organic material, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorocarbon compound (such as Teflon) and / or a benzocyclobutene compound can be used. As the inorganic material, polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. can be used.

[0127] The light-emitting film EML forming the light-emitting element may be easily damaged by moisture or oxygen from the outside. The encapsulation film TFE protects the light-emitting element by covering the light-emitting film EML. The encapsulation film TFE covers the display area DA and may extend to the non-display area NDA outside the display area DA. However, in the case of an insulating film formed of an organic material, there are advantages in flexibility and elasticity, but moisture and oxygen may more easily penetrate the insulating film formed of the organic material than the insulating film formed of an inorganic material. In the disclosed embodiment, in order to prevent or reduce moisture or oxygen from penetrating through the insulating film formed of the organic material, the end of the insulating film formed of the organic material may be covered by the insulating film formed of the inorganic material so as not to be exposed to the outside. For example, the first via film VIA1, the second via film VIA2, and the pixel defining layer PDL formed of an organic material extend discontinuously to the non-display area NDA and may be covered by the first encapsulation film ENC1. Therefore, the upper surface of the pixel defining layer PDL and the sides of the first via film VIA1 , the second via film VIA2 , and the pixel defining layer PDL may be prevented or substantially prevented from being exposed to the outside by being sealed by the encapsulation film TFE including an inorganic material.

[0128] However, whether the encapsulation film TFE is formed of a plurality of layers or the material of the encapsulation film TFE is not limited thereto and may be variously changed. For example, the encapsulation film TFE may include a plurality of organic material layers and a plurality of inorganic material layers alternately stacked.

[0129] The first sensing electrode layer ISM1 may be located on the encapsulation film TFE. According to an embodiment, an additional buffer film may be located between the first sensing electrode layer ISM1 and the encapsulation film TFE. The first sensing electrode layer ISM1 may be formed of a metal film such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr, a transparent conductive film such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide ("ZnO"), indium tin zinc oxide ("ITZO"), etc.

[0130] The first sensing insulating film ISI1 may exist on the first sensing electrode layer ISM1. The first sensing insulating film ISI1 may be an inorganic insulating film formed of an inorganic material. Inorganic insulating materials such as polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. may be used for the first sensing insulating film ISI1.

[0131] The second sensing electrode layer ISM2 may be present on the first sensing insulating film ISI1. The second sensing electrode layer ISM2 may be formed of a metal film such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr, a transparent conductive film such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide ("ZnO"), or indium tin zinc oxide ("ITZO"), etc.

[0132] Will refer to later Figures 17 to 19 Configurations of various input sensors using the first sensing electrode layer ISM1 , the first sensing insulating film ISI1 , and the second sensing electrode layer ISM2 are described.

[0133] exist Figure 5 In the embodiment of FIG. 5 , the second sensing electrode layer ISM2 may be patterned to form the first pattern IST1 a of the first sensing wiring IST1 .

[0134] The second sensing insulating film ISI2 may be located on the second sensing electrode layer ISM2. The second sensing insulating film ISI2 may be constructed of an organic film. For example, as an organic insulating material, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorocarbon compound (such as Teflon), or a benzocyclobutene compound may be used. For example, the second sensing insulating film ISI2 may be constructed of polymethyl methacrylate, polydimethylsiloxane, polyimide, acrylate, polyethylene terephthalate, polyethylene naphthalate, etc.

[0135] Next, the non-display area NDA, the first additional area ADA1, and the second additional area ADA2 will be described. Figure 5 The non-display area NDA and the first additional area ADA1 are not described separately because they are not typical in the cross-sectional view. Hereinafter, when describing the non-display area NDA and the second additional area ADA2, in order to avoid repeated description, their description will be omitted or briefly described.

[0136] The dam DAM may be located at the boundary of the second encapsulation film ENC2. For example, the dam DAM may be located between the planarization film FLT and the second encapsulation film ENC2. The dam DAM may be a multilayer structure and may include, for example, a first dam DAM1 and a second dam DAM2. For example, the first dam DAM1 and the second dam DAM2 may be formed of an organic material. The first dam DAM1 and the second dam DAM2 may correspond to any one of the first via film VIA1, the second via film VIA2, and the pixel defining layer PDL. For example, when the first dam DAM1 is constructed of the same material by the same process as the first via film VIA1, the second dam DAM2 may be constructed of the same material by the same process as the second via film VIA2 or the pixel defining layer PDL. In another example, when the first dam DAM1 is constructed of the same material by the same process as the second via film VIA2, the second dam DAM2 may be constructed of the same material by the same process as the pixel defining layer PDL. In addition, when the spacer is formed on the pixel defining layer PDL of the display area DA, the dam DAM may also be constructed using the same material as the spacer.

[0137] The dam DAM prevents or substantially prevents the organic material of the second encapsulation film ENC2 having high fluidity from overflowing to the outside of the dam DAM during a process (e.g., a formation process). The first encapsulation film ENC1 and the third encapsulation film ENC3 constructed of an inorganic material may cover the dam DAM and extend, thereby increasing adhesion to the substrate SUB or other films on the substrate SUB.

[0138] The first pad PDE1 may be located on the substrate SUB and may be spaced apart from the planarization film FLT. The first pad PDE1 may be supported by the second insulation film group ING2. The insulation film of the second insulation film group ING2 may correspond to the insulation film of the first insulation film group ING1. The first pad PDE1 may include a first pad electrode PDE1a and a second pad electrode PDE1b. The first pad electrode PDE1a may be constructed of the same material as the first connection pattern CNP1. The second pad electrode PDE1b may be constructed of the same material as the second connection pattern CNP2.

[0139] The planarization film FLT may be located on the substrate SUB and may be spaced apart from the area covered by the encapsulation film TFE. The planarization film FLT may be an organic insulating film formed of an organic material. An organic insulating material (such as a polyacrylic compound, a polyimide compound, a fluorocarbon compound (such as Teflon), a benzocyclobutene compound, etc.) may be used for the planarization film FLT.

[0140] In the present embodiment, the planarization film FLT may be formed after forming the interlayer insulating film ILD and before forming the first connection pattern CNP1. Therefore, the planarization film FLT and the first via film VIA1 may be formed by different processes. According to the embodiment, the planarization film FLT and the first via film VIA1 may include different organic materials.

[0141] One end of the planarization film FLT may cover the first insulation film group ING1. In addition, a portion of the planarization film FLT corresponding to the second bending area BA2 may fill the first trench TCH1 between the first insulation film group ING1 and the second insulation film group ING2.

[0142] Since inorganic insulating films have higher rigidity and lower flexibility than organic insulating films, the possibility of cracks is relatively high. When cracks occur in the inorganic insulating film, the cracks spread to the wiring on the inorganic insulating film and cause defects, disconnection, etc. of the wiring.

[0143] Therefore, if Figure 5As shown in FIG. 1 , the first trench TCH1 may be formed by removing the inorganic insulating film from the second bending area BA2, and the first insulating film group ING1 and the second insulating film group ING2 may be distinguished. In the present embodiment, all inorganic insulating films corresponding to the region of the first trench TCH1 are removed, but in one or more embodiments, some inorganic insulating films may be retained. In this case, the retained inorganic insulating film may include slits to disperse the bending stress.

[0144] The second pattern IST1b of the first sensing wiring IST1 may extend on the planarization film FLT and may be electrically connected to the first pad PDE1. In the present embodiment, the second pattern IST1b may be configured of the same material through the same process as the first connection pattern CNP1.

[0145] The first wiring protection film LPL1 may cover the planarization film FLT and the second pattern IST1b. In addition, the second wiring protection film LPL2 may cover the first wiring protection film LPL1. According to an embodiment, the construction of the second wiring protection film LPL2 may be omitted. The first wiring protection film LPL1 and the second wiring protection film LPL2 may be formed of an organic material. The first wiring protection film LPL1 and the second wiring protection film LPL2 may correspond to any one of the first via film VIA1, the second via film VIA2, and the pixel defining layer PDL. For example, when the first wiring protection film LPL1 is constructed of the same material by the same process as the first via film VIA1, the second wiring protection film LPL2 may be constructed of the same material by the same process as the second via film VIA2 or the pixel defining layer PDL. In another example, when the first wiring protection film LPL1 is constructed of the same material by the same process as the second via film VIA2, the second wiring protection film LPL2 may be constructed of the same material by the same process as the pixel defining layer PDL.

[0146] The first and second wiring protection films LPL1 and LPL2 and the first sensing insulating film ISI1 may include a first opening portion OPN1 exposing the second pattern IST1 b .

[0147] The first pattern IST1a may be connected to the second pattern IST1b through the first opening portion OPN1. According to the present embodiment, the height of the second pattern IST1b (e.g., the first portion of the second pattern IST1b) located on one end of the first insulating film group ING1 and the planarization film FLT may be greater than the height of the second pattern IST1b (e.g., the second portion of the second pattern IST1b) located on the planarization film FLT corresponding to the first trench TCH1.

[0148] Therefore, the first pattern IST1a and the second pattern IST1b can be directly connected to each other without another bridge wiring. Because there is no bridge wiring, the connection reliability between the first pattern IST1a and the second pattern IST1b is improved. In addition, because the length of the non-display area NDA can reduce the length of the bridge wiring, the dead zone is reduced, thereby more easily realizing a thin frame.

[0149] The third pattern IST1c of the first sensing wiring IST1 may connect the first pad PDE1 and the second pattern ISTb to each other. The third pattern IST1c may be formed of the same material by the same process as the gate electrode GE of the transistor. According to an embodiment, the third pattern IST1c may be formed of the same material by the same process as the upper electrode UE. According to an embodiment, the third pattern IST1c numbered odd along the first direction DR1 may be formed of the same material by the same process as the gate electrode GE of the transistor, and the third pattern IST1c numbered even along the first direction DR1 may be formed of the same material by the same process as the upper electrode UE. In one or more embodiments, the third pattern IST1c numbered even along the first direction DR1 may be formed of the same material by the same process as the gate electrode GE of the transistor, and the third pattern IST1c numbered odd along the first direction DR1 may be formed of the same material by the same process as the upper electrode UE. Therefore, short circuits between adjacent wirings may be more effectively prevented or the risk of short circuits may be reduced.

[0150] The second insulating film group ING2 may include a second opening portion OPN2 exposing the third pattern IST1c. In addition, the planarization film FLT may include an opening portion corresponding to the second opening portion OPN2. The second pattern IST1b may be connected to the third pattern IST1c through the second opening portion OPN2.

[0151] Figures 6 to 8 Shown along Figure 2 A cross section taken along line II-II'.

[0152] Figure 2 The line II-II' may correspond to the first bending axis BX1. However, the same embodiment may be applied to the second side RC2 in addition to the first side RC1.

[0153] The display wiring DST may be constructed by a single-layer wiring or a multi-layer wiring using at least one of the wirings G1L, G2L, and SDL. The wiring G1L may be constructed by the same material through the same process as the gate electrode GE. The wiring G2L may be constructed by the same material through the same process as the upper electrode UE. The wiring SDL may be constructed by the same material through the same process as the first connection pattern CNP1.

[0154] The first patterns IST1a and IST2a of the sensing wirings IST1 and IST2 may be located on the packaging film TFE and the first sensing insulating film ISI1 (in the third direction DR3), and may be located between the dam DAM and the display area DA (in the second direction DR2). The first sensing insulating film ISI1 may be located between the packaging film TFE and the first patterns IST1a and IST2a of the sensing wirings IST1 and IST2.

[0155] exist Figure 6 In the embodiment of the present invention, the second sensing insulating film ISI2 covers the first sensing insulating film ISI1. Figure 3 Compared to the embodiment shown in , there is no non-coverage area NCA.

[0156] In this case, since the distance D21 from the first side RC1 is not sufficiently ensured, a large stress may be applied to the second sensing insulating film ISI2 when the first bending area BA1 is bent, and a crack may occur in the second sensing insulating film ISI2.

[0157] exist Figure 7 In the embodiment of FIG. 1 , a portion of the first sensing insulating film ISI1 is not covered by the second sensing insulating film ISI2. Figure 3 In an embodiment, there is a non-coverage area NCA.

[0158] In this case, since the distance D22 from the first side RC1 is sufficiently ensured, stress applied to the second sensing insulating film ISI2 when the first bending area BA1 is bent may be relatively small, and cracks may not occur in the second sensing insulating film ISI2.

[0159] exist Figure 7 In the embodiment of the present invention, at least some boundaries of the second sensing insulating film ISI2 may be closer to the first side RC1 than the dam DAM.

[0160] exist Figure 8 In the embodiment of FIG. 1 , a portion of the first sensing insulating film ISI1 is not covered by the second sensing insulating film ISI2. Figure 3 In an embodiment, there is a non-coverage area NCA.

[0161] In this case, since the distance D23 from the first side RC1 is sufficiently ensured, the stress applied to the second sensing insulating film ISI2 when the first bending area BA1 is bent may be smaller than that of the first side RC1. Figure 7 The stress is small, and cracks do not occur in the second sensing insulating film ISI2.

[0162] exist Figure 8In the embodiment of the present invention, at least some boundaries of the second sensing insulating film ISI2 may be farther from the first side RC1 than the dam DAM. In addition, at least some boundaries of the second sensing insulating film ISI2 may be closer to the first side RC1 than the first patterns IST1a and IST2a of the sensing wirings IST1 and IST2. Therefore, the second sensing insulating film ISI2 may cover the first patterns IST1a and IST2a of the sensing wirings IST1 and IST2, and thus may protect the first patterns IST1a and IST2a.

[0163] Fig. 9 It is along Figure 2 An embodiment of a cross section taken along line II'.

[0164] and Figure 5 Compared with the embodiment of Fig. 9 In the embodiment of FIG. 5 , the first sensing electrode layer ISM1 may be patterned to form a first pattern IST1 a ′ of the first sensing wiring IST1 .

[0165] The first wiring protection film LPL1 and the second wiring protection film LPL2 may include a first opening portion OPN1. Figure 5 Compared with the embodiment of the present invention, the first sensing insulating film ISI1 does not include the first opening portion OPN1. The first pattern IST1a' may be connected to the second pattern IST1b through the first opening portion OPN1. The first sensing insulating film ISI1 may cover the first pattern IST1a'.

[0166] Will omit Figure 5 The constructs in are redundant with the descriptions of other constructs.

[0167] Figures 10 to 12 It is along Figure 2 An embodiment of a cross section taken along line II-II'.

[0168] Figure 2 The line II-II' may correspond to the first bending axis BX1. However, the same embodiment may be applied to the second side RC2 in addition to the first side RC1.

[0169] The display wiring DST may be constructed by a single-layer wiring or a multi-layer wiring using at least one of the wirings G1L, G2L, and SDL. The wiring G1L may be constructed by the same material through the same process as the gate electrode GE. The wiring G2L may be constructed by the same material through the same process as the upper electrode UE. The wiring SDL may be constructed by the same material through the same process as the first connection pattern CNP1.

[0170] The first patterns IST1a' and IST2a' of the sensing wirings IST1 and IST2 may be located between the encapsulation film TFE and the first sensing insulating film ISI1 (in the third direction DR3), and may be located between the dam DAM and the display area DA (in the second direction DR2). The first sensing insulating film ISI1 may be located between the first patterns IST1a' and IST2a' of the sensing wirings IST1 and IST2 and the second sensing insulating film ISI2.

[0171] exist Fig.10 In the embodiment of the present invention, the second sensing insulating film ISI2 covers the first sensing insulating film ISI1. Figure 3 Compared with the embodiment, there is no non-coverage area NCA.

[0172] In this case, since the distance D21 ′ from the first side RC1 is not sufficiently ensured, a large stress may be applied to the second sensing insulating film ISI2 when the first bending area BA1 is bent, and a crack may occur in the second sensing insulating film ISI2 .

[0173] exist Fig.11 In the embodiment of FIG. 1 , a portion of the first sensing insulating film ISI1 is not covered by the second sensing insulating film ISI2. Figure 3 In an embodiment, there is a non-coverage area NCA.

[0174] In this case, since the distance D22 ′ from the first side RC1 is sufficiently ensured, stress applied to the second sensing insulating film ISI2 when the first bending area BA1 is bent may be relatively small, and cracks may not occur in the second sensing insulating film ISI2 .

[0175] exist Fig.11 In the embodiment of the present invention, at least some boundaries of the second sensing insulating film ISI2 may be closer to the first side RC1 than the dam DAM.

[0176] exist Fig.12 In the embodiment of FIG. 1 , a portion of the first sensing insulating film ISI1 is not covered by the second sensing insulating film ISI2. Figure 3 In an embodiment, there is a non-coverage area NCA.

[0177] In this case, since the distance D23′ from the first side RC1 is sufficiently ensured, the stress applied to the second sensing insulating film ISI2 when the first bending area BA1 is bent may be smaller than that of the first side RC1. Fig.11 The stress is small, and cracks do not occur in the second sensing insulating film ISI2.

[0178] exist Fig.12In the embodiment of the present invention, at least some boundaries of the second sensing insulating film ISI2 may be farther from the first side RC1 than the dam DAM. In addition, at least some boundaries of the second sensing insulating film ISI2 may be closer to the first side RC1 than the first patterns IST1a' and IST2a' of the sensing wirings IST1 and IST2. Therefore, the second sensing insulating film ISI2 may cover the first patterns IST1a' and IST2a' of the sensing wirings IST1 and IST2, and thus may protect the first patterns IST1a' and IST2a'.

[0179] Figures 13 to 16 It is along Figure 2 An embodiment of a cross section taken along line II'.

[0180] Reference Fig.13 ,and Figure 5 In contrast, the first pattern IST1 a of the first sensing wiring IST1 is not directly connected to the second pattern IST1 b .

[0181] Fig.13 The first sensing wiring IST1 of the embodiment may further include a fourth pattern IST1d and a fifth pattern IST1e. The fourth pattern IST1d may be formed of the same material by the same process as the first connection pattern CNP1. The fifth pattern IST1e may be formed of the same material by the same process as the gate electrode GE.

[0182] The first pattern IST1a can be connected to the fourth pattern IST1d through the opening portion of the first sensing insulating film ISI1. In addition, the fourth pattern IST1d can be connected to the fifth pattern IST1e through the opening portion of the interlayer insulating film ILD and the second gate insulating film GI2. The existing second pattern IST1b can be connected to the fifth pattern IST1e through the opening portion of the interlayer insulating film ILD and the second gate insulating film GI2. That is, in Fig.13 In the embodiment of FIG. 5 , the fifth pattern IST1e is used as a bridge wiring. In this case, the step difference due to the organic film can be minimized or reduced, and thus the disconnection possibility of the first sensing wiring IST1 can be reduced.

[0183] In one or more embodiments, the first via film VIA1 may exist below the end (or boundary) of the encapsulation film TFE. In one or more embodiments, the first via film VIA1 may extend to cover the fourth pattern IST1d. In this case, the first pattern IST1a may be connected to the fourth pattern IST1d through the first sensing insulating film ISI1 and the opening portion of the first via film VIA1.

[0184] Fig.14 Examples and Fig.13The embodiment of the present invention is different in that the first pattern IST1a' of the first sensing wiring IST1 is configured as the first sensing electrode layer ISM1. In this case, the first sensing insulating film ISI1 does not include an opening portion on the fourth pattern IST1d. Fig.13 The construction is redundant with the description of the remaining constructions.

[0185] and Figure 5 Compared with the embodiment of Fig.15 In the embodiment of the present invention, the planarization film FLT' can be constructed of the same material by the same process as the first via film VIA1. In this case, the method for forming the planarization film FLT' can be omitted. Figure 5 Therefore, the process cost can be reduced.

[0186] exist Fig.15 In the embodiment of the present invention, the second pattern IST1b′ may be formed of the same material through the same process as the second connection pattern CNP2.

[0187] and Figure 5 Compared with the embodiment, Fig.15 The embodiment may further include a fourth pattern IST1d' connecting the third pattern IST1c' and the second pattern IST1b'. The second opening portion OPN2 of the second insulating film group ING2 may expose the third pattern IST1c' and may be covered by the fourth pattern IST1d'. The planarization film FLT' may include an opening portion exposing the fourth pattern IST1d' corresponding to the second opening portion OPN2. The fourth pattern IST1d' may be constructed of the same material by the same process as the first connection pattern CNP1.

[0188] exist Fig.15 In the embodiment of Figure 5 A construct is redundant with the description of other constructs.

[0189] Reference Fig.16 ,and Fig.15 In contrast, the first pattern IST1 a of the first sensing wiring IST1 is not directly connected to the second pattern IST1 b ′.

[0190] Fig.16 The first sensing wiring IST1 of the embodiment may further include a fifth pattern IST1e', a sixth pattern IST1f', and a seventh pattern IST1g'. The fifth pattern IST1e' and the seventh pattern IST1g' may be formed of the same material by the same process as the first connection pattern CNP1. The sixth pattern IST1f' may be formed of the same material by the same process as the gate electrode GE.

[0191] The first pattern IST1a may be connected to the fifth pattern IST1e' through the opening portion of the first sensing insulating film ISI1. As described above, in one or more embodiments, the first via film VIA1 may exist below the end (or boundary) of the packaging film TFE. In one or more embodiments, the first via film VIA1 may extend to cover the fifth pattern IST1e'. In this case, the first pattern IST1a may be connected to the fifth pattern IST1e' through the first sensing insulating film ISI1 and the opening portion of the first via film VIA1.

[0192] The fifth pattern IST1e' may be connected to the sixth pattern IST1f' through the opening portion of the interlayer insulating film ILD and the second gate insulating film GI2.

[0193] The existing second pattern IST1b' can be connected to the sixth pattern IST1f' through the seventh pattern IST1g'. Fig.16 In the embodiment of FIG. 1 , the sixth pattern IST1f′ is used as a bridge wiring. In this case, the step difference due to the organic film can be minimized and reduced, and the disconnection possibility of the first sensing wiring IST1 can be reduced.

[0194] Fig.17 and Fig.18 is a diagram for describing sensing electrodes and bridging electrodes according to a disclosed embodiment. Fig.18 It is along Fig.17 A cross-sectional view taken along line III-III'.

[0195] The bridge electrode CP1 may be disposed on the packaging film TFE by patterning the first sensing electrode layer ISM1 .

[0196] The first sensing insulating film ISI1 may cover the bridge electrode CP1 , and may include a contact hole CNT exposing a portion of the bridge electrode CP1 .

[0197] The first sensing electrode SC1 and the second sensing electrode SC2 may be formed on the first sensing insulating film ISI1 by patterning the second sensing electrode layer ISM2. The first sensing electrode SC1 may be connected to the bridge electrode CP1 through the contact hole CNT.

[0198] The second sensing electrode SC2 may have the connection pattern CP2 in the same layer by patterning the second sensing electrode layer ISM2. Therefore, when connecting the second sensing electrode SC2, a separate bridge electrode may not be required.

[0199] According to an embodiment, each of the sensing electrodes SC1 and SC2 may cover a plurality of pixels PX. In one or more embodiments, when each of the sensing electrodes SC1 and SC2 is configured as an opaque conductive film, each of the sensing electrodes SC1 and SC2 may include a plurality of opening portions capable of exposing a plurality of covered pixels PX. For example, each of the sensing electrodes SC1 and SC2 may be configured in a mesh shape. When each of the sensing electrodes SC1 and SC2 is configured as a transparent conductive film, each of the sensing electrodes SC1 and SC2 may be configured in a plate form that does not include an opening portion.

[0200] Fig.19 is a diagram for describing sensing electrodes and bridge electrodes according to a disclosed embodiment.

[0201] Fig.19 It is along Fig.17 Another cross-sectional view along line III-III'.

[0202] The first and second sensing electrodes SC1 and SC2 may be formed on the encapsulation film TFE by patterning the first sensing electrode layer ISM1 .

[0203] The first sensing insulating film ISI1 may cover the first and second sensing electrodes SC1 and SC2 , and may include a contact hole CNT exposing a portion of the first sensing electrode SC1 .

[0204] The bridge electrode CP1 may be constructed on the first sensing insulating film ISI1 by patterning the second sensing electrode layer ISM2. The bridge electrode CP1 may be connected to the first sensing electrode SC1 through the contact hole CNT.

[0205] Fig. 20 is based on Figure 3 An enlarged view of a portion of the first additional region of the comparative embodiment. Fig.21 is based on Fig. 20 Along the lines of Figure 2 An embodiment of a cross section taken along line II'. Figure 22 to Figure 24 is based on Fig. 20 Along the lines of Figure 2 An embodiment of a cross section taken along line II-II'.

[0206] A point where the first side RC1 crosses (eg, intersects) the first boundary ED1 may be defined as a first point PT1. In addition, a point where the first side RC1 crosses (eg, intersects) the second boundary ED2 may be defined as a second point PT2.

[0207] Compared to the second point PT2 of the first side RC1, the boundary of the sensing insulating film ISI in the first bending area BA1 may be closer to the first point PT1 of the first side RC1. That is, the boundary of the sensing insulating film ISI in the first bending area BA1 may be closer to the first side RC1 in the second direction DR2. For example, the distance between the first point PT1 and the boundary of the sensing insulating film ISI in the second direction DR2 may be referred to as a third distance DI3. In addition, the distance between the second point PT2 and the boundary of the sensing insulating film ISI in the second direction DR2 may be referred to as a fourth distance DI4. Fig. 20 As shown in , the fourth distance DI4 can be longer than the third distance DI3. Such an arrangement can also be applied to Figure 3 Embodiment of the invention.

[0208] In an embodiment, with respect to the first boundary ED1, the distance between the first point PT1 and the boundary of the sensing insulating film ISI in the first direction DR1 may be referred to as a fifth distance DI5. In addition, with respect to the second boundary ED2, the distance between the second point PT2 and the boundary of the sensing insulating film ISI in the first direction DR1 may be referred to as a sixth distance DI6. In one or more embodiments, the fifth distance DI5 may be longer than the sixth distance DI6. Such an arrangement may also be applied to Figure 3 Embodiment of the invention.

[0209] According to the above embodiment, since the separation distance between the boundary of the sensing insulating film ISI and the first side RC1 can be sufficiently ensured in the first bending area BA1, even if the substrate SUB is designed so that the curvature radius CR is reduced, cracks can be prevented or substantially prevented from occurring in the sensing insulating film ISI.

[0210] Reference Figure 20 to Figure 24 ,and Figure 3 In contrast, the first sensing insulating film ISI1 does not exist, and a sensing insulating film ISI corresponding to the second sensing insulating film ISI2 exists. In addition, the second sensing electrode layer ISM2 does not exist, and a sensing electrode layer corresponding to the first sensing electrode layer ISM1 exists. The first patterns IST1a and IST2a of the sensing wirings IST1 and IST2 and the sensing electrodes SC1 and SC2 may exist as patterns of the sensing electrode layer.

[0211] exist Fig. 22 In this case, the boundary of the sensing insulating film ISI may be closer to the first side RC1 than the boundary of the packaging film TFE. In one or more embodiments, the distance between the boundary of the sensing insulating film ISI and the first side RC1 may correspond to the distance D21″.

[0212] exist Fig.23In this case, the boundary of the sensing insulating film ISI may be farther away from the first side RC1 than the boundary of the packaging film TFE. In addition, the boundary of the sensing insulating film ISI may be closer to the first side RC1 than the dam DAM. In one or more embodiments, the distance between the boundary of the sensing insulating film ISI and the first side RC1 may correspond to the distance D22".

[0213] exist Fig.24 In this case, the boundary of the sensing insulating film ISI may be farther away from the first side RC1 than the boundary of the dam DAM. In addition, the boundary of the sensing insulating film ISI may be closer to the first side RC1 than the first patterns IST1a and IST2a. In one or more embodiments, the distance between the boundary of the sensing insulating film ISI and the first side RC1 may correspond to the distance D23".

[0214] The distance D23 ″ may be longer than the distance D22 ″. The distance D22 ″ may be longer than the distance D21 ″. As described above, as the distance between the boundary of the sensing insulating film ISI and the first side RC1 increases, the possibility of cracks occurring in the sensing insulating film ISI may be reduced.

[0215] Fig.25 and Fig.26 is based on Fig. 20 Embodiments of the sensing electrodes and sensing wiring of the embodiments.

[0216] exist Fig.25 and Fig.26 In the embodiment, Figures 17 to 19 Depending on the embodiment, a bridging electrode may be unnecessary.

[0217] For example, Fig.25 As shown in FIG, the sensing electrodes SC1 and SC2 may have substantially the same area and may be connected to first patterns IST1a and IST2a of the sensing wirings IST1 and IST2, respectively. Each of the first patterns IST1a and IST2a may be connected to a different first pad PDE1.

[0218] exist Fig.26 In the embodiment of the present invention, the area of ​​the first sensing electrode SC1' and the area of ​​the second sensing electrodes SC21' to SC26' may be different from each other. For example, the area of ​​the first sensing electrode SC1' may be larger than the area of ​​each of the second sensing electrodes SC21' to SC26'. The area of ​​the first sensing electrode SC1' and the area of ​​the third sensing electrode SC3' may be substantially the same. The width of the first sensing electrode SC1' and the third sensing electrode SC3' in the fourth direction DR4 may be smaller than the length in the fifth direction DR5.

[0219] The first sensing electrode SC1' may correspond to the second sensing electrodes SC21', SC22', and SC23'. For example, the first sensing electrode SC1' may form a mutual capacitance with the most adjacent second sensing electrodes SC21', SC22', and SC23'. Here, "most adjacent" may refer to the case where the first sensing electrode SC1' is most adjacent to the second sensing electrodes SC21', SC22', and SC23' in the fourth direction DR4 or in a direction opposite to the fourth direction DR4. In one or more embodiments, the length of the first sensing electrode SC1' in the fifth direction DR5 may correspond to the sum of the lengths of the corresponding second sensing electrodes SC21', SC22', and SC23' in the fifth direction DR5.

[0220] The third sensing electrode SC3' may correspond to the second sensing electrodes SC24', SC25', and SC26'. For example, the third sensing electrode SC3' may form a mutual capacitance with the most adjacent second sensing electrodes SC24', SC25', and SC26'. Here, "most adjacent" may refer to a case where the third sensing electrode SC3' is most adjacent to the second sensing electrodes SC24', SC25', and SC26' in the fourth direction DR4 or in a direction opposite to the fourth direction DR4. In one or more embodiments, the length of the third sensing electrode SC3' in the fifth direction DR5 may correspond to the sum of the lengths of the corresponding second sensing electrodes SC24', SC25', and SC26' in the fifth direction DR5.

[0221] The first sensing electrode SC1' may be connected to the first pattern IST1a', and the third sensing electrode SC3' may be connected to the first pattern IST3a'. The first patterns IST1a' and IST3a' may be connected to different first pads PDE1, respectively.

[0222] The second sensing electrode SC21' may be connected to the second sensing electrode SC26' through the first pattern IST21a'. The second sensing electrode SC22' may be connected to the second sensing electrode SC25' through the first pattern IST22a'. The second sensing electrode SC23' may be connected to the second sensing electrode SC24' through the first pattern IST23a'. The second sensing electrodes SC24', SC25', and SC26' may be connected to different first pads PDE1 through the first patterns IST24a', IST25a', and IST26a', respectively.

[0223] For example, the first patterns IST1a' and IST3a' may be connected to the receiving channel of the touch IC through the first pad PDE1, respectively. For example, the first patterns IST24a', IST25a', and IST26a' may be connected to the transmitting channel of the touch IC through the first pad PDE1, respectively. The touch IC may sequentially send driving signals to the first patterns IST24a', IST25a', and IST26a', and receive sensing signals corresponding to the respective driving signals from the first patterns IST1a' and IST3a'. According to the embodiment, the method of sending and receiving signals may be appropriately changed.

[0224] The fourth direction DR4 and the fifth direction DR5 may be directions orthogonal to each other. A plane formed by the fourth direction DR4 and the fifth direction DR5 may be parallel to a plane formed by the first direction DR1 and the second direction DR2.

[0225] and Fig.25 Compared with the embodiment, Fig.26 The embodiment can reduce the number of sensing wirings IST1 and IST2 connected to the first pad PDE1. Fig.25 In this case, there is no need to send driving signals sequentially, so the sensing time can be reduced.

[0226] Figure 27 to Figure 29 is a diagram for describing a pixel according to a disclosed embodiment.

[0227] Reference Fig. 27 , a display device 10 according to the disclosed embodiment includes a timing controller 11 , a data driver 12 , a scan driver 13 , a light emitting driver 14 and a pixel unit 15 .

[0228] The timing controller 11 may receive a gray value (or gray level) and a control signal for each image frame from an external processor. The timing controller 11 may render gray values ​​to correspond to the specifications of the display device 10. For example, the external processor may provide a red gray value (or red gray level), a green gray value (or green gray level), and a blue gray value (or blue gray level) for each unit point. However, for example, when the pixel unit 15 is a pentile structure, because adjacent unit points share pixels, the pixels do not correspond to each gray value on a one-to-one basis. In this case, the rendering of gray values ​​is necessary. When the pixels correspond to each gray value on a one-to-one basis, the rendering of gray values ​​may be unnecessary. Gray values ​​that are not rendered or rendered may be provided to the data driver 12. In addition, the timing controller 11 may provide control signals suitable for each specification to display frames to the data driver 12, the scan driver 13, the light emitting driver 14, etc.

[0229] The data driver 12 may use the grayscale value and the control signal to generate a data voltage to be supplied to the data lines D1, D2, D3 to Dn. For example, the data driver 12 may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data lines D1 to Dn in units of pixel columns, where n may be an integer greater than zero.

[0230] The scan driver 13 may receive a clock signal, a scan start signal, etc. from the timing controller 11 to generate scan signals to be provided to the scan lines S1 , S2 , S3 to Sm, where m may be an integer greater than zero.

[0231] The scan driver 13 may sequentially supply a scan signal having a pulse of an on level to the scan lines S1, S2, S3 to Sm. The scan driver 13 may include a scan stage constructed in the form of a shift register. The scan driver 13 may generate a scan signal in a manner of sequentially transmitting a scan start signal in the form of a pulse of an on level to a next scan stage under the control of a clock signal.

[0232] The light-emitting driver 14 may receive a clock signal, a light-emitting stop start signal, etc. from the timing controller 11 to generate a light-emitting signal to be provided to the light-emitting lines E1, E2, E3 to Eo. For example, the light-emitting driver 14 may sequentially provide a light-emitting signal having a pulse of a cut-off level to the light-emitting lines E1 to Eo. For example, each light-emitting stage of the light-emitting driver 14 may be constructed in the form of a shift register, and may generate a light-emitting signal in a manner of sequentially transmitting a light-emitting stop start signal in the form of a pulse of a cut-off level to the next light-emitting stage under the control of a clock signal, where o may be an integer greater than zero.

[0233] The pixel unit 15 includes pixels PX. Each pixel PXij can be connected to a corresponding data line, a scan line, and a light-emitting line, where i and j can be natural numbers. The pixel PXij can refer to a pixel whose scan transistor is connected to the i-th scan line and the j-th data line. For example, the scan input terminal of the pixel PXij can be connected to the i-th scan line, and the data input terminal of the pixel PXij can be connected to the j-th data line.

[0234] Reference Fig.28 , the pixel PXij includes transistors T1, T2, T3, T4, T5, T6 and T7, a capacitor Cst and a light emitting diode LD.

[0235] In the following, a circuit constructed by a p-type transistor (p-channel transistor) will be described as an example. However, those skilled in the art will be able to design a circuit constructed by an n-type transistor (n-channel transistor) by distinguishing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design a circuit constructed by a combination of a p-type transistor and an n-type transistor. P-type transistors are generally referred to as transistors in which the amount of conduction current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. N-type transistors are generally referred to as transistors in which the amount of conduction current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. Transistors can be constructed in various suitable forms such as thin film transistors (TFTs), field effect transistors (FETs), and bipolar junction transistors (BJTs).

[0236] The first transistor T1 may have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may be referred to as a driving transistor.

[0237] The second transistor T2 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the data line Dj, and a second electrode connected to the second node N2. The second transistor T2 may be referred to as a scan transistor.

[0238] The third transistor T3 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be referred to as a diode-connected transistor.

[0239] The fourth transistor T4 may have a gate electrode connected to the i-1th scan line S(i-1), a first electrode connected to the first node N1, and a second electrode connected to the initialization line INTL. In an embodiment, the gate electrode of the fourth transistor T4 may be connected to another scan line. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0240] The fifth transistor T5 may have a gate electrode connected to the i-th emission line Ei, a first electrode connected to the first power line ELVDDL, and a second electrode connected to the second node N2. The fifth transistor T5 may be referred to as a light emitting transistor. In an embodiment, the gate electrode of the fifth transistor T5 may be connected to another emission line.

[0241] The sixth transistor T6 may have a gate electrode connected to the i-th light emitting line Ei, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light emitting diode LD. The sixth transistor T6 may be referred to as a light emitting transistor. In an embodiment, the gate electrode of the sixth transistor T6 may be connected to another light emitting line.

[0242] The seventh transistor T7 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light emitting diode LD. The seventh transistor T7 may be referred to as an anode initialization transistor. In an embodiment, the gate electrode of the seventh transistor T7 may be connected to another scan line.

[0243] A first electrode of the capacitor Cst may be connected to the first power line ELVDDL, and a second electrode may be connected to the first node N1.

[0244] An anode of the light emitting diode LD may be connected to the second electrode of the sixth transistor T6, and a cathode may be connected to the second power line ELVSSL. The light emitting diode LD may be constructed of an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0245] The first power line ELVDDL may be supplied with a first power voltage, the second power line ELVSSL may be supplied with a second power voltage, and the initialization line INTL may be supplied with an initialization voltage. For example, the first power voltage may be greater than the second power voltage. For example, the initialization voltage may be equal to or greater than the second power voltage.

[0246] Will refer to Fig.29 A method of driving a pixel according to a disclosed embodiment is described.

[0247] First, a data voltage DATA(i-1)j for an i-1th pixel is applied to the data line Dj, and a scan signal of an on level (low level) is applied to the i-1th scan line S(i-1).

[0248] In one or more embodiments, because the scan signal of the off level (high level) is applied to the i-th scan line Si, the second transistor T2 is turned off and prevents or substantially prevents the data voltage DATA(i-1)j from being introduced into the pixel PXij.

[0249] In one or more embodiments, because the fourth transistor T4 is turned on, the first node N1 is connected to the initialization line INTL, and the voltage of the first node N1 is initialized. Because the light emitting signal of the cut-off level is applied to the light emitting line Ei, the transistors T5 and T6 are turned off, and unnecessary light emitting diode LD is prevented or substantially prevented from emitting light according to the initialization voltage application process.

[0250] Next, the data voltage DATAij for the i-th pixel PXij is applied to the data line Dj, and the scan signal of the on-level is applied to the i-th scan line Si. Therefore, the transistors T2, T7 and T3 are turned on, and the data line Dj and the first node N1 are electrically connected to each other. Therefore, the compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DATAij is applied to the second electrode (i.e., the first node N1) of the capacitor Cst, and the capacitor Cst maintains a voltage corresponding to the difference between the first power voltage and the compensation voltage. Such a period may be referred to as a threshold voltage compensation period.

[0251] In one or more embodiments, because the seventh transistor T7 is turned on, the anode of the light emitting diode LD and the initialization line INTL are connected to each other, and the light emitting diode LD is initialized to a charge amount corresponding to a voltage difference between the initialization voltage and the second power voltage.

[0252] Thereafter, as the on-level emission signal is applied to the emission line Ei, the transistors T5 and T6 may be turned on. Thus, a driving current path is formed as a path of the first power line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light emitting diode LD and the second power line ELVSSL.

[0253] The amount of driving current flowing to the first electrode and the second electrode of the first transistor T1 is adjusted according to the voltage held in the capacitor Cst. The light emitting diode LD emits light at a brightness corresponding to the amount of driving current. The light emitting diode LD emits light until a light emission signal of a cutoff level is applied to the light emission line Ei.

[0254] The drawings referred to so far and the detailed description of the disclosure described herein are only examples of the disclosure, are only used to describe the disclosure, and are not intended to limit the meaning and scope of the disclosure described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments derived from the drawings and detailed description are feasible. Therefore, the true scope of the disclosure should be determined by the technical spirit of the attached claims and their equivalents.

Claims

1. A display device, comprising: a substrate including a display area, a non-display area surrounding a periphery of the display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; A pixel located in the display area; A packaging film, located on the pixel; A sensing electrode, located on the packaging film; a pad located in said second additional region; a sensing wiring connecting the sensing electrode and the pad; A first sensing insulating film, located on the packaging film; as well as a second sensing insulating film, located on the first sensing insulating film, the sensing electrode and the sensing wiring, wherein the substrate comprises a curved first side in the first additional region and the first additional region decreases in width from the first boundary to the second boundary, and A boundary of the first sensing insulating film is closer to the first side than a boundary of the second sensing insulating film.

2. The display device according to claim 1, wherein: The boundary of the first sensing insulating film is not covered by the second sensing insulating film.

3. The display device according to claim 1, wherein: The substrate includes a first curved area extending from the first side to overlap the non-display area.

4. The display device according to claim 3, wherein: The boundary of the first sensing insulating film and the boundary of the second sensing insulating film are located in the first bending region.

5. The display device according to claim 4, wherein: The second additional region comprises a second curved region, and The first bending region and the second bending region do not overlap.

6. The display device according to claim 1, wherein: The encapsulation film comprises an organic film, The display device further includes a dam located at a boundary of the organic film, and The boundary of the second sensing insulating film is closer to the first side than the dam.

7. The display device according to claim 1, wherein: The encapsulation film comprises an organic film, The display device further includes a dam located at a boundary of the organic film, and The boundary of the second sensing insulating film is farther away from the first side than the dam.

8. The display device according to claim 7, wherein: The boundary of the second sensing insulating film is closer to the first side than the sensing wiring.

9. The display device according to claim 1, wherein: The first sensing insulating film is located between the packaging film and the sensing wiring.

10. The display device according to claim 9, wherein: The sensing electrode is located on the first sensing insulating film, The display device further includes a bridge electrode located below the first sensing insulating film, and The sensing electrode is connected to the bridge electrode through a contact hole of the first sensing insulating film.

11. The display device according to claim 9, wherein: The sensing electrode is located below the first sensing insulating film. The display device further includes a bridge electrode located on the first sensing insulating film, and The bridge electrode is connected to the sensing electrode through a contact hole of the first sensing insulating film.

12. The display device according to claim 1, wherein: The first sensing insulating film is located between the sensing wiring and the second sensing insulating film.

13. The display device according to claim 12, wherein: The sensing electrode is located on the first sensing insulating film, The display device further includes a bridge electrode located below the first sensing insulating film, and The sensing electrode is connected to the bridge electrode through a contact hole of the first sensing insulating film.

14. The display device according to claim 12, wherein: The sensing electrode is located below the first sensing insulating film. The display device further includes a bridge electrode located on the first sensing insulating film, and The bridge electrode is connected to the sensing electrode through a contact hole of the first sensing insulating film.

15. A display device, comprising: a substrate including a display area, a non-display area surrounding a periphery of the display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; A pixel located in the display area; A packaging film, located on the pixel; A sensing electrode, located on the packaging film; a pad located in said second additional region; a sensing wiring connecting the sensing electrode and the pad; A first sensing insulating film, located on the packaging film; as well as a second sensing insulating film, located on the first sensing insulating film, the sensing electrode and the sensing wiring, wherein the substrate comprises a curved first side in the first additional region and the first additional region decreases in width from the first boundary to the second boundary, and A boundary of the second sensing insulating film is spaced apart from the first side by 200 μm or more.

16. The display device according to claim 15, wherein: The first side of the first additional area and the non-display area jointly include a first bending area, The second additional region comprises a second curved region, and The first bending region and the second bending region do not overlap.

17. The display device according to claim 15, wherein: The encapsulation film comprises an organic film, The display device further includes a dam located at a boundary of the organic film, and The boundary of the second sensing insulating film is closer to the first side than the dam.

18. The display device according to claim 15, wherein: The encapsulation film comprises an organic film, The display device further includes a dam located at a boundary of the organic film, and The boundary of the second sensing insulating film is farther away from the first side than the dam.

19. The display device according to claim 18, wherein: The boundary of the second sensing insulating film is closer to the first side than the sensing wiring.

20. A display device, comprising: a substrate including a display area, a non-display area surrounding a periphery of the display area, a first additional area connected to the non-display area at a first boundary, and a second additional area connected to the first additional area at a second boundary; A pixel located in the display area; A packaging film, located on the pixel; A sensing electrode, located on the packaging film; a pad located in said second additional region; a sensing wiring connecting the sensing electrode and the pad; as well as a sensing insulating film, located on the sensing electrode and the sensing wiring, wherein the substrate comprises a curved first side in the first additional region and the first additional region decreases in width from the first boundary to the second boundary, The substrate includes a first curved area extending from the first side to overlap the non-display area, and In the first bending region, a boundary of the sensing insulating film is closer to a first point of the first side intersecting the first boundary than a second point of the first side intersecting the second boundary.

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