Display device and method of manufacturing the same

Abstract

The present application provides a display device and a method for manufacturing the display device. The display device includes a display panel and a first module, the display panel includes a first area with a first transmittance and a second area with a second transmittance higher than the first transmittance, the first module is below the second area, wherein the display panel includes a substrate layer, a circuit layer, a first pixel electrode, a second pixel electrode, a first stacked structure, and a second stacked structure, wherein the circuit layer is on the substrate layer, the first pixel electrode is electrically connected to the circuit layer and in the first area, the second pixel electrode is electrically connected to the circuit layer and in the second area, the first stacked structure is on the circuit layer and adjacent to the first pixel electrode, and the second stacked structure is on the circuit layer, adjacent to the second pixel electrode, and different from the first stacked structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0063794, filed on May 30, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Herein, aspects of some exemplary embodiments of the present disclosure relate to a display device and a method for manufacturing the display device. Background Art

[0004] The display device may include various electronic components, such as a display panel for displaying an image, an input sensing member for sensing an external input, and an electronic module. The electronic components may be electrically connected to each other via signal lines arranged differently. The display panel may include a light-emitting element for generating an image. The input sensing member may include a sensing electrode for sensing an external input. The electronic module may include a camera, an infrared sensor, and / or a proximity sensor.

[0005] The electronic module may be located below the display panel. The hole may be provided in a portion of the display panel that overlaps the electronic module. Some components of the display panel may be removed using a laser to form the hole. During the laser process, particles may be generated and / or the shape of the display panel may be deformed by heating.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some exemplary embodiments of the present disclosure may provide a display device capable of reducing or minimizing a defect rate and a method for manufacturing the display device.

[0008] According to some exemplary embodiments of the inventive concept, a display device may include a display panel and a first module, the display panel including a first region having a first transmittance and a second region having a second transmittance higher than the first transmittance, and the first module is below the second region. The display panel may include a substrate layer, a circuit layer, a first pixel electrode, a second pixel electrode, a first stacked structure, and a second stacked structure, wherein the circuit layer is on the substrate layer, the first pixel electrode is electrically connected to the circuit layer and is disposed in the first region, the second pixel electrode is electrically connected to the circuit layer and is disposed in the second region, the first stacked structure is disposed on the circuit layer and adjacent to the first pixel electrode, and the second stacked structure is disposed on the circuit layer, adjacent to the second pixel electrode, and different from the first stacked structure.

[0009] According to some exemplary embodiments, the first stacked structure may include a first intermediate layer disposed on the circuit layer and exposing at least a portion of the first pixel electrode and a first spacer disposed on the first intermediate layer. When viewed in a plan view, an area of ​​the first spacer may be smaller than an area of ​​the first intermediate layer.

[0010] According to some example embodiments, the second stack structure may include a second intermediate layer disposed on the circuit layer and covering the second pixel electrode, and a second spacer disposed on the second intermediate layer.

[0011] According to some example embodiments, when viewed in a plan view, an area of ​​the second intermediate layer may be equal to an area of ​​the second spacer.

[0012] According to some example embodiments, the first intermediate layer and the second intermediate layer may include the same material and may be disposed on the same layer.

[0013] According to some example embodiments, a first maximum thickness of the first stack structure may be greater than a second maximum thickness of the second stack structure.

[0014] According to some example embodiments, the second stack structure may include a second intermediate layer disposed on the same layer as the first intermediate layer.

[0015] According to some exemplary embodiments, the display panel may further include a third region having a third transmittance higher than the second transmittance. In this case, the display device may further include a second module below the third region. The display panel may further include a third pixel electrode electrically connected to the circuit layer and disposed in the third region.

[0016] According to some example embodiments, the first intermediate layer and the first spacer may not be disposed in the third region.

[0017] According to some example embodiments, the first stack structure may include m layers, the second stack structure may include n layers, and m may be greater than n.

[0018] According to some exemplary embodiments, the display panel may further include a common electrode having the first hole and the second hole.

[0019] According to some exemplary embodiments, the first hole and the second hole may be disposed in the second region.

[0020] According to some example embodiments, the second region may include a first subregion providing light and a second subregion not providing light. The first hole may be disposed in the first subregion, and the second hole may be disposed in the second subregion.

[0021] According to some example embodiments, the second pixel electrode may be disposed in the second sub-region.

[0022] According to some exemplary embodiments, the display panel may further include a fourth pixel electrode disposed in the first sub-region and a third stacked structure disposed on the circuit layer and adjacent to the fourth pixel electrode. The third stacked structure may have the same structure as the first stacked structure.

[0023] According to some exemplary embodiments, the third stacked structure may include an intermediate layer exposing at least a portion of the fourth pixel electrode and a spacer disposed on the intermediate layer. The first hole may be defined on the spacer.

[0024] According to some exemplary embodiments of the inventive concept, a method for manufacturing a display device may include: forming a base layer; forming a circuit layer on the base layer; forming a first pixel electrode and a second pixel electrode on the circuit layer; forming a first stack structure in a region adjacent to the first pixel electrode; forming a second stack structure different from the first stack structure in a region adjacent to the second pixel electrode; forming a common electrode covering the first stack structure and the second stack structure; and removing a portion of the common electrode disposed on the second stack structure by using a stamping process.

[0025] According to some exemplary embodiments, the method may further include: forming a third pixel electrode on the circuit layer; forming a third stacked structure having the same structure as the first stacked structure in a region adjacent to the third pixel electrode; and removing a portion of the common electrode disposed on the third stacked structure by using a stamping process. The portion of the common electrode disposed on the second stacked structure and the portion disposed on the third stacked structure may be removed at the same time.

[0026] According to some example embodiments, the number of layers constituting the second stack structure may be different from the number of layers constituting the first stack structure.

[0027] According to some example embodiments, shapes of layers constituting the first stack structure may be different from shapes of layers constituting the second stack structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0029] Figure 1A is a perspective view showing a display device according to some exemplary embodiments of the inventive concept;

[0030] Figure 1B is an exploded perspective view showing a display device according to some exemplary embodiments of the inventive concept;

[0031] FIG. 2A to FIG. 2Dis a cross-sectional view showing a display device according to some exemplary embodiments of the inventive concept;

[0032] Figure 3 is a cross-sectional view showing a display panel according to some exemplary embodiments of the inventive concept;

[0033] Figure 4 is a plan view showing a display panel according to some exemplary embodiments of the inventive concept;

[0034] Figure 5 yes Figure 4 An enlarged plan view of area AA′;

[0035] Figure 6 yes Figure 4 An enlarged plan view of region BB′;

[0036] Figure 7 yes Figure 4 An enlarged plan view of region CC′;

[0037] Figure 8 is an enlarged plan view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0038] Fig. 9 is a cross-sectional view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0039] Fig.10 is a cross-sectional view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0040] Fig.11 is a cross-sectional view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0041] Fig.12 is a plan view showing some components of a display panel according to some exemplary embodiments of the inventive concept;

[0042] Fig.13 is a cross-sectional view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0043] Fig.14 is a cross-sectional view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0044] Fig.15 is a cross-sectional view showing a portion of a display panel according to some exemplary embodiments of the inventive concept;

[0045] Fig.16is a perspective view showing a punching unit according to some exemplary embodiments of the inventive concept;

[0046] Fig.17A and Fig. 17B are cross-sectional views illustrating some processes of a method for manufacturing a display device according to some exemplary embodiments of the inventive concept;

[0047] Fig.18A and Fig.18B are cross-sectional views illustrating some processes of a method for manufacturing a display device according to some exemplary embodiments of the inventive concept; and

[0048] Fig.19A and Fig.19B are cross-sectional views illustrating some processes of a method for manufacturing a display device according to some exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0049] Aspects of some exemplary embodiments of the inventive concept will now be described in more detail below with reference to the accompanying drawings, in which various embodiments are shown. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. More specifically, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. The same reference numerals represent the same elements throughout.

[0050] It should be understood that when an element such as a layer, region, or substrate is referred to as being on another element, it can be directly on the other element, or there may be intervening elements. In contrast, the term "directly" means that there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the content clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to include plural meanings, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that the terms "comprises" and / or "comprising" or "includes" and / or "including" when used in this specification indicate the presence of the features, regions, integrated, steps, operations, elements and / or components described, but do not exclude the presence or addition of one or more other features, regions, integrated, steps, operations, elements, components and / or combinations thereof.

[0052] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the accompanying drawings. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the elements described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the exemplary term "below" may cover both the above and below orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0053] It should be understood that although the terms first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present invention, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0054] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements being made and errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] Aspects of some exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are ideal exemplary schematic views. In the accompanying drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions illustrated herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0056] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0057] Figure 1A is a perspective view illustrating a display device according to some exemplary embodiments of the inventive concept. Figure 1B is an exploded perspective view illustrating a display device according to some exemplary embodiments of the inventive concept.

[0058] refer to Figure 1A and Figure 1B , the display device EA can be enabled by an electrical signal. The display device EA can be implemented as various embodiments. For example, the display device EA can be used in large electronic devices (e.g., televisions, monitors, and external billboards) and small and medium-sized electronic devices (e.g., personal computers, notebook computers, personal digital assistants (PDAs), car navigation units, game consoles, portable electronic devices, and cameras). However, these are only provided as examples of inventive concepts, and without departing from the spirit and scope of inventive concepts, the display device EA according to the inventive concept can also be applied to other electronic devices. According to some exemplary embodiments, a smart phone is shown as an example of the display device EA.

[0059] The display device EA may display an image IM on a display surface FS parallel to the first direction DR1 and the second direction DR2 in the third direction DR3. The image IM may include a dynamic image and a static image. Figure 1A , the time display frame and the icon are illustrated as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display apparatus EA and may correspond to the front surface of the window panel WP.

[0060] According to some exemplary embodiments, the front surface (or top surface) and the rear surface (or bottom surface) of each component may be defined based on the direction (e.g., the third direction DR3) in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. However, the directions referred to by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and may be changed to other directions.

[0061] According to some exemplary embodiments, the display device EA may sense a user input applied from the outside. The user input may include at least one of various external inputs such as a part of the user's body (e.g., a finger), light, heat, and pressure. In some embodiments, the display device EA may sense a user input applied to a side surface or a rear surface of the display device EA according to the structure of the display device EA. However, the inventive concept is not limited to a specific embodiment.

[0062] The display apparatus EA may include a window panel WP, an anti-reflection panel RPP, a display module DM, first and second modules SS1 and SS2, and a housing HU. According to some exemplary embodiments, the window panel WP and the housing HU may be coupled to each other to form an exterior appearance of the display apparatus EA.

[0063] The window panel WP may include an optically transparent material or a transparent insulating material. For example, the window panel WP may include glass or plastic. The window panel WP may have a single-layer structure or a multi-layer structure. For example, the window panel WP may include a plurality of plastic films coupled to each other by an adhesive, or may include a glass substrate and a plastic film coupled to each other by an adhesive.

[0064] As described above, the front surface FS of the window panel WP may define the front surface of the display apparatus EA. The front surface FS may include the transmissive area TA and the bezel area BZA.

[0065] The transmission area TA may be optically transparent. For example, the transmission area TA may have a visible light transmittance of about 90% or more. The light transmittance of the frame area BZA may be less than the light transmittance of the transmission area TA. The frame area BZA may have a predetermined color. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and may surround the transmission area TA in a plan view. According to some exemplary embodiments, the frame area BZA may be omitted in the window panel WP.

[0066] The anti-reflection panel RPP may be located below the window panel WP. The anti-reflection panel RPP may reduce reflectivity of external light incident through the window panel WP. In certain embodiments, the anti-reflection panel RPP may be omitted or may be embedded in the display module DM.

[0067] The display module DM may display an image IM and may sense an external input. The display module DM may include a front surface IS having an active area AA and a peripheral area NAA. The active area AA may be an area enabled by an electrical signal.

[0068] According to some exemplary embodiments, the active area AA may be an area for displaying an image IM, and may also be an area for sensing an external input. The transmissive area TA may overlap at least with the active area AA. For example, the transmissive area TA may overlap with all or at least a portion of the active area AA. Therefore, the user may view the image IM through the transmissive area TA and / or may provide an external input through the transmissive area TA. However, embodiments of the inventive concept are not limited thereto. According to some exemplary embodiments, in the active area AA, an area for displaying an image IM and an area for sensing an external input may be separated from each other.

[0069] The peripheral area NAA may be covered by the bezel area BZA. The peripheral area NAA may be adjacent to the active area AA. When viewed in a plan view, the peripheral area NAA may surround the active area AA. A driving circuit and / or a driving line for driving the active area AA may be provided in the peripheral area NAA.

[0070] According to some exemplary embodiments, the display module DM may be assembled in a flat state where the active area AA and the peripheral area NAA face the window panel WP. However, embodiments of the inventive concept are not limited thereto. According to some exemplary embodiments, a portion of the peripheral area NAA of the display module DM may be bent. In this case, a portion of the peripheral area NAA may face the rear surface of the display device EA, and thus a bezel area BZA in the front surface FS of the display device EA may be reduced. According to some exemplary embodiments, the display module DM may be assembled in a state where a portion of the active area AA is also bent.

[0071] The display module DM may include a display panel DP, an input sensing layer ISL, and a driving circuit DC.

[0072] The display panel DP may be a component that basically generates an image IM. The image IM generated from the display panel DP may be visible to a user through the transmissive area TA.

[0073] The input sensing layer ISL may sense an external input applied from the outside. As described above, the input sensing layer ISL may sense an external input provided to the window panel WP.

[0074] The driving circuit DC may be electrically connected to the display panel DP and the input sensing layer ISL. The driving circuit DC may include a main circuit board MB, a first circuit board CF1, and a second circuit board CF2.

[0075] The first circuit board CF1 and the second circuit board CF2 may be flexible circuit films. The first circuit board CF1 may provide a signal to the display panel DP, and the second circuit board CF2 may provide an electrical signal for driving the input sensing layer ISL. Alternatively, according to some exemplary embodiments, the first circuit board CF1 and the second circuit board CF2 may be replaced with a single board. According to some exemplary embodiments, the first circuit board CF1 and the second circuit board CF2 may be omitted, and the main circuit board MB may be directly connected to the display panel DP and the input sensing layer ISL.

[0076] The main circuit board MB may include various driving circuits for driving the display module DM and / or connectors for supplying power. The first circuit board CF1 and the second circuit board CF2 may be connected to the main circuit board MB. According to some exemplary embodiments of the inventive concept, the display module DM may be easily controlled by one main circuit board MB. However, the embodiments of the inventive concept are not limited thereto. In other embodiments, the display panel DP and the input sensing layer ISL of the display module DM may be connected to different main circuit boards, or one of the first circuit board CF1 and the second circuit board CF2 may not be connected to the main circuit board MB.

[0077] The first module SS1 and the second module SS2 may be located below the display module DM. The first module SS1 and the second module SS2 may be located below the display panel DP. When viewed in a plan view, the first module SS1 and the second module SS2 may overlap with the active area AA. Therefore, a space of the bezel area BZA in which the first module SS1 and the second module SS2 may be located may be omitted. As a result, an increase in the area (or size) of the bezel area BZA may be prevented.

[0078] The first module SS1 and the second module SS2 may receive external input transmitted through the transmission area TA and / or may provide output signals through the transmission area TA. Each of the first module SS1 and the second module SS2 may include, but is not limited to, an infrared sensor, a proximity sensor, a camera, a speaker, a light sensor, or a thermal sensor.

[0079] The housing HU may be coupled to the window panel WP. The housing HU and the window panel WP may be coupled to each other to provide a space for receiving the display module DM and the first and second modules SS1 and SS2.

[0080] The housing HU may be formed of a material having relatively high rigidity. For example, the housing HU may include a plurality of frames and / or a plate formed of glass, plastic, metal, or a combination thereof. The housing HU may stably protect the components of the display device EA received in the space from external impacts.

[0081] FIG. 2A to FIG. 2D is a cross-sectional view illustrating a display device according to some embodiments of the inventive concept.

[0082] FIG. 2A to FIG. 2D A cross section defined by the first direction DR1 and the third direction DR3 is shown. FIG. 2A to FIG. 2D The display device EA is simply illustrated to describe the stacking relationship of the functional components of the display device EA.

[0083] The display device EA according to some exemplary embodiments of the inventive concept may include a display panel, an input sensing sensor, an anti-reflector, and a window. At least some of the display panel, the input sensing sensor, the anti-reflector, and the window may be integrally formed with each other through a continuous process, or may be coupled to each other through an adhesive member. FIG. 2A to FIG. 2D In the embodiment, an optically transparent adhesive member OCA is shown as an example of an adhesive member. The adhesive member described below may include a general adhesive or glue. In some embodiments, the anti-reflector and the window may be replaced with other components or may be omitted.

[0084] exist FIG. 2A to FIG. 2DIn the embodiment, at least one of the input sensing sensor, the anti-reflector, and the window that is integrally formed with another component through a continuous process is represented as a "layer". At least one of the input sensing sensor, the anti-reflector, and the window that is connected to another component through a bonding member is represented as a "panel". The "panel" may include a base layer that provides a base surface. For example, the base layer may be a synthetic resin film, a composite material film, or a glass substrate. The "layer" may not include a base layer. In other words, the component represented as a "layer" is located on a base surface provided by another component.

[0085] Hereinafter, the input sensing sensor, the anti-reflector and the window may be referred to as an input sensing panel ISP, an anti-reflection panel RPP and a window panel WP, or an input sensing layer ISL, an anti-reflection layer RPL and a window layer WL, depending on whether a substrate layer exists.

[0086] like Figure 2A As shown in , the display device EA may include a display panel DP, an input sensing layer ISL, an anti-reflection panel RPP and a window panel WP. The input sensing layer ISL may be directly located on the display panel DP. In this specification, it is to be understood that when component "B" is directly located on component "A", no additional adhesive layer / adhesive member is positioned between component "A" and component "B". In other words, the term "directly" means that there is no intermediate component. After component "A" is formed, component "B" is formed on the base surface provided by component "A" through a continuous process.

[0087] The display panel DP and the input sensing layer ISL directly on the display panel DP may be defined as a display module DM. An optically transparent adhesive member OCA may be located between the display module DM and the anti-reflection panel RPP and between the anti-reflection panel RPP and the window panel WP, respectively.

[0088] The display panel DP may generate an image, and the input sensing layer ISL may obtain coordinate information of an external input (e.g., a touch event). The display module DM according to some exemplary embodiments of the inventive concept may further include a protective member located on the bottom surface of the display panel DP. The protective member and the display panel DP may be coupled to each other by an adhesive member. FIG. 2B to FIG. 2D Each of the display devices EA may also further include a protective member.

[0089] The display panel DP according to some exemplary embodiments of the inventive concept may be, but is not limited to, a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods. Hereinafter, the display panel DP as an organic light-emitting display panel will be described as an example.

[0090] The anti-reflection panel RPP may reduce the reflectivity of external light incident through the window panel WP. The anti-reflection panel RPP according to some exemplary embodiments of the inventive concept may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type and may include an elongated synthetic resin film. The anti-reflection panel RPP may also include a protective film. The retarder and / or the polarizer may be defined as a base layer of the anti-reflection panel RPP, or the protective film may be defined as a base layer of the anti-reflection panel RPP.

[0091] The anti-reflection panel RPP according to some exemplary embodiments of the inventive concept may include a color filter. The color filter may be arranged in a set or predetermined form. The arrangement of the color filter may be determined in consideration of the luminous color of the pixels included in the display panel DP. The anti-reflection panel RPP may also include a black matrix adjacent to the color filter.

[0092] The anti-reflection panel RPP according to some exemplary embodiments of the inventive concept may include a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. The first reflected light and the second reflected light respectively reflected from the first reflective layer and the second reflective layer may destructively interfere with each other, and thus the reflectivity of the external light may be reduced.

[0093] The window panel WP according to some exemplary embodiments of the inventive concept may include a base layer WP-BS and a light blocking pattern WP-BZ. The base layer WP-BS may include a glass substrate and / or a synthetic resin film. The base layer WP-BS is not limited to a single layer. The base layer WP-BS may include two or more films coupled to each other by an adhesive member.

[0094] The light blocking pattern WP-BZ may partially overlap with the base layer WP-BS. The light blocking pattern WP-BZ may be located on the rear surface of the base layer WP-BS and may substantially define the bezel area BZA of the display device EA. The area in which the light blocking pattern WP-BZ is not located may define the transmissive area TA of the display device EA. In the window panel WP, the area in which the light blocking pattern WP-BZ is located may be defined as the light blocking area of ​​the window panel WP, and the area in which the light blocking pattern WP-BZ is not located may be defined as the transmissive area of ​​the window panel WP.

[0095] The light blocking pattern WP-BZ may have a multi-layer structure. The multi-layer structure may include a coloring layer and a light blocking layer having a black color. The coloring layer and the light blocking layer having a black color may be formed by a deposition process, a printing process, and / or a coating process. According to some exemplary embodiments, the window panel WP may further include a functional coating layer located on the front surface of the base layer WP-BS. The functional coating layer may include at least one of an anti-fingerprint layer, an anti-reflection layer, and a hard coating layer. FIG. 2B to FIG. 2D , for the purpose of simplicity and convenience of explanation, the window panel WP and the window layer WL are simply shown without distinguishing the base layer WP-BS and the light blocking pattern WP-BZ.

[0096] like Figure 2B and Figure 2C As shown in , the display device EA may include a display panel DP, an input sensing panel ISP, an anti-reflection panel RPP, and a window panel WP. The stacking order of the input sensing panel ISP and the anti-reflection panel RPP may be changed.

[0097] like Figure 2D As shown in , the display device EA may include a display panel DP, an input sensing layer ISL, an anti-reflection layer RPL and a window layer WL. Figure 2A Compared with the display device EA, Figure 2D The optically transparent adhesive member OCA is omitted in the display device EA. In addition, the input sensing layer ISL, the anti-reflection layer RPL and the window layer WL can be integrally formed on the base surface of the display panel DP through a continuous process. The stacking order of the input sensing layer ISL and the anti-reflection layer RPL can be changed.

[0098] Figure 3 are cross-sectional views illustrating display panels according to some exemplary embodiments of the inventive concept.

[0099] refer to Figure 3 , the display panel DP may include a base layer BL, a circuit layer ML, a light emitting element layer EL, an encapsulation layer CL, and a coupling member SLM.

[0100] Each of the base layer BL and the encapsulation layer CL may be a plastic substrate, a glass substrate, an insulating film, or a stack structure including a plurality of insulating layers.

[0101] The circuit layer ML may be located on the base layer BL. The circuit layer ML may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit layer ML may constitute a signal line and / or a control circuit of a pixel.

[0102] The light emitting element layer EL may be located on the circuit layer ML. The light emitting element layer EL may be a layer for generating light. For example, the light emitting element layer EL may include an organic light emitting diode. However, the embodiments of the inventive concept are not limited thereto. In some embodiments, the light emitting element layer EL may include an inorganic light emitting diode or an organic-inorganic light emitting diode.

[0103] The encapsulation layer CL may be located above the light emitting element layer EL. A set or predetermined space PIL may be defined between the encapsulation layer CL and the light emitting element layer EL. The space PIL may be filled with an inert gas.

[0104] The coupling member SLM may be located between the base layer BL and the encapsulation layer CL. The coupling member SLM may couple the base layer BL and the encapsulation layer CL to each other. The coupling member SLM may include an organic material such as a photocurable resin or a photoresist resin, or may include an inorganic material such as a sealant. However, embodiments of the inventive concept are not limited thereto.

[0105] Figure 4 are plan views illustrating display panels according to some exemplary embodiments of the inventive concept.

[0106] refer to Figure 4 , the display panel DP may include a base layer BL, a plurality of pixels PX, a plurality of signal lines GL, DL, PL and ECL, and a plurality of display pads PDD.

[0107] Figure 4 The active area AA and the peripheral area NAA of the display panel DP are shown. The active area AA of the display panel DP may be an area where an image is displayed, and the peripheral area NAA may be an area where a driving circuit and / or a driving line are located. A plurality of pixels PX may be located in the active area AA.

[0108] A first area DA1, a second area DA2, and a third area DA3 may be defined in the display panel DP. The first area DA1, the second area DA2, and the third area DA3 may constitute an active area AA of the display panel DP. The first area DA1 may surround the second area DA2 and the third area DA3.

[0109] The second area DA2 may be aligned with the first module SS1 (see FIG. Figure 1B ) and the third area DA3 may overlap with the second module SS2 (see Figure 1B )overlapping.

[0110] The resolution of the first area DA1 may be different from the resolutions of the second area DA2 and the third area DA3. For example, the resolution of the second area DA2 may be lower than the resolution of the first area DA1. The resolution of the third area DA3 may be lower than the resolution of the first area DA1. In addition, the resolution of the third area DA3 may be lower than the resolution of the second area DA2.

[0111] The transmittance of the second and third areas DA2 and DA3 may be higher than that of the first area DA1. Therefore, the first and second modules SS1 and SS2 located under the second and third areas DA2 and DA3 may easily transmit / receive signals.

[0112] A plurality of signal lines GL, DL, PL, and ECL may be connected to the pixels PX and may transmit electrical signals to the pixels PX. Figure 4 2 shows, as an example, a scan line GL, a data line DL, a power line PL, and an emission control line ECL among the signal lines GL, DL, PL, and ECL included in the display panel DP. However, the embodiments of the inventive concept are not limited thereto. In some embodiments, the signal lines GL, DL, PL, and ECL may further include an initialization voltage line.

[0113] The power pattern VDD may be located in the peripheral area NAA. According to some exemplary embodiments, the power pattern VDD may be connected to the plurality of power lines PL. Since the display panel DP includes the power pattern VDD, the same first power signal may be provided to the plurality of pixels PX.

[0114] The display pad PDD may include a first pad D1 and a second pad D2. The first pad D1 may be provided in plurality, and the plurality of first pads D1 may be respectively connected to the data line DL. The second pad D2 may be connected to the power pattern VDD and thus may be electrically connected to the power line PL. The display panel DP may provide an externally provided electrical signal to the pixel PX through the display pad PDD. According to some exemplary embodiments, the display pad PDD may further include a pad for receiving other electrical signals in addition to the first pad D1 and the second pad D2. However, the inventive concept is not limited to one embodiment.

[0115] Figure 5 yes Figure 4 An enlarged plan view of area AA′.

[0116] refer to Figure 4 and Figure 5 , the first area DA1 may be divided into first sub-areas AR1. At least one pixel may be located in each of the first sub-areas AR1. The first sub-areas AR1 may be arranged in the first direction DR1 and the second direction DR2. The pixels located in the first sub-areas AR1 may provide light.

[0117] Figure 6 yes Figure 4 An enlarged plan view of region BB′.

[0118] refer to Figure 4 and Figure 6 , the second area DA2 may include a first sub-area AR1′ and a second sub-area AR2. The first sub-area AR1′ may be substantially similar to Figure 5 One of the multiple first sub-areas AR1.

[0119] At least one pixel may be located in the first sub-region AR1′, and at least one incomplete pixel may be located in the second sub-region AR2. The incomplete pixel may be a pixel in which a component corresponding to one or some of the multiple components of the pixel is omitted. The pixel located in the first sub-region AR1′ may provide light. The incomplete pixel located in the second sub-region AR2 may not provide light. In other words, the second sub-region AR2 may be an area that does not provide light. The second sub-region AR2 may be an area that does not include pixels that provide light. The second sub-region AR2 may be referred to as a low-reflection area, a transmission area, a non-display area, a non-luminous area, or a semi-transmission area. Because the second area DA2 includes the second sub-region AR2 that cannot provide an image, the resolution of the second area DA2 may be lower than the resolution of the first area DA1.

[0120] The first sub-region AR1′ may be provided in plural, and the second sub-region AR2 may be provided in plural. The first sub-region AR1′ and the second sub-region AR2 may be arranged according to a rule (eg, a set or predetermined rule). Figure 6 , the first sub-regions AR1′ and the second sub-regions AR2 may be alternately arranged in a first row in the first direction DR1. The first sub-regions AR1′ may be arranged in a second row in the first direction DR1. The first row and the second row may be alternately arranged in the second direction DR2.

[0121] Figure 6 The arrangement of the first sub-region AR1 ′ and the second sub-region AR2 in the second area DA2 is shown as an example. However, embodiments of the inventive concept are not limited thereto. The arrangement of the first sub-region AR1 ′ and the second sub-region AR2 in the second area DA2 may be variously modified.

[0122] Figure 7 yes Figure 4 An enlarged plan view of area CC′.

[0123] refer to Figure 4 and Figure 7 , the third area DA3 may be divided into a plurality of third sub-areas AR3. Incomplete pixels may be located in each of the plurality of third sub-areas AR3. The third area DA3 may not include the above reference Figure 6Therefore, the resolution of the third area DA3 may be lower than that of the second area DA2. In addition, the transmittance of the third area DA3 may be higher than that of the second area DA2.

[0124] The second area DA2 (see Figure 6 ) and the third area DA3 may have a larger area than the first area DA1 (see Figure 5 ) has a higher transmittance. Therefore, the first module SS1 and the second module SS2 (see Figure 1B ) operational reliability.

[0125] According to some exemplary embodiments, all of the second area DA2 and the third area DA3 may consist of only the third sub-area AR3. According to some exemplary embodiments, each of the second area DA2 and the third area DA3 may include both the first sub-area AR1' and the second sub-area AR2.

[0126] Figure 8 is an enlarged plan view showing a portion of a display panel according to some exemplary embodiments of the inventive concept. For example, Figure 8 It can be shown that the Figure 5 The first sub-area AR1 described in Figure 6 A plan view of a pixel area in the first sub-area AR1′ described in FIG.

[0127] refer to Figure 8 , each of the first sub-regions AR1 and AR1′ may include a first pixel region PXA1, a second pixel region PXA2, and a third pixel region PXA3. Each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a rectangular shape. The first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may be defined as long in a horizontal direction.

[0128] Display panel DP (see Figure 4 ) may provide red light through the first pixel area PXA1, may provide green light through the second pixel area PXA2, and may provide blue light through the third pixel area PXA3.

[0129] exist Figure 8 2 shows the arrangement and shape of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 as an example. However, embodiments of the inventive concept are not limited thereto. The arrangement and shape of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may be variously modified.

[0130] Fig. 9is a cross-sectional view illustrating a portion of a display panel according to some exemplary embodiments of the inventive concept. Fig. 9 The area shown in FIG. 1 may be a first sub-area AR1. The first sub-area AR1 may include a first area DA1 (see FIG. 1 ). Figure 4 )middle.

[0131] refer to Figure 4 and Fig. 9 , each of the pixels PX may include a light emitting element OLED and a pixel circuit. The pixel circuit may include a plurality of transistors, signal lines GL, DL, PL and ECL, and a capacitor. Fig. 9 , one transistor TR is shown as an example. A pixel area may be defined in each of the pixels PX, and Fig. 9 A single pixel area PXA3 is shown in FIG.

[0132] The display panel DP may include a base layer BL, a circuit layer ML, a light emitting element layer EL, and an encapsulation layer CL. The circuit layer ML may include a transistor TR and a plurality of insulating layers BFL, L1, L2, L3, and L4.

[0133] The insulating layer BFL may be located on the base layer BL, and the transistor TR may be located on the insulating layer BFL. The transistor TR may include a semiconductor layer ACL, a control electrode GED, a first electrode ED1, and a second electrode ED2.

[0134] The semiconductor layer ACL may be located on the insulating layer BFL. The insulating layer BFL may be a buffer layer for providing low surface energy to the semiconductor layer ACL. In this case, the semiconductor layer ACL may have a higher bonding strength to the insulating layer BFL than to the base layer BL. In addition, the insulating layer BFL may be a barrier layer for protecting the bottom surface of the semiconductor layer ACL. In this case, the insulating layer BFL may suppress or prevent contaminants or moisture from penetrating into the semiconductor layer ACL from the inside of the base layer BL or through the base layer BL. According to some exemplary embodiments, the insulating layer BFL may be a light blocking layer for preventing external light from being incident on the semiconductor layer ACL through the base layer BL. In this case, the insulating layer BFL may further include a light blocking material.

[0135] The semiconductor layer ACL may include polycrystalline silicon or amorphous silicon. Alternatively, the semiconductor layer ACL may include a metal oxide semiconductor. The semiconductor layer ACL may include a channel region serving as a path through which electrons or holes move, and a first ion doped region and a second ion doped region spaced apart from each other with the channel region interposed therebetween.

[0136] The first insulating layer L1 may be located on the insulating layer BFL and may cover the semiconductor layer ACL. The first insulating layer L1 may include an inorganic material. The inorganic material may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0137] The control electrode GED may be located on the first insulating layer L1. The second insulating layer L2 may be located on the first insulating layer L1 and may cover the control electrode GED. The second insulating layer L2 may include an inorganic material.

[0138] The third insulating layer L3 may be located on the second insulating layer L2. The first electrode ED1 and the second electrode ED2 may be located on the third insulating layer L3. The first electrode ED1 and the second electrode ED2 may be connected to the semiconductor layer ACL through a through hole penetrating the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3.

[0139] The fourth insulating layer L4 may be located on the third insulating layer L3 and may cover the first electrode ED1 and the second electrode ED2. The fourth insulating layer L4 may be a single layer or may include a plurality of layers. For example, the single layer may include an organic layer. The plurality of layers may include stacked organic layers and inorganic layers. The fourth insulating layer L4 may be a planarization layer that provides a flat top surface.

[0140] The light emitting element layer EL may be located on the fourth insulating layer L4. The light emitting element layer EL may include a light emitting element OLED and a first stacked structure ST1. The light emitting element OLED may include a first pixel electrode PE1, an emission layer EM, and a common electrode CE. The first pixel electrode PE1 may be located on the fourth insulating layer L4 and may be electrically connected to the second electrode ED2 through a through hole defined in the fourth insulating layer L4. In addition, the first pixel electrode PE1 may be located in the first sub-region AR1.

[0141] The emission layer EM may be located on the first pixel electrode PE1. The emission layer EM may have a single-layer structure formed of a single material, a single-layer structure formed of materials different from each other, or a multi-layer structure including a plurality of layers formed of materials different from each other. The emission layer EM may include an organic material. The organic material may include a commonly used material. For example, the emission layer EM may include at least one of a material emitting red light, green light, and blue light. According to some exemplary embodiments, the emission layer EM may include a fluorescent material or a phosphorescent material.

[0142] The first stacked structure ST1 may be positioned adjacent to the first pixel electrode PE1. The first stacked structure ST1 may include a first middle layer ML1 and a first spacer SP1.

[0143] The first middle layer ML1 may be located on the circuit layer ML to define the pixel area PXA3. The first middle layer ML1 may be located on the fourth insulating layer L4 and may expose at least a portion of the first pixel electrode PE1. A portion of the first pixel electrode PE1 may not be covered by the first middle layer ML1, and the portion may correspond to the pixel area PXA3. The first middle layer ML1 may be referred to as a pixel defining layer.

[0144] The first spacer SP1 may be located on the first middle layer ML1. When viewed in a plan view, the area (or size) of the first spacer SP1 may be smaller than the area (or size) of the first middle layer ML1. Therefore, a portion of the top surface of the first middle layer ML1 may be exposed by the first spacer SP1. The first spacer SP1 may support the encapsulation layer CL.

[0145] The common electrode CE may be located on the emission layer EM and the first stacked structure ST1. The common electrode CE may be located on the side surface and the exposed top surface of the first middle layer ML1 and the side surface and the top surface of the first spacer SP1.

[0146] According to some exemplary embodiments, a protective layer covering the common electrode CE may be further provided The protective layer may include an inorganic material and may prevent the common electrode CE from being oxidized.

[0147] Fig.10 is a cross-sectional view illustrating a portion of a display panel according to some exemplary embodiments of the inventive concept. Fig.11 is a cross-sectional view illustrating a portion of a display panel according to some exemplary embodiments of the inventive concept. Fig.10 The area shown in may be the first sub-area AR1 ′. Fig.11 The area shown in FIG. 1 may be the second sub-area AR2. The first sub-area AR1′ and the second sub-area AR2 may include a second area DA2 (see FIG. Figure 4 The first sub-region AR1′ may provide light, and the second sub-region AR2 may not provide light.

[0148] refer to Fig.10 The light emitting element OLED-1 may include a second pixel electrode PE2-1, an emission layer EM and a common electrode CE. The second pixel electrode PE2-1 may be electrically connected to the circuit layer ML. The second pixel electrode PE2-1 may be located in the first sub-region AR1′.

[0149] The first stacked structure ST1-1 may be positioned adjacent to the second pixel electrode PE2-1. The first stacked structure ST1-1 may include a first middle layer ML1-1 and a first spacer SP1-1. The first stacked structure ST1-1 may have a Fig. 9 The first stacked structure ST1 described has the same structure.

[0150] The common electrode CE may be located on the emission layer EM. In addition, the common electrode CE may also be located on a portion of the first stacked structure ST1-1. For example, the common electrode CE may be located on a side surface of the first middle layer ML1-1, a top surface of the first middle layer ML1-1 exposed by the first spacer SP1-1, and a side surface of the first spacer SP1-1. The common electrode CE may not be located on the top surface of the first spacer SP1-1. For example, a first hole CE-H1 may be provided in the common electrode CE. The first hole CE-H1 may be provided in a region overlapping with the first spacer SP1-1.

[0151] refer to Fig.11 , the second pixel electrode PE2-2 may be located in the second sub-region AR2. The second stacked structure ST2 may be located adjacent to the second pixel electrode PE2-2. The second stacked structure ST2 may have a similar structure to the first stacked structure ST1 (see Fig. 9 ) and the first stacked structure ST1-1 (see Fig.10 ) different shapes. For example, the second stacked structure ST2 may include a second middle layer ML2 and a second spacer SP2. The second middle layer ML2 may completely cover the second pixel electrode PE2-2. In the second sub-region AR2, when viewed in a plan view, the area (or size) of the second middle layer ML2 may be equal to the area (or size) of the second spacer SP2. Therefore, the top surface of the second middle layer ML2 may be completely covered by the second spacer SP2.

[0152] The second intermediate layer ML2 can be formed by the same process as the first intermediate layer ML1 (see Fig. 9 ) and the first intermediate layer ML1-1 (see Fig.10 ) is formed of the same material. The second spacer SP2 can be formed by the same process as the first spacer SP1 (see Fig. 9 ) and the first spacer SP1-1 (see Fig.10 ) are formed of the same material.

[0153] The common electrode CE is not located in the second sub-region AR2. For example, the second hole CE-H2 may be provided in the common electrode CE. The second hole CE-H2 may be provided in a region corresponding to the second sub-region AR2.

[0154] Fig.12 are plan views illustrating some components of a display panel according to some exemplary embodiments of the inventive concept.

[0155] refer to Fig.12 , showing three first sub-regions AR1 ′, a second sub-region AR2 and a common electrode CE.

[0156] The first hole CE-H1 and the second hole CE-H2 may be defined in the common electrode CE. The first hole CE-H1 and the second hole CE-H2 may be formed by removing a portion of the common electrode CE. Since a portion of the common electrode CE is removed, the transmittance of the first sub-region AR1′ and the second sub-region AR2 may be improved. The first hole CE-H1 may be disposed in the first sub-region AR1′, and the second hole CE-H2 may be disposed in the second sub-region AR2. Specifically, the first hole CE-H1 may be disposed in the first spacer SP1-1 (see Fig.10 )superior.

[0157] Fig.13 is a cross-sectional view illustrating a portion of a display panel according to some exemplary embodiments of the inventive concept. Fig.13 The area shown in FIG. 1 may be the third sub-area AR3. The third sub-area AR3 may be included in the third area DA3 (see FIG. Figure 4 The third sub-region AR3 may not provide light.

[0158] refer to Fig.13 , the third pixel electrode PE3 may be located on the circuit layer ML. In addition, the third pixel electrode PE3 may be located in the third sub-region AR3. The third pixel electrode PE3 may be electrically connected to the circuit layer ML.

[0159] The encapsulation layer CL may be located on the third pixel electrode PE3. The encapsulation layer CL may be spaced apart from the third pixel electrode PE3.

[0160] The first middle layer ML1 (see Fig. 9 ) and the first spacer SP1 (see Fig. 9 ) may not be located in the third sub-region AR3. Fig.12 ) may not be located in the third sub-region AR3. Therefore, the transmittance of the third sub-region AR3 may be improved.

[0161] Fig.14 is a cross-sectional view illustrating a portion of a display panel according to some exemplary embodiments of the inventive concept. Fig.14 The area shown in FIG. 1 may be the first sub-area AR1′. Fig.14 In the embodiments of the present invention, the same reference numerals will be used to refer to the same Fig.10 The same components as described above, and will mainly describe Fig.14 implementation and Fig.10 differences between the implementations of .

[0162] refer to Fig.14, a first hole CE-H1a may be provided in the common electrode CE. A top surface and a side surface of the first spacer SP1-1 and a portion of a top surface of the first middle layer ML1-1 may be exposed through the first hole CE-H1a. Fig.14 The area of ​​the first hole CE-H1a may be larger than Fig.10 In this case, the transmittance of the first sub-region AR1′ can be further improved.

[0163] Fig.15 is a cross-sectional view illustrating a portion of a display panel according to some exemplary embodiments of the inventive concept. Fig.15 The sub-area ARx shown in FIG. Figure 6 The second sub-area AR2 or Figure 7 The third sub-area AR3 corresponds to Fig.15 In the embodiments of the present invention, the same reference numerals will be used to refer to the same Fig.11 The same components as described above, and will mainly describe Fig.15 implementation and Fig.11 differences between the implementations of .

[0164] refer to Fig.15 The pixel electrode PEx may be located in the sub-region ARx. The pixel electrode PEx may be electrically connected to the circuit layer ML. The pixel electrode PEx may be connected to the second pixel electrode PE2-2 (see Fig.11 ) or the third pixel electrode PE3 (see Fig.13 )correspond.

[0165] The second stacked structure ST2-1 may be positioned adjacent to the pixel electrode PEx. The second stacked structure ST2-1 may include a second middle layer ML2-1. The number of layers constituting the second stacked structure ST2-1 may be the same as the number of layers constituting the first stacked structures ST1 and ST1-1 (see Fig. 9 and Fig.10 ) are different in number of layers. Therefore, the maximum thickness of the second stacked structure ST2-1 may be smaller than that of the first stacked structures ST1 and ST1-1 (see Fig. 9 and Fig.10 ) is the maximum thickness of each of the .

[0166] Fig.16 is a perspective view illustrating a punching unit according to some exemplary embodiments of the inventive concept.

[0167] refer to Fig.16 , the punching unit SU may include a first substrate BSP1, a second substrate BSP2, a punching piece ST, guide members LB1 and LB2, and an elastic member ES.

[0168] The first substrate BSP1 may be coupled to the stamping substrate to fix the stamping unit SU to the stamping substrate. The second substrate BSP2 may be spaced apart from the first substrate BSP1 by a certain distance (e.g., a set or predetermined distance) and may be positioned parallel to the first substrate BSP1. The stamping piece ST may be located on the top surface of the second substrate BSP2.

[0169] The stamping part ST may be formed of a rubber material having adhesive properties. For example, the stamping part ST may be formed of, but not limited to, polydimethylsiloxane or silicon. In addition, the adhesive strength of the stamping part ST may be 300 gf / inch or greater.

[0170] The stamping piece ST may be fixed to the second substrate BSP2 by an additional fixing member. The stamping piece ST may be detachably fixed to the second substrate BSP2, and thus when the adhesive strength of the stamping piece ST becomes weak, the stamping piece ST may be easily replaced.

[0171] The first substrate BSP1 and the second substrate BSP2 may be connected to each other by guide members LB1 and LB2. When external force is applied to the first substrate BSP1 and the second substrate BSP2, the second substrate BSP2 may move along the guide members LB1 and LB2 in a direction toward the first substrate BSP1. Fig.16 As shown in FIG. 8 , the guide members LB1 and LB2 may have two guide rods. However, the number of the guide rods is not limited thereto.

[0172] The elastic member ES may be disposed between the first substrate BSP1 and the second substrate BSP2. When a force is applied to the first substrate BSP1 and the second substrate BSP2, the elastic member ES may be contracted by elasticity, and the restoring force of the elastic member ES may be transmitted to the stamping part ST located on the second substrate BSP2, and thus the stamping part ST may be in close contact with the work object.

[0173] exist Fig.16 In the embodiment, the top surface TS and the bottom surface of the stamping piece ST may have circular shapes, and the stamping piece ST may have a truncated cone shape in which the diameter of the top surface TS is smaller than that of the bottom surface. However, the shape of the stamping piece ST is not limited thereto.

[0174] Fig.17A and Fig. 17B are cross-sectional views illustrating some processes of a method for manufacturing a display device according to some exemplary embodiments of the inventive concept.

[0175] refer to Fig.17A and Fig. 17B A base layer BL may be formed. A circuit layer ML may be formed on the base layer BL. A first pixel electrode PE1 and a third pixel electrode PE3 may be formed on the circuit layer ML.

[0176] The first stacked structure ST1 may be formed in a region adjacent to the first pixel electrode PE1. The first stacked structure ST1 may include a first middle layer ML1 and a first spacer SP1. The first middle layer ML1 and the first spacer SP1 may not be located on the third pixel electrode PE3.

[0177] A common electrode layer CE-B may be formed. The common electrode layer CE-B may cover the first stacked structure ST1, the emission layer EM, and the third pixel electrode PE3. According to some exemplary embodiments, the emission layer EM may also be located between the third pixel electrode PE3 and the common electrode layer CE-B.

[0178] A portion of the common electrode layer CE-B may be removed using a stamping process. Therefore, the transmittance of the region where the portion of the common electrode layer CE-B is removed may be improved. The stamping piece ST may contact a portion of the common electrode layer CE-B corresponding to the third area DA3. This portion in contact with the stamping piece ST may be bonded to the stamping piece ST. Therefore, a hole CE-H may be formed in the common electrode layer CE-B.

[0179] Fig.18A and Fig.18B are cross-sectional views illustrating some processes of a method for manufacturing a display device according to some exemplary embodiments of the inventive concept.

[0180] refer to Fig.18A and Fig.18B , the second pixel electrodes PE2-1 and PE2-2 may be formed on the circuit layer ML. The second pixel electrode PE2-1 may be formed in the first sub-region AR1′, and the second pixel electrode PE2-2 may be formed in the second sub-region AR2.

[0181] The first stacked structure ST1-1 may be formed in a region adjacent to the second pixel electrode PE2-1. The first stacked structure ST1-1 may include a first middle layer ML1-1 and a first spacer SP1-1. The second stacked structure ST2 may be formed in a region adjacent to the second pixel electrode PE2-2. The second stacked structure ST2 may include a second middle layer ML2 and a second spacer SP2.

[0182] The first stacked structure ST1-1 and the second stacked structure ST2 may have different structures from each other. For example, the first stacked structure ST1-1 and the second stacked structure ST2 may include the same layer, but the second middle layer ML2 and the second spacer SP2 may completely cover the second pixel electrode PE2-2. In other words, the shapes of the first stacked structure ST1-1 and the second stacked structure ST2 may be different from each other.

[0183] According to some exemplary embodiments, the first middle layer ML1 (see FIG. 1 ) may be formed simultaneously by the same process. Fig.17A), the first middle layer ML1-1 and the second middle layer ML2. In addition, the first spacer SP1 (see Fig.17A ), a first spacer SP1-1 and a second spacer SP2.

[0184] The common electrode layer CE-B may be formed on the first stacked structure ST1-1, the second stacked structure ST2, and the emission layer EM. A portion of the common electrode layer CE-B may be removed using a stamping process. Therefore, the transmittance of the region where the portion of the common electrode layer CE-B is removed may be increased.

[0185] The stamping piece ST may be in contact with a portion of the common electrode layer CE-B corresponding to the second area DA2. The portion of the common electrode layer CE-B in contact with the stamping piece ST may be bonded to the stamping piece ST. Thus, a first hole CE-H1 and a second hole CE-H2 may be formed in the common electrode layer CE-B. The first hole CE-H1 may be formed in the first sub-area AR1′, and the second hole CE-H2 may be formed in the second sub-area AR2.

[0186] According to some exemplary embodiments of the inventive concept, the third area DA3 may consist of only the third sub-area AR3 (see Figure 7 ), and the second area DA2 may be composed of the first sub-area AR1′ and the second sub-area AR2 (see Figure 6 ) Fig. 17B In the embodiment, the portion of the common electrode layer CE-B located in the third sub-region AR3 may be completely removed. Fig.18B In the embodiment, the portion of the common electrode layer CE-B located in the second sub-region AR2 may be completely removed, but because the first sub-region AR1′ provides light, the portion of the common electrode layer CE-B located in the first sub-region AR1′ may not be completely removed. Therefore, the transmittance of the third area DA3 may be higher than the transmittance of the second area DA2.

[0187] If a portion of the common electrode layer CE-B is removed using a laser process, the defect rate may increase due to particles and / or shape deformation caused by heating. However, according to an embodiment of the inventive concept, a portion of the common electrode layer CE-B may be removed using a stamping member ST. In this case, the shape deformation of the display panel DP caused by heating may be reduced or minimized, and / or particles generated during the removal of the common electrode layer CE-B may be reduced or minimized. Therefore, the defect rate caused by the process of removing a portion of the common electrode layer CE-B may be reduced.

[0188] Fig.19A and Fig.19B are cross-sectional views illustrating some processes of a method for manufacturing a display device according to some exemplary embodiments of the inventive concept.

[0189] refer to Fig.19A and Fig.19B , a first stacked structure ST1-1 may be formed in a region adjacent to the second pixel electrode PE2-1. The first stacked structure ST1-1 may include a first middle layer ML1-1 and a first spacer SP1-1. The second stacked structure ST2-1 may be formed in a region adjacent to the second pixel electrode PE2-2. The first stacked structure ST1-1 may include m layers, the second stacked structure ST2-1 may include n layers, and "m" may be greater than "n". For example, "m" may be 2, and "n" may be 1. Therefore, the maximum thickness TK1 of the first stacked structure ST1-1 may be greater than the maximum thickness TK2 of the second stacked structure ST2-1.

[0190] The second stacked structure ST2-1 may be the same layer as the first intermediate layer ML1-1 or may be the same layer as the first spacer SP1-1. For example, when the second stacked structure ST2-1 is the same layer as the first intermediate layer ML1-1, the second stacked structure ST2-1 may be formed simultaneously with the first intermediate layer ML1-1.

[0191] A common electrode layer CE-B may be formed. The common electrode layer CE-B may cover the first stacked structure ST1-1, the emission layer EM, the second stacked structure ST2-1, and the second pixel electrode PE2-2. According to some exemplary embodiments, the emission layer EM may also be located between the second pixel electrode PE2-2 and the common electrode layer CE-B.

[0192] The portion of the common electrode layer CE-B may be removed using a stamping process. Therefore, the transmittance of the region where the portion of the common electrode layer CE-B is removed may be improved. The stamping member ST-1 may contact a portion of the common electrode layer CE-B corresponding to the second area DA2.

[0193] According to some exemplary embodiments, the common electrode layer CE-B located in the second sub-region AR2 may be completely removed. The common electrode layer CE-B located in the second sub-region AR2 may have a stepped top surface. Therefore, the hardness of the stamping part ST-1 may be lower than Fig.18A The hardness of the stamping piece ST shown in . Therefore, the shape of the stamping piece ST-1 can be easily deformed by pressure. Fig.19A The stamping piece ST-1 whose shape is deformed is shown in FIG. The entire portion of the common electrode layer CE-B located in the second sub-area AR2 may be in contact with the stamping piece ST-1.

[0194] A portion of the common electrode layer CE-B in contact with the stamping member ST-1 may be bonded to the stamping member ST-1. Thus, a first hole CE-H1a and a second hole CE-H2 may be formed in the common electrode layer CE-B. The first hole CE-H1a may be formed in the first sub-region AR1′, and the second hole CE-H2 may be formed in the second sub-region AR2.

[0195] According to the above-described embodiments of the inventive concept, a portion of the common electrode may be removed using a punching process, and thus a defect rate in a manufacturing process may be reduced.

[0196] Although the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive, but illustrative. Therefore, the scope of the inventive concept is determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the foregoing detailed description.

Claims

1. Display equipment, including: A display panel, the display panel comprising: a first region having a first resolution; and a second region having a second resolution lower than the first resolution; Wherein, the display panel comprises: Basal layer; a circuit layer, on the base layer; a first pixel electrode electrically connected to the circuit layer and in the first region; a second pixel electrode electrically connected to the circuit layer and in the second region; a common electrode on the circuit layer and including a hole on the circuit layer and in an area of ​​the second area where no light is provided; a first stacked structure on the circuit layer and adjacent to the first pixel electrode; and A second stacked structure is on the circuit layer and adjacent to the second pixel electrode, the second stacked structure is different from the first stacked structure, and the hole of the common electrode on the circuit layer and in the area of ​​the second area where no light is provided overlaps with the second stacked structure.

2. The display device according to claim 1, wherein: The first stacking structure comprises: a first intermediate layer on the circuit layer and exposing at least a portion of the first pixel electrode; and The first spacer is on the first intermediate layer, and the area of ​​the first spacer is smaller than the area of ​​the first intermediate layer in a plan view.

3. The display device according to claim 2, wherein: The second stacking structure comprises: a second intermediate layer, on the circuit layer and covering the second pixel electrode; and A second spacer is on the second intermediate layer.

4. The display device according to claim 3, wherein: An area of ​​the second intermediate layer in a plan view is equal to an area of ​​the second spacer.

5. The display device according to claim 3, wherein: The first intermediate layer and the second intermediate layer include the same material and are at the same layer.

6. The display device according to claim 2, wherein: A first maximum thickness of the first stacked structure is greater than a second maximum thickness of the second stacked structure.

7. The display device according to claim 6, wherein: The second stack structure includes: a second intermediate layer at the same layer as the first intermediate layer.

8. The display device according to claim 2, wherein: The display panel further includes a third area, the third area having a third resolution lower than the first resolution of the first area, and the display device further includes: A first module, below the second area, A second module, below the third area, Wherein, the display panel further includes: a third pixel electrode electrically connected to the circuit layer and located in the third area.

9. The display device according to claim 8, wherein: The first intermediate layer and the first spacer are not in the third region.

10. The display device according to claim 8, wherein: The third resolution of the third area is lower than the second resolution of the second area.

11. The display device according to claim 1, in, The first stacked structure includes one or more first layers, Wherein, the second stacking structure includes one or more second layers, and The number of the one or more first layers is greater than the number of the one or more second layers.

12. The display device according to claim 1, wherein: The common electrode includes a first hole and a second hole as the hole in the region where light is not provided in the second region.

13. The display device according to claim 12, wherein: The first hole is in the second region.

14. The display device according to claim 12, wherein: The second region includes a first subregion configured to provide light and a second subregion as the region not providing light, the first hole is in the first subregion, and the second hole is in the second subregion.

15. The display device according to claim 14, wherein: The second pixel electrode is in the second sub-region.

16. The display device according to claim 14, wherein: The display panel further includes: a fourth pixel electrode, in the first sub-region; and A third stacked structure is on the circuit layer and adjacent to the fourth pixel electrode, and the third stacked structure has the same structure as the first stacked structure.

17. The display device according to claim 16, wherein: The third stacking structure comprises: an intermediate layer exposing at least a portion of the fourth pixel electrode; and a spacer, on the intermediate layer, Wherein, the first hole is defined on the spacer.

18. The display device of claim 1, further comprising a module below the second area.

19. A display device comprising: Display panel, including: a first region having a first resolution; and a second region having a second resolution lower than the first resolution, Wherein, the display panel comprises: Basal layer; a circuit layer, on the base layer; a common electrode on the circuit layer and including a hole on the circuit layer and in an area of ​​the second area where no light is provided; a first stacked structure on the circuit layer and in the first region; and A second stacked structure is provided on the circuit layer and in the second region, the second stacked structure being different from the first stacked structure, and the hole of the common electrode in the region of the second region not providing light and on the circuit layer overlaps with the second stacked structure.

20. The display device according to claim 19, wherein: The common electrode further includes a hole on the circuit layer and in a light providing region of the second region.

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