Code generator including asynchronous and synchronous counters and method of operating the same

Abstract

A code generator is disclosed, including: an asynchronous counter including a first flip-flop to an m-th flip-flop, the first flip-flop to the m-th flip-flop being configured to asynchronously output a first output signal to an m-th output signal respectively corresponding to a first bit to an m-th bit (m is an integer greater than or equal to 2) of a code in response to a first clock signal; and a synchronous counter including an (m + 1)-th flip-flop to an (m + n)-th flip-flop, the (m + 1)-th flip-flop to the (m + n)-th flip-flop being configured to synchronously output an (m + 1)-th output signal to an (m + n)-th output signal corresponding to the (m + 1)-th bit to the (m + n)-th bit (n is an integer greater than or equal to 2) of the code in response to the first clock signal. The asynchronous counter further includes: a first delay circuit to an m-th delay circuit, configured to respectively delay the first output signal to the m-th output signal such that when the (m + 1)-th bit to the (m + n)-th bit are output, the first bit to the m-th bit of the code are output together simultaneously.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0063868, filed on May 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the inventive concept disclosed herein relate to a code generator and an operating method thereof, and more particularly, to a code generator including an asynchronous counter and a synchronous counter and an operating method thereof. Background art

[0004] A counter may receive a clock signal and may perform a counting operation based on the clock signal. The counter may increase or decrease a count value at the rising edge or the falling edge of the clock signal. The counter may count the number of times the logical value of the clock signal changes. The counter may be classified as an asynchronous counter or a synchronous counter. The counter may output a binary code.

[0005] An asynchronous counter may receive a clock signal and divide the received clock signal. However, the code output from the asynchronous counter may not be synchronized with the received clock signal. In contrast, a synchronous counter may receive a clock signal, and the code output from the synchronous counter may be synchronized with the received clock signal. However, compared with the asynchronous counter, it is difficult for the synchronous counter to operate at a relatively high speed. Summary of the invention

[0006] Embodiments of the inventive concept provide a code generator including an asynchronous counter and a synchronous counter and an operating method thereof.

[0007] According to an exemplary embodiment, a code generator includes: an asynchronous counter including a first flip-flop to an m-th flip-flop, the first flip-flop to the m-th flip-flop being configured to asynchronously output a first output signal to an m-th output signal in response to a first clock signal, the first output signal to the m-th output signal corresponding to a first bit to an m-th bit of a code respectively (m is an integer greater than or equal to 2); and a synchronous counter including an (m + 1)-th flip-flop to an (m + n)-th flip-flop, the (m + 1)-th flip-flop to the (m + n)-th flip-flop being configured to synchronously output an (m + 1)-th output signal to an (m + n)-th output signal in response to the first clock signal, the (m + 1)-th output signal to the (m + n)-th output signal corresponding to an (m + 1)-th bit to an (m + n)-th bit of the code respectively (n is an integer greater than or equal to 2). The asynchronous counter further includes a first delay circuit to an m-th delay circuit, the first delay circuit to the m-th delay circuit being configured to delay the first output signal to the m-th output signal respectively, such that when the (m + 1)-th bit to the (m + n)-th bit are output, the first bit to the m-th bit of the code are output together simultaneously.

[0008] According to an exemplary embodiment, a code generator includes: an asynchronous counter that receives a first clock signal and outputs a first output signal corresponding to a first bit of a binary code respectively based on the first clock signal; a synchronous counter that outputs a second output signal corresponding to a second bit of the binary code respectively based on a second clock signal obtained by dividing the frequency of the first clock signal by the asynchronous counter; and a code converter that receives the first bit and the second bit of the binary code and converts the binary code into a Gray code.

[0009] According to an exemplary embodiment, an operation method of a code generator includes: receiving a first clock signal; outputting a first output signal based on the first clock signal by using a first flip-flop; outputting a second output signal to an m-th output signal (m is an integer greater than or equal to 2) by dividing the frequency of the first clock signal by using a second flip-flop to an m-th flip-flop; delaying the first output signal to the m-th output signal corresponding to a first bit to an m-th bit of a code respectively by a first delay circuit to an m-th delay circuit; and synchronously outputting an (m + 1)-th output signal to an (m + n)-th output signal corresponding to an (m + 1)-th bit to an (m + n)-th bit respectively at an edge of a second clock signal generated by dividing the frequency of the first clock signal by using a first flip-flop to an m-th flip-flop (n is an integer greater than or equal to 2). Description of the Drawings

[0010] The above and other objects and features of the inventive concept will become apparent by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings.

[0011] Figure 1 A block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown.

[0012] Figures 2A to 2C A block diagram of an Figure 1 asynchronous counter according to an exemplary embodiment is shown.

[0013] Figure 3 A block diagram of a Figure 1 synchronous counter according to an exemplary embodiment is shown.

[0014] Figure 4 A timing diagram showing the operation of a Figure 1 code generator according to an exemplary embodiment is shown.

[0015] Figure 5 A block diagram of an Figure 1 asynchronous counter according to an exemplary embodiment is shown.

[0016] Figure 6 A timing diagram showing the operation of a Figure 1 code generator according to an exemplary embodiment is shown.

[0017] Figure 7 A block diagram of flip-flops shown in Figures 2A to 2C , Figure 3 and Figure 5 according to an exemplary embodiment is shown.

[0018] Figure 8 A block diagram of a Figure 1 synchronous counter according to an exemplary embodiment is shown.

[0019] Figure 9 A block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown.

[0020] Figure 10 A block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown.

[0021] Figure 11 A block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown.

[0022] Figure 12 A block diagram of a Figure 11 code converter according to an exemplary embodiment is shown.

[0023] Figure 13 A timing diagram showing the operation of a Figure 11 and Figure 12 code converter according to an exemplary embodiment is shown.

[0024] Figure 14 The flowchart of a code generator according to an exemplary embodiment of the inventive concept is shown.

[0025] Figure 15 The block diagram of an image sensor to which a code generator according to an exemplary embodiment of the inventive concept is applied is shown.

[0026] Figure 16 The block diagram of a display device to which a code generator according to an exemplary embodiment of the inventive concept is applied is shown.

[0027] Figure 17 The block diagram of an electronic device to which a code generator according to an exemplary embodiment of the inventive concept is applied is shown. DETAILED DESCRIPTION

[0028] Figure 1 The block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown. For example, the code generator 100 may be included in an electronic device, a semiconductor device, an integrated circuit, etc. The code generator 100 may use a counter. For example, the counter is implemented in an analog-to-digital converter (ADC) for converting an analog signal into a digital signal. Referring Figure 1 , the code generator 100 may include an asynchronous counter 110 and a synchronous counter 120.

[0029] The asynchronous counter 110 may receive a clock signal CK1 and may output or generate bits CODE[m:1] of a code (hereinafter referred to as “code bits”) based on the clock signal CK1. For example, “m” may be an integer of 2 or greater, and the asynchronous counter 110 may output a plurality of bits. For example, the clock signal CK1 may be sent from outside the code generator 100. For another example, the code generator 100 may further include a clock generator (e.g., a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit) that generates the clock signal CK1.

[0030] The asynchronous counter 110 may asynchronously output the code bits CODE[m:1] in response to the clock signal CK1. Here, the term “asynchronous” may mean that the output times of the code bits CODE[m:1] are different from each other. The output times of the code bits CODE[m:1] determined by the asynchronous counter 110 may not be aligned with respect to the clock signal CK1. For example, the asynchronous counter 110 may output the code bit CODE[1] and then may output the code bit CODE[2]. The asynchronous counter 110 may sequentially output the code bits CODE[m:1] in the above-described manner.

[0031] The synchronous counter 120 can receive the clock signal CK2 and can output or generate code bits CODE[m+n:m+1] based on the clock signal CK2. For example, "n" can be an integer of 2 or greater and can be equal to or different from "m". The synchronous counter 120 can output multiple bits. The synchronous counter 120 can synchronously output the code bits CODE[m+n:m+1] in response to the clock signal CK2. Here, the term "synchronous" can mean that the output times of the code bits CODE[m+n:m+1] are the same as each other. The output times of the code bits CODE[m+n:m+1] determined by the synchronous counter 120 can be aligned with respect to the clock signal CK2. For example, the synchronous counter 120 can output the code bits CODE[m+n:m+1] simultaneously.

[0032] The code bits CODE[m:1] output by the asynchronous counter 110 can correspond to the low bits. The code bits CODE[m+n:m+1] output by the synchronous counter 120 can correspond to the high bits. The code bit CODE[1] can correspond to the least significant bit (LSB). The code bit CODE[m+n] can correspond to the most significant bit (MSB).

[0033] Different from Figure 1 In the example shown in

[0034] Different from Figure 1 In the example shown in Figure 3) to output the code bits CODE[m+n:1]. Due to the propagation delay of the combinational logic circuit, as the number of code bits CODE[m+n:1] increases (or the size of the code becomes larger), the frequency of the clock signal CK1 to be provided to the synchronous counter 120 can be further restricted. Additionally, since the propagation delay of the combinational logic circuit increases as the level of the power supply voltage of the code generator 100 decreases, the frequency of the clock signal CK1 to be provided to the synchronous counter 120 can be further restricted.

[0035] Reference Figure 1 , the code generator 100 according to an exemplary embodiment of the inventive concept can address the above limitations and can include a hybrid counter that is capable of operating even under high-speed and low-power conditions. The hybrid counter can include both an asynchronous counter 110 and a synchronous counter 120. The asynchronous counter 110 can divide the frequency of the clock signal CK1. The clock signal CK1 received by the asynchronous counter 110 can be different from the clock signal CK2 received by the synchronous counter 120. For example, when the frequency of the clock signal CK1 is "f", the frequency of the clock signal CK2 generated as a result of the division by the asynchronous counter 110 can be "f / 2" m ". Compared to the case of directly receiving the clock signal CK1, since the synchronous counter 120 receives the clock signal CK2 obtained by dividing the clock signal CK1, the limitation on the frequency of the clock signal CK2 due to the combinational logic circuit of the synchronous counter 120 can be addressed.

[0036] Figures 2A to 2C illustrates an asynchronous counter according to an exemplary embodiment Figure 1 of. Each of the asynchronous counters 110a, 110b, and 110c can be an Figure 1 example of the asynchronous counter 110. The asynchronous counters 110a, 110b, and 110c will be described together. The asynchronous counter 110a can include flip-flops 111_1 to 111_m. The asynchronous counter 110b can include flip-flops 111_1 to 111_m. The asynchronous counter 110c can include flip-flops 111_1 to 111_m and inverters 112_1 to 112_m.

[0037] Each of the flip-flops 111_1 to 111_m can include a clock port, a reset port "R", and an output port "Q". Each of the flip-flops 111_1 to 111_m can include an input port and an inverted output port (not shown) (reference Figure 7)。The inverted output port of each of the flip - flops 111_1 to 111_m can be electrically connected to its input port. For example, each of the flip - flops 111_1 to 111_m can be a trigger (toggle) flip - flop or a JK flip - flop, but the types of flip - flops are not limited to this. Each of the flip - flops 111_1 to 111_m can switch, change, or invert the logical value of the output signal to be output through the output port "Q" at the edge of the clock signal received through the clock port. This edge can be the rising edge or the falling edge of the clock signal received through the clock port.

[0038] Each of the flip - flops 111_1 to 111_m can reset the logical value of the output signal to be output through the output port "Q" to a given value (e.g., logical "0" or logical "1") in response to the reset signal RESET received through the reset port "R". When the reset signal RESET is activated, each of the flip - flops 111_1 to 111_m can reset the logical value of the output signal. Each of the flip - flops 111_1 to 111_m can switch the logical value of the output signal at the edge of the clock signal received through the clock port in a state where the reset signal RESET is deactivated. For example, the flip - flops 111_1 to 111_m can be implemented to be the same as each other.

[0039] The flip - flop 111_1 can receive the clock signal CK1 input to the code generator 100 through the clock port. For example, the flip - flop 111_1 may not receive the inverted clock signal of the clock signal CK1. The clock signal CK1 can be sent to the code generator 100 in a single - mode rather than a differential mode. The flip - flop 111_1 can switch the logical value of the output signal Q[1] to be output through the output port "Q" at the edge of the clock signal CK1. The output signal Q[1] of the flip - flop 111_1 can correspond to the code bit CODE[1]. The inverted output port of the flip - flop 111_1 can be electrically connected to its input port. The frequency of the output signal Q[1] can be half of the frequency of the clock signal CK1. The flip - flop 111_1 can divide the clock signal CK1 by 2 and can output the output signal Q[1].

[0040] Figure 2A The flip - flop 111_2 can directly receive the output signal Q[1] of the flip - flop 111_1 through the clock port. In Figure 2A this case, the flip - flop 111_2 can be the same as the flip - flop 111_1. However, the flip - flop 111_1 can perform a switching operation at the rising edge of the clock signal CK1, while the flip - flop 111_2 can perform a switching operation at the falling edge of the output signal Q[1]. Figure 2AThe remaining flip - flops 111_3 to flip - flop 111_m can perform a switching operation at the falling edge of the output signals Q[2] to Q[m]. In some examples, different from Figure 2A the example shown in

[0041] Figure 2B flip - flop 111_2 can directly receive the inverted output signal Qb[1] of flip - flop 111_1 through the clock port. Figure 2B Flip - flops 111_1 to 111_m of Figure 2B can be implemented to be identical to each other and can perform a switching operation at the rising edge of the clock signal CK1 and the output signals Qb[1] to Qb[m]. In some examples, different from

[0042] Figure 2C the example shown in Figure 2C flip - flops 111_1 to 111_m can perform a switching operation at the falling edge of the clock signal CK1 and the output signals Qb[1] to Qb[m].

[0043] In addition to Figures 2A to 2C flip - flop 111_2 receiving the output signal Q[1] of the previous flip - flop 111_1, the inverted output signal Qb[1] of the previous flip - flop 111_1, or the output signal of inverter 112_1 through the clock port, the operation of flip - flop 111_2 can be the same as that of flip - flop 111_1.

[0044] The flip - flop 111_2 can switch the logical value of the output signal Q[2] to be output through the output port "Q" at the edge of the output signal Q[1], the inverted output signal Qb[1], or the output signal of the inverter 112_1. The output signal Q[2] of the flip - flop 111_2 can correspond to the code bit CODE[2]. The inverted output port of the flip - flop 111_2 can be electrically connected to its input port. The frequency of the output signal Q[2] can be half of the frequency of the output signal Q[1] and can be 1 / 4 of the frequency of the clock signal CK1. The flip - flop 111_2 can divide the output signal Q[1] by 2 and can output the output signal Q[2]. The inverter 112 - 2 can invert the logical value of the output signal Q[2].

[0045] Each of the asynchronous counters 110a, 110b, and 110c in the asynchronous counter can include "m" flip - flops 111_1 to flip - flop 111_m and / or "m" inverters 112_1 to inverter 112_m respectively corresponding to the code bits CODE[m:1]. Except that the flip - flop 111_m receives the output signal Q[m - 1] or the inverted output signal Qb[m - 1] of the previous flip - flop 111_m - 1 (not shown) through the clock port, or the output signal of the inverter in front of the flip - flop 111_m, the operation of the flip - flop 111_m can be the same as the operation of the flip - flop 111_2. The output signal Q[m] output through the output port "Q" of the flip - flop 111_m can correspond to the code bit CODE[m]. The inverter 112_m can invert the logical value of the output signal Q[m].

[0046] Figure 2A The output signal Q[m] of the flip - flop 111_m can be the inverted clock signal CK2b, and its frequency can correspond to the result of dividing the frequency of the clock signal CK1 by 2 m of the result. Figure 2B The output signal Q[m] of the flip - flop 111_m can be the clock signal CK2, and its frequency can correspond to the result of dividing the frequency of the clock signal CK1 by 2 m of the result. Through Figure 2C The frequency of the clock signal CK2 output by the inverter 112_m can correspond to the result of dividing the frequency of the clock signal CK1 by 2 m of the result. The flip - flops 111_2 to 111_m can divide the output signals Q[m - 11:1] provided by the previous flip - flops 111_1 to 111_m - 1 by 2 respectively. For example, the clock signal CK2 or the inverted clock signal CK2b obtained by dividing the clock signal CK1 by "m" can be sent to the synchronous counter 120.

[0047] The output signal Q[1] of the flip-flop 111_1 can correspond to the code bit CODE[1] and can be provided as a clock signal to the flip-flop 111_2. The flip-flop 111_1 can determine the output time of the output signal Q[1] (i.e., the time to determine the logical value of the output signal Q[1]) with respect to the edge of the clock signal CK1. The flip-flop 111_2 can determine the output time of the output signal Q[2] with respect to the edge of the output signal Q[1] or the inverted output signal Qb[1] rather than the edge of the clock signal CK1. The flip-flop 111_m can determine the output time of the output signal Q[m] with respect to the edge of the output signal Q[m-1], the inverted output signal Qb[m-1], or the output signal of the inverter preceding the flip-flop 111_m. The output time of the flip-flop 111_m can be adjacent to the output time of the flip-flop 111_m-1. The asynchronous counters 110a, 110b, and 110c can output the code bits CODE[m:1] asynchronously or sequentially.

[0048] Figure 3 shows a Figure 1 block diagram of a synchronous counter according to an exemplary embodiment. The synchronous counter 120a can be Figure 1 an example of the synchronous counter 120. The synchronous counter 120a can include flip-flops 121_1 to 121_n and a combinational logic circuit 122.

[0049] Each of the flip-flops 121_1 to 121_n can include a clock port, an input port "D", an output port "Q", an inverted output port Qb, and a reset port "R". For example, each of the flip-flops 121_1 to 121_n can be a D flip-flop.

[0050] Each of the flip-flops 121_1 to 121_n can latch the logical value of the input signal received through the input port "D" at the edge of the clock signal received through the clock port and can output an output signal having the latched logical value through the output port "Q". Different from the flip-flops 111_1 to 111_m of the asynchronous counters 110a, 110b, and 110c, the flip-flops 121_1 to 121_n of the synchronous counter 120a can commonly receive the clock signal CK2. Different from Figure 3 the example shown, the flip-flops 121_1 to 121_n of the synchronous counter 120a can commonly receive the inverted clock signal CK2b.

[0051] For example, the inverter 112_m may be a driver that drives the clock signal CK2 such that the clock signal CK2 is properly sent to all the flip-flops 121_1 to 121_n of the synchronous counter 120a. For another example, the asynchronous counter 110 may include a driver that drives the clock signal CK2. The driver may include the inverter 112_m, or may buffer and output the clock signal CK2 provided from the inverter 112_m. The flip-flops 121_1 to 121_n may latch the logical values of the input signal D[m+n:m+1] at the edges of the clock signal CK2 respectively and may output corresponding output signals Q[m+n:m+1] (not shown). For example, the flip-flops 121_1 to 121_n may be implemented to be the same as each other. In some examples, when the flip-flops 121_1 to 121_n of the synchronous counter 120a use the inverted clock signal CK2b, the flip-flops 121_1 to 121_n may receive a clock signal inverted with respect to the inverted clock signal CK2b by using an inverter.

[0052] The output signals Q[m+n:m+1] may respectively correspond to the code bits CODE[m+n:m+1]. The edges of the clock signal CK2 may correspond to the edges of the output signals Q[m] of the flip-flops 111_m of the asynchronous counters 110a, 110b or 110c. The flip-flops 121_1 to 121_n of the synchronous counter 120a may commonly receive the clock signal CK2. The synchronous counter 120a may output the code bits CODE[m+n:m+1] in synchronization with each other or simultaneously.

[0053] Each of the flip-flops 121_1 to 121_n may reset the logical value of the output signal to be output through the output port "Q" to a given value (e.g., logical "0" or logical "1") in response to the reset signal RESET received through the reset port "R". When the reset signal RESET is activated, each of the flip-flops 121_1 to 121_n may reset the logical value of the output signal. In a state where the reset signal RESET is deactivated, each of the flip-flops 121_1 to 121_n may latch the logical value of the input signal at the edge of the clock signal CK2 received through the clock port. The reset signal RESET sent to the flip-flops 121_1 to 121_n of the synchronous counter 120a may be the same as or different from the reset signal RESET sent to the flip-flops 111_1 to 111_m of each of the asynchronous counters 110a, 110b and 110b.

[0054] The combinational logic circuit 122 can perform various logical operations, such as inverter (INV), NAND, AND, NOR, OR, exclusive-NOR (XNOR), and exclusive-OR (XOR) operations, on the inverted output signals Qb[m+n:m+1] or the output signals Q[m+n:m+1] of the flip-flops 121_1 to 121_n. The combinational logic circuit 122 can include at least one logic gate (e.g., an inverter, a NAND gate, an AND gate, a NOR gate, an OR gate, a XNOR gate, or a XOR gate) for performing the logical operations. The combinational logic circuit 122 can output the input signals D[m+2:m+n] of the flip-flops 121_2 to 121_n by using the inverted output signals Qb[m+n:m+1].

[0055] Reference Figure 3 , the inverted output port Qb of the flip-flop 121_1 of the synchronous counter 120a that outputs the code bit CODE[m+1] can be electrically connected to the flip-flop input port “I)”. For example, like the flip-flops 111_1 to 111_m of the asynchronous counters 110a, 110b, and 110c, the flip-flop 121_1 can be a T flip-flop. The flip-flop 121_1 can be implemented to be the same as the flip-flops 111_1 to 111_m of the asynchronous counters 110a, 110b, and 110c. In contrast, each of the remaining flip-flops 121_2 to 121_n of the synchronous counter 120a can be a D flip-flop, respectively. The flip-flops 121_2 to 121_n can be implemented to be the same as each other. Different from Figure 3 the example shown in, all of the flip-flops 121_1 to 121_n of the synchronous counter 120a can be implemented by D flip-flops according to the logical operations performed by the combinational logic circuit 122.

[0056] Figure 4 is a timing diagram showing the operation of the Figure 1 code generator according to an exemplary embodiment. Reference will be made to Figure 1 , Figure 2C and Figure 3 to describe Figure 4 . In Figure 4 , it is assumed that Figure 1 the asynchronous counter 110 of Figure 2C is the asynchronous counter 110c of Figure 1 and the synchronous counter 120 of Figure 3synchronous counter 120a, and "m" and "n" are 2 respectively. The timing diagrams of the asynchronous counter 110a and the asynchronous counter 110b can be similar to the timing diagram of the asynchronous counter 110c. The asynchronous counter 110c can output code bits CODE[2:1], and the synchronous counter 120a can output code bits CODE[4:3]. For example, when "m" and "n" are 2 respectively, the code generator 100 can count from 0 to 15 (= 2 4(＝m+n) -1) with respect to the rising edge of the clock signal CK1. For another example, the code generator 100 can perform a counting operation with respect to the falling edge of the clock signal CK1. For another example, the code generator 100 can perform a counting operation with respect to both the rising edge and the falling edge of the clock signal CK1. The reset signal RESET can be activated before the time point T1 and then can be deactivated. The logical values of all the code bits CODE[4:1] can be reset to 0 in response to the reset signal RESET. Figure 4 The values assumed in the above are only exemplary.

[0057] After the reset signal RESET is activated and then deactivated, at the time point T1, the logical value of the clock signal CK1 can be switched (changed) from 0 to 1. The clock signal CK1 can have a rising edge at the time point T1. The flip-flop 111_1 of the asynchronous counter 110c can switch the logical value of the code bit CODE[1] from 0 to 1 at the rising edge of the clock signal CK1 (i.e., in response to the rising edge of the clock signal CK1). The value of the code bits CODE[4:1] can be updated from 0000 (2) to 0001 (2) . Referring to Figure 4 , after the time point T1 when the clock signal CK1 has a low-to-high transition (rise) (the rising edge of the clock signal CK1 can be placed at the time point T1), the flip-flop 111_1 can output the code bit CODE[1] or the output signal Q[1]. The time difference (delay) between the time point T1 and the output time of the code bit CODE[1] can be tD1. The time difference tD1 can correspond to the CK-Q delay of the flip-flop 111_1. The delay can be referred to as the "delay time".

[0058] The clock signal CK1 may have a rising edge at time point T2. In another embodiment, the flip-flop 111_1 of the asynchronous counter 110c may switch the logical value of the code bit CODE[1] from 1 to 0 at the rising edge of the clock signal CK1. The flip-flop 111_2 of the asynchronous counter 110c may switch the logical value of the code bit CODE[2] from 0 to 1 at the falling edge of the output signal Q[1] (i.e., CODE[1]) of the flip-flop 111_1. The value of the code bits CODE[4:1] may change from 0001 with respect to the time point T2 (2) to 0010 (2) . Refer to Figure 4 , the code bit CODE[2] (or Q[2]) may be output by the flip-flop 111_2 after the output time of the code bit CODE[1].

[0059] The time difference between the time point T2 and the output time of the code bit CODE[1] may be tD1. The time difference between the output time of the code bit CODE[1] and the output time of the code bit CODE[2] may be the sum of the propagation delay of the inverter 112_1 and the CK-Q delay of the flip-flop 111_2. The time difference between the time point T2 and the output time of the code bit CODE[2] may be tD2. The time difference tD2 may correspond to the CK-Q delay of the flip-flop 111_1, the propagation delay of the inverter 112_1, and the CK-Q delay of the flip-flop 111_2. The asynchronous counter 110c may asynchronously output the code bits CODE[2:1]. In the case where the inverter 112_1 is not included in the asynchronous counter 110c, the propagation delay of the inverter 112_1 may not be applied to the above time difference.

[0060] The operation of the asynchronous counter 110c at each time point from time point T3 to time point T8 is substantially the same as the operation of the asynchronous counter 110c at time point T1 or time point T2. The value of the code bits CODE[4:1] may change from 0010 with respect to the time point T3 (2) to 0011 (2) .

[0061] At time point T4, the flip - flops 121_1 and 121_2 of the synchronous counter 120a can latch the logical values of code bit CODE[3] and code bit CODE[4] respectively at the falling edge of the output signal Q[2] of the flip - flop 111_2 (i.e., CODE[2]). The flip - flop 121_1 can determine the logical value of code bit CODE[3] as "1" at the falling edge of the output signal Q[2] of the flip - flop 111_2. The flip - flop 121_2 can determine the logical value of code bit CODE[4] as "0" at the falling edge of the output signal Q[2] of the flip - flop 111_2. In this case, the combinational logic circuit 122 can output "0" as D[m + 2] with respect to time point T4. The value of code bits CODE[4:1] can change from 0011 with respect to time point T4 (2) to 0100 (2) .

[0062] The time difference between time point T4 and the output time of code bit CODE[1] can be tD1. The time difference between time point T4 and the output time of code bit CODE[2] can be tD2. The time difference between the output time of code bit CODE[2] and the output time of code bit CODE[3] can be the sum of the propagation delay of the inverter 112_2 and the CK - Q delay of the flip - flop 121_1. The time difference between time point T4 and the output time of code bit CODE[3] can be tD3. The time difference tD3 can correspond to the CK - Q delay of the flip - flop 111_1, the propagation delay of the inverter 112_1, the CK - Q delay of the flip - flop 111_2, the propagation delay of the inverter 112_2, and the CK - Q delay of the flip - flop 121_1. In the case where the inverters 112_1 and 112_2 are not included in the asynchronous counter 110c, the propagation delays of the inverters 112_1 and 112_2 may not be applied to the above - mentioned time differences.

[0063] The operation of the synchronous counter 120a at time point T8 is basically the same as the operation of the asynchronous counter 110c at time point T4. The value of code bits CODE[4:1] can change from 0100 with respect to time point T5 (2) to 0101 (2) . The value of code bits CODE[4:1] can change from 0101 with respect to time point T6 (2) to 0110 (2) . The value of code bits CODE[4:1] can change from 0110 with respect to time point T7 (2) to 0111 (2) . The value of code bits CODE[4:1] can change from 0111 with respect to time point T8 (2) to 1000 (2)。

[0064] The time difference between time point T4 and the output time of code bit CODE[1] may be tD1. The time difference between time point T4 and the output time of code bit CODE[2] may be tD2. The time difference between time point T4 and the output time of code bit CODE[3] may be tD3. The time difference between time point T4 and the output time of code bit CODE[4] may be tD3. The asynchronous counter 110c may asynchronously output code bits CODE[2:1]. The synchronous counter 120a may synchronously output code bits CODE[4:3].

[0065] Figure 5 illustrates an Figure 1 asynchronous counter according to an example embodiment. The asynchronous counter 110d may be Figure 1 another example of the asynchronous counter 110. The differences between the asynchronous counter 110d and the asynchronous counter 110c will be mainly described. The asynchronous counter 110d may include flip-flops 111_1 to flip-flops 111_m and inverters 112_1 to inverters 112_m. Compared with the asynchronous counter 110c, the asynchronous counter 110d may further include delay circuits 113_1 to delay circuits 113_m.

[0066] The delay circuits 113_1 to delay circuits 113_m may respectively delay the output signals Q[m:1] of the flip-flops 111_1 to flip-flops 111_m and may output the code bits CODE[m:1] simultaneously or synchronously. The code bits CODE[m:1] may correspond to the signals obtained by delaying the output signals Q[m:1]. For example, the delay circuits 113_1 to delay circuits 113_m may delay the output signals Q[m:1] such that the code bits CODE[m:1] are output synchronously (or simultaneously). The delays performed by the delay circuits 113_1 to delay circuits 113_m in delaying the output signals Q[m:1] of the flip-flops 111_1 to flip-flops 111_m may be different from each other.

[0067] Delay circuits 113_1 through 113_m can delay output signal Q[m:1] so that code bit CODE[m:1] is output simultaneously at the same time as code bits [m+1:m+n]. For example, delay circuit 113_1 can delay output signal Q[1] by the sum of the CK-Q delay of flip-flops 111_2 through 111_m, the propagation delay of inverters 112_1 through 112_m, and the CK-Q delay of flip-flop 121_1. Delay circuit 113_1 can be a replica circuit implemented by replicating flip-flops 111_2 through 111_m, inverters 112_1 through 112_m, and flip-flop 121_1. In the case where the inverters 112_1 to 112_m are not included in the flip-flops 111_1 to 111_m, the delay circuit 113_1 may delay the output signal Q[1] by as much as the sum of the CK-Q delay of the flip-flops 111_2 to 111_m and the CK-Q delay of the flip-flop 121_1.

[0068] Delay circuit 113_2 can delay output signal Q[2] by the sum of the C-Q delay from flip-flop 111_3 to flip-flop 111_m, the propagation delay from inverter 112_2 to inverter 112_m, and the C-Q delay of flip-flop 121_1. Delay circuit 113_2 can be a replica circuit implemented by replicating flip-flops 111_3 to 111_m, inverters 112_2 to 112_m, and flip-flop 121_1. Delay circuit 113_m can delay output signal Q[m] by the sum of the propagation delay of inverter 112_m and the C-Q delay of flip-flop 121_1. For example, the difference between the delay of delay circuit 113_m and the delay of delay circuit 113_m-1 can correspond to the sum of the propagation delay of inverter 112_m-1 and the C-Q delay of flip-flop 111_m. The delay of the delay circuit 113_1 may be the largest, and the delay of the delay circuit 113_m may be the smallest. As "m" increases, the delay of the delay circuit 113_m may gradually decrease.

[0069] Figure 6 is a diagram showing a method according to an example embodiment Figure 1 The timing diagram of the operation of the code generator will refer to Figure 1 、 Figure 3 and Figure 5 To describe Figure 6 .exist Figure 6 middle, Figure 1 The asynchronous counter 110 is Figure 5 The asynchronous counter 110d, Figure 1 The synchronous counter 120 is Figure 3 The synchronous counter 120a is configured as follows, and "m" and "n" are 2 respectively. Next, the timing will be described.Figure 6 and the timing sequence Figure 4 between them.

[0070] The flip-flop 111_1 of the asynchronous counter 110d can switch the logical value of the code bit CODE[1] from 0 to 1 at the rising edge of the clock signal CK1 (time point T1). The time difference between the time point T1 and the output time of the code bit CODE[1] can correspond to tD3 instead of tD1 through the delay circuit 113_1. The time difference tD3 can correspond to the sum of the CK-Q delay of the flip-flop 111_1, the propagation delay of the inverter 112_1, the CK-Q delay of the flip-flop 111_2, the propagation delay of the inverter 112_2, and the CK-Q delay of the flip-flop 121_1. The delay of the delay circuit 113_1 can correspond to the sum of the propagation delay of the inverter 112_1, the CK-Q delay of the flip-flop 111_2, the propagation delay of the inverter 112_2, and the CK-Q delay of the flip-flop 121_1.

[0071] The flip-flop 111_1 of the asynchronous counter 110d can switch the logical value of the code bit CODE[1] from 1 to 0 at the rising edge of the clock signal CK1 (time point T8). The flip-flop 111_2 of the asynchronous counter 110d can switch the logical value of the code bit CODE[2] from 1 to 0 at the rising edge of the clock signal CK1 (time point T8). The time difference between the time point T8 and the output time of the code bit CODE[1] can be tD3. The time difference between the time point T8 and the output time of the code bit CODE[2] can be tD3. According to the exemplary embodiment, the asynchronous counter 110d can switch the logical values of the code bit CODE[1] and the code bit CODE[2] simultaneously.

[0072] The flip-flop 111_2 of the asynchronous counter 110d can switch the logical value of the code bit CODE[2] from 0 to 1 at the rising edge of the clock signal CK1 (time point T2). The time difference between the time point T2 and the output time of the code bit CODE[2] can correspond to tD3 instead of tD2 through the delay circuit 113_2. The delay of the delay circuit 113_2 can correspond to the sum of the propagation delay of the inverter 112_2 and the CK-Q delay of the flip-flop 121_1. Different from the asynchronous counter 110c, the asynchronous counter 110d can synchronize the output code bits CODE[2:1] by using the delay circuit 113_1 and the delay circuit 113_2.

[0073] The flip-flop 121_1 of the synchronous counter 120a can switch the logical value of the code bit CODE[3] from 1 to 0 at the rising edge of the clock signal CK1 (time point T8). The flip-flop 121_2 of the synchronous counter 120a can switch the logical value of the code bit CODE[4] from 0 to 1 at the rising edge of the clock signal CK1 (time point T8). The time difference between the time point T8 and the output time of the code bit CODE[3] can be tD3. The time difference between the time point T8 and the output time of the code bit CODE[4] can be tD3. According to the exemplary embodiment, the synchronous counter 120a can switch the logical values of the code bit CODE[3] and the code bit CODE[4] simultaneously.

[0074] According to the exemplary embodiment, the code generator 100 including the asynchronous counter 110d and the synchronous counter 120a can switch the logical values of each of the code bits CODE[1] to CODE[4] simultaneously at the rising edge of the clock signal CK1.

[0075] Figure 7 Illustrated is according to the exemplary embodiment in Figures 2A to 2C , Figure 3 and Figure 5 the flip-flops shown in. Figure 7 The flip-flop 111 of can be one of the flip-flops 111_1 to 111_m of the asynchronous counters 110a to 110c and can be a T flip-flop. Figure 7 The flip-flop 121 of can be one of the flip-flops 121_1 to 121_n of the synchronous counter 120a and can be a D flip-flop. Referring to Figure 7 , when the inverted output port Qb of the flip-flop 121 is fed back to the input port "D" or can be electrically connected to the input port "D", the flip-flop 121 can operate in the same manner as the flip-flop 111. For example, the flip-flops 111_1 to 111_m of the asynchronous counters 110a to 110c can be respectively implemented by using the flip-flop 121, where the output port Qb is electrically connected to the input port "D".

[0076] Figure 8 Illustrated is according to the exemplary embodiment of Figure 1 the synchronous counter. The synchronous counter 120b can be Figure 1 an example of the synchronous counter 120 of. In Figure 8In this case, assume that “n” is 4. The synchronous counter 120b may include flip-flops 121_1 to 121_4 and combinational logic circuit 122b. The flip-flops 121_1 to 121_n of the synchronous counter 120a may be the same as the flip-flops 121_1 to 121_4 of the synchronous counter 120b. The combinational logic circuit 122b may be Figure 3 an example of the combinational logic circuit 122.

[0077] The combinational logic circuit 122b may include at least one or more logic gates that perform a logical operation on the inverted output signals Qb[m + 4:m + 1] of the flip-flops 121_1 to 121_4. The combinational logic circuit 122b may include an XOR gate XOR1 that performs an exclusive OR (XOR) operation on the inverted output signal Qb[m + 1] and the inverted output signal Qb[m + 2]. The output signal of the XOR gate XOR1 may be sent to the input port “D” of the flip-flop 121_2. The combinational logic circuit 122b may include a NOR gate NOR1 that performs a NOR operation on the inverted output signal Qb[m + 1] and the inverted output signal Qb[m + 2]. The combinational logic circuit 122b may include an XOR gate XOR2 that performs an XOR operation on the output signal of the NOR gate NOR1 and the inverted output signal Qb[m + 3]. The output signal of the XOR gate XOR2 may be sent to the input port “D” of the flip-flop 121_3. The combinational logic circuit 122b may include a NOR gate NOR2 that performs a NOR operation on the inverted output signal Qb[m + 1] and the inverted output signal Qb[m + 2]. The combinational logic circuit 122b may include a NOR gate NOR3 that performs a NOR operation on the output signal of the NOR gate NOR2 and the inverted output signal Qb[m + 3]. The combinational logic circuit 122b may include an XOR gate XOR3 that performs an XOR operation on the output signal of the NOR gate NOR3 and the inverted output signal Qb[m + 4]. The output signal of the XOR gate XOR3 may be sent to the input port “D” of the flip-flop 121_4. The logical operations performed by the combinational logic circuit 122b and the logic gates included in the combinational logic circuit 122b are merely exemplary.

[0078] The synchronous counter 120b may have a critical path that starts from the inverted output port Qb of the flip-flop 121_1, passes through the combinational logic circuit 122b, and ends at the input port "D" of the flip-flop 121_4. The critical path of the synchronous counter 120b may become longer as "n" increases. When "n" is 4, the critical path may correspond to the path that starts from the inverted output port Qb of the flip-flop 121_1, passes through the logic gates NOR2, NOR3, and XOR3 of the combinational logic circuit 122b, and ends at the input port "D" of the flip-flop 121_4. The propagation delay of the critical path may correspond to the time required to propagate the inverted output signal Qb[m+1] output from the inverted output port Qb of the flip-flop 121_1 to the input port "D" of the flip-flop 121_4 through the logic gates NOR2, NOR3, and XOR3 of the combinational logic circuit 122b.

[0079] The synchronous counter 120b may receive a clock signal CK2, which is the result of dividing the clock signal CK1 by the asynchronous counter 110. The speed of the clock signal CK2 may be lower than the speed of the clock signal CK1. The clock signal CK2 may have a frequency lower than that of the clock signal CK1 and may have a period greater than that of the clock signal CK1. The synchronous counter 120b may operate based on the clock signal CK2. For example, the period of the clock signal CK2 may be equal to or greater than the sum of the CK-Q delay of the flip-flop 121_1, the propagation delay of the critical path, and the setup time of the flip-flop 121_4. Here, "m", which is the number of code bits CODE[m:1] output from the asynchronous counter, may be determined according to the propagation delay of the critical path of the synchronous counter 120b. For example, when the period of the clock signal CK1 is "P", "P×m" may be equal to or greater than the propagation delay of the critical path.

[0080] The code generator 100 may solve the limitation on the frequency of the clock signal caused by the critical path by using a hybrid counter including both the asynchronous counter 110 and the synchronous counter 120. Moreover, the code generator 100 may synchronize the output code bits CODE[m+n:1] by using the delay circuits 113_1 to 113_m of both the asynchronous counter 110 and the synchronous counter 120. Compared with the case of using only the asynchronous counter 110, the code generator 100 may include or use a smaller number of delay circuits than the number of the delay circuits 113_1 to 113_m. Even when the number of the code bits CODE[m+n:1] increases, the code generator 100 may adjust the time of the output code bits CODE[m+n:1] to be the same by using the hybrid counter.

[0081] Figure 9A block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown. The differences between the code generator 100 and the code generator 200 will be mainly described. The code generator 200 may include an asynchronous counter 210, a synchronous counter 220, and an asynchronous counter 230. The asynchronous counter 210 and the synchronous counter 220 may be substantially the same as the asynchronous counter and the synchronous counter described with reference to Figure 1 , Figures 2A to 2C , Figure 3 , Figure 5 , Figure 7 and Figure 8 .

[0082] The asynchronous counter 230 may receive a clock signal CK3 and may output or generate a code bit CODE[m + n + 1:m + n + 1] based on the clock signal CK3. For example, "l" may be an integer of 2 or greater, "m" and "n" may be equal or unequal, and the asynchronous counter 230 may output a plurality of bits. With respect to the code bit CODE[m + n:1], the code bit CODE[m + n + 1:m + n + 1] may be a high bit. The asynchronous counter 230 may operate substantially the same as the asynchronous counter 210 except for receiving the clock signal CK3. The clock signal CK3 may be the same as the clock signal CK2 or may correspond to a clock signal obtained by buffering the clock signal CK2.

[0083] Figure 10 A block diagram of a code generator according to an exemplary embodiment of the inventive concept is shown. The differences between the code generator 100 and the code generator 300 will be mainly described. The code generator 300 may include a synchronous counter 310, an asynchronous counter 320, and a synchronous counter 330. The asynchronous counter 320 and the synchronous counter 330 may be substantially the same as the asynchronous counter and the synchronous counter described with reference to Figure 1 , Figures 2A to 2C , Figure 3 , Figure 5 , Figure 7 and Figure 8 .

[0084] The synchronous counter 310 may receive the clock signal CK1 and may output or generate code bits CODE[m:1] based on the clock signal CK1. The asynchronous counter 320 may receive the clock signal CK2 and may output or generate code bits CODE[m+n:m+1] based on the clock signal CK2. The clock signal CK2 may be the same as the clock signal CK1 or may correspond to a clock signal obtained by buffering the clock signal CK1. The synchronous counter 330 may receive the clock signal CK3 and may output or generate code bits CODE[m+n+1:m+n+1] based on the clock signal CK3. The clock signal CK3 may correspond to a signal obtained by dividing the clock signal CK2 by the asynchronous counter 320. Figure 10 In , "m", "n" and "1" may be integers of 2 or more and may be equal to or different from each other.

[0085] Figure 11 1 and 2. A block diagram of a code generator according to an exemplary embodiment of the present inventive concept is shown. Differences between the code generator 100 and the code generator 400 will be mainly described.

[0086] The code generator 400 may include an asynchronous counter 410, a synchronous counter 420, and a code converter 430. The asynchronous counter 410 and the synchronous counter 420 may be connected to a reference Figure 1 、 Figures 2A to 2C , Figure 3 、 Figure 5 、 Figure 7 as well as Figure 8 The asynchronous counter and synchronous counter described are basically the same. The code converter 430 can convert the binary code BCODE into the Gray code GCODE. The binary code bit BCODE[m+n:1] can be compared with the reference Figure 1 、 Figures 2A to 2C 、 Figure 3 、 Figure 5 、 Figure 7 and Figure 8 The described code bits CODE[m+n:1] are the same. For example, the code generator 400 may output a binary code BCODE, may output a Gray code GCODE, or may output both the binary code BCODE and the Gray code GCODE.

[0087] Figure 12 According to an example embodiment, Figure 11Block diagram of a code converter. The code converter 430 may include flip-flops 431_1 to 431_m+n-1 and a delay circuit 431_m+n. Each of the flip-flops 431_1 to 431_m+n-1 may include a clock port, a reset port "R", and an output port "Q". Each of the flip-flops 431_1 to 431_m+n-1 may also include an input port and an inverted output port (not shown). The inverted output port of each of the flip-flops 431_1 to 431_m+n-1 may be electrically connected to the input port of that flip-flop. For example, each of the flip-flops 431_1 to 431_m+n-1 may be the above-mentioned T flip-flop. The flip-flops 431_1 to 431_m+n-1 may receive a clock signal (or the output signals of the asynchronous counter 410 and the synchronous counter 420) having binary code bits BCODE[m+n-1:1] through the clock port. The binary code bits BCODE[m+n-1:1] received by the flip-flops 431_1 to 431_m+n-1 may not include the MSB BCODE[m+n] of all the binary code bits BCODE[m+n:1]. The flip-flops 431_1 to 431_m+n-1 may switch the logical values of the Gray code bits GCODE[m+n:1] at the edges of the clock signal. For example, the flip-flops 431_1 to 431_m+n-1 may be implemented to be the same as each other.

[0088] The delay circuit 431_m+n may receive the binary code bit BCODE[m+n] as a clock signal and may output the received clock signal as the Gray code bit GCODE[m+n] without modification. The delay circuit 431_m+n may be a replication circuit implemented by replicating one of the flip-flops 431_1 to 431_m+n-1. The delay circuit 431_m+n may delay the received clock signal by up to the CK-Q delay of each of the flip-flops 431_1 to 431_m+n-1. For example, the binary code bit BCODE[m+n] and the Gray code bit GCODE[m+n] may be the same and may correspond to the MSB of the binary code BCODE and the Gray code GCODE.

[0089] The flip-flops 431_1 to 431_m+n-1 and the delay circuit 431_m+n may jointly receive a reset signal RESET. The reset operation of the flip-flops 431_1 to 431_m+n-1 and the delay circuit 431_m+n may be the same as that in reference Figures 2A to 2C and Figure 3The described reset operations are the same. For example, a reset signal RESET can be provided to the asynchronous counter 410, the synchronous counter 420, and the code converter 430 together. For another example, reset signals can be provided to the asynchronous counter 410, the synchronous counter 420, and the code converter 430 separately.

[0090] Figure 13 is a timing diagram showing the operation of the code converter according to an exemplary embodiment. It will be described with reference to Figure 11 and Figure 12 together. Figure 11 and Figure 12 will be described Figure 13 . Figure 13 The time points T1 to T8 of Figure 4 and Figure 6 are different from the time points T1 to T8 of Figure 13 . For ease of description, it is assumed that "m + n" is 3 in

[0091] At time point T1, the logical value of the binary code bit BCODE[1] can be switched from 0 to 1. The flip - flop 431_1 of the code converter 430 can switch the logical value of the Gray code bit GCODE[1] from 0 to 1 at the edge of the output signal having the binary code bit BCODE[1] (time point T1). The time difference between the output time of the binary code bit BCODE[1] and the output time of the Gray code bit GCODE[1] can correspond to the CK - Q delay of the flip - flop 431_1. The logical values of the remaining Gray code bits GCODE[2] and Gray code bits GCODE[3] can remain. The value of the Gray code bits GCODE[3:1] can be updated from 000 (2) to 001 (2) .

[0092] At time point T2, the logical value of the binary code bit BCODE[2] can be switched from 0 to 1. The flip - flop 431_2 of the code converter 430 can switch the logical value of the Gray code bit GCODE[2] from 0 to 1 at the edge of the output signal having the binary code bit BCODE[2] (time point T2). The time difference between the output time of the binary code bit BCODE[2] and the output time of the Gray code bit GCODE[2] can correspond to the CK - Q delay of the flip - flop 431_2. The logical values of the remaining Gray code bits GCODE[1] and Gray code bits GCODE[3] can remain. The value of the Gray code bits GCODE[3:1] can be updated from 001 (2) to 011 (2) .

[0093] The operation of the flip-flop 431_1 at time point T3 can be the same as the operation of the flip-flop 431_1 at time T1. The value of the Gray code bits GCODE[3:1] can be updated from 011 (2) to 010 (2) at time point T3. At time point T4, the logical value of the binary code bit BCODE[3] can be switched from 0 to 1. The delay circuit 431_3 of the code converter 430 can output the binary code bit BCODE[3] as the Gray code bit GCODE[3] without modification. The time difference between the output time of the binary code bit BCODE[3] and the output time of the Gray code bit GCODE[3] can correspond to the CK-Q delay of each of the flip-flops 431_1 and 431_2 (i.e., the delay of the delay circuit 431_3). The logical values of the remaining Gray code bits GCODE[1] and GCODE[2] can be maintained. The value of the Gray code bits GCODE[3:1] can be updated from 010 (2) to 110 (2) at time point T4.

[0094] The operation of the code converter 430 from time point T5 to time point T8 is substantially the same as the operation of the code converter 430 from time point T1 to time point T4. The value of the Gray code bits GCODE[3:1] can be updated from 110 (2) to 111 (2) at time point T5. The value of the Gray code bits GCODE[3:1] can be updated from 111 (2) to 101 (2) at time point T6. The value of the Gray code bits GCODE[3:1] can be updated from 101 (2) to 100 (2) at time point T7. The value of the Gray code bits GCODE[3:1] can be updated from 100 (2) to 000 (2) at time point T8.

[0095] Figure 14 FIG. shows a flowchart of a code generator according to an exemplary embodiment of the inventive concept. Figure 14 The flowchart of Figure 1 can be associated with Figure 14 the code generator 100 of Figure 9 . However, Figure 10 the flowchart of Figure 11 can also be applied to Figure 1 the code generator 200, Figures 2A to 2C the code generator 300, Figures 3 to 13 and Figure 14。

[0096] In operation S110, the code generator 100 may receive a clock signal. The clock signal may be the clock signal CK1 described in the reference Figure 1 In operation S120, the asynchronous counter 110 of the code generator 100 may generate the low bits CODE[m:1] of the code by dividing the clock signal CK1 using flip-flops 111_1 to 111_m. In operation S130, the synchronous counter 120 of the code generator 100 may generate the high bits CODE[m + n:m + 1] of the code at the edges of the divided clock signal by flip-flops 121_1 to 121_n. The divided clock signal may be the clock signal CK2 described in the reference Figure 1 For example, operation S130 may be performed after dividing the clock signal in operation S120. For example, in the case where the Figure 14 flowchart is applied to Figure 11 the code generator 400, after operation S130, the code generator 400 may convert the binary code generated by operations S120 and S130 into a Gray code.

[0097] Figure 15 FIG. shows a block diagram of an image sensor to which a code generator according to an exemplary embodiment of the present inventive concept is applied. The image sensor 1000 may include a pixel array 1100, a row driver 1200, an analog-to-digital converter (ADC) 1300, and a timing controller 1400. Although not shown in Figure 15 , the image sensor 1000 may further include a processor such as an image signal processor (ISP) that processes image data from the ADC 1300. According to an exemplary embodiment, Figure 15 the components of the image sensor 1000 of

[0098] The pixel array 1100 may include pixels (not shown) arranged in a row direction and a column direction and convert incident light into an electrical signal. Under the control of the timing controller 1400, the row driver 1200 may decode a row address and may select and control the pixels corresponding to the row address. The row driver 1200 may send a control signal to the selected pixels. Under the control of the timing controller 1400, the ADC 1300 may generate a digital code corresponding to an output signal (e.g., an analog signal) output from the pixel array 1100. For example, the ADC 1300 may perform dual sampling and holding on the output signal. The ADC 1300 may perform correlated double sampling. The ADC 1300 may convert the level difference of the double-sampled output signal into a digital code. The timing controller 1400 may control the row driver 1200 and the ADC 1300. The timing controller 1400 may receive image data from the ADC 1300. The timing controller 1400 may provide the image data sensed by the image sensor 1000 to an external device in response to a request for the external device to communicate with the image sensor 1000.

[0099] Figure 16 A block diagram of a display device is shown, to which a code generator according to an exemplary embodiment of the present inventive concept is applied. The display device 2000 may include a display panel 2100, a gate driver 2200, a data driver 2300, and a timing controller 2400. According to the exemplary embodiment, Figure 16 the components of the display device 2000 may include and use one of the code generators 100, 200, 300, and 400 disclosed herein.

[0100] The display panel 2100 may display an image. The display panel 2100 may be implemented with a liquid crystal display (LCD) panel, a light emitting diode (LED) display panel, an organic LED (OLED) panel, an active matrix OLED (AMOLED) display panel, a flexible display panel, or the like. Alternatively, the display panel 2100 may be implemented with a flat display panel of a type different from the above display panels. The display panel 2100 may include pixels arranged in a row direction and a column direction and be driven by the gate driver 2200 and the data driver 2300 to display an image corresponding to pixel data.

[0101] The gate driver 2200 may drive gate lines (not shown) of pixels connected to the display panel 2100 and may select pixels. The data driver 2300 may drive data lines of pixels connected to the display panel 2100. The data driver 2300 may send a Gray voltage corresponding to pixel data to the pixels. For example, a pixel may include a thin film transistor, and a liquid crystal capacitor and a storage capacitor connected to a drain electrode of the thin film transistor. The Gray voltage may be applied to the capacitors of the pixels.

[0102] The timing controller 2400 may receive pixel data (or, image data) from an external device communicating with the display device 2000. The timing controller 2400 may control the gate driver 2200 and the data driver 2300.

[0103] Figure 17 A block diagram of an electronic device is shown to which a code generator according to an exemplary embodiment of the inventive concept is applied. The electronic device 3000 may be implemented with a data processing device capable of using or supporting an interface protocol proposed by the Mobile Industry Processor Interface (MIPI) Alliance and may be referred to as a “computer system”. For example, the electronic device 3000 may be one of electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smart phone, a tablet PC, and a wearable device. According to an exemplary embodiment, Figure 17 the components of the electronic device 3000 may include and use one of the code generators 100, 200, 300, and 400 disclosed herein.

[0104] The electronic device 3000 may include an application processor 3100, a display 3220, and an image sensor 3230. The application processor 3100 may include a DigRF master 3110, a Display Serial Interface (DSI) host 3120, a Camera Serial Interface (CSI) host 3130, and a physical layer 3140.

[0105] The DSI host 3120 can communicate with the DSI device 3225 of the display 3220 in accordance with DSI. For example, the serializer SER can be implemented in the DSI host 3120, and the deserializer DES can be implemented in the DSI device 3225. The CSI host 3130 can communicate with the CSI device 3235 of the image sensor 3230 via CSI. For example, the deserializer DES can be implemented in the CSI host 3130, and the serializer SER can be implemented in the CSI device 3235. The electronic device 3000 may further include an RF (radio frequency) chip 3240 that communicates with the application processor 3100. The RF chip 3240 may include a physical layer 3242, a DigRF slave device 3244, and an antenna 3246. For example, the physical layer 3242 of the RF chip 3240 and the physical layer 3140 of the application processor 3100 may exchange data with each other through the DigRF interface proposed by the MIPI Alliance.

[0106] The electronic device 3000 may further include a working memory 3250, an embedded storage device 3251, and a card storage device 3252. The working memory 3250, the embedded storage device 3251, and the card storage device 3252 may store or output data for the application processor 3100. The working memory 3250 may temporarily store data that has been or is to be processed by the application processor 3100. The working memory 3250 may include volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM)) and / or non-volatile memory (e.g., flash memory, phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM)). The embedded storage device 3251 and the card storage device 3252 may store data regardless of whether power is supplied to them. The electronic device 3000 may communicate with an external device / system through a communication module that is a communication module based on Worldwide Interoperability for Microwave Access (WiMAX) 3260, Wireless Local Area Network (WLAN) 3262, or Ultra-Wideband (UWB) 3264. Additionally, the electronic device 3000 may communicate with an external device / system based on at least one of various wireless communication protocols such as Long Term Evolution (LTE), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID) and / or various wired communication protocols such as Transmission Control Protocol / Internet Protocol (TCP / IP), USB, SCSI, Mobile PCIe (M-PCIe), and Firewire. The electronic device 3000 may further include a speaker 3270 and a microphone 3275 for processing voice information. Additionally, the electronic device 3000 may further include a Global Positioning System (GPS) device 3280 for processing location information. The electronic device 3000 may further include a bridge chip 3290 for managing connections with peripheral devices.

[0107] A code generator according to an embodiment of the inventive concept may output a code by using a hybrid counter including an asynchronous counter and a synchronous counter. The code generator may solve the limitation on the frequency of a clock signal caused by the synchronous counter and the variation in code output caused by the asynchronous counter. Accordingly, the code generator may operate even under the conditions of high speed and low power voltage.

[0108] Although the inventive concept has been described with reference to exemplary embodiments of the present invention, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A code generator, comprising: An asynchronous counter, including a first flip - flop to an m - th flip - flop, where the first flip - flop to the m - th flip - flop are configured to asynchronously output a first output signal to an m - th output signal, and the first output signal to the m - th output signal respectively correspond to the first bit to the m - th bit of the code, and m is an integer of 2 or greater; And A synchronous counter, including a (m + 1)-th flip - flop to a (m + n)-th flip - flop, where the (m + 1)-th flip - flop to the (m + n)-th flip - flop are configured to synchronously output a (m + 1)-th output signal to a (m + n)-th output signal, and the (m + 1)-th output signal to the (m + n)-th output signal correspond to the (m + 1)-th bit to the (m + n)-th bit of the code, and n is an integer of 2 or greater, wherein the asynchronous counter further includes a first delay circuit to an m - th delay circuit, and the first delay circuit to the m - th delay circuit are configured to respectively delay the first output signal to the m - th output signal, such that when the (m + 1)-th bit to the (m + n)-th bit are output, the first bit to the m - th bit of the code are output simultaneously.

2. The code generator according to claim 1, wherein the first flip - flop of the asynchronous counter is further configured to receive a first clock signal, wherein the second flip - flop to the m - th flip - flop of the asynchronous counter are further configured to respectively receive the inverted signals of the first output signal to the (m - 1)-th output signal, and wherein each of the (m + 1)-th flip - flop to the (m + n)-th flip - flop of the synchronous counter is further configured to receive the inverted signal of the m - th output signal as a second clock signal.

3. The code generator according to claim 1, wherein the delay times of the first output signal to the m - th output signal delayed by the first delay circuit to the m - th delay circuit are different from each other.

4. The code generator according to claim 1, wherein the first flip - flop of the asynchronous counter is further configured to switch the logic value of the first bit of the code at the edge of the first clock signal, and wherein the m - th flip - flop of the asynchronous counter is further configured to switch the logic value of the m - th bit of the code at the edge of the (m - 1)-th output signal.

5. The code generator according to claim 1, wherein the (m + 1)-th flip - flop of the synchronous counter is further configured to switch the logic value of the (m + 1)-th bit of the code at the edge of the m - th output signal, and wherein the (m + 2)-th flip - flop to the (m + n)-th flip - flop of the synchronous counter are further configured to respectively latch the logic values of the (m + 2)-th bit to the (m + n)-th bit of the code at the edge of the m - th output signal.

6. The code generator according to claim 1, wherein the first flip - flop to the m - th flip - flop of the asynchronous counter and the (m + 1)-th flip - flop of the synchronous counter are implemented to be the same as each other.

7. The code generator according to claim 1, wherein the synchronous counter further comprises: A combinational logic circuit, configured to perform a logic operation on the (m + 1)-th output signal to the (m + n)-th output signal; And wherein the period of the m-th output signal is greater than the propagation delay of the combinational logic circuit.

8. The code generator according to claim 1, wherein the asynchronous counter further comprises: A driver configured to drive the m-th output signal to be sent to the (m + 1)-th flip-flop to the (m + n)-th flip-flop of the synchronous counter.

9. The code generator according to claim 1, wherein the code is a binary code, and wherein the first bit to the m-th bit output by the asynchronous counter are the low bits of the binary code, and the (m + 1)-th bit to the (m + n)-th bit output by the synchronous counter are the high bits of the binary code.

10. The code generator according to claim 1, wherein the first flip-flop of the asynchronous counter is configured to receive a clock signal without receiving the inverted clock signal.

11. A code generator, comprising: An asynchronous counter configured to receive a first clock signal and respectively output a first output signal corresponding to the first bit of a binary code based on the first clock signal; A synchronous counter configured to respectively output a second output signal corresponding to the second bit of the binary code based on a second clock signal obtained by dividing the first clock signal by the asynchronous counter; And A code converter configured to receive the first bit and the second bit of the binary code and convert the binary code into a Gray code, wherein the code converter includes: A plurality of first flip-flops configured to switch the logical values of the bits of the Gray code except the most significant bit (MSB) of the Gray code at the edges of output signals respectively corresponding to the bits of the first bit and the second bit of the binary code except the MSB of the binary code, and A delay circuit configured to delay the output signal corresponding to the MSB of the binary code and output the MSB of the Gray code.

12. The code generator according to claim 11, wherein each of the plurality of first flip - flops includes: A clock port receiving each of the first output signal and the second output signal; An output port outputting each of the logical values; An inverted output port outputting each of the inverted logical values; And an input port electrically connected to the inverted output port.

13. The code generator according to claim 11, wherein the asynchronous counter comprises: A plurality of second flip-flops configured to asynchronously output the first bit of the binary code based on the first clock signal, and wherein the synchronous counter includes: a plurality of third flip-flops configured to synchronously output the second bit of the binary code based on the second clock signal.

14. The code generator according to claim 11, wherein the asynchronous counter includes: A plurality of second flip-flops configured to asynchronously output the first output signal based on the first clock signal; And A plurality of delay circuits configured to respectively delay the first output signal and synchronously output the first bit of the binary code, and wherein the synchronous counter includes: a plurality of third flip-flops configured to synchronously output the second output signal corresponding to the second bit of the binary code based on the second clock signal.

15. A method of operating a code generator, the method comprising: Receiving a first clock signal; Outputting a first output signal based on the first clock signal by using a first flip-flop; Dividing the frequency of the first clock signal by using a second flip-flop to an m-th flip-flop to output a second output signal to an m-th output signal, where m is an integer greater than or equal to 2; Delaying the first output signal to the m-th output signal corresponding to the first bit to the m-th bit of the code respectively by a first delay circuit to an m-th delay circuit; And At the edge of a second clock signal generated by dividing the first clock signal by using the first flip-flop to the m-th flip-flop, synchronously outputting a (m + 1)-th output signal to a (m + n)-th output signal corresponding to the (m + 1)-th bit to the (m + n)-th bit of the code by using a (m + 1)-th flip-flop to a (m + n)-th flip-flop, where n is an integer greater than or equal to 2.

16. The method of operation according to claim 15, wherein outputting the second output signal to the m-th output signal comprises: Outputting a second output signal of a second flip-flop at the edge of the first output signal of the first flip-flop; And Outputting the m-th output signal at the edge of the (m - 1)-th output signal of the (m - 1)-th flip-flop after the edge of the first clock signal.

17. The method of operation according to claim 15, wherein the first output signal to the m-th output signal are output sequentially, and wherein the (m + 1)-th output signal to the (m + n)-th output signal are output simultaneously.

18. The method of operation according to claim 15, wherein the (m + 1)-th output signal to the (m + n)-th output signal are output after the first output signal to the m-th output signal are output.

19. The method of operation according to claim 15, further comprising: Converting the code to a Gray code by using a code converter, wherein the code is a binary code.

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