A servo drive that supports multiple encoder protocols

Abstract

The present invention relates to a servo driver supporting multiple encoder protocols. The servo driver supporting multiple encoder protocols is based on a DSP+FPGA servo driver control architecture, uses a low-cost solid-state memory, and can support multiple encoder communication protocols without adding additional hardware and interfaces, so that the entire system has the characteristics of simple structure and low cost.

Description

Technical Field

[0001] The present invention relates to the field of encoder driving, and in particular to a servo driver supporting multiple encoder protocols. Background Art

[0002] In servo control systems, encoders are often used as position detection components. Different application systems will select different encoders according to design requirements, and different encoders often support different communication protocols. When a servo drive is used in a multi-encoder system and an external encoder needs to be replaced, the drive needs to be replaced or the Field-Programmable Gate Array (FPGA) firmware needs to be re-downloaded.

[0003] In the prior art, patent CN206563893U mentions a data transmission system that uses multiple encoder interface circuits to support multiple encoders at the same time. The encoder module can expand more encoder channels by cascading. While supporting multiple encoders, this patent requires multiple external encoder interfaces, which makes the hardware structure complex and increases the system cost.

[0004] The servo controller in patent CN206848742U needs to re-download the FPGA firmware when supporting multiple communication protocol encoders, without replacing the servo control circuit board. This patent requires re-downloading the FPGA firmware that supports different communication protocols to support different encoders. It is troublesome to download the program at some customer application sites, and when the number of drives is large, it affects the debugging efficiency.

[0005] Patent CN202710997U mentions that when the servo controller supports multiple communication protocol encoders, there is no need to replace the servo control circuit board, but the FPGA firmware needs to be re-downloaded. For customer sites with complex servo drive installations, when encoders with different communication protocols need to be replaced, the device must be disassembled and the FPGA firmware must be re-downloaded, which greatly increases the workload of product maintenance and reduces production efficiency. Summary of the invention

[0006] The object of the present invention is to provide a servo driver which supports multiple encoder protocols and has the characteristics of simple structure, low cost, etc. on the basis of supporting the use of multiple encoders.

[0007] To achieve the above object, the present invention provides the following solutions:

[0008] A servo driver supporting multiple encoder protocols, including: an encoder interface, FPGA, DSP (Chinese full name: Digital Signal Processor, English full name: Digital Signal Process) and solid-state memory (Flash);

[0009] The encoder interface is connected to the FPGA; the FPGA is connected to the DSP and the solid-state memory respectively; the DSP is connected to the solid-state memory;

[0010] The solid-state memory is used to store FPGA program data of multiple encoder communication protocols, and the encoder communication protocols corresponding to the program data stored in the solid-state memory are all different; the encoder interface is used to connect the encoder to be driven; the DSP is used to generate a chip select signal according to the servo parameters to turn on or off the solid-state memory; the FPGA is used to read the program data stored in the solid-state memory, to determine the connected encoder communication protocol according to the servo parameters of the driver, to parse the transmission data of the encoder to be driven through the encoder data parsing function module, and to upload it to the DSP through the DSP data interaction function module; the DSP is used to exchange data with the FPGA through the FPGA interaction function module, and to update the servo drive data in real time according to the position data uploaded by the FPGA to drive the motor to run smoothly.

[0011] Preferably, the encoder interface is connected to the encoder data parsing module of the FPGA; the FPGA is connected to the DSP through an SPI interface, an nCFG interface and an Init interface; the SEL interface of the DSP is connected to the / CE signal of the solid-state memory through a switch selection device; the nCSC interface of the FPGA is connected to the / CE signal of the solid-state memory through a switch selection device.

[0012] Preferably, the solid-state memory comprises: a first solid-state memory and a second solid-state memory;

[0013] The / CE interface of the first solid-state memory and the / CE interface of the second solid-state memory are both connected to the SEL interface of the DSP through a signal switch selector; the data output interface of the first solid-state memory and the data output interface of the second solid-state memory are both connected to the nCSC interface of the FPGA through a switch selection device.

[0014] Preferably, when the SEL interface output value is 0, the first solid-state memory is turned on; when the SEL interface output value is 1, the second solid-state memory is turned on.

[0015] Preferably, it also includes a host computer;

[0016] The host computer is used to send a command to the DSP to update the encoder communication program data stored in the solid-state memory, thereby realizing the online upgrade of the FPGA.

[0017] Preferably, the number of the FPGA is 1.

[0018] Preferably, the number of the encoder interface is 1.

[0019] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: the servo drive supporting multiple encoder protocols provided by the present invention, the servo drive control architecture based on DSP+FPGA, and the use of low-cost solid-state memory can support multiple encoder communication protocols without adding additional hardware and interfaces, so that the entire system has the characteristics of simple structure and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 A structural schematic diagram of a servo driver supporting multiple encoder protocols provided by the present invention;

[0022] Figure 2 A control block diagram of a servo drive supporting multiple encoder protocols provided by the present invention;

[0023] Figure 3 This is a control block diagram of supporting the first solid-state storage by default in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the structure of the DSP after replacing the solid-state memory in the embodiment of the present invention;

[0025] Figure 5 This is a functional block diagram of encoder data processing in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The object of the present invention is to provide a servo driver which supports multiple encoder protocols and has the characteristics of simple structure, low cost, etc. on the basis of supporting the use of multiple encoders.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] Figure 1 The structural principle diagram of the servo driver supporting multiple encoder protocols provided by the present invention is a servo driver supporting multiple encoder protocols, including: an encoder interface, an FPGA, a DSP and a solid-state memory; wherein the number of the FPGA and the encoder interface is preferably 1.

[0030] The encoder interface is connected to the FPGA; the FPGA is connected to the DSP and the solid-state memory respectively; the DSP is connected to the solid-state memory;

[0031] The solid-state memory is used to store a variety of program data supporting encoder communication protocols, and the program data stored in the solid-state memory supports different encoder communication protocols; the encoder interface is used to read the position data collected by the encoder to be driven; the DSP is used to control the input value of the Flash chip select signal according to the servo parameter to turn on or off the solid-state memory; the FPGA is used to read the program data stored in the solid-state memory, parse the encoder data currently connected to the servo drive through the encoder data parsing module, and upload the parsed position data to the DSP through the DSP data interaction module; the DSP exchanges data with the FPGA through the FPGA interaction function module, and updates the servo drive data in real time according to the position data uploaded by the FPGA to drive the motor to run smoothly.

[0032] In the above technical solution provided by the present invention, the driver can support but is not limited to encoders of synchronous and asynchronous protocols such as Nikon, Tamagawa, Biss, SSI and Endat2.2.

[0033] Preferably, the encoder interface is connected to the encoder data parsing module of the FPGA; the FPGA is connected to the DSP via the SPI interface, the nCFG interface and the Init interface; the SEL interface of the DSP is connected to the / CE interface of the solid-state memory via a switch selector; the nCSC interface of the FPGA is connected to the / CE interface of the solid-state memory. The SPI communication between the DSP and the FPGA may use any other communication method.

[0034] In the DSP+FPGA-based servo drive control architecture, the solid-state memory can use two low-cost program storage chips Flash1 and Flash2 (first solid-state memory and second solid-state memory);

[0035] The / CE interface of the first solid-state memory and the / CE interface of the second solid-state memory are both connected to the SEL interface of the DSP through a switch selection device; the data output interface of the first solid-state memory and the data output interface of the second solid-state memory are both connected to the nCSC interface of the FPGA through a switch selection device.

[0036] Preferably, when the SEL interface output value is 0, the first solid-state memory is turned on; when the SEL interface output value is 1, the second solid-state memory is turned on.

[0037] In order to facilitate updating of the encoder communication protocol in the solid-state memory, the servo driver supporting multiple encoder protocols provided by the present invention further includes a host computer;

[0038] The solid-state memory is implanted in the host computer; the host computer is used to update the encoder communication protocol stored in the solid-state memory.

[0039] The present invention not only supports encoders of asynchronous communication protocols, but also supports encoders of synchronous communication protocols, thereby expanding the adaptability of the driver.

[0040] At the same time, the present invention can also realize the online upgrade of FPGA. Through the switching of Flash, the reliability of the online upgrade of FPGA can be improved.

[0041] The advantages of the present invention are further described below based on the working principle of the servo driver supporting multiple encoder protocols provided by the present invention.

[0042] like Figure 2 As shown, based on the technical solution provided by the present invention, the DSP has the functions of servo drive, communication with the host, fault detection, interaction with FPGA, AD sampling, etc. After the FPGA analyzes the encoder data, it is uploaded to the DSP for servo control.

[0043] FPGA internal functional modules such as Figure 5 As shown, it includes an encoder data parsing module, a DSP data interaction module and other auxiliary function modules.

[0044] Flash1 and Flash2 store programs that support different encoders. Suppose Flash1 supports encoders A, B, C, and D, while Flash2 supports encoders E, F, and G. When SEL=0 in the system default DSP, Flash1 is selected as the default startup Flash of the FPGA. The driver supports encoders A, B, C, and D by default. Figure 3 shown.

[0045] When the system is powered on, if the driver uses the default servo parameters, the DSP outputs SEL=0 according to the driver's servo parameters, that is, the Flash1 chip select signal / CE is valid at this time. At the same time, the low-level pulse signal of nCFG is output, and the FPGA reads the program data from the Flash connected at this time and completes the self-startup. When the FPGA completes the initialization, the Init signal becomes a high level. After the DSP receives the Init high level, it believes that the FPGA has entered the normal working mode and can parse the external encoder data. At this time, the encoder types supported by the driver are: encoder A, encoder B, encoder C and encoder D.

[0046] When you need to replace an encoder with a different communication protocol, you only need to modify the encoder type of the servo parameters through the host computer. The DSP determines whether to switch the FPGA from Flash1 to the program in Flash2 based on the currently set servo parameters. Therefore, if you only need to change one of the A, B, C and D encoder types, keep SEL = 0; if you need to change to the program in Flash2, the SEL signal in the DSP is changed to SEL = 1. After the FPGA completes the restart, it can support encoder types of encoder E, encoder F and encoder G. When Flash2 is selected, the system function is shown in Figure 4 .

[0047] After the Flash is started and the FPGA is working normally, the encoder data analysis module analyzes the data of the supported encoder and uploads the real-time position value to the DSP through SPI communication.

[0048] When the FPGA program needs to be upgraded online, the DSP selects the Flash chip select signal / CE according to the encoder type setting value.

[0049] Assuming the current encoder type is set to A, and the customer needs to change the encoder to type B on site, the DSP output keeps SEL=0 and selects Flash1 ( Figure 1 ①), FPGA receives the upgrade data through SPI bus and writes it into the corresponding Flash1. DSP monitors the FPGA upgrade status and outputs nCFG control signal ( Figure 1②) in the FPGA reconfiguration. After the FPGA completes the reconfiguration, it enters the initialization phase, at which time all interfaces are high impedance. After the FPGA initialization is completed, the initialization completion signal init_DONE ( Figure 1 ③) in the figure and start automatically, you can enter the user mode and complete the designed functions.

[0050] During the upgrade process, only one Flash is operated, and the data of the other Flash is guaranteed to remain unchanged. Therefore, it can be guaranteed that the driver can ensure that the FPGA can be correctly started from the Flash at any time. Among them, the upgrade method of the FPGA in the technical solution provided by the present invention is a prior art, which is specifically referred to in the patent document CN110737452A, and will not be repeated here.

[0051] Compared with the prior art, the technical solution provided by the present invention also has the following advantages:

[0052] 1. It can support multiple encoder protocols without increasing the hardware and structural complexity of the servo drive.

[0053] 2. The hardware design is simple, using only one FPGA and one encoder interface to support both synchronous communication protocol and asynchronous communication protocol encoders. At the same time, it can also complete the online upgrade function to improve the adaptability and reliability of the driver.

[0054] 3. FPGA firmware development is simple, with the characteristics of low system cost and short development cycle.

[0055] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0056] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A servo driver supporting multiple encoder protocols, characterized in that: include: Encoder interface, FPGA, DSP, solid-state memory and host computer; The encoder interface is connected to the FPGA; the FPGA is connected to the DSP and the solid-state memory respectively; the DSP is connected to the solid-state memory; The solid-state memory is used to store FPGA program data of multiple encoder communication protocols, and the encoder communication protocols corresponding to the program data stored in the solid-state memory are all different; the encoder interface is used to connect the encoder to be driven; the DSP is used to generate a chip select signal according to the servo parameter to open or close the solid-state memory; The FPGA is used to read the program data stored in the solid-state memory, to determine the communication protocol of the connected encoder according to the servo parameters of the driver, to parse the transmission data of the encoder to be driven through the encoder data parsing function module, and to upload it to the DSP through the DSP data interaction function module; the DSP is used to perform data interaction with the FPGA through the FPGA interaction function module, and to update the servo drive data in real time according to the position data uploaded by the FPGA, so as to drive the motor to run smoothly; The host computer is used to send a command to the DSP to update the encoder communication program data stored in the solid-state memory, thereby realizing the online upgrade of the FPGA; The FPGA is connected to the DSP via the SPI interface, the nCFG interface and the Init interface; the SEL interface of the DSP is connected to the / CE interface of the solid-state memory via a switch selector; the nCSC interface of the FPGA is connected to the / CE interface of the solid-state memory; The solid-state memory comprises: a first solid-state memory and a second solid-state memory; The / CE interface of the first solid-state memory and the / CE interface of the second solid-state memory are both connected to the SEL interface of the DSP through a switch selection device; the data output interface of the first solid-state memory and the data output interface of the second solid-state memory are both connected to the nCSC interface of the FPGA through a switch selection device; When the system is powered on, if the driver uses the default servo parameters, the DSP outputs SEL=0 according to the driver's servo parameters, that is, the first solid-state memory chip select signal / CE is valid; at the same time, it outputs a low-level pulse signal of nCFG, and the FPGA reads the program data from the solid-state memory connected at this time and completes self-starting; when the FPGA completes initialization, the Init signal becomes a high level; after receiving the Init high level, the DSP considers that the FPGA has entered the normal working mode and parses the external encoder data; at this time, the encoder types supported by the driver are: encoder A, encoder B, encoder C and encoder D; When replacing an encoder with a different communication protocol, the encoder type of the servo parameters is modified through the host computer; the DSP determines whether to switch the FPGA from the first solid-state memory to the program in the second solid-state memory based on the currently set servo parameters; if only one of the A, B, C and D encoder types is replaced, SEL=0 is maintained; if it is replaced with the program of the second solid-state memory, the SEL signal in the DSP is changed to SEL=1; after the FPGA completes the restart, the supported encoder types are encoder E, encoder F and encoder G.

2. The servo driver supporting multiple encoder protocols according to claim 1, characterized in that: The number of the FPGA is 1.

3. The servo driver supporting multiple encoder protocols according to claim 1, characterized in that: The number of the encoder interface is 1.

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