Shift register, driving method thereof, gate driving circuit and display device

Abstract

Disclosed are a shift register, a driving method thereof, a gate driving circuit and a display device, comprising: an input circuit (10) configured to be coupled with an input signal end (IP) and a second clock signal end (CK2) respectively; a first transistor (M1), a first electrode of the first transistor (M1) being coupled with an output end (PU2) of the input circuit; and the first transistor (M1) being a double-gate transistor; wherein a first gate of the first transistor (M1) is configured to be coupled with a first reference signal end (VREF1), and a second gate of the first transistor (M1) is configured to be coupled with a first threshold value control signal end (VS1); and an output circuit configured to be coupled with a first clock signal end (CK1) and a signal output end (OP) respectively, and a control end of the output circuit (OP) being coupled with a second electrode of the first transistor (M1).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to shift registers, their driving methods, gate driving circuits, and display devices. Background Technology

[0002] With the rapid development of display technology, display devices are increasingly moving towards higher integration and lower cost. Among these technologies, GOA (Gate Driver on Array) integrates the TFT (Thin Film Transistor) gate driving circuitry onto the array substrate of the display device to form a scanning drive for the display. This gate driving circuit typically consists of multiple cascaded shift registers. However, unstable shift register outputs can lead to display abnormalities. Summary of the Invention

[0003] The shift register provided in this disclosure includes:

[0004] The input circuit is configured to be coupled to the input signal terminal and the second clock signal terminal, respectively.

[0005] A first transistor, wherein the first terminal of the first transistor is coupled to the output terminal of the input circuit; and the first transistor is a dual-gate transistor; wherein the first gate of the first transistor is configured to be coupled to a first reference signal terminal, and the second gate of the first transistor is configured to be coupled to a first threshold control signal terminal;

[0006] The output circuit is configured to be coupled to a first clock signal terminal and a signal output terminal, respectively, and the control terminal of the output circuit is coupled to the second terminal of the first transistor.

[0007] Optionally, in an embodiment of this disclosure, the input circuit includes: a single-gate type second transistor;

[0008] The gate of the second transistor is configured to be coupled to the second clock signal terminal, the first terminal of the second transistor is configured to be coupled to the input signal terminal, and the second terminal of the second transistor is coupled to the first terminal of the first transistor.

[0009] Optionally, in embodiments of this disclosure, the second gate of the first transistor is coupled to the gate of the second transistor; or,

[0010] The second gate of the first transistor is coupled to the first terminal of the second transistor.

[0011] Optionally, in an embodiment of this disclosure, the input circuit includes: a dual-gate second transistor; wherein, the first gate of the second transistor is configured to be coupled to the second clock signal terminal, the second gate of the second transistor is configured to be coupled to the second threshold control signal terminal, the first electrode of the second transistor is configured to be coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the first transistor.

[0012] Optionally, in embodiments of this disclosure, the second gate of the second transistor is coupled to the first gate of the second transistor; or,

[0013] The second gate of the second transistor is coupled to the first terminal of the second transistor.

[0014] Optionally, in embodiments of this disclosure, the second gate of the first transistor is coupled to the first gate of the second transistor; or,

[0015] The second gate of the first transistor is coupled to the first terminal of the second transistor.

[0016] Optionally, in this embodiment of the present disclosure, the shift register further includes: a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor;

[0017] The gate of the fifth transistor is configured to be coupled to the second clock signal terminal, the first terminal of the fifth transistor is configured to be coupled to the first reference signal terminal, and the second terminal of the fifth transistor is coupled to the gate of the seventh transistor.

[0018] The gate of the sixth transistor is coupled to the first terminal of the first transistor, the first terminal of the sixth transistor is configured to be coupled to the second clock signal terminal, and the second terminal of the sixth transistor is coupled to the gate of the seventh transistor.

[0019] The first terminal of the seventh transistor is configured to be coupled to the second reference signal terminal, and the second terminal of the seventh transistor is coupled to the signal output terminal;

[0020] The first terminal of the first capacitor is coupled to the gate of the seventh transistor, and the second terminal of the first capacitor is configured to be coupled to the second reference signal terminal.

[0021] Optionally, in this embodiment of the present disclosure, the shift register further includes: a pull-up control circuit; wherein, the first control terminal of the pull-up control circuit is configured to be coupled to the first clock signal terminal, the second control terminal of the pull-up control circuit is coupled to the gate of the seventh transistor, the input terminal of the pull-up control circuit is configured to be coupled to the second reference signal terminal, and the output terminal of the pull-up control circuit is coupled to the first pole of the first transistor.

[0022] Optionally, in this embodiment of the disclosure, the pull-up control circuit includes: a third transistor and a single-gate fourth transistor;

[0023] The gate of the third transistor is configured to be coupled to the first clock signal terminal, the first terminal of the third transistor is coupled to the first terminal of the first transistor, and the second terminal of the third transistor is coupled to the first terminal of the fourth transistor.

[0024] The gate of the fourth transistor is coupled to the gate of the seventh transistor, and the second terminal of the fourth transistor is configured to be coupled to the second reference signal terminal.

[0025] Optionally, in this embodiment of the disclosure, the pull-up control circuit includes: a third transistor and a dual-gate fourth transistor;

[0026] The gate of the third transistor is configured to be coupled to the first clock signal terminal, the first terminal of the third transistor is coupled to the first terminal of the first transistor, and the second terminal of the third transistor is coupled to the first terminal of the fourth transistor.

[0027] The first gate of the fourth transistor is coupled to the gate of the seventh transistor, the second gate of the fourth transistor is configured to be coupled to the third threshold control signal terminal, and the second terminal of the fourth transistor is configured to be coupled to the second reference signal terminal.

[0028] Optionally, in embodiments of this disclosure, the second gate of the fourth transistor is coupled to the gate of the seventh transistor; or,

[0029] The second gate of the fourth transistor is coupled to the gate of the fifth transistor.

[0030] Optionally, in an embodiment of this disclosure, the output circuit includes: an eighth transistor and a second capacitor;

[0031] The gate of the eighth transistor is coupled to the second terminal of the first transistor, the first terminal of the eighth transistor is configured to be coupled to the first clock signal terminal, and the second terminal of the eighth transistor is coupled to the signal output terminal.

[0032] The first terminal of the second capacitor is coupled to the second terminal of the first transistor, and the second terminal of the second capacitor is coupled to the signal output terminal.

[0033] Optionally, in this embodiment of the disclosure, the first threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal;

[0034] The second threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal;

[0035] The third threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal.

[0036] Optionally, in this embodiment of the disclosure, at least one of the first threshold control signal terminal, the second threshold control signal terminal, and the third threshold control signal terminal is configured to receive a clock signal with the same timing as the second clock signal terminal.

[0037] Optionally, in this embodiment of the disclosure, at least one of the first threshold control signal terminal, the second threshold control signal terminal, and the third threshold control signal terminal is configured to receive a fixed voltage signal.

[0038] Accordingly, embodiments of this disclosure also provide a gate drive circuit, including a plurality of cascaded shift registers as described above;

[0039] The input signal terminal of the first-stage shift register is configured to be coupled to the frame trigger signal terminal;

[0040] In each pair of adjacent shift registers, the input signal terminal of the next-level shift register is configured to be coupled to the signal output terminal of the previous-level shift register.

[0041] Accordingly, embodiments of this disclosure also provide a display device including the gate driving circuit described above.

[0042] Accordingly, this disclosure also provides a method for driving the shift register described above, including:

[0043] During the input phase, the input circuit controls the signal level of the first terminal of the first transistor according to the signal between the input signal terminal and the second clock signal terminal; the first transistor is turned on; the output circuit responds to the signal of the second terminal of the first transistor and provides the signal of the first clock signal terminal to the signal output terminal.

[0044] During the output phase, the threshold voltage of the first transistor shifts in response to the signal at the first threshold control signal terminal, and the first transistor is turned off; the output circuit responds to the signal at the second terminal of the first transistor and provides the signal at the first clock signal terminal to the signal output terminal; wherein, the signal at the first threshold control signal terminal is at the opposite level to the signal at the first reference signal terminal.

[0045] Optionally, in this embodiment of the disclosure, the input stage further includes: a fifth transistor providing a signal from the first reference signal terminal to the gate of a seventh transistor in response to a signal from the second clock signal terminal; a sixth transistor providing a signal from the second clock signal terminal to the gate of the seventh transistor in response to a signal from the first terminal of the first transistor; and the seventh transistor providing a signal from the second reference signal terminal to the signal output terminal in response to a signal from the gate of the seventh transistor.

[0046] Following the output phase, the driving method further includes:

[0047] During the reset phase, the input circuit controls the signal level of the first terminal of the first transistor according to the signals of the input signal terminal and the second clock signal terminal; the first transistor turns on the input circuit and the output circuit; the fifth transistor, in response to the signal of the second clock signal terminal, provides the signal of the first reference signal terminal to the gate of the seventh transistor; the seventh transistor, in response to the signal of the gate of the seventh transistor, provides the signal of the second reference signal terminal to the signal output terminal.

[0048] Optionally, in an embodiment of this disclosure, during the output phase, the threshold voltage of the second transistor moves in response to the signal at the second threshold control signal terminal, and the second transistor is turned off; the threshold voltage of the fourth transistor moves in response to the signal at the third threshold control signal terminal, and the fourth transistor is turned off. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the structure of a shift register in related technologies;

[0050] Figure 2 for Figure 1 The signal timing diagram of the shift register shown is shown below;

[0051] Figure 3a For the corresponding Figure 1 The simulation diagram of the signal output terminal of the shift register is shown.

[0052] Figure 3b For the corresponding Figure 1 The simulation diagram of the first pull-up node of the shift register is shown.

[0053] Figure 4a This is one of the schematic diagrams of the shift register provided in the embodiments of this disclosure;

[0054] Figure 4b This is the second schematic diagram of the structure of the shift register provided in the embodiments of this disclosure;

[0055] Figure 5a This is one of the signal timing diagrams provided in the embodiments of this disclosure;

[0056] Figure 5b This is the second signal timing diagram provided in the embodiments of this disclosure;

[0057] Figure 6 For the corresponding Figure 4b The simulation diagram of the signal output terminal of the shift register is shown.

[0058] Figure 7 This is the third schematic diagram of the shift register structure provided in the embodiments of this disclosure;

[0059] Figure 8 This is the third signal timing diagram provided in the embodiments of this disclosure;

[0060] Figure 9a Fourth schematic diagram of the shift register structure provided in the embodiments of this disclosure;

[0061] Figure 9b For the corresponding Figure 9a The simulation diagram of the signal output terminal of the shift register is shown.

[0062] Figure 9c For the corresponding Figure 9a The simulation diagram of the first pull-up node of the shift register is shown.

[0063] Figure 10a This is the fourth signal timing diagram provided in the embodiments of this disclosure;

[0064] Figure 10b This is the fifth signal timing diagram provided in the embodiments of this disclosure;

[0065] Figure 10c This is the sixth signal timing diagram provided in the embodiments of this disclosure;

[0066] Figure 11 Fifth schematic diagram of the shift register structure provided in the embodiments of this disclosure;

[0067] Figure 12 This is the seventh signal timing diagram provided in the embodiments of this disclosure;

[0068] Figure 13 Sixth schematic diagram of the shift register structure provided in the embodiments of this disclosure;

[0069] Figure 14a Seventh schematic diagram of the structure of the shift register provided in the embodiments of this disclosure;

[0070] Figure 14b This is the eighth signal timing diagram provided in the embodiments of this disclosure;

[0071] Figure 15 A flowchart of the driving method provided in the embodiments of this disclosure;

[0072] Figure 16 This is a schematic diagram of the gate drive circuit provided in an embodiment of the present disclosure;

[0073] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, the specific implementation methods of the shift register, its driving method, gate driving circuit, and display device provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustration and explanation of this disclosure and are not intended to limit this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. And throughout the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions.

[0075] like Figure 1 As shown, the shift register may include transistors M01 to M08 and capacitors C01 to C02. Figure 1 The signal timing diagram corresponding to the shift register shown is as follows: Figure 2As shown. In input phase t1, transistors M02 and M05 are turned on under the control of the clock signal terminal CK. The turned-on transistor M05 provides the low-level signal of signal terminal VSS to the pull-down node PD, making the signal of pull-down node PD low, thus controlling transistors M04 and M07 to turn on, while transistor M03 is turned off under the control of the clock signal terminal CKB. The turned-on transistor M07 provides the high-level signal of signal terminal VDD to the signal output terminal OP, making the signal output terminal OP output a high-level signal. Furthermore, the turned-on transistor M02 provides the low-level signal of input signal terminal IP to the second pull-up node PU_2, making the signal of the second pull-up node PU_2 low. Transistor M06 is turned on under the control of the signal of the second pull-up node PU_2, providing the low-level signal of clock signal terminal CK to pull-down node PD. Since transistor M01 satisfies V... gs01 <V th01 This causes transistor M01 to conduct; where, at this time, the terminal of transistor M01 connected to the first pull-up node PU_1 serves as the source, V gs01 V represents the voltage difference between the gate and source of transistor M01. th01 This represents the threshold voltage of transistor M01. When transistor M01 is active, it connects the second pull-up node PU_2 and the first pull-up node PU_1, making the signal at the first pull-up node PU_1 low, thus controlling transistor M08 to turn on. The active transistor M08 provides the high-level signal from the clock signal terminal CKB to the signal output terminal OP, causing OP to output a high-level signal. It should be noted that in practical applications, the low-level signal voltage of the first pull-up node PU_1 can be the same as the voltage of the signal at the signal terminal VSS. Due to the threshold voltage of transistor M01, the low-level signal voltage of the first pull-up node PU_1 can be less than the low-level signal voltage of the second pull-up node PU_2. Of course, the specific voltage can be designed and determined according to the actual application environment, and is not limited here.

[0076] After input stage t1 and before output stage t2, transistors M02 and M05 are turned off under the control of the high-level signal at the clock signal terminal CK, and transistor M03 is also turned off under the control of the high-level signal at the clock signal terminal CKB. Therefore, the first pull-up node PU_1 is kept at a low level under the action of capacitor C01. Generally, the terminal with the higher voltage can be used as the source of the transistor. Therefore, in this stage, the terminal of transistor M01 electrically connected to the second pull-up node PU_2 serves as its source, allowing transistor M01 to satisfy V... gs01 <V th01Therefore, transistor M01 is turned on, making the signal at the second pull-up node PU_2 low. Transistor M06 is turned on under the control of the signal at the second pull-up node PU_2 to provide the high-level signal at the clock signal terminal CKB to the pull-down node PD, making the signal at the pull-down node PD high, thus controlling transistors M04 and M07 to be turned off. Transistor M08 is turned on under the control of the signal at the first pull-up node PU_1 to provide the high-level signal at the clock signal terminal CKB to the signal output terminal OP, making the signal output terminal OP output a high-level signal.

[0077] During output phase t2, transistors M02 and M05 are cut off under the control of the high-level signal at the clock signal terminal CK. The first pull-up node PU_1 is kept at a low level under the action of capacitor C01 to control transistor M08 to turn on, thereby providing the low-level signal at the clock signal terminal CKB to the signal output terminal OP. Due to the action of capacitor C01, the level of the first pull-up node PU_1 is further pulled low to control transistor M08 to be turned on as fully as possible, so as to provide the low-level signal at the clock signal terminal CKB to the signal output terminal OP, causing the signal output terminal OP to output a low-level signal.

[0078] However, during the output phase t2, due to the prolonged leakage current accumulation in transistor M01, the voltage level of the first pull-up node PU_1, which is further pulled down, also experiences leakage. This causes the voltage level of the first pull-up node PU_1 to rise, resulting in incomplete opening of transistor M08 and consequently, abnormal signal output from the signal output terminal OP. This is especially problematic when the display device uses a low refresh rate (e.g., 1Hz). Furthermore, the prolonged leakage current accumulation in transistors M01, M02, and M04 causes the voltage levels of PU_2 and PU_1 to rise, leading to abnormal signal output from the signal output terminal OP.

[0079] Furthermore, according to Figure 2 The signal timing diagram shown is for Figure 1 The signal output from the shift register's signal output terminal OP and the signal from the first pull-up node PU_1 are simulated, as shown. Figure 3a and Figure 3b As shown. Figure 3a for Figure 1 The shift register shown is in Figure 2 The diagram shows a simulation of the signal output by the signal output terminal OP under the control of the signal shown. Figure 3b for Figure 1 The shift register shown is in Figure 2 The simulation diagram shows the signal of the first pull-up node PU_1 under the control of the signal shown. The horizontal axis represents time, and the vertical axis represents voltage. Combined with... Figure 3a and Figure 3bIt can be seen that during the output stage t2, leakage occurs in the level of the first pull-up node PU_1, causing the level of the first pull-up node PU_1 to rise. This, in turn, causes the level of the signal output from the signal output terminal OP to rise as well, resulting in an abnormal signal output from the signal output terminal OP. Furthermore, due to the leakage, the aforementioned shift register is not suitable for display devices that should be configured for low-frequency (e.g., 1Hz) driving.

[0080] Based on this, embodiments of this disclosure provide some shift registers, such as Figure 4a As shown, it may include:

[0081] Input circuit 10 is configured to be coupled to input signal terminal IP and second clock signal terminal CK2 respectively;

[0082] The first transistor M1 has its first terminal coupled to the output terminal of the input circuit 10; and the first transistor M1 is a dual-gate transistor; wherein, the first gate of the first transistor M1 is configured to be coupled to the first reference signal terminal VREF1, and the second gate of the first transistor M1 is configured to be coupled to the first threshold control signal terminal VS1.

[0083] The output circuit 20 is configured to be coupled to the first clock signal terminal CK1 and the signal output terminal OP respectively, and the control terminal of the output circuit 20 is coupled to the second terminal of the first transistor M1.

[0084] The shift register provided in this disclosure, by configuring the first transistor as a dual-gate transistor, wherein the first gate of the first transistor receives a first reference signal terminal and the second gate of the first transistor receives a first threshold control signal terminal, enables the first transistor to be turned on during the input phase, reset phase, and reset hold phase. Furthermore, at least during the output phase, the threshold voltage V of the first transistor can be controlled by the signal at the first threshold control signal terminal. th1 This makes the threshold voltage V of the first transistor... th1 By moving the transistor to keep it as off as possible during the output phase, the signal level of the first pull-up node can be kept stable, preventing leakage current from affecting the signal of the first pull-up node. This improves the stability of the output signal, which is beneficial for applications in low-frequency driven display devices and helps reduce power consumption.

[0085] In specific implementation, such as Figure 4aAs shown, the first pull-up node PU_1 is located between the control terminal of the output circuit 20 and the second terminal of the first transistor M1. The second pull-up node PU_2 is located between the output terminal of the input circuit 10 and the first terminal of the first transistor M1. It should be noted that the first pull-up node PU_1 and the second pull-up node PU_2 are virtual nodes in the shift register. These two nodes are only for the convenience of describing the structure of the shift register and the signal transmission. The specific structure of the shift register and the signal transmission can be determined based on the coupling method between the transistors and capacitors in the shift register.

[0086] In specific implementation, as described in the embodiments of this disclosure, Figure 4a As shown, the input circuit 10 is configured to control the signal level of the second pull-up node PU_2 based on the input signal terminal IP and the second clock signal terminal CK2. This allows the input signal terminal IP to be input through the input circuit 10. The output circuit 20 is configured to provide the signal of the first clock signal terminal CK1 to the signal output terminal OP in response to the signal of the first pull-up node PU_1. This allows the output circuit 20 to output the signal of the first clock signal terminal CK1. Furthermore, the second pull-up node PU_2 is coupled to the first pull-up node PU_1 through the first transistor M1.

[0087] In specific implementation, as described in the embodiments of this disclosure, Figure 4a As shown, the first terminal of the first transistor M1 is coupled to the second pull-up node PU_2, and the second terminal of the first transistor M1 is coupled to the first pull-up node PU_1.

[0088] Specifically, in a practical implementation, the input circuit 10 may include a single-gate second transistor M2; wherein the gate of the second transistor M2 is configured to be coupled to the second clock signal terminal CK2, the first terminal of the second transistor M2 is configured to be coupled to the input signal terminal IP, and the second terminal of the second transistor M2 is coupled to the first terminal of the first transistor M1, that is, the second terminal of the second transistor M2 is coupled to the second pull-up node PU_2. Further, when the second transistor M2 is in a conducting state under the control of the signal at the second clock signal terminal CK2, it can provide the signal at the input signal terminal IP to the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2) to control the signal level of the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2).

[0089] In specific implementation, as described in the embodiments of this disclosure, Figure 4a As shown, the shift register may also include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first capacitor C1;

[0090] The gate of the fifth transistor M5 is configured to be coupled to the second clock signal terminal CK2, the first terminal of the fifth transistor M5 is configured to be coupled to the first reference signal terminal VREF1, and the second terminal of the fifth transistor M5 is coupled to the gate of the seventh transistor M7 (i.e., the pull-down node PD).

[0091] The gate of the sixth transistor M6 is coupled to the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2), the first terminal of the sixth transistor M6 is configured to be coupled to the second clock signal terminal CK2, and the second terminal of the sixth transistor M6 is coupled to the gate of the seventh transistor M7 (i.e., the pull-down node PD).

[0092] The first terminal of the seventh transistor M7 is configured to be coupled to the second reference signal terminal VREF2, and the second terminal of the seventh transistor M7 is coupled to the signal output terminal OP.

[0093] The first terminal of the first capacitor C1 is coupled to the gate (i.e., the pull-down node PD) of the seventh transistor M7, and the second terminal of the first capacitor C1 is configured to be coupled to the second reference signal terminal VREF2.

[0094] Furthermore, when the fifth transistor M5 is in the ON state under the control of the second clock signal terminal CK2, it can provide the signal of the first reference signal terminal VREF1 to the gate of the seventh transistor M7 (i.e., the pull-down node PD). When the sixth transistor M6 is in the ON state under the control of the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2), it can provide the signal of the second clock signal terminal CK2 to the gate of the seventh transistor M7 (i.e., the pull-down node PD). When the seventh transistor M7 is in the ON state under the control of its gate (i.e., the pull-down node PD), it can provide the signal of the second reference signal terminal VREF2 to the signal output terminal OP for coupling. The first capacitor C1 can store the signal input to the gate of the seventh transistor M7 (i.e., the pull-down node PD) and the signal of the second reference signal terminal VREF2, and keep them stable.

[0095] In specific implementation, as described in the embodiments of this disclosure, Figure 4aAs shown, the shift register may further include a pull-up control circuit 30. The first control terminal of the pull-up control circuit 30 is configured to be coupled to the first clock signal terminal CK1, the second control terminal of the pull-up control circuit 30 is coupled to the gate of the seventh transistor M7, the input terminal of the pull-up control circuit 30 is configured to be coupled to the second reference signal terminal VREF2, and the output terminal of the pull-up control circuit 30 is coupled to the first terminal of the first transistor M1. The pull-up control circuit 30 is configured to provide the signal from the second reference signal terminal VREF2 to the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2) in response to the signals from the first clock signal terminal CK1 and the gate of the seventh transistor M7 (i.e., the pull-down node PD).

[0096] Specifically, in practical implementation, such as Figure 4a As shown, the pull-up control circuit 30 may include a third transistor M3 and a single-gate fourth transistor M4; wherein, the gate of the third transistor M3 is configured to be coupled to the first clock signal terminal CK1, the first terminal of the third transistor M3 is coupled to the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2), and the second terminal of the third transistor M3 is coupled to the first terminal of the fourth transistor M4. The gate of the fourth transistor M4 is coupled to the gate of the seventh transistor M7 (i.e., the pull-down node PD), and the second terminal of the fourth transistor M4 is configured to be coupled to the second reference signal terminal VREF2.

[0097] Furthermore, when the fourth transistor M4 is in the on state under the control of the gate (i.e., pull-down node PD) of the seventh transistor M7, the signal of the second reference signal terminal VREF2 can be provided to the first terminal of the fourth transistor M4. When the third transistor M3 is in the on state under the control of the signal of the first clock signal terminal CK1, the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2) can be connected to the first terminal of the fourth transistor M4.

[0098] In specific implementation, as described in the embodiments of this disclosure, such as Figure 4a As shown, the output circuit 20 may include: an eighth transistor M8 and a second capacitor C2; wherein, the gate of the eighth transistor M8 is coupled to the second terminal (i.e., the first pull-up node PU_1) of the first transistor M1, the first terminal of the eighth transistor M8 is configured to be coupled to the first clock signal terminal CK1, and the second terminal of the eighth transistor M8 is coupled to the signal output terminal OP. The first terminal of the second capacitor C2 is coupled to the second terminal (i.e., the first pull-up node PU_1) of the first transistor M1, and the second terminal of the second capacitor C2 is coupled to the signal output terminal OP.

[0099] Furthermore, when the eighth transistor M8 is in the conducting state under the control of the signal at the second terminal (i.e., the first pull-up node PU_1) of the first transistor M1, it can provide the signal from the first clock signal terminal CK1 to the signal output terminal OP. The second capacitor C2 can store and stabilize the signal input to the second terminal (i.e., the first pull-up node PU_1) of the first transistor M1 and the signal input to the signal output terminal OP, and when the second terminal (i.e., the first pull-up node PU_1) of the first transistor M1 is in the floating state, it can maintain the stability of the voltage difference between the first pull-up node PU_1 and the signal output terminal OP.

[0100] In practical implementation, depending on the direction of signal flow, the first terminal of the transistor can be used as its source and the second terminal as its drain; or, the first terminal can be used as its drain and the second terminal as its source. No specific distinction is made here.

[0101] It should be noted that the transistors mentioned in the above embodiments of this disclosure can be TFTs or metal-oxide-semiconductor field-effect transistors (MOS), and are not limited thereto.

[0102] To simplify the preparation process, in specific implementations, as described in the embodiments of this disclosure, Figure 4a As shown, all transistors can be P-type transistors. In a P-type transistor, the voltage difference V between its gate and source is... gs Its threshold voltage V th Satisfying relation V gs <V th When the transistor is turned on. For example, if the first transistor M1 can be a P-type transistor, then the voltage difference V between the gate and source of the first transistor M1 is... gs1 Its threshold voltage V th1 The relationship between them satisfies the formula: V gs1 <V th1 When the transistor is turned on, it conducts. Of course, in this embodiment, only a P-type transistor is used as an example for illustration. For N-type transistors, the design principle is the same as this disclosure and also falls within the scope of protection of this disclosure. Furthermore, the voltage difference V between the gate and source of an N-type transistor... gs Its threshold voltage V th Satisfying relation V gs >V th When the transistor is turned on, it conducts. For example, the first transistor M1 can be an N-type transistor, and the voltage difference V between its gate and its source is... gs1 Its threshold voltage V th1 The relationship between them satisfies the formula: V gs1 >V th1 Time conduction.

[0103] In general, a gate insulating layer is disposed between the gate and the active layer of a transistor. In specific implementations, the dominant gate in a dual-gate transistor can be determined by adjusting the thickness of the gate insulating layer. For example, in the embodiments of this disclosure, the thickness of the gate insulating layer can be adjusted so that the first gate of the first transistor dominates, and the voltage difference V between the gate (i.e., the first gate) and the source of the first transistor M1 is determined. gs1 Its threshold voltage V th1 The relationship between them satisfies the formula V gs1 <V th1 Time conduction. From now on, V will be used. gs1 The following explanation uses the voltage difference between the first gate and the source of the first transistor M1 as an example.

[0104] To make the threshold voltage V of the first transistor M1 th1 It is movable, and in specific implementation, the first threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal VREF1.

[0105] In a specific implementation, in this embodiment of the disclosure, when the effective pulse signal of the input signal terminal IP is a low-level signal, the signal of the first reference signal terminal VREF1 is a low-level signal, the signal of the second reference signal terminal VREF2 is a high-level signal, and the first threshold control signal terminal VS1 is configured to receive a signal with at least a high-level signal. Alternatively, in a specific implementation, in this embodiment of the disclosure, when the effective pulse signal of the input signal terminal IP is a high-level signal, the signal of the first reference signal terminal VREF1 is a high-level signal, the signal of the second reference signal terminal VREF2 is a low-level signal, and the first threshold control signal terminal VS1 is configured to receive a signal with at least a low-level signal. It should be noted that, in conjunction with... Figure 5a As shown, the effective pulse signal at the input signal terminal IP refers to the low-level signal input to the second transistor M2 within one frame time to control the shift register to perform output operation.

[0106] Furthermore, in specific implementations, P-type transistors are cut off under high-level signals and turn on under low-level signals. N-type transistors turn on under high-level signals and cut off under low-level signals.

[0107] The above are merely illustrative examples of the specific structure of the shift register provided in the embodiments of this disclosure. In specific implementations, the specific structure of each circuit is not limited to the structure provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art, which are not limited here.

[0108] The following is based on Figure 4a Taking the shift register shown as an example, combined with Figure 5a The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure. In the following description, 1 represents a high-level signal and 0 represents a low-level signal. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiments of this disclosure, and are not the voltages applied to the gates of each transistor in actual implementation.

[0109] Specifically, select such as Figure 5a The signal timing diagram shown includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4. It should be noted that... Figure 5a The signal timing diagram shown only illustrates the operation of a single shift register in the current frame. The operation of this shift register in other frames is essentially the same as that in the current frame, and will not be elaborated upon here.

[0110] In input phase T1, IP = 0, CK1 = 1, CK2 = 0, VS1 = 0.

[0111] Since CK1 = 1, the third transistor M3 is off. Since CK2 = 0, both the second transistor M2 and the fifth transistor M5 are on. The on fifth transistor M5 provides the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal of the pull-down node PD low, thus controlling the fourth transistor M4 and the seventh transistor M7 to turn on. The on seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, making the signal output terminal OP output a high-level signal. The on second transistor M2 provides the low-level signal from the input signal terminal IP to the second pull-up node PU_2, making the signal of the second pull-up node PU_2 low. The sixth transistor M6 turns on under the control of the signal from the second pull-up node PU_2, providing the low-level signal from the second clock signal terminal CK2 to the pull-down node PD, further making the signal of the pull-down node PD low. Since VS1 = 0, the V of the first transistor M1 can be turned on. th1 Shift to the right, so that the first transistor M1 satisfies V gs1 <V th1This is to ensure that the first transistor M1 is turned on as fully as possible. Since the signal of the first pull-up node PU_1 was high in the previous frame, the terminal connected to the first pull-up node PU_1 in the current frame serves as the source. The turned-on first transistor M1 connects the second pull-up node PU_2 to the first pull-up node PU_1, thus ensuring that the signal of the first pull-up node PU_1 is low in a timely manner, thereby controlling the turn-on of the eighth transistor M8. The turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0112] After input stage T1 and before output stage T2, since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are turned off. Since CK1 = 1, the third transistor M3 is also turned off. Therefore, the second pull-up node PU_2 and the first pull-up node PU_1 are in a floating state, and the first pull-up node PU_1 remains at a low level under the action of the second capacitor C2. Furthermore, since the threshold voltage V of the first transistor M1... th1 Because of this, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, in this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Since VS1 = 0, the voltage of the first transistor M1 can be reduced by VS1. th1 Shift to the right, so that the first transistor M1 satisfies V gs1 <V th1 This process ensures that the first transistor M1 is fully turned on, making the signal at the second pull-up node PU_2 low, thus controlling the sixth transistor M6 to turn on. The turned-on sixth transistor M6 provides the high-level signal from the second clock signal terminal CK2 to the pull-down node PD, making the signal at pull-down node PD high, thereby controlling the fourth transistor M4 and the seventh transistor M7 to turn off. The eighth transistor M8, under the control of the signal from the first pull-up node PU_1, turns on, providing the high-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0113] In the output phase T2, IP=1, CK1=0, CK2=1, VS1=1.

[0114] Since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are off. Therefore, the first pull-up node PU_1 remains at a low level under the action of the second capacitor C2, controlling the eighth transistor M8 to conduct. This provides the low-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing OP to output a low-level signal. Due to the action of the second capacitor C2, the level of the first pull-up node PU_1 is further pulled low, allowing the eighth transistor M8 to conduct as fully as possible, providing the low-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing OP to output a low-level signal. Furthermore, due to the threshold voltage V of the first transistor M1... th1 Because of this, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, in this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Since VS1 = 1, the voltage of the first transistor M1 can be reduced by VS1. th1 Shifting left, the gate voltage of the first transistor M1 is a low-level signal voltage, and the source voltage of the first transistor M1 is also a low-level signal voltage, thus preventing the first transistor M1 from satisfying V. gs1 <V th1 This ensures that the first transistor M1 is turned off, thereby maintaining a stable level at the first pull-up node PU_1 and preventing instability in the signal output terminal OP due to leakage causing a rise in the level of the first pull-up node PU_1. Furthermore, the first capacitor C1 maintains a high-level signal at the pull-down node PD, thus controlling the fourth transistor M4 and the seventh transistor M7 to be turned off, preventing adverse effects on the signal output at the signal output terminal OP.

[0115] During the reset phase T3, IP = 1, CK1 = 1, CK2 = 0, and VS1 = 0.

[0116] Since CK2 = 0, both the second transistor M2 and the fifth transistor M5 are turned on. The turned-on second transistor M2 provides the high-level signal at the input signal terminal IP to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 a high-level signal, thus controlling the sixth transistor M6 to turn off. Furthermore, during this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source, and the first transistor M1 satisfies V... gs1 <V th1The conduction of transistor M5 causes the second pull-up node PU_2 to conduct with the first pull-up node PU_1, thereby controlling the eighth transistor M8 to turn off. The conducting fifth transistor M5 provides the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal at pull-down node PD a low-level signal, thus controlling the fourth transistor M4 and the seventh transistor M7 to conduct. Furthermore, since CK1 = 1, the third transistor M3 is turned off. The conducting seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0117] During the reset holding phase T4, IP = 1, CK1 = 0, CK2 = 1, VS1 = 0.

[0118] Since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are off. The first capacitor C1 keeps the signal at the pull-down node PD low, thus controlling the fourth transistor M4 and the seventh transistor M7 to conduct. Since CK1 = 0, the third transistor M3 is on. The conducting third transistor M3 and the fourth transistor M4 provide the high-level signal from the second reference signal terminal VREF2 to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 high, thus controlling the sixth transistor M6 to turn off. Furthermore, during this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source, and the first transistor M1 satisfies V... gs1 <V th1 When the transistor is turned on, the second pull-up node PU_2 is connected to the first pull-up node PU_1, thereby controlling the eighth transistor M8 to be turned off. The turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0119] After the reset hold phase T4, the reset phase T3 and reset hold phase T4 are repeated until the signal level of the input signal terminal IP goes low again.

[0120] It should be noted that there are buffer phases between input phase T1 and output phase T2, between output phase T2 and reset phase T3, and between reset phase T3 and reset hold phase T4. During the buffer phases, the characteristics of the transistors in the shift register can be stabilized so that they can enter the next operating phase after stabilization. Furthermore, this avoids the rising edge of the first clock signal CK1 from aligning with the falling edge of the second clock signal CK2, and also avoids the falling edge of the first clock signal CK1 from aligning with the rising edge of the second clock signal CK2, thereby improving the stability of the shift register.

[0121] It should be noted that in practical applications, the specific voltage values ​​of the above signals can be designed and determined according to the actual application environment, and are not limited here.

[0122] This disclosure also provides other signal timing diagrams for shift registers, such as... Figure 5b As shown, it targets Figure 5a The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 4a The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0123] In specific implementation, as described in the embodiments of this disclosure, such as Figure 5b As shown, the first threshold control signal terminal VS1 uses the same signal as the input signal terminal IP. The first threshold control signal terminal VS1 and the input signal terminal IP can be input to the shift register using different signal lines. Alternatively, they can be input to the shift register using the same signal line, thus reducing the number of signal lines required.

[0124] The following is based on Figure 4a Taking the shift register shown as an example, combined with Figure 5b The signal timing diagram shown illustrates the operation of the shift register provided in the embodiments of this disclosure. Specifically, the following is selected: Figure 5b The signal timing diagram shown includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4.

[0125] In input phase T1, IP = 0, CK1 = 1, CK2 = 0, VS1 = 0.

[0126] Since CK1 = 1, the third transistor M3 is off. Since CK2 = 0, both the second transistor M2 and the fifth transistor M5 are on. The on fifth transistor M5 provides the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal of the pull-down node PD low, thus controlling the fourth transistor M4 and the seventh transistor M7 to turn on. The on seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, making the signal output terminal OP output a high-level signal. The on second transistor M2 provides the low-level signal from the input signal terminal IP to the second pull-up node PU_2, making the signal of the second pull-up node PU_2 low. The sixth transistor M6 turns on under the control of the signal from the second pull-up node PU_2, providing the low-level signal from the second clock signal terminal CK2 to the pull-down node PD, further making the signal of the pull-down node PD low. Since VS1 = 0, the V of the first transistor M1 can be turned on. th1Shift to the right, so that the first transistor M1 satisfies V gs1 <V th1 This is to ensure that the first transistor M1 is turned on as fully as possible. Since the signal of the first pull-up node PU_1 was high in the previous frame, the terminal connected to the first pull-up node PU_1 in the current frame serves as the source. The turned-on first transistor M1 connects the second pull-up node PU_2 to the first pull-up node PU_1, thus ensuring that the signal of the first pull-up node PU_1 is low in a timely manner, thereby controlling the turn-on of the eighth transistor M8. The turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0127] After input stage T1 and before output stage T2, since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are turned off. Since CK1 = 1, the third transistor M3 is also turned off. Therefore, the second pull-up node PU_2 and the first pull-up node PU_1 are in a floating state, and the first pull-up node PU_1 remains at a low level under the action of the second capacitor C2. Furthermore, since the threshold voltage V of the first transistor M1... th1 Because of this, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, in this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Since VS1 = 1, the voltage of the first transistor M1 can be reduced by VS1. th1 Shift left, thus preventing the first transistor M1 from satisfying V. gs1 <V th1 This causes the first transistor M1 to turn off. Due to the coupling capacitance of the transistors, the signal at the second pull-up node PU_2 can be made low, thus controlling the sixth transistor M6 to turn on. The turned-on sixth transistor M6 provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD, making the signal of the pull-down node PD a high-level signal, thereby controlling the fourth transistor M4 and the seventh transistor M7 to turn off. The eighth transistor M8 turns on under the control of the signal at the first pull-up node PU_1, providing the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0128] In the output phase T2, IP=1, CK1=0, CK2=1, VS1=1.

[0129] Since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are off. Therefore, the first pull-up node PU_1 remains at a low level under the action of the second capacitor C2, controlling the eighth transistor M8 to conduct. This provides the low-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing OP to output a low-level signal. Due to the action of the second capacitor C2, the level of the first pull-up node PU_1 is further pulled low, allowing the eighth transistor M8 to conduct as fully as possible, providing the low-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing OP to output a low-level signal. Furthermore, due to the threshold voltage V of the first transistor M1... th1 Because of this, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, in this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Since VS1 = 1, the voltage of the first transistor M1 can be reduced by VS1. th1 Shift left, and the gate voltage of the first transistor M1 is a low-level signal voltage, and the source voltage of the first transistor M1 is also a low-level signal voltage, thereby preventing the first transistor M1 from satisfying V. gs1 <V th1 This ensures that the first transistor M1 is turned off as much as possible, thereby maintaining a stable level at the first pull-up node PU_1 and preventing instability in the signal output terminal OP due to leakage causing a rise in the level of the first pull-up node PU_1. Furthermore, the first capacitor C1 maintains a high-level signal at the pull-down node PD, thus controlling the fourth transistor M4 and the seventh transistor M7 to be turned off, preventing adverse effects on the signal output at the signal output terminal OP.

[0130] During the reset phase T3, IP = 1, CK1 = 1, CK2 = 0, and VS1 = 1.

[0131] Since CK2 = 0, both the second transistor M2 and the fifth transistor M5 are turned on. The turned-on second transistor M2 provides the high-level signal at the input signal terminal IP to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 a high-level signal, thus controlling the sixth transistor M6 to turn off. Furthermore, during this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Although VS1 = 1, it can make the V of the first transistor M1... th1 Shift left. However, if the gate voltage of the first transistor M1 is a low-level signal voltage and the source voltage of the first transistor M1 is a high-level signal voltage, then the first transistor M1 can satisfy V gs1 <V th1The conduction of transistor M5 causes the second pull-up node PU_2 to conduct with the first pull-up node PU_1, thereby controlling the eighth transistor M8 to turn off. The conducting fifth transistor M5 provides the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal at pull-down node PD a low-level signal, thus controlling the fourth transistor M4 and the seventh transistor M7 to conduct. Furthermore, since CK1 = 1, the third transistor M3 is turned off. The conducting seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0132] During the reset holding phase T4, IP=1, CK1=0, CK2=1, VS1=1.

[0133] Since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are off. The first capacitor C1 keeps the signal at the pull-down node PD low, thus controlling the fourth transistor M4 and the seventh transistor M7 to conduct. Since CK1 = 0, the third transistor M3 is on. The conducting third transistor M3 and fourth transistor M4 provide the high-level signal of the second reference signal terminal VREF2 to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 high, thus controlling the sixth transistor M6 to turn off. Furthermore, during this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Although VS1 = 1, it can keep the V of the first transistor M1 low. th1 Shift left. However, if the gate voltage of the first transistor M1 is a low-level signal voltage and the source voltage of the first transistor M1 is a high-level signal voltage, then the first transistor M1 can satisfy V gs1 <V th1 When the transistor is turned on, the second pull-up node PU_2 is connected to the first pull-up node PU_1, thereby controlling the eighth transistor M8 to be turned off. The turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0134] After the reset hold phase T4, the reset phase T3 and reset hold phase T4 are repeated until the signal level of the input signal terminal IP goes low again.

[0135] This disclosure provides other shift registers, such as Figure 4b As shown, it targets Figure 4a The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 4a The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0136] In specific implementation, as described in the embodiments of this disclosure, Figure 4b As shown, the second gate of the first transistor M1 can be coupled to the first gate of the second transistor M2 to further reduce the space occupied by the signal lines. Furthermore, Figure 4b The signal timing diagram corresponding to the shift register shown is as follows: Figure 5b As shown, Figure 4b The working process of the shift register shown can be found in [reference needed]. Figure 4a The shift register shown is in Figure 5b The working process shown in the signal timing diagram is not described in detail here. Alternatively, in specific implementations, in the embodiments of this disclosure, the second gate of the first transistor M1 can be coupled to the gate of the second transistor M2 to further reduce the space occupied by the signal lines, which is not limited here.

[0137] Furthermore, according to Figure 5b The signal timing diagram shown is for Figure 4b The signal output from the shift register's signal output terminal OP is simulated, and the simulation diagram is shown below. Figure 6 As shown in the figure. The horizontal axis represents time, and the vertical axis represents voltage. Combined with... Figure 4b , Figure 5b as well as Figure 6 It can be seen that in the output stage T2, the signal output terminal OP can output a stable signal, thereby avoiding the instability caused by leakage of the first pull-up node PU_1.

[0138] This disclosure provides other shift registers, such as Figure 7 As shown, it targets Figure 4a The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 4a The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0139] In specific implementation, as described in the embodiments of this disclosure, Figure 7 As shown, the input circuit 10 may also include: a dual-gate type second transistor M2; wherein, the first gate of the second transistor M2 is configured to be coupled to the second clock signal terminal CK2, the second gate of the second transistor M2 is configured to be coupled to the second threshold control signal terminal VS2, the first terminal of the second transistor M2 is configured to be coupled to the input signal terminal IP, and the second terminal of the second transistor M2 is coupled to the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2).

[0140] In a specific implementation, in this embodiment of the disclosure, the second threshold modulation signal terminal VS2 is configured to receive a signal having a level opposite to that of the first reference signal terminal VREF1. For example, as Figure 8As shown, a portion of the signal at the second threshold control signal terminal VS2 can be opposite to the level of the signal at the first reference signal terminal VREF1, and the remaining portion of the signal at the second threshold control signal terminal VS2 can be the same as the level of the signal at the first reference signal terminal VREF1.

[0141] In a specific implementation, in the embodiments of this disclosure, the thickness of the gate insulating layer can be adjusted to make the first gate of the second transistor dominate, thus the voltage difference V between the gate (i.e., the first gate) and the source of the second transistor M2 is... gs2 Its threshold voltage V th2 The relationship between them satisfies the formula V gs2 <V th2 Time conduction. From now on, V will be used. gs2 The following explanation uses the voltage difference between the first gate and the source of the second transistor M2 as an example.

[0142] In specific implementation, as described in the embodiments of this disclosure, Figure 7 As shown, the pull-up control circuit 30 may also include: a third transistor M3 and a dual-gate fourth transistor M4; wherein, the gate of the third transistor M3 is configured to be coupled to the first clock signal terminal CK1, the first terminal of the third transistor M2 is coupled to the first terminal of the first transistor M1 (i.e., the second pull-up node PU_2), and the second terminal of the third transistor M3 is coupled to the first terminal of the fourth transistor M4. The first gate of the fourth transistor M4 is coupled to the gate of the seventh transistor M7 (i.e., the pull-down node PD), the second gate of the fourth transistor M4 is configured to be coupled to the third threshold control signal terminal VS3, and the second terminal of the fourth transistor M4 is configured to be coupled to the second reference signal terminal VREF2.

[0143] In a specific implementation, in this embodiment of the disclosure, the third threshold modulation signal terminal VS3 is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal VREF1. For example, as Figure 8 As shown, a portion of the signal at the third threshold control signal terminal VS3 can be opposite to the level of the first reference signal terminal VREF1, and the remaining portion of the signal at the third threshold control signal terminal VS3 can be the same as the level of the first reference signal terminal VREF1.

[0144] In a specific implementation, in the embodiments of this disclosure, the thickness of the gate insulating layer can be adjusted to make the first gate of the fourth transistor dominant, thus the voltage difference V between the gate (i.e., the first gate) and the source of the fourth transistor M4 is... gs4 Its threshold voltage V th4 The relationship between them satisfies the formula V gs4 <V th4 Time conduction. From now on, V will be used. gs4The following explanation uses the voltage difference between the first gate and the source of the fourth transistor M4 as an example.

[0145] The following is based on Figure 7 Taking the shift register shown as an example, combined with Figure 8 The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure.

[0146] Specifically, select such as Figure 8 The signal timing diagram shown includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4.

[0147] In input phase T1, IP = 0, CK1 = 1, CK2 = 0, VS1 = 0, VS2 = 0, VS3 = 0.

[0148] Since CK1 = 1, the third transistor M3 is off. Since CK2 = 0, the fifth transistor M5 is on, providing the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal at the pull-down node PD a low-level signal, thus controlling the seventh transistor M7 to turn on. The on-state seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal. Since CK2 = 0 and VS2 = 0, the threshold voltage V of the second transistor M2 is reduced. th2 The transistor can be shifted to the right to make the second transistor M2 as fully turned on as possible, thereby accelerating the charging process of providing the low-level signal from the input signal terminal IP to the second pull-up node PU_2, and making the signal of the second pull-up node PU_2 a low-level signal as quickly as possible. The sixth transistor M6 is turned on under the control of the signal from the second pull-up node PU_2 to provide the low-level signal from the second clock signal terminal CK2 to the pull-down node PD, further making the signal of the pull-down node PD a low-level signal. Since VS1 = 0, the V of the first transistor M1 can be... th1 Shift to the right, so that the first transistor M1 satisfies V gs1 <V th1 This ensures that the first transistor M1 is turned on as fully as possible. The turned-on first transistor M1 connects the second pull-up node PU_2 and the first pull-up node PU_1, thus ensuring that the signal at the first pull-up node PU_1 is low in a timely manner, thereby controlling the eighth transistor M8 to turn on. The turned-on eighth transistor M8 provides the high-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0149] After input stage T1 and before output stage T2, since CK2 = 1, the fifth transistor M5 is turned off. Since CK1 = 1, the third transistor M3 is also turned off. Since VS1 = 1 and CK2 = 1, the voltage of the second transistor M2 can be turned off. th2 Shifting left causes the second transistor M2 to no longer satisfy V. gs2 <V th2 And to keep it as low as possible. Therefore, the first pull-up node PU_1 remains at a low level under the action of the second capacitor C2. Furthermore, due to the threshold voltage V of the first transistor M1... th1 Because of this, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, in this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Since VS1 = 1, the voltage of the first transistor M1 can be reduced by VS1. th1 Shift left, thus preventing the first transistor M1 from satisfying V. gs1 <V th1 This causes the first transistor M1 to turn off. Due to the coupling capacitance of the transistors, the signal at the second pull-up node PU_2 can be made low, thus controlling the sixth transistor M6 to turn on. The turned-on sixth transistor M6 provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD, making the signal of the pull-down node PD a high-level signal, thereby controlling the fourth transistor M4 and the seventh transistor M7 to turn off. The eighth transistor M8 turns on under the control of the signal at the first pull-up node PU_1, providing the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal.

[0150] In the output phase T2, IP=1, CK1=0, CK2=1, VS1=1, VS2=1, VS3=1.

[0151] Since CK2 = 1, the fifth transistor M5 is off. The first pull-up node PU_1 remains low under the influence of the second capacitor C2, controlling the eighth transistor M8 to conduct, thereby providing the low-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing OP to output a low-level signal. Due to the effect of the second capacitor C2, the level of the first pull-up node PU_1 is further pulled low, controlling the eighth transistor M8 to conduct as fully as possible, providing the low-level signal from the first clock signal terminal CK1 to the signal output terminal OP, causing OP to output a low-level signal. Furthermore, due to the threshold voltage V of the first transistor M1... th1Because of this, the voltage of the low-level signal of the first pull-up node PU_1 can be less than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, in this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Since VS1 = 1, the voltage of the first transistor M1 can be reduced by VS1. th1 Shift left, and the gate voltage of the first transistor M1 is a low-level signal voltage, and the source voltage of the first transistor M1 is also a low-level signal voltage, thereby preventing the first transistor M1 from satisfying V. gs1 <V th1 This allows the first transistor M1 to be turned off, thus maintaining a stable level at the first pull-up node PU_1 and preventing instability in the signal output terminal OP due to leakage current causing a rise in the level of the first pull-up node PU_1. Furthermore, since CK2=1 and VS2=1, the threshold voltage of the second transistor M2 can be shifted to the left, allowing the second transistor M2 to be turned off as completely as possible. This avoids the leakage current of the second transistor M2 affecting the leakage current of the second pull-up node PU_2, extending the holding time of the low-level signal of the second pull-up node PU_2. Additionally, since VS3=1 and the signal of the pull-down node PD is a high-level signal, the threshold voltage of the fourth transistor M4 can be shifted to the left, allowing the fourth transistor M4 to be turned off as completely as possible. This avoids the leakage current of the fourth transistor M4 affecting the leakage current of the second pull-up node PU_2, extending the holding time of the low-level signal of the second pull-up node PU_2. The sixth transistor M6, under the control of the signal from the second pull-up node PU_2, provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD, so as to control the seventh transistor M7 to be turned off and avoid adversely affecting the signal output from the signal output terminal OP.

[0152] During the reset phase T3, IP = 1, CK1 = 1, CK2 = 0, VS1 = 1, VS2 = 1, and VS3 = 0.

[0153] Since CK2 = 0, both the second transistor M2 and the fifth transistor M5 are turned on. The turned-on second transistor M2 provides the high-level signal at the input signal terminal IP to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 a high-level signal, thus controlling the sixth transistor M6 to turn off. Furthermore, during this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Although VS1 = 1, it can make the V of the first transistor M1... th1 Shift left. However, if the gate voltage of the first transistor M1 is a low-level signal voltage and the source voltage of the first transistor M1 is a high-level signal voltage, then the first transistor M1 can satisfy V gs1 <V th1The conduction of transistor M5 connects the second pull-up node PU_2 to the first pull-up node PU_1, thus controlling the eighth transistor M8 to turn off. The conducting fifth transistor M5 provides the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal at pull-down node PD low, thereby controlling the seventh transistor M7 to conduct. The conducting seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal. Furthermore, since CK1 = 1, the third transistor M3 is turned off.

[0154] During the reset holding phase T4, IP = 1, CK1 = 0, CK2 = 1, VS1 = 1, VS2 = 1, and VS3 = 0.

[0155] Since CK2 = 1, both the second transistor M2 and the fifth transistor M5 are off. The first capacitor C1 keeps the signal at the pull-down node PD low, controlling the seventh transistor M7 to turn on. This provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, causing OP to output a high-level signal. Since VS3 = 0 and the signal at the pull-down node PD is low, the fourth transistor M4 is controlled to be fully turned on. Since CK1 = 0, the third transistor M3 is turned on. The turned-on third transistor M3 and fourth transistor M4 can promptly provide the high-level signal from the second reference signal terminal VREF2 to the second pull-up node PU_2, thus controlling the signal at the second pull-up node PU_2 to be high and turning off the sixth transistor M6. Furthermore, during this stage, the terminal of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source. Although VS1 = 1, it can keep the voltage of the first transistor M1 low. th1 Shift left. However, if the gate voltage of the first transistor M1 is a low-level signal voltage and the source voltage of the first transistor M1 is a high-level signal voltage, then the first transistor M1 can satisfy V gs1 <V th1 When the circuit is turned on, the second pull-up node PU_2 is connected to the first pull-up node PU_1, thereby controlling the eighth transistor M8 to be turned off.

[0156] After the reset hold phase T4, the reset phase T3 and reset hold phase T4 are repeated until the signal level at the input signal terminal IP becomes high again.

[0157] This disclosure provides several other shift registers, such as... Figure 9a As shown, it targets Figure 7 The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 7The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0158] To reduce the number of signal lines used for signal transmission, in specific implementations, as described in the embodiments of this disclosure, Figure 9a As shown, the second gate of the first transistor M1 can be coupled to the first terminal of the second transistor M2. This allows the first threshold control signal terminal and the input signal terminal to receive the same signal; that is, the second gate of the first transistor M1 receives the signal from the input signal terminal IP, further reducing the space occupied by the signal line. This allows signals to be input to both the first threshold control signal terminal and the input signal terminal using the same signal line.

[0159] To reduce the number of signal lines used for signal transmission, in specific implementations, as described in the embodiments of this disclosure, Figure 9a As shown, the second gate of the second transistor M2 can be coupled to its first terminal. This allows the second threshold control signal terminal and the input signal terminal to receive the same signal, meaning the second gate of the second transistor M2 receives the signal from the input signal terminal IP, further reducing the space occupied by the signal line. This allows signals to be input to both the second threshold control signal terminal and the input signal terminal using the same signal line.

[0160] To reduce the number of signal lines used for signal transmission, in specific implementations of this disclosure, the first threshold control signal terminal and the second threshold control signal terminal can be configured to receive the same signal. For example... Figure 9a As shown, the second gate of the first transistor M1 can be coupled to the second gate of the second transistor M2 so that both can receive the signal from the input signal terminal IP.

[0161] To reduce the number of signal lines used for signal transmission, in specific implementations of this disclosure, the signal at the third threshold control terminal and the signal at the pull-down node can be set to the same signal. For example... Figure 9a As shown, the second gate of the fourth transistor M4 can be coupled to the gate (i.e., the pull-down node PD) of the seventh transistor M7.

[0162] In practice, Figure 9a The working process of the shift register shown can be found in [reference needed]. Figure 7 The operation of the shift register shown will not be elaborated here. Furthermore, the following is also discussed... Figure 9a The signal output from the shift register's signal output terminal OP and the signal from the first pull-up node PU_1 are simulated, as shown. Figure 9b and Figure 9c As shown in the figure. The horizontal axis represents time, and the vertical axis represents voltage. Combined with... Figures 9a to 9cIt can be seen that in the output stage T2, the signal output terminal OP can output a stable signal, thereby avoiding the instability caused by leakage of the first pull-up node PU_1.

[0163] This disclosure provides further signal timing diagrams for shift registers, such as... Figure 10a and Figure 10b As shown, it targets Figure 8 The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 8 The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0164] To reduce the number of signal lines used for signal transmission, in specific implementations, as described in the embodiments of this disclosure, Figure 10a and Figure 10b As shown, the first threshold control signal terminal VS1 can be configured as a clock signal.

[0165] To reduce the number of signal lines used for signal transmission, in specific implementations, as described in the embodiments of this disclosure, Figure 10a and Figure 10b As shown, the second threshold control signal terminal VS2 can be configured as a clock signal.

[0166] To reduce the number of signal lines used for signal transmission, in specific implementations, as shown in Figure 10 and... Figure 10b As shown, the third threshold control signal terminal VS3 can be configured as a clock signal.

[0167] Furthermore, in order to reduce the number of signal lines used for transmitting signals, in specific implementations, as described in the embodiments of this disclosure, Figure 10a As shown, the first threshold control signal terminal VS1 and the second threshold control signal terminal VS2 can be configured to receive the same signal.

[0168] Furthermore, in order to reduce the number of signal lines used for transmitting signals, in specific implementations, as described in the embodiments of this disclosure, Figure 10a As shown, the first threshold control signal terminal VS1 and the third threshold control signal terminal VS3 can be configured to receive the same signal.

[0169] Furthermore, in order to reduce the number of signal lines used for transmitting signals, in specific implementations, as described in the embodiments of this disclosure, Figure 10a As shown, the first threshold control signal terminal VS1, the second threshold control signal terminal VS2, and the third threshold control signal terminal VS3 can be configured to receive the same signal. This allows a single signal line to be used to input a clock signal to the first threshold control signal terminal VS1, the second threshold control signal terminal VS2, and the third threshold control signal terminal VS3.

[0170] The following is based on Figure 7Taking the shift register shown as an example, combined with Figure 10b The signal timing diagram shown illustrates the operation of the shift register provided in the embodiments of this disclosure. Specifically, the following is selected: Figure 10b The signal timing diagram shown includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4.

[0171] In input phase T1, IP = 0, CK1 = 1, CK2 = 0, VS1 = 0, VS2 = 0, VS3 = 0. The working process of this phase can be found in [link to relevant documentation]. Figure 7 The operation of the shift register shown in the input stage T1 will not be described in detail here.

[0172] After input phase T1 and before output phase T2, see also Figure 7 The operation of the shift register shown, after input stage T1 and before output stage T2, will not be described in detail here.

[0173] In output phase T2, IP = 1, CK1 = 0, CK2 = 1, VS1 = 1, VS2 = 1, and VS3 = 1. The working process of this phase can be found in [link to documentation]. Figure 7 The operation of the shift register shown in the output stage T2 will not be described in detail here.

[0174] During the reset phase T3, IP = 1, CK1 = 1, CK2 = 0, VS1 = 0, VS2 = 0, and VS3 = 0. Since CK2 = 0 and VS2 = 0, the threshold voltage V of the second transistor M2 is reduced. th2 The transistor can be shifted to the right to ensure that the second transistor M2 is fully turned on as much as possible, thereby accelerating the charging process of providing the high-level signal from the input signal terminal IP to the second pull-up node PU_2, and ensuring that the signal of the second pull-up node PU_2 becomes a high-level signal as quickly as possible. Since VS1 = 0 and the first reference signal terminal VREF1 is a low-level signal, the first transistor M1 can be turned on promptly to provide the high-level signal from the second pull-up node PU_2 to the first pull-up node PU_1, thus controlling the eighth transistor M8 to turn off. The remaining operation of this stage can be found in [reference needed]. Figure 7 The operation of the shift register shown in the reset phase T3 will not be described in detail here.

[0175] During the reset hold phase T4, IP = 1, CK1 = 0, CK2 = 1, VS1 = 1, VS2 = 1, and VS3 = 1. Although, since VS3 = 1, the V of the fourth transistor M4 can be... th4 Shifting left, however, if the gate voltage of the fourth transistor M4 is a low-level signal voltage and the source voltage of the fourth transistor M4 is a high-level signal voltage, then the fourth transistor M4 can satisfy Vgs4 <V th4 And then it's connected. The remaining steps in this stage can be found in [link to documentation]. Figure 7 The operation of the shift register shown in the reset and hold phase T4 will not be described in detail here.

[0176] After the reset hold phase T4, the reset phase T3 and reset hold phase T4 are repeated until the signal level at the input signal terminal IP becomes high again.

[0177] This disclosure provides further signal timing diagrams for shift registers, such as... Figure 10c As shown, it targets Figure 8 The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 8 The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0178] To reduce computational load, in specific implementations, as described in this disclosure embodiment, Figure 10c As shown, the first threshold control signal terminal VS1 can be configured to have the same timing as the second clock signal terminal CK2. This allows the timing of the second clock signal terminal CK2 to be directly used as the input clock signal to the first threshold control signal terminal VS1.

[0179] To reduce computational load, in specific implementations, as described in this disclosure embodiment, Figure 10c As shown, the second threshold control signal terminal VS2 can be configured to have the same timing as the second clock signal terminal CK2. This allows the timing of the second clock signal terminal CK2 to be directly used as the input clock signal to the second threshold control signal terminal VS2.

[0180] To reduce computational load, in specific implementations, as described in this disclosure embodiment, Figure 10c As shown, the third threshold control signal terminal VS3 can be configured to have the same timing as the second clock signal terminal CK2. This allows the timing of the second clock signal terminal CK2 to be directly used as the input clock signal to the third threshold control signal terminal VS3.

[0181] In practice, Figure 8 The shift register shown is in Figure 10c The working process shown in the signal timing diagram can be found in [reference]. Figure 8 The shift register shown is in Figure 10b The working process shown in the signal timing diagram will not be elaborated here.

[0182] This disclosure provides several other shift registers, such as... Figure 11 As shown, it targets Figure 7The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 7 The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0183] In specific implementations, in this embodiment of the disclosure, the first threshold control signal terminal and the second clock signal terminal can be set to the same clock signal. For example... Figure 11 and Figure 12 As shown, the first threshold control signal terminal is the second clock signal terminal CK2. The second gate of the first transistor M1 is coupled to the first gate of the second transistor M2, so that the second gate of the first transistor M1 receives the signal from the second clock signal terminal CK2. In this way, the same signal line can be used to input signals to both the first threshold control signal terminal and the second clock signal terminal.

[0184] In specific implementations, in the embodiments of this disclosure, the second threshold control signal terminal and the second clock signal terminal can be set to the same clock signal. For example... Figure 11 and Figure 12 As shown, the second threshold control signal terminal is the second clock signal terminal CK2. The second gate of the second transistor M2 is coupled to the first gate of the second transistor M2 so that the second gate of the second transistor M2 receives the signal from the second clock signal terminal CK2. This allows signals to be input to both the first threshold control signal terminal and the second clock signal terminal using the same signal line.

[0185] In specific implementations, in this embodiment of the disclosure, the third threshold control signal terminal and the second clock signal terminal can be set to the same clock signal. For example... Figure 11 and Figure 12 As shown, the second gate of the fourth transistor M4 is coupled to the gate of the fifth transistor M5. Alternatively, the second gate of the fourth transistor M4 can be coupled to the first gate of the second transistor M2, so that the second gate of the fourth transistor M4 receives the signal from the second clock signal terminal CK2. This allows signals to be input to both the first threshold control signal terminal and the second clock signal terminal using the same signal line.

[0186] The following is based on Figure 11 Taking the shift register shown as an example, combined with Figure 12 The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure.

[0187] During input phase T1, IP = 0, CK1 = 1, and CK2 = 0. The working process of this phase can be found in [link to relevant documentation]. Figure 7 The operation of the shift register shown in the input stage T1 will not be described in detail here.

[0188] The process after input phase T1 and before output phase T2 can also be found in [reference needed]. Figure 7The operation of the shift register shown, after input stage T1 and before output stage T2, will not be described in detail here.

[0189] Output phase T2, IP=1, CK1=0, CK2=1. The working process of this phase can be found in [link to documentation]. Figure 7 The operation of the shift register shown in the output stage T2 will not be described in detail here.

[0190] During the reset phase T3, IP = 1, CK1 = 1, and CK2 = 0. Since CK2 = 0, the second transistor M2 can be fully turned on as much as possible, providing the high-level signal from the input signal terminal IP to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 a high-level signal, and thus controlling the sixth transistor M6 to turn off. Furthermore, since CK2 = 0 and the first reference signal terminal VREF1 is a low-level signal, the first transistor M1 can be turned on promptly, providing the high-level signal from the second pull-up node PU_2 to the first pull-up node PU_1, making the signal at the first pull-up node PU_1 a high-level signal, and thus controlling the eighth transistor M8 to turn off. The remaining operation of this phase can be found in [reference needed]. Figure 7 The operation of the shift register shown in the reset phase T3 will not be described in detail here.

[0191] During the reset hold phase T4, IP = 1, CK1 = 0, CK2 = 1. Although, since CK2 = 1, the V of the fourth transistor M4 can be... th4 Shifting left, however, with the gate (i.e., the first gate) of the fourth transistor M4 at a low-level voltage and the source (i.e., the terminal coupled to the second reference signal terminal VREF2) of the fourth transistor M4 at a high-level voltage, the fourth transistor M4 can satisfy V gs4 <V th4 And then it's connected. The remaining steps in this stage can be found in [link to documentation]. Figure 7 The operation of the shift register shown in the reset and hold phase T4 will not be described in detail here.

[0192] This disclosure provides several other shift registers, such as... Figure 13 As shown, it targets Figure 11 The illustrated implementation has been modified. The following description only refers to this embodiment and... Figure 11 The differences between the embodiments of the shift register shown are as follows, while the similarities are not described here.

[0193] To reduce the number of signal lines used for signal transmission, in specific implementations of this disclosure, the signal at the third threshold control terminal and the signal at the pull-down node can be the same signal. For example... Figure 13As shown, the second gate of the fourth transistor M4 is coupled to the gate (i.e., the pull-down node PD) of the seventh transistor M7.

[0194] The following is based on Figure 13 Taking the shift register shown as an example, combined with Figure 12 The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure.

[0195] Specifically, select such as Figure 12 The signal timing diagram shown includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4.

[0196] During input phase T1, IP = 0, CK1 = 1, and CK2 = 0. The working process of this phase can be found in [link to relevant documentation]. Figure 7 The operation of the shift register shown in the input stage T1 will not be described in detail here.

[0197] The process after input phase T1 and before output phase T2 can also be found in [reference needed]. Figure 7 The operation of the shift register shown, after input stage T1 and before output stage T2, will not be described in detail here.

[0198] Output phase T2, IP=1, CK1=0, CK2=1. The working process of this phase can be found in [link to documentation]. Figure 7 The operation of the shift register shown in the output stage T2 will not be described in detail here.

[0199] During the reset phase T3, IP = 1, CK1 = 1, and CK2 = 0. Since CK2 = 0, the second transistor M2 can be fully turned on as much as possible, providing the high-level signal from the input signal terminal IP to the second pull-up node PU_2, making the signal at the second pull-up node PU_2 a high-level signal, and thus controlling the sixth transistor M6 to turn off. Furthermore, since CK2 = 0 and the first reference signal terminal VREF1 is a low-level signal, the first transistor M1 can be turned on promptly, providing the high-level signal from the second pull-up node PU_2 to the first pull-up node PU_1, making the signal at the first pull-up node PU_1 a high-level signal, and thus controlling the eighth transistor M8 to turn off. The remaining operation of this phase can be found in [reference needed]. Figure 7 The operation of the shift register shown in the reset phase T3 will not be described in detail here.

[0200] During the reset hold phase T4, IP = 1, CK1 = 0, and CK2 = 1. The working process of this phase can be found in [link to relevant documentation]. Figure 7 The operation of the shift register shown in the reset and hold phase T4 will not be described in detail here.

[0201] This disclosure provides several other shift registers, such as... Figure 14a As shown, it targets Figure 8 The implementation of the signal timing diagram shown has been modified. The following only describes this embodiment and... Figure 8 The differences between the signal timing diagrams shown are not detailed here, but their similarities are not elaborated upon.

[0202] In specific implementation, as described in the embodiments of this disclosure, Figure 14b As shown, the first threshold control signal terminal VS1 can be set to receive a fixed voltage signal, such as a DC fixed voltage signal with a first voltage value, to ensure that the first transistor M1 can be completely cut off as much as possible in the output stage T2, thereby reducing the leakage current's impact on the first pull-up node PU_1. Specifically, when the first transistor M1 is a P-type transistor, the first threshold control signal terminal VS1 can be set to receive a high-level fixed voltage signal. Furthermore, when the display device uses different refresh frequencies, the first voltage value can be set according to the actual application. For example, when the display device uses a lower refresh frequency, since the shift register operates at a lower refresh frequency (e.g., 1Hz) or in a hold state, the first voltage value can be set to a high voltage to reduce leakage current and ensure the stability of the shift register output, thus preventing the shift register from malfunctioning. Alternatively, when the display device uses a higher refresh frequency, since the shift register operates at a higher refresh frequency (e.g., 60Hz, 120Hz), the first voltage value can be set to 0V or a negative voltage to ensure the shift register's response speed. Of course, the above-mentioned first voltage value can be designed and determined according to the actual application environment, and is not limited here.

[0203] In practical implementation, when the first transistor M1 is an N-type transistor, the first threshold control signal terminal VS1 can be set to receive a low-level fixed voltage signal. Furthermore, when the display device uses different refresh rates, the first voltage value can be set according to the actual application, and no limitation is made here.

[0204] In specific implementations, in this embodiment, the second threshold control signal terminal VS2 can also be configured to receive a fixed voltage signal, such as a DC fixed voltage signal with a second voltage value, to ensure that the second transistor M2 can be completely cut off as much as possible during the output stage T2, thereby reducing the leakage current's impact on the second pull-up node PU_2. Specifically, when the second transistor M2 is a P-type transistor, the second threshold control signal terminal VS2 can be configured to receive a high-level fixed voltage signal. Furthermore, when the display device uses different refresh frequencies, the second voltage value can be set according to the actual application. For example, when the display device uses a lower refresh frequency, since the shift register operates at a lower refresh frequency (e.g., 1Hz) or in a hold state, the second voltage value can be set to a high voltage to reduce leakage current and ensure the stability of the shift register output, so that the shift register will not malfunction. Alternatively, when the display device uses a higher refresh frequency, since the shift register operates at a higher refresh frequency (e.g., 60Hz, 120Hz), the second voltage value can be set to 0V or a negative voltage to ensure the shift register's response speed. Of course, the second voltage value mentioned above can be designed and determined according to the actual application environment, and is not limited here.

[0205] In practical implementation, when the second transistor M2 is an N-type transistor, the second threshold control signal terminal VS2 can be set to receive a low-level fixed voltage signal. Furthermore, when the display device uses different refresh rates, the second voltage value can be set according to the actual application, and is not limited here.

[0206] In specific implementations, in this embodiment, the third threshold control signal terminal VS3 can also be set to receive a fixed voltage signal, such as a DC fixed voltage signal with a third voltage value, to ensure that the fourth transistor M4 can be completely cut off as much as possible in the output stage T2, thereby reducing the leakage current's impact on the second pull-up node PU_2. Specifically, when the fourth transistor M4 is a P-type transistor, the third threshold control signal terminal VS3 can be set to receive a high-level fixed voltage signal. Furthermore, when the display device uses different refresh frequencies, the third voltage value can be set according to the actual application. For example, when the display device uses a lower refresh frequency, since the shift register operates at a lower refresh frequency (e.g., 1Hz) or in a hold state, the third voltage value can be set to a high voltage to reduce leakage current and ensure the stability of the shift register output, so that the shift register will not malfunction. Alternatively, when the display device uses a higher refresh frequency, since the shift register operates at a higher refresh frequency (e.g., 60Hz, 120Hz), the third voltage value can be set to 0V or a negative voltage to ensure the shift register's response speed. Of course, the third voltage value mentioned above can be designed and determined according to the actual application environment, and is not limited here.

[0207] In practical implementation, when the fourth transistor M4 is an N-type transistor, the third threshold control signal terminal VS3 can be set to receive a low-level fixed voltage signal. Furthermore, when the display device uses different refresh rates, the third voltage value can be set according to the actual application, and is not limited here.

[0208] Furthermore, to reduce the number of signal lines used for signal transmission, in specific implementations, in this embodiment, the second threshold control signal terminal VS2 and the first threshold control signal terminal VS1 can be configured to receive the same signal. For example, Figure 14a As shown, the second gate of the first transistor M1 is coupled to the second gate of the second transistor M2 so as to receive the signal from the first threshold control signal terminal VS1, so as to input the signal to the second gate of the first transistor M1 and the second gate of the second transistor M2 using a single signal line.

[0209] Furthermore, to reduce the number of signal lines used for signal transmission, in specific implementations, in this embodiment, the third threshold control signal terminal VS3 and the first threshold control signal terminal VS1 can be configured to receive the same signal. For example, Figure 14a As shown, the second gate of the first transistor M1 and the second gate of the fourth transistor M4 are coupled to receive the signal from the first threshold control signal terminal VS1, so as to input the signal to the second gate of the first transistor M1 and the second gate of the fourth transistor M4 using a single signal line.

[0210] Furthermore, in specific implementations, in this embodiment of the disclosure, the third threshold control signal terminal VS3, the second threshold control signal terminal VS2, and the first threshold control signal terminal VS1 can also be configured to receive the same signal. For example, Figure 14a As shown, the second gates of the first transistor M1, the second gate of the second transistor M2, and the second gate of the fourth transistor M4 are coupled together to receive the signal from the first threshold control signal terminal VS1, so as to input a signal to the second gates of the first transistor M1, the second gate of the second transistor M2, and the second gate of the fourth transistor M4 using a single signal line.

[0211] The following is based on Figure 14a Taking the shift register shown as an example, combined with Figure 14b The signal timing diagram shown describes the operation of the shift register provided in the embodiments of this disclosure.

[0212] Specifically, select such as Figure 14b The signal timing diagram shown includes four stages: input stage T1, output stage T2, reset stage T3, and reset hold stage T4.

[0213] During input phase T1, IP = 0, CK1 = 1, CK2 = 0, and VS1 = 1. Since CK1 = 1, the third transistor M3 is off. Since CK2 = 0, the fifth transistor M5 is on, providing the low-level signal from the first reference signal terminal VREF1 to the pull-down node PD, making the signal at pull-down node PD low, thus controlling the seventh transistor M7 to turn on. The on-state seventh transistor M7 provides the high-level signal from the second reference signal terminal VREF2 to the signal output terminal OP, causing the signal output terminal OP to output a high-level signal. Although since VS1 = 1, the V of the second transistor M2 can be turned off. th2 Shifting left, however, since CK2 = 0 and IP = 0, the second transistor M2 will still cause the second pull-up node PU_2 to discharge, making the signal of the second pull-up node PU_2 a low-level signal. Although since VS1 = 1, the V of the first transistor M1 can be... th1 Shift left; however, since the first reference signal VREF is low and the signal of the first pull-up node PU_1 is high, the first transistor M1 satisfies V. gs1 <V th1 This turns on the first transistor M1, thus turning it on. The operation process of this stage can be found in [reference needed]. Figure 8 The working process in the input stage T1 will not be described in detail here.

[0214] The process after input phase T1 and before output phase T2 can also be found in [reference needed]. Figure 8 The working process after input stage T1 and before output stage T2 will not be described in detail here.

[0215] In output phase T2, IP=1, CK1=0, CK2=1, VS1=1. The working process of this phase can be found in [link to documentation]. Figure 8 The working process in the output stage T2 will not be described in detail here.

[0216] During the reset phase T3, IP=1, CK1=1, CK2=0, VS1=1. The remaining procedures for this phase can be found in [link to relevant documentation]. Figure 8 The working process during the reset phase T3 will not be described in detail here.

[0217] During the reset hold phase T4, IP = 1, CK1 = 0, CK2 = 1, and VS1 = 1. Although, since VS3 = 1, the V of the fourth transistor M4 can be... th4 Shifting left, however, if the gate voltage of the fourth transistor M4 is a low-level signal voltage and the source voltage of the fourth transistor M4 is a high-level signal voltage, then the fourth transistor M4 can satisfy V gs4 <V th4 And then it's connected. The remaining steps in this stage can be found in [link to documentation]. Figure 8The working process during the reset and holding phase T4 will not be described in detail here.

[0218] Based on the same inventive concept, this disclosure also provides a driving method for the above-mentioned shift register, wherein, as Figure 15 As shown, it may include:

[0219] S100, Input stage: The input circuit controls the signal level of the first terminal of the first transistor according to the signal of the input signal terminal and the second clock signal terminal; the first transistor is turned on; the output circuit responds to the signal of the second terminal of the first transistor and provides the signal of the first clock signal terminal to the signal output terminal.

[0220] S200, Output stage: The threshold voltage of the first transistor moves in response to the signal at the first threshold control signal terminal, and the first transistor is turned off; the output circuit responds to the signal at the second terminal of the first transistor and provides the signal at the first clock signal terminal to the signal output terminal; wherein, the signal at the first threshold control signal terminal is opposite in level to the signal at the first reference signal terminal.

[0221] In a specific implementation, in the embodiments of this disclosure, during the output stage, the threshold voltage of the second transistor moves in response to the signal at the second threshold control signal terminal, and the second transistor is turned off; the threshold voltage of the fourth transistor moves in response to the signal at the third threshold control signal terminal, and the fourth transistor is turned off.

[0222] In specific implementation, as described in the embodiments of this disclosure, Figure 15 As shown, the S100 input stage may further include: the fifth transistor responding to the signal at the second clock signal terminal to provide the signal at the first reference signal terminal to the gate of the seventh transistor; the sixth transistor responding to the signal at the first terminal of the first transistor to provide the signal at the second clock signal terminal to the gate of the seventh transistor; and the seventh transistor responding to the signal at the gate of the seventh transistor to provide the signal at the second reference signal terminal to the signal output terminal.

[0223] In specific implementation, as described in the embodiments of this disclosure, Figure 15 As shown, after the output stage S200, the driving method may further include:

[0224] S300, during the reset phase, the input circuit controls the signal level of the first terminal of the first transistor according to the signals of the input signal terminal and the second clock signal terminal; the first transistor turns on the input circuit and the output circuit; the fifth transistor responds to the signal of the second clock signal terminal and provides the signal of the first reference signal terminal to the gate of the seventh transistor; the seventh transistor responds to the signal of the gate of the seventh transistor and provides the signal of the second reference signal terminal to the signal output terminal.

[0225] In a specific implementation, in this embodiment of the disclosure, after the reset phase S300, the driving method may further include:

[0226] During the reset and hold phase, the first capacitor holds the signal of the gate of the seventh transistor; the seventh transistor, in response to the signal of its gate, provides the signal of the second reference signal terminal to the signal output terminal; the pull-up control circuit, in response to the signals of the first clock signal terminal and the gate of the seventh transistor, provides the signal of the second reference signal terminal to the second pull-up node.

[0227] The driving principle and specific implementation of this driving method are the same as those of the shift register in the above embodiments. Therefore, this driving method can be implemented by referring to the specific implementation of the shift register in the above embodiments, and will not be repeated here.

[0228] Based on the same inventive concept, embodiments of this disclosure also provide a gate driving circuit, such as... Figure 16 As shown, the present disclosure includes multiple cascaded shift registers SR(1), SR(2)...SR(n-1), SR(n)...SR(N-1), SR(N) (a total of N shift registers, 1≤n≤N); wherein, the input signal terminal IP of the first-stage shift register SR(1) is configured to be coupled to the frame trigger signal terminal STV;

[0229] In each pair of adjacent shift registers, the input signal terminal IP of the next-level shift register SR(n) is configured to be coupled to the signal output terminal OP of the previous-level shift register SR(n-1).

[0230] Specifically, the specific structure of each shift register in the gate driving circuit described above is the same as that of the shift registers described in this disclosure in terms of function and structure, and the repetitions will not be repeated. This gate driving circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, and is not limited thereto.

[0231] Specifically, in the gate drive circuit provided in the embodiments of this disclosure, such as Figure 16 As shown, the first reference signal terminal VREF1 of each shift register SR(n) is coupled to the same DC signal terminal vdd, and the second reference signal terminal VREF2 of each shift register SR(n) is coupled to the same DC signal terminal vss.

[0232] Specifically, in the gate drive circuit provided in the embodiments of this disclosure, such as Figure 16As shown, the first clock signal terminal CK1 of the (2k-1)th stage shift register and the second clock signal terminal CK2 of the 2kth stage shift register are both coupled to the same clock terminal, namely the first clock terminal ck1; the second clock signal terminal CK2 of the (2k-1)th stage shift register and the first clock signal terminal CK1 of the 2kth stage shift register are both coupled to the same clock terminal, namely the second clock terminal ck2; where k is a positive integer.

[0233] Specifically, when the first threshold control signal terminal is configured to receive a clock signal with the same timing as the second clock signal terminal, the first threshold control signal terminal of the 2k-1 stage shift register and the first threshold control signal terminal of the 2k-1 stage shift register are both coupled to the same clock terminal, namely the third clock terminal ck3; the first threshold control signal terminal of the 2k-1 stage shift register and the first threshold control signal terminal of the 2k-1 stage shift register are both coupled to the same clock terminal, namely the fourth clock terminal ck4.

[0234] Specifically, when the third threshold control signal terminal is configured to receive a clock signal with the same timing as the second clock signal terminal, the third threshold control signal terminals of the 2k-1 stage shift register and the 2k stage shift register are both coupled to the same clock terminal, namely the fifth clock terminal ck5; the third threshold control signal terminals of the 2k-1 stage shift register and the 2k stage shift register are both coupled to the same clock terminal, namely the sixth clock terminal ck6.

[0235] Based on the same inventive concept, this disclosure also provides a display device, including the gate driving circuit described above. The principle by which this display device solves the problem is similar to that of the aforementioned shift register; therefore, the implementation of this display device can refer to the implementation of the aforementioned shift register, and the repetitions will not be repeated here.

[0236] In specific implementation, the display device provided in the embodiments of this disclosure can be as follows: Figure 17 The mobile phone shown is an example. Of course, the display device provided in this embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0237] The shift register, its driving method, gate driving circuit, and display device provided in this disclosure, by configuring the first transistor as a dual-gate transistor, wherein the first gate of the first transistor receives a first reference signal terminal and the second gate of the first transistor receives a first threshold control signal terminal, can enable the first transistor to be turned on during the input phase, the reset phase, and the reset hold phase. Furthermore, at least during the output phase, the threshold voltage V of the first transistor can be controlled by the signal at the first threshold control signal terminal. th1 This makes the threshold voltage V of the first transistor... th1 By moving the transistor to keep it as off as possible during the output phase, the signal level of the first pull-up node can be kept stable, preventing leakage current from affecting the signal of the first pull-up node. This improves the stability of the output signal, which is beneficial for applications in low-frequency driven display devices and helps reduce power consumption.

[0238] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A shift register, wherein, Display devices used in low-frequency driving include: An input circuit is configured to be coupled to an input signal terminal and a second clock signal terminal respectively. The input circuit is used to control the signal level of the first terminal of the first transistor according to the signals of the input signal terminal and the second clock signal terminal during the input phase. A first transistor, wherein the first terminal of the first transistor is coupled to the output terminal of the input circuit; and the first transistor is a dual-gate transistor; wherein the first gate of the first transistor is configured to be coupled to a first reference signal terminal, and the second gate of the first transistor is configured to be coupled to a first threshold control signal terminal, the first transistor is used to be turned on during the input phase, and to shift the threshold voltage in response to the signal of the first threshold control signal terminal during the output phase, so as to turn off the first transistor and keep the signal level of the first pull-up node stable, wherein the signal of the first threshold control signal terminal is opposite to the signal level of the first reference signal terminal; An output circuit is configured to be coupled to a first clock signal terminal and a signal output terminal respectively, and the control terminal of the output circuit is coupled to the second terminal of the first transistor, and a first pull-up node is formed at the coupling point between the control terminal of the output circuit and the second terminal of the first transistor. The output circuit is used to provide the signal of the first clock signal terminal to the signal output terminal in response to the signal of the second terminal of the first transistor during the input phase and the output phase. The shift register also includes: a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; The gate of the fifth transistor is configured to be coupled to the second clock signal terminal, the first terminal of the fifth transistor is configured to be coupled to the first reference signal terminal, and the second terminal of the fifth transistor is coupled to the gate of the seventh transistor. The gate of the sixth transistor is coupled to the first terminal of the first transistor, the first terminal of the sixth transistor is configured to be coupled to the second clock signal terminal, and the second terminal of the sixth transistor is coupled to the gate of the seventh transistor. The first terminal of the seventh transistor is configured to be coupled to the second reference signal terminal, and the second terminal of the seventh transistor is coupled to the signal output terminal; The first terminal of the first capacitor is coupled to the gate of the seventh transistor, and the second terminal of the first capacitor is configured to be coupled to the second reference signal terminal.

2. The shift register as described in claim 1, wherein, The input circuit includes: a single-gate type second transistor; The gate of the second transistor is configured to be coupled to the second clock signal terminal, the first terminal of the second transistor is configured to be coupled to the input signal terminal, and the second terminal of the second transistor is coupled to the first terminal of the first transistor.

3. The shift register as described in claim 2, wherein, The second gate of the first transistor is coupled to the gate of the second transistor; or, The second gate of the first transistor is coupled to the first terminal of the second transistor.

4. The shift register as described in claim 1, wherein, The input circuit includes: a dual-gate second transistor; wherein, the first gate of the second transistor is configured to be coupled to the second clock signal terminal, the second gate of the second transistor is configured to be coupled to the second threshold control signal terminal, the first electrode of the second transistor is configured to be coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first electrode of the first transistor.

5. The shift register as described in claim 4, wherein, The second gate of the second transistor is coupled to the first gate of the second transistor; or, The second gate of the second transistor is coupled to the first terminal of the second transistor.

6. The shift register as described in claim 4 or 5, wherein, The second gate of the first transistor is coupled to the first gate of the second transistor; or... The second gate of the first transistor is coupled to the first terminal of the second transistor.

7. The shift register as claimed in claim 1, wherein, The shift register further includes a pull-up control circuit; wherein, the first control terminal of the pull-up control circuit is configured to be coupled to the first clock signal terminal, the second control terminal of the pull-up control circuit is coupled to the gate of the seventh transistor, the input terminal of the pull-up control circuit is configured to be coupled to the second reference signal terminal, and the output terminal of the pull-up control circuit is coupled to the first pole of the first transistor.

8. The shift register as described in claim 7, wherein, The pull-up control circuit includes: a third transistor and a single-gate fourth transistor; The gate of the third transistor is configured to be coupled to the first clock signal terminal, the first terminal of the third transistor is coupled to the first terminal of the first transistor, and the second terminal of the third transistor is coupled to the first terminal of the fourth transistor. The gate of the fourth transistor is coupled to the gate of the seventh transistor, and the second terminal of the fourth transistor is configured to be coupled to the second reference signal terminal.

9. The shift register as described in claim 7, wherein, The pull-up control circuit includes: a third transistor and a dual-gate fourth transistor; The gate of the third transistor is configured to be coupled to the first clock signal terminal, the first terminal of the third transistor is coupled to the first terminal of the first transistor, and the second terminal of the third transistor is coupled to the first terminal of the fourth transistor. The first gate of the fourth transistor is coupled to the gate of the seventh transistor, the second gate of the fourth transistor is configured to be coupled to the third threshold control signal terminal, and the second terminal of the fourth transistor is configured to be coupled to the second reference signal terminal.

10. The shift register as claimed in claim 9, wherein, The second gate of the fourth transistor is coupled to the gate of the seventh transistor; or, The second gate of the fourth transistor is coupled to the gate of the fifth transistor.

11. The shift register as described in any one of claims 1-5, wherein, The output circuit includes: an eighth transistor and a second capacitor; The gate of the eighth transistor is coupled to the second terminal of the first transistor, the first terminal of the eighth transistor is configured to be coupled to the first clock signal terminal, and the second terminal of the eighth transistor is coupled to the signal output terminal. The first terminal of the second capacitor is coupled to the second terminal of the first transistor, and the second terminal of the second capacitor is coupled to the signal output terminal.

12. The shift register as described in any one of claims 7-10, wherein, The first threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal; The second threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal; The third threshold control signal terminal is configured to receive a signal having a level opposite to that of the signal at the first reference signal terminal.

13. The shift register as claimed in claim 12, wherein, At least one of the first threshold control signal terminal, the second threshold control signal terminal, and the third threshold control signal terminal is configured to receive a clock signal with the same timing as the second clock signal terminal.

14. The shift register as claimed in claim 12, wherein, At least one of the first threshold control signal terminal, the second threshold control signal terminal, and the third threshold control signal terminal is configured to receive a fixed voltage signal.

15. A gate driving circuit, wherein, Includes multiple cascaded shift registers as described in any one of claims 1-14; The input signal terminal of the first-stage shift register is configured to be coupled to the frame trigger signal terminal; In each pair of adjacent shift registers, the input signal terminal of the next-level shift register is configured to be coupled to the signal output terminal of the previous-level shift register.

16. A display device, wherein, Includes the gate drive circuit as described in claim 15.

17. A method for driving a shift register as described in any one of claims 1-14, wherein, include: During the input phase, the input circuit controls the signal level of the first terminal of the first transistor based on the signal between the input signal terminal and the second clock signal terminal. The first transistor is turned on; The output circuit responds to the signal at the second terminal of the first transistor and provides the signal at the first clock signal terminal to the signal output terminal. During the output phase, the threshold voltage of the first transistor shifts in response to the signal at the first threshold control signal terminal, and the first transistor is turned off to maintain the signal level of the first pull-up node stable; the output circuit responds to the signal at the second terminal of the first transistor and provides the signal at the first clock signal terminal to the signal output terminal; wherein, the signal at the first threshold control signal terminal is opposite in level to the signal at the first reference signal terminal.

18. The driving method as described in claim 17, wherein, The input phase further includes: a fifth transistor responding to the signal at the second clock signal terminal to provide the signal at the first reference signal terminal to the gate of a seventh transistor; a sixth transistor responding to the signal at the first terminal of the first transistor to provide the signal at the second clock signal terminal to the gate of the seventh transistor; and the seventh transistor responding to the signal at the gate of the seventh transistor to provide the signal at the second reference signal terminal to the signal output terminal. Following the output phase, the driving method further includes: During the reset phase, the input circuit controls the signal level of the first terminal of the first transistor according to the signals of the input signal terminal and the second clock signal terminal; the first transistor turns on the input circuit and the output circuit; the fifth transistor, in response to the signal of the second clock signal terminal, provides the signal of the first reference signal terminal to the gate of the seventh transistor; the seventh transistor, in response to the signal of the gate of the seventh transistor, provides the signal of the second reference signal terminal to the signal output terminal.

19. The driving method as described in claim 17 or 18, wherein, During the output phase, the threshold voltage of the second transistor shifts in response to the signal at the second threshold control signal terminal, and the second transistor is turned off; the threshold voltage of the fourth transistor shifts in response to the signal at the third threshold control signal terminal, and the fourth transistor is turned off.

Images