Device and method for power management

Abstract

Various embodiments of the present disclosure relate to devices and methods for power management. A device and method for power management, the embodiment device includes a processing circuit and an IP circuit device coupled to a power line, wherein the IP circuit device has an IP circuit device power supply threshold for IP circuit device operation. A power supply monitor circuit is coupled to the power line to sense the voltage on the power line and switch the processing circuit to a low power mode due to a drop in the voltage on the power line. The power supply monitor circuit includes a threshold setting node and is configured to be deactivated due to the voltage on the power line dropping below a deactivation threshold level set at the threshold setting node. The threshold setting circuit is configured to apply the IP circuit device power supply threshold to the threshold setting node of the power supply monitor circuit due to the processing circuit being in low power mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French application number IT102019000008385, filed on June 7, 2019, which is incorporated herein by reference. Technical Field

[0003] The present description relates to power supplies in electronic devices.

[0004] For example, one or more embodiments may be applied to power a processing device such as a general-purpose microcontroller (MCU).

[0005] One or more embodiments may be applied in low power devices. Background Art

[0006] In various application environments, facilitating power efficient coexistence of circuit arrangements with different (minimum) operating voltages may represent a desired functionality. For example, this may help a user to define in a flexible manner the actions to be taken when a low voltage condition is detected.

[0007] An approach to addressing this problem may involve limiting the operating voltage to a "worst case" condition. This approach may be far from providing an ideal solution: in fact, in various situations, it may be desirable to maintain the ability to operate the device (albeit with limited functionality / performance).

[0008] Another approach may involve the use of a dedicated voltage monitor. While satisfactory in various respects, this approach may be subject to certain limitations related to the ability of various components of the system to operate autonomously with different voltage specifications. Summary of the invention

[0009] One or more embodiments aim to contribute to further solving the above problems.

[0010] According to one or more embodiments, this object may be achieved by means of a device having the features set out in the appended claims.

[0011] A device including a microcontroller unit (MCU) and an IP core circuit device (IP circuit device for short) may be an example of such a device.

[0012] The claims are an integral part of the technical disclosure of the embodiments provided herein.

[0013] One or more embodiments may involve using a universal voltage monitor in conjunction with specific hardware methods to help manage the operation of a low power system even when different parts of the system are operating autonomously.

[0014] In various aspects, one or more embodiments may provide the following advantages, such as, for example:

[0015] Flexibility in software configuration, e.g. via software enable mechanism, threshold configuration through registers, interrupt driven operation when the CPU is not in low power mode;

[0016] Autonomous operation: for example, some parts of the system can be optionally made active while the MCU is in low power mode, with the ability to wake up the MCU (CPU) from low power mode, for example due to detection of a power drop; and

[0017] Low power support, for example, via hardware monitor shutdown (when the associated IP is inactive and the system is in low power mode) and / or via a mechanism that enforces IP thresholds (when the system is in low power mode).

[0018] One or more embodiments retain the possibility to configure the operating characteristics through software, with software-defined actions that help the end user decide what to do in the event of a voltage drop. This facilitates taking actions related to specific application circumstances (such as output power reduction, shutdown, etc.), while retaining a lot of flexibility in choosing such actions.

[0019] One or more embodiments may be directed to a universal voltage monitor circuit combined with a hardware approach to facilitate management of low power system operations even in those arrangements where different portions of the system are intended to operate autonomously. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0021] Figure 1 is a schematic representation of a problem solved in one or more embodiments,

[0022] Figure 2 is an exemplary representation of a possible environment of use of the embodiments, and

[0023] Figures 3 to 8 is a functional block diagram illustrating possible operation of an embodiment. DETAILED DESCRIPTION

[0024] In the following description, one or more specific details are explained to provide a deeper understanding of the examples of the embodiments. The embodiments can be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not illustrated or described in detail so that some aspects of the embodiments will not be obscured.

[0025] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more points of this description do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0026] The reference signs used herein are provided for convenience only and therefore do not limit the degree of protection or the scope of the embodiments.

[0027] Figure 1 It is a schematic representation of the possible power supply conditions of electronic equipment.

[0028] An electronic circuit comprising a processing unit (eg, a microcontroller unit or MCU) having the capability to be coupled to IP circuitry, ie, one or more intellectual property cores (IP cores or simply IP for short), may be an example of such a device.

[0029] The name IP core (or IP for short) is a well-known name used in electronic design to designate a reusable unit of logic, cell, or integrated circuit design that can be used as a building block for an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array).

[0030] Figure 1 Concerning possible power supply conditions of such a device via a supply voltage VDD in the range from 0 V to a maximum value Vmax, wherein the voltage VDD is expected to have a current (nominal) value V2.

[0031] In various cases and for different reasons known to those skilled in the art, this supply voltage may be reduced to a minimum value Vmin or lower.

[0032] Figure 1 The representation in illustrates the possibility that different parts of such a device (generally designated by I and II) can:

[0033] On the one hand, for values ​​of VDD higher than V2, it is able to operate reliably (both are "OK"),

[0034] On the other hand, for values ​​of VDD below Vmin, reliable operation is not possible (both are again "KO").

[0035] Figure 1The representation in also illustrates the possibility that parts I and II exhibit different behaviors for values ​​of VDD between V2 and Vmin: for example, part I (left) may enter a “grey area” where, in addition to degraded performance, no performance may be guaranteed, while part II (right) may still operate reliably at the required performance level (“OK”): i.e., part I (left) can operate reliably down to V2, while part II (right) can operate reliably down to Vmin.

[0036] Figure 1 The right side of is also schematically represented a possible action of a voltage monitor with hysteresis H, where H is the difference between a rising threshold (high) and a falling threshold (low) in case of possible variations of the supply voltage VDD.

[0037] Figure 1 Possible variations of VDD around V2 (V2: V2+S and V2+H: V2+H+S, as indicated at VM) and around Vmin (Vmin: Vmin+S and Vmin+H: Vmin+H+S, as indicated at POR) are illustrated, depending on whether only one part or both parts (e.g., a microcontroller and associated IP circuit devices) are powered.

[0038] The entity S represents the spread, i.e. the maximum difference between different silicon parts and between different operating conditions (PVT); the POR can indicate a power-on reset condition in the voltage monitoring system voltage to facilitate correct initialization at power-on. The hysteresis H helps ensure the stability of the monitor output and prevent power supply noise.

[0039] Figure 2 A possible system architecture is illustrated which includes, for example, a low voltage logic circuit 10 comprising a processing unit 12 (e.g., a CPU) having associated registers 14 powered from a power supply rail 16 which is brought to a voltage VDD via a (voltage) regulator 18 (e.g., in a manner known to those skilled in the art).

[0040] Figure 2 Reference numeral 20 in FIG. 1 denotes an IP circuit device (ie, one or more IP cores) powered via the rail 16 .

[0041] Figure 2 Reference numeral 22 in ref. 1 indicates a universal voltage monitor which is configured to monitor (in a manner known per se to a person skilled in the art) a (main) power supply line (eg rail 16).

[0042] like Figure 2As illustrated in FIG. 1 , the voltage monitor 22 may be configured to cooperate with the low voltage logic circuit 10 by exchanging signals, including:

[0043] The threshold signal, sent from the logic circuit 10 (e.g., from the register 14) to the input 22a of the voltage monitor 22,

[0044] The enable signal, again sent from the logic circuit 10 (e.g., from the register 14) to the input 22b of the voltage monitor 22,

[0045] An interrupt signal is sent from the output 22c of the voltage monitor 22 to the logic circuit 10 (eg, to the CPU 12).

[0046] like Figure 2 As illustrated in , such signal exchange may be performed via horizontal shifters 24 , 26 and 28 .

[0047] Figure 2 Reference numeral 30 in the drawing denotes a conventional power-on reset (POR) circuit in the art.

[0048] It will be understood that throughout Figures 2 to 8 , the same parts or elements are indicated by the same reference numerals, and thus, for the sake of brevity, a detailed description of these parts or elements will not be repeated for each figure.

[0049] As mentioned above (and Figure 3 ), one possible method of managing a low power mode in a device contemplated herein may involve shutting down (“OFF”) the low voltage domain 10 and shutting down the voltage monitor 22. This option may be determined by considering that keeping the monitor 22 active would cause the supply power to be consumed unnecessarily.

[0050] However, the ideal type of operation would involve keeping IP circuitry 20 active ("ON") while shutting down the rest of the system, with the supply voltage provided to IP circuitry 20 still being monitored so that possible action can be taken if the supply voltage drops below a desired minimum level.

[0051] For example, by referring to Figure 1 , Figure 2 The IP circuit device 20 in may be Figure 1 An example of part I in FIG. 1 , which can reliably operate down to voltage V2.

[0052] The voltage monitor POR can help (in a manner known to those skilled in the art) maintain the supply level above Vmin. This may not be sufficient because the IP circuit device 20 cannot fully operate between Vmin and V2, and the monitor 22 will help check whether the supply voltage is above V2.

[0053] In one or more embodiments, such monitoring (e.g., of the supply voltage to the IP circuit device 20) may be facilitated by keeping the monitor circuit 22 “active” such that, even when the low voltage logic 10 is switched to a low power state, a threshold IPT corresponding to the desired operating condition of the IP circuit device 20 is selected and made available to the monitor circuit 22.

[0054] exist Figure 4 In the embodiment illustrated in , such a method may be implemented by means of a multiplexer 100 arranged between the logic circuit device 10 (eg, register 14 ) and the voltage monitor circuit 22 , wherein the multiplexer 100 is driven via a signal LP indicating that a low power state is implemented for the low voltage domain 10 .

[0055] For example, such a signal LP (which may be generated in any manner known to a person skilled in the art) may be applied to the multiplexer 100 according to the following principles:

[0056] LP=0: This corresponds to normal “transparent” operation of the device, in which the threshold signal from register 14 is transmitted to input 22a of voltage monitor circuit 22,

[0057] LP=1: This corresponds to low power operation (eg, logic circuit arrangement 10 is switched off: this may be for various reasons known to those skilled in the art), wherein the desired threshold IPT facilitating IP operation is applied to input 22 a of voltage monitor circuit 22 .

[0058] The IP threshold IPT may be generated in any manner known to those skilled in the art (eg by means of a hard-wired arrangement).

[0059] In such Figure 5 In one or more of the embodiments illustrated in , this type of operation can be facilitated by providing a specific register bit 140 in register 14, which can be retained in a shadow register 142 and can be set (e.g., via software) to keep the voltage monitor circuit 22 "active" even in a low power mode (i.e., the low voltage domain 10 is shut down).

[0060] For example (such as Figure 5), a corresponding circuit arrangement may include an OR gate 102 having a first input coupled to the logic circuit device 10 (e.g., coupled to the register 14 via the horizontal shifter 26) and having a second input coupled to the register bit 140 (via the shadow register 142) so that the enable input 22b can be brought to a logic level (e.g., "high") to keep the voltage monitor 22 active even when a signal from the register 14 (via the horizontal shifter 26) would otherwise indicate that the voltage monitor circuit 22 should be disabled.

[0061] Figure 6 The diagram of exemplifies the possibility of sensing (eg, via sense line 20a) that the IP circuit arrangement 20 is inactive (ie, not currently activated even though the supply voltage may allow operation) so that the voltage monitor circuit 22 can be switched off.

[0062] In such Figure 6 In the arrangement illustrated in , this result may be achieved by means of a logic gate, such as AND gate 104 , arranged between gate 102 and enable input 22 b of voltage monitor circuit 22 .

[0063] exist Figure 6 In the arrangement illustrated in , gate 104 has a first input coupled to the output of gate 102, and has a second input coupled to the output from another logic gate 106 (e.g., an OR gate), which in turn has a first input coupled to sense line 20a, and has a second input receiving a negated version of signal LP (i.e., LPneg).

[0064] In this manner, the enable input 22 b of the voltage monitor circuit 22 will receive an enable signal (e.g., “high”) to keep the voltage monitor circuit 22 active, either because the signal on line 20 a indicates that IP 20 is active, or because LP=0 (i.e., during normal operation with the low voltage domain 10 turned on). In this normal operating condition, the enable signal from register 14 can be forwarded to the input 22 b of the voltage monitor circuit 22 via gates 102 and 104 to keep it active.

[0065] In short, one or more embodiments illustrated herein may help achieve the conditions considered below.

[0066] When in low power (LP) mode (ie, 10 is OFF and LP=1):

[0067] If IP 20 is inactive (i.e., for example, 20a is 0), then monitor 22 will be OFF;

[0068] If IP 20 is active (ie, for example, 20a is 1), whether voltage monitor 22 is enabled will depend on the contents of shadow register 142: for example, this may depend on the fact that the user requested to make the monitor active by programming a specific register bit before entering LP mode.

[0069] When in normal mode (ie, 10 is ON and LP=0), the fact that monitor 22 is active or not may depend (exclusively) on a selection made by the user by programming a specific register bit (and not on the IP activation state).

[0070] In such Figure 7 In the embodiment illustrated in , register bit 144 may be provided in register 14 and register bit 144 may be retained in shadow register 142 to facilitate software configuration of waking the system from a low power mode via voltage monitor circuit 22 .

[0071] like Figure 7 Such an arrangement illustrated in may involve wake-up logic circuit 32 being sensitive to wake-up register bit 144 in shadow register 142 and to an interrupt signal being sent from voltage monitor circuit 22 to logic circuit arrangement 10 via output 22 c.

[0072] The wake-up logic circuit 32 can be as follows Figure 8 1, so that when the supply voltage drops to the IP operating threshold (e.g., IPT), the wake-up signal WU is sent to the logic circuit device 10, so that if the IP 20 is active, the voltage monitor circuit 22 can be kept active in any case. In this way, the voltage drop below the IP threshold IPT can be detected (by the voltage monitor circuit 22, in a manner known to those skilled in the art), and the low voltage domain 10 (e.g., CPU 12) is "woken up" to take actions that may be required (e.g., reduce RF power, shut down, etc.).

[0073] Thus, one or more embodiments may provide the ability to monitor supply voltage VDD in the case of autonomous IP operation, by making it unnecessary to keep the entire system active, by possibly providing automatic monitor shutdown (when the IP portion moves to an inactive state) and system wake-up capabilities.

[0074] Devices as exemplified herein may include:

[0075] processing circuitry (e.g., 10) and IP (core) circuitry (e.g., 20) coupled to a power supply line (e.g., 16), wherein the IP circuitry has an IP circuitry power supply threshold (e.g., IPT) for IP circuitry operation (i.e., above which satisfactory operation of the IP circuitry is achieved), and

[0076] a power supply monitor circuit (e.g., 22) coupled to the power supply line and sensitive to a voltage (e.g., VDD) on the power supply line, the power supply monitor circuit being configured (e.g., 22c) to: switch the processing circuit to a low power mode due to a drop in the voltage on the power supply line,

[0077] in:

[0078] The power supply monitor circuit includes a threshold setting node (e.g., 22a) and is configured to be deactivated due to a voltage on the power supply line falling below a deactivation threshold level set at the threshold setting node,

[0079] A threshold setting circuit (e.g., 100) is provided, the threshold setting circuit being coupled to a threshold setting node of the power supply monitor circuit, the threshold setting circuit being configured to apply the IP circuit device power supply threshold to the threshold setting node of the power supply monitor circuit due to the processing circuit being in the low power mode.

[0080] In this manner, the monitor circuit may remain "active" and monitor the power supply of the IP circuit device as long as the IP circuit device is active.

[0081] In the device as illustrated herein, the threshold setting circuit may include a multiplexer (e.g., 100) having an input configured to receive the above-mentioned IP circuit device power supply threshold and having an output coupled to the threshold setting node of the power supply monitor circuit, the multiplexer being controlled by a low power mode signal (e.g., LP) indicating that the processing circuit is switched to the above-mentioned low power mode.

[0082] In the device as exemplified herein:

[0083] The supply monitor circuit may include an enable input (eg, 22b) coupled (eg, via gate 102) to the processing circuit,

[0084] An enable maintaining circuit device (e.g., 140, 142, 102, 104, 106) may be provided, which couples the enable inputs of the processing circuit and the power supply monitor circuit, and the enable maintaining circuit device is configured to: apply an enable signal to the enable input of the power supply monitor circuit regardless of whether the processing circuit is in the above-mentioned low power mode (i.e., regardless of whether the value of the low power mode signal LP indicates that the processing circuit is switched to the low power mode).

[0085] In an apparatus as exemplified herein, enabling the maintaining circuit means may include:

[0086] a memory circuit device (e.g., 140, 142) having stored therein power supply monitor circuit enable information (e.g., enable bits), and

[0087] An OR gate (e.g., 102) having an output coupled to an enable input of the supply monitor circuit and having first and second inputs coupled (e.g., 26) to the processing circuit (e.g., via 26) and the above-mentioned memory circuit device (e.g., to receive the enable bit), respectively.

[0088] Devices as exemplified herein may include:

[0089] an IP activation sense line (e.g., 20a) coupled to the IP circuit device, the IP activation sense line being configured to carry an IP activation signal indicating whether the IP circuit device is active or inactive,

[0090] The enable maintaining circuit device is coupled to the IP activation sense line (eg, at 104) to receive the IP activation signal therefrom and stops applying the enable signal to the enable input of the supply monitor circuit because the IP activation signal indicates that the IP circuit device is inactive.

[0091] In the device as illustrated in this document, the above-mentioned enable maintenance circuit device is sensitive to a low power mode signal (e.g., LP), the low power mode signal indicates that the processing circuit is switched to the above-mentioned low power mode, and the above-mentioned enable maintenance circuit device is configured to: deactivate the power supply monitor circuit because the above-mentioned IP activation signal indicates that the IP circuit device is inactive and the above-mentioned low power mode signal indicates that the processing circuit is switched to the above-mentioned low power mode.

[0092] The device as illustrated herein may include a wake-up circuit device (e.g., 32) coupled to the power supply monitor circuit and configured to apply a wake-up signal (e.g., WU) to the processing circuit, the wake-up signal causing the processing circuit to exit the above-mentioned low power mode due to the voltage on the power line dropping below the above-mentioned IP circuit device power supply threshold.

[0093] Without affecting the underlying principle, the details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without departing from the scope of protection.

[0094] The extent of protection is determined by the appended claims.

Claims

1. A device for power management, comprising: processing circuitry and intellectual property core (IP) circuitry coupled to the power supply line, wherein the IP circuitry has an IP circuitry power supply threshold for IP circuitry operation; a power supply monitor circuit coupled to the power line and sensitive to a voltage on the power line, the power supply monitor circuit being configured to switch the processing circuit to a low power mode due to a drop in the voltage on the power line, wherein the supply monitor circuit includes a threshold setting node and is configured to be deactivated due to the voltage on the power supply line falling below a deactivation threshold level set at the threshold setting node; as well as A threshold setting circuit is coupled to the threshold setting node of the supply monitor circuit, and is configured to apply the IP circuit device supply threshold to the threshold setting node of the supply monitor circuit due to the processing circuit being in the low power mode.

2. The apparatus of claim 1 , wherein the threshold setting circuit comprises a multiplexer having an input configured to receive the IP circuit device power supply threshold and having an output coupled to the threshold setting node of the power supply monitor circuit, the multiplexer being controlled by a low power mode signal indicating that the processing circuit is switched to the low power mode.

3. The device according to claim 1, wherein the supply monitor circuit includes an enable input coupled to the processing circuit; and The device includes an enable maintaining circuit device, which couples the processing circuit with the enable input of the power supply monitor circuit, and the enable maintaining circuit device is configured to: apply an enable signal to the enable input of the power supply monitor circuit regardless of whether the processing circuit is in the low power mode.

4. The apparatus of claim 3, wherein the enable maintenance circuit means comprises: a memory circuit device storing therein power supply monitor circuit enable information; as well as An OR gate has an output coupled to the enable input of the supply monitor circuit and has first and second inputs coupled to the processing circuit and the memory circuitry, respectively.

5. The device according to claim 3, comprising: an IP activation sense line coupled to the IP circuit device, the IP activation sense line being configured to carry an IP activation signal, the IP activation signal indicating that the IP circuit device is active or inactive, The enable maintaining circuit device is coupled to the IP activation sense line to receive the IP activation signal therefrom, and stops applying the enable signal to the enable input of the power supply monitor circuit because the IP activation signal indicates that the IP circuit device is inactive.

6. The apparatus of claim 5 , wherein the enable-maintaining circuit device is sensitive to a low-power mode signal indicating that the processing circuit is switched to the low-power mode, and the enable-maintaining circuit device is configured to deactivate the supply monitor circuit due to the IP activation signal indicating that the IP circuit device is inactive and the low-power mode signal indicating that the processing circuit is switched to the low-power mode.

7. The apparatus of claim 1 , comprising a wake-up circuit device coupled to the power supply monitor circuit and configured to apply a wake-up signal to the processing circuit, the wake-up signal causing the processing circuit to exit the low power mode due to the voltage on the power line dropping below the IP circuit device power supply threshold.

8. A method for power management, comprising: receiving power from a power supply line by the processing circuitry and the intellectual property core IP circuitry, the IP circuitry having an IP circuitry power supply threshold for IP circuitry operation; In response to a voltage drop on the power line, switching the processing circuit to a low power mode by a power supply monitor circuit; deactivating the supply monitor circuit in response to the voltage on the power line falling below a deactivation threshold level set at a threshold setting node of the supply monitor circuit; as well as In response to the processing circuit switching to the low power mode, the IP circuitry power supply threshold is applied by a threshold setting circuit to the threshold setting node of the power supply monitor circuit.

9. The method according to claim 8, further comprising: receiving the IP circuit device power supply threshold by a multiplexer of the threshold setting circuit; generating, by the multiplexer, an output to the threshold setting node of the supply monitor circuit; as well as The multiplexer is controlled by a low power mode signal that instructs the processing circuit to switch to the low power mode.

10. The method according to claim 8, further comprising: An enable signal is applied by the enable maintaining circuitry to an enable input of the supply monitor circuit regardless of whether the processing circuit is in the low power mode.

11. The method according to claim 10, further comprising: storing power supply monitor circuit enable information in a memory circuit device of the enable maintaining circuit; as well as First and second inputs coupled to the processing circuitry and the memory circuitry, respectively, are logically ORed to generate an enable output to the supply monitor circuitry.

12. The method according to claim 10, comprising: An IP activation signal is carried by the IP activation sensing line, wherein the IP activation signal indicates whether the IP circuit device is active or inactive; receiving, by the enable maintaining circuit device, the IP activation signal from the IP activation sensing line; as well as In response to the IP activation signal indicating that the IP circuitry is inactive, ceasing to apply the enable signal to the enable input of the supply monitor circuit.

13. The method according to claim 12, further comprising: receiving, by the enable maintaining circuit device, a low power mode signal, the low power mode signal indicating that the processing circuit is switched to the low power mode; as well as In response to the IP activation signal indicating that the IP circuitry is inactive and the low power mode signal indicating that the processing circuitry is switched to the low power mode, the supply monitor circuitry is deactivated by the enable maintenance circuitry.

14. The method according to claim 8, further comprising: In response to the voltage on the power line falling below the IP circuitry supply threshold, a wake-up signal is applied to the processing circuitry by a wake-up circuitry coupled to the supply monitor circuitry, the wake-up signal causing the processing circuitry to exit the low power mode.

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