Vertical semiconductor device and manufacturing method thereof

Abstract

A vertical semiconductor device and a method for manufacturing the same are provided. The vertical semiconductor device includes: a common source semiconductor layer located on a substrate; a support layer located on the common source semiconductor layer; gate electrodes and interlayer insulating layers alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to the upper surface of the substrate and passing through the gate electrodes and the support layer, with a sidewall of the support layer facing the channel pattern offset relative to a sidewall of the gate electrodes facing the channel pattern; and an information storage layer extending between the gate electrodes and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2019-0068800, titled “Vertical Semiconductor Device and Method of Manufacturing the Same,” filed on June 11, 2019, in the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to a vertical semiconductor device and a method of manufacturing the same, and more particularly, to a vertical semiconductor device having excellent electrical characteristics and high reliability and a method of manufacturing the same. Background Art

[0004] In a vertical semiconductor device formed on an n-well, an erase operation of a memory cell can be performed using a gate-induced drain leakage (GIDL) method that utilizes the GIDL phenomenon. In this case, there is still room for improving the distributed control of the electrical characteristics of the device. Summary of the Invention

[0005] According to one aspect of the embodiment, a vertical semiconductor device is provided, which includes: a common source semiconductor layer located on a substrate; a support layer located on the common source semiconductor layer; a gate and an interlayer insulating layer alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to the upper surface of the substrate while passing through the gate and the support layer, with the side wall of the support layer facing the channel pattern offset relative to the side wall of the gate facing the channel pattern; and an information storage layer extending between the gate and the channel pattern, the information storage layer extending at least to the side wall of the support layer facing the channel pattern.

[0006] According to another aspect of the embodiment, a vertical semiconductor device is provided, which includes: a common source semiconductor layer located on an n-well of a substrate; a support layer located on the common source semiconductor layer; a gate and an interlayer insulating layer alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to the upper surface of the substrate while passing through the gate and the support layer, the channel pattern including a channel pattern extension protruding toward the support layer in a lateral direction of the support layer, and a side wall of the support layer facing the channel pattern is offset relative to a side wall of the gate facing the channel pattern; and an information storage layer extending between the gate and the channel pattern.

[0007] According to another aspect of the embodiment, a vertical semiconductor device is provided, which includes: a common source semiconductor layer located on an n-well of a substrate having a p-conductivity type; a support layer located on the common source semiconductor layer; gates and interlayer insulating layers alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to the upper surface of the substrate while passing through the gates and the support layer, the channel pattern extending through the channel hole, and the support layer directly contacting the lowest gate of the gates located in the channel hole; and an information storage layer extending between the gate and the channel pattern, wherein the side wall of the support layer facing the channel hole is offset relative to the side wall of the gate facing the channel hole, wherein the information storage layer extends horizontally along the lower surface of the lowest gate of the gates toward the support layer, and then extends along the side wall of the support layer in the first direction.

[0008] According to another aspect of the embodiment, a method for manufacturing a vertical semiconductor device is provided, the method comprising the following steps: forming a lower sacrificial layer pattern on an n-well of a substrate having a p-conductivity type; forming a supporting layer on the lower sacrificial layer pattern; alternately stacking sacrificial layers and insulating layers on the supporting layer; forming a channel hole passing through the sacrificial layer, the insulating layer, the supporting layer and the lower sacrificial layer; partially removing the exposed sidewalls of the supporting layer in the channel hole; forming an information storage material layer and a channel pattern in the channel hole; replacing the lower sacrificial layer with a common source semiconductor layer; and replacing the sacrificial layer with a gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0010] Figure 1 An equivalent circuit diagram of a memory cell array of a semiconductor device according to an embodiment is shown;

[0011] Figure 2 shows a lateral cross-sectional view of a semiconductor device according to an embodiment;

[0012] Figure 3 It shows the embodiment Figure 2 An enlarged view of region III in FIG;

[0013] Figure 4 It shows the embodiment Figure 2 An enlarged view of region III in FIG;

[0014] Figure 5 shows a lateral cross-sectional view of a semiconductor device according to an embodiment;

[0015] Figure 6 It shows the embodiment Figure 5 An enlarged view of region VI in FIG;

[0016] 7A to 7I Transverse cross-sectional views showing various stages in a method of manufacturing a semiconductor device according to an embodiment;

[0017] Figures 8 to 10 Shown respectively Figures 7D to 7F An enlarged view of region B in FIG;

[0018] Figures 11 to 13 Transverse cross-sectional views showing stages in a method of removing exposed portions of an information storage material layer;

[0019] Figure 14 Shown Figure 7G An enlarged view of region B in FIG;

[0020] Figures 15A to 15F Transverse cross-sectional views showing various stages in a method of manufacturing a semiconductor device according to an embodiment;

[0021] Figures 16 to 18 Shown Figures 15A to 15C An enlarged view of region B in FIG;

[0022] Figures 19 to 21 Transverse cross-sectional views showing stages in a method of removing exposed portions of an information storage material layer;

[0023] Figure 22 Shown Figure 15D an enlarged view of region B in FIG; and

[0024] Figure 23 A cross-sectional view of a semiconductor device according to an embodiment is shown. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 : is an equivalent circuit diagram of a memory cell array MCA of a semiconductor device. Specifically, Figure 1 An equivalent circuit diagram of a vertical NAND (VNAND) flash memory device having a vertical channel structure according to an embodiment is shown.

[0027] Reference Figure 1 , the memory cell array MCA may include a plurality of memory cell strings MS, which include a plurality of memory cell strings MS arranged in a vertical direction ( Figure 1A plurality of memory cells MC1, MC2, ..., MCn-1, MCn are arranged in the z direction (in the z direction). Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, a gate-induced drain leakage (GIDL) transistor GDT, and a plurality of memory cells MC1, MC2, ..., MCn-1, MCn connected in series. The plurality of memory cells MC1, MC2, ..., MCn-1, MCn can store data, and a plurality of word lines WL1, WL2, ..., WLn can be connected to the memory cells MC1, MC2, ..., MCn-1, MCn, respectively, to control the memory cells MC1, MC2, ..., MCn-1, MCn.

[0028] The gate terminal of the ground selection transistor GST can be connected to the ground selection line GSL, the source terminal of the ground selection transistor GST can be connected to the drain terminal of the GIDL transistor GDT, and the source terminal of the GIDL transistor GDT can be connected to the common source line CSL. The gate terminal of the string selection transistor SST can be connected to the string selection line SSL, the source terminal of the string selection transistor SST can be connected to the drain terminal of the memory cell MCn, and the drain terminal of the string selection transistor SST can be connected to multiple bit lines BL (BL1, BL2, ..., BLm). Although Figure 1 An example is shown in which each memory cell string MS includes one ground selection transistor GST, one string selection transistor SST, and one GIDL transistor GDT, but each memory cell string MS may include two or more ground selection transistors GST, two or more string selection transistors SST, and / or two or more GIDL transistors GDT.

[0029] When a signal is applied to the gate terminal of the string selection transistor SST via the string selection line SSL, a signal applied via the plurality of bit lines BL can be supplied to the plurality of memory cells MC1, MC2, ..., MCn-1, MCn, thereby enabling a data write operation to be performed. When a signal is applied to the gate terminal of the ground selection transistor GST via the ground selection line GSL, an erase operation can be performed on the plurality of memory cells MC1, MC2, ..., MCn-1, MCn.

[0030] According to an embodiment, the common source semiconductor layer 110 (see FIG. Figure 2) can be set between the ground selection line GSL and the common source line CSL, so the erase operation of the memory cell array MCA can be performed by using the GIDL method. For example, the erase voltage Ver can be applied to the common source line CSL, and the reference voltage Vref can be applied to the GIDL erase line GEL connected to the gate of the GIDL transistor GDT. At this time, due to the potential difference between the erase voltage Ver and the reference voltage Vref, a high electric field can be generated in the common source semiconductor layer 110 adjacent to the GIDL erase line GEL, and electrons and holes can be generated in the common source semiconductor layer 110. The holes generated in the common source semiconductor layer 110 can be injected into the memory cell string MS, so that the erase operation of the plurality of memory cells MC1, MC2, ..., MCn-1, MCn can be performed.

[0031] Semiconductor devices in related art use an erase method that utilizes a substrate as the main body and performs an erase operation on multiple memory cells by directly injecting holes from the substrate into a memory cell string electrically connected to the substrate. However, in order to provide a hole injection path from the substrate to the memory cell string, a complex process is required to form the lower substructure. However, the semiconductor device according to the embodiment can implement an erase operation using a simple structure by utilizing the GIDL method.

[0032] Figure 2 is a lateral cross-sectional view showing a semiconductor device 100 according to an embodiment.

[0033] Reference Figure 2 , the substrate 101 may include an upper surface 101M extending in a first horizontal direction (x direction) and a second horizontal direction (y direction). The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include single crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium. The substrate 101 may be configured as a bulk wafer or an epitaxial layer. In another embodiment, the substrate 101 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0034] The substrate 101 may have a first conductivity type, and a potential well of a second conductivity type opposite to the first conductivity type may be formed in the substrate 101. In some embodiments, the substrate 101 may have a p conductivity type, and an n-type conductivity type n-well 101n may be provided in the substrate 101. For example, the substrate 101 may have a p conductivity type, and an n-type conductivity type n-well 101n may be provided in the substrate 101, extending from the upper surface 101M of the substrate 101 to a predetermined depth.

[0035] A common source semiconductor layer 110 may be disposed on the substrate 101. The common source semiconductor layer 110 may include a conductive layer, for example, a semiconductor layer doped with impurities. In some embodiments, the common source semiconductor layer 110 may include a polysilicon layer doped with impurities. The common source semiconductor layer 110 may be separated by an isolation region 180 and may be configured to contact a common source line 103 n disposed below (e.g., adjacent to) the isolation region 180.

[0036] In some embodiments, the protective layer 161 and the supporting insulating layer 162 may be disposed on the common source semiconductor layer 110. For example, Figure 2 As shown in , the protection layer 161 may be formed between the supporting insulating layer 162 and the common source semiconductor layer 110 , for example, to completely separate the supporting insulating layer 162 from the common source semiconductor layer 110 .

[0037] When the support layer 120 (described later) is conductive, the support insulating layer 162 can isolate the support layer 120 from the common source semiconductor layer 110. The support insulating layer 162 may include, for example, silicon oxide. In some embodiments, the support insulating layer 162 may include at least one of a high-density plasma (HDP) oxide layer, tetraethyl orthosilicate (TEOS), plasma-enhanced TEOS (PE-TEOS), O3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), and Tonen silazane (TOSZ).

[0038] When the information storage layer 140 is partially removed (described later), the protective layer 161 can protect the support insulating layer 162 from being removed. The protective layer 161 can include, for example, polysilicon. In some embodiments, the protective layer 161 can include, for example, polysilicon doped with carbon.

[0039] The support layer 120 may be disposed on the protective layer 161. For example, a support insulating layer 162 may be formed between the support layer 120 and the protective layer 161. For example, the support layer 120 may include polysilicon doped with or undoped with impurities. The support layer 120 may include, for example, a support connection structure 120 c located between the common source semiconductor layers 110.

[0040] A plurality of gate electrodes 130 may be stacked on the support layer 120. For example, Figure 2 As shown in FIG, the plurality of gate electrodes 130 may include a plurality of gate electrodes 130 that are sequentially disposed on the support layer 120 and that may be separated from each other by the interlayer insulating layer 160 and the GIDL erase line GEL (see FIG. Figure 1 ) connected to the gate electrode 130GD, and the ground selection line GSL (see Figure 1 ) connected to the gate electrode 130G, the gate electrodes 130W1, ..., 130Wn connected to the memory cell word lines WL1, ..., WLn, and the string selection line SSL (see Figure 1 ) connected to the gate electrode 130s. That is, Figure 2 As shown in FIG, a plurality of gate electrodes 130 and a plurality of interlayer insulating layers 160 may be alternately arranged on the support layer 120. An upper interlayer insulating layer 165 may be formed on an uppermost one of the gate electrodes 130 (eg, on the gate electrode 130s connected to the string selection line SSL).

[0041] Each of the gate electrodes 130 (i.e., the gate electrode 130GD connected to the GIDL erase line, the gate electrode 130G connected to the ground selection line GSL, the gate electrodes 130W1, ..., 130Wn connected to the memory cell word lines WL1, ..., WLn, and the gate electrode 130s connected to the string selection line SSL) may include a metal such as tungsten (W). Each of the gate electrodes 130 may also include a diffusion barrier region and may include any one of tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN).

[0042] Channel hole 150H( Figure 3 ) may be provided through the upper interlayer insulating layer 165, the gate electrode 130, the interlayer insulating layer 160, the supporting layer 120, the supporting insulating layer 162, the protective layer 161, and the common source semiconductor layer 110 on the substrate 101. In the channel hole 150H, the information storage layer 140, the channel pattern 150, and the buried insulating layer 175 may be provided.

[0043] like Figure 3 and Figure 4 As shown in FIG, the information storage layer 140 may have a structure including a tunneling dielectric layer 142, a charge storage layer 144, and a blocking dielectric layer 146 sequentially formed in the stated order from the channel pattern 150 toward the sidewall of the channel hole 150H. For example, the tunneling dielectric layer 142 may be located between the charge storage layer 144 and the channel pattern 150. The relative thicknesses of the tunneling dielectric layer 142, the charge storage layer 144, and the blocking dielectric layer 146 forming the information storage layer 140 are not limited to Figure 3 and Figure 4 The thickness is shown in , and various modifications can be made.

[0044] The tunneling dielectric layer 142 may tunnel charges from the channel pattern 150 to the charge storage layer 144. The tunneling dielectric layer 142 may include, for example, silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like.

[0045] The charge storage layer 144 is a region that can store electrons that pass through the tunnel dielectric layer 142 from the channel pattern 150, and can include a charge trapping layer. The charge storage layer 144 can include, for example, quantum dots or nanocrystals. Here, the quantum dots or nanocrystals can be composed of fine particles of a conductor (such as a metal or semiconductor). The charge storage layer 144 can include, for example, silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities.

[0046] The blocking dielectric layer 146 may include, for example, silicon oxide, silicon nitride, or a high-k metal oxide having a dielectric constant higher than that of silicon oxide. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof. Here, the high-k metal oxide may refer to a metal oxide having a dielectric constant higher than that of silicon oxide.

[0047] The channel pattern 150 may include a semiconductor material such as polycrystalline silicon or single crystal silicon. The semiconductor material may be doped with impurity ions of p-type or n-type conductivity. A buried insulating layer 175 may be disposed in the channel pattern 150. In some embodiments, the buried insulating layer 175 may have a substantially cylindrical columnar structure. For example, Figure 2 As shown in FIG, a buried insulating layer 175 may be formed at the center of each channel hole 150H, and a channel pattern 150 may be formed along the entire sidewall of the buried insulating layer 175. For example, the channel pattern 150 may be located between the sidewall of the buried insulating layer 175 and the sidewall of the channel hole 150H. In some embodiments, when the channel pattern 150 is formed in a columnar shape, the buried insulating layer 175 may be omitted.

[0048] like Figure 3 As shown in FIG, the residual information storage layer 140res may be disposed adjacent to a lower portion of the channel pattern 150. The residual information storage layer 140res may have substantially the same structure as the information storage layer 140 and may be disposed between a bottom portion of the channel pattern 150 and the n-well 101n of the substrate 101.

[0049] Isolation regions 180 may be formed between adjacent memory cell strings using different gate electrodes 130. Isolation regions 180 may extend in the second direction (y-direction), may be spaced apart in the first direction (x-direction), and may separate gate electrodes 130 from each other in the first direction (x-direction). Common source line 103n may be disposed below isolation region 180.

[0050] Isolation region 180 may include a conductive layer 182, a barrier layer 186, and insulating spacers 184. Conductive layer 182 may include a metal such as tungsten (W), aluminum (Al), titanium (Ti), or copper (Cu). Barrier layer 186 may include, for example, TiN. Insulating spacers 184 may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0051] For example, Figure 2 As shown in FIG, the conductive layer 182, the barrier layer 186 and the insulating spacer 184 may have a Figure 1 ) extends above the gate electrode 130s. In another example, the isolation region 180 may have a structure in which a portion of the conductive layer 182 that is adjacent to the common source line 103n and does not extend higher than the lowermost interlayer insulating layer 160 has a small thickness, and a buried insulating layer is provided on the upper portion of the conductive layer 182. When the isolation region 180 has such a structure, the insulating spacer 184 may be omitted. In yet another example, the isolation region 180 may have a structure in which the insulating spacer 184 is formed only to the ground selection transistor GST (see Figure 1 ) of the gate electrode 130G, so that the conductive layer 182 is formed to a predetermined height between the insulating spacers 184, and the buried insulating layer is provided on the upper portion of the conductive layer 182.

[0052] Bit line 193 ( Figure 1 BL1, BL2, ..., BLm) in the string selection line SSL can be connected to the string selection transistor SST (see Figure 1 ). For example, the bit lines 193 may extend in a first direction (x direction) and may be formed in a line shape spaced apart from each other in a second direction (y direction). The bit lines 193 may be electrically connected to the string selection transistors SST (see FIG. 1 ) connected to the string selection line SSL through contact plugs 195 formed on the channel pattern 150. Figure 1 ) of the drain.

[0053] Figure 3 is a diagram showing in detail the Figure 2 A partial enlarged view of region III.

[0054] Reference Figure 3 , the channel pattern 150 may include a channel pattern extension portion 150p. The channel pattern extension portion 150p may be integrally formed with a portion of the channel pattern 150 extending in the vertical direction (z direction). Figure 2 and Figure 3As shown in , the channel pattern 150 may include a vertical portion 150v and a channel pattern extension 150p, for example, the vertical portion 150v has a linear film shape extending along the z-direction and conforming to the outer side wall of the buried insulating layer 175, and the channel pattern extension 150p may extend laterally along the x-direction away from the vertical portion 150v of the channel pattern 150, for example, the channel pattern extension 150p and the vertical portion 150v may be integrated with each other to define a single seamless structure.

[0055] The portion of the vertical portion 150v of the channel pattern 150 extending along the vertical direction (z direction) may have a thickness T2 (e.g., measured from the buried insulating layer 175 to the information storage layer 140 along the x direction). In addition, the channel pattern extension 150p may have a thickness T1 in the vertical direction (z direction) (e.g., measured from the top surface of the common source semiconductor layer 110 along the z direction). The thickness T1 may be greater than the thickness T2. In some embodiments, the thickness T1 may be at least twice the thickness T2. In some embodiments, the thickness T1 may have a value ranging from approximately 2 times the thickness T2 (2×T2) to approximately 100 times the thickness T2 (100×T2), for example, from approximately (2×T2) to approximately (80×T2), from approximately (2.2×T2) to approximately (70×T2), and from approximately (2.5×T2) to approximately (50×T2).

[0056] The supporting layer 120 may have a sidewall 120W that is set back (e.g., offset) by a length L1 relative to the sidewall of the channel hole 150H. For example, the distance along the x-direction between the sidewall of the channel hole 150H and the sidewall 120W of the supporting layer 120 may be defined as the length L1. Since the sidewall of the channel hole 150H and the lateral sidewall of the gate electrode 130 are in contact with each other, the sidewall 120W of the supporting layer 120 facing the channel hole 150H may be set back (e.g., offset) by a length L1 relative to the sidewall of the gate electrode 130. For example, the gate electrode 130 may extend toward the channel hole 150H to protrude by a length L1 relative to the supporting layer 120 along the x-direction. As a result, the information storage layer 140 can conform to the lateral sidewalls of the gate electrode 130 and the lateral sidewalls of the support layer 120, that is, extend in the vertical direction (z-direction) along the sidewalls of the interlayer insulating layer 160 and the sidewalls of the gate electrode 130, and extend toward the support layer 120 in the horizontal direction (x-direction, y-direction, and / or a combination thereof) along the lower surface of the gate electrode 130GD connected to the GIDL erase line. In addition, the information storage layer 140 can extend in the vertical direction (z-direction) along the sidewalls of the support layer 120. For example, the information storage layer 140 can extend to at least the lower end of the support layer 120. For example, the information storage layer 140 can extend to the lower end of the support layer 120 and then extend in the horizontal direction (x-direction, y-direction, and / or a combination thereof) along the upper surface of the supporting insulating layer 162.

[0057] The tunneling dielectric layer 142, charge storage layer 144, and blocking dielectric layer 146 constituting the information storage layer 140 may extend horizontally for a predetermined length along the upper surface of the supporting insulating layer 162 and then terminate. At this point, the positions of the termination ends of the tunneling dielectric layer 142 and the blocking dielectric layer 146 may differ from each other in the direction along which the information storage layer 140 extends. For example, the charge storage layer 144 may extend beyond the tunneling dielectric layer 142 and the blocking dielectric layer 146 along the x-direction. The channel pattern 150 may, for example, extend at least partially relative to the bottom of the substrate 101 to a level lower than the upper surface 101M of the substrate 101. The residual information storage layer 140res may be disposed below the lowest end of the channel pattern 150. The residual information storage layer 140res may have the same structure as that of the information storage layer 140. That is, the residual information storage layer 140res may include a residual tunneling dielectric layer 142b, a residual charge storage layer 144b, and a residual blocking dielectric layer 146b, and their compositions may be substantially the same as those of the tunneling dielectric layer 142, the charge storage layer 144, and the blocking dielectric layer 146, respectively.

[0058] The common source semiconductor layer 110 may extend horizontally along the upper surface 101M of the substrate 101 (e.g., along the x-direction) and contact the channel pattern 150. In some embodiments, a portion of the common source semiconductor layer 110 may extend in the vertical direction (z-direction), for example, continuously, and also contact the lower surface of the channel pattern extension portion 150p. The common source semiconductor layer 110 may also extend in the horizontal direction (x-direction, y-direction, and / or a combination thereof) while contacting the lower surface of the channel pattern extension portion 150p and may contact an end portion of the information storage layer 140. For example, as Figure 3 As shown in the figure, a portion of the common source semiconductor layer 110 can extend continuously in the vertical direction (z direction) along the channel pattern 150, for example, and bend toward the edge of the information storage layer 140 near the edge of the protective layer 161 and the supporting insulating layer 162 (below the channel pattern extension portion 150p).

[0059] The common source semiconductor layer 110 may generally be disposed below the channel pattern extension 150p in the vertical direction (z direction). For example, the uppermost end of the common source semiconductor layer 110 may be at a level equal to or lower than the lower surface of the channel pattern extension 150p in the vertical direction (z direction).

[0060] like Figure 3 As shown in , since the uppermost end of the common source semiconductor layer 110 is defined by the channel pattern extension 150p, the distance between the gate electrode 130GD connected to the GIDL erase line and the uppermost end of the common source semiconductor layer 110 (i.e., the distance T3 which is the sum of the thickness T1 and the thickness of the information storage layer 140) can be ensured to be constant. That is, even if the exact position of the end of the information storage layer 140 on the channel pattern extension 150p along the horizontal direction may change, the end of the information storage layer 140 is still located (e.g., directly located) on the lower surface of the channel pattern extension 150p, thereby providing a constant distance T3 between the gate electrode 130GD and the common source semiconductor layer 110.

[0061] In other words, due to various parameters in the manufacturing process, the position of the end of the information storage layer 140 may be different for each individual semiconductor device. If the distance between the gate electrode 130GD connected to the GIDL erase line and the common source semiconductor layer 110 is determined based on the position of the end of the information storage layer 140, then, for example, since the position of the end of the information storage layer 140 may slightly vary between individual semiconductor devices, performance deviations may occur between individual semiconductor devices. In contrast, in the semiconductor device according to the embodiment, as shown in FIG. Figure 3As shown in FIG, because the end of the information storage layer 140 is located at any point in the horizontal direction (x direction, y direction, and / or a combination thereof) along the lower surface of the channel pattern extension portion 150p, even if the position of the end of the information storage layer 140 varies for each individual semiconductor device, the distance T3 between the gate electrode 130GD connected to the GIDL erase line and the common source semiconductor layer 110 can be maintained constant. Therefore, performance variations between individual semiconductor devices can be greatly reduced.

[0062] In addition, since an overlapping area between the channel pattern 150 and the gate electrode 130GD connected to the GIDL erase line (ie, the entire side surface and a portion of the lower surface of the gate electrode 130GD) is increased, an erase operation using the GIDL method may be more easily performed.

[0063] In addition, the thickness of the channel pattern extension 150 p may be sufficiently large, and thus, the concentration of impurities (eg, phosphorus (P)) due to diffusion may be sufficiently ensured.

[0064] Figure 4 FIG. 1 is a diagram showing in detail a semiconductor device 100 according to another embodiment. Figure 2 In addition to the information storage layer 140 further including a vertical extension portion extending from the lower portion of the channel pattern extension portion 150p in the vertical direction (z direction), Figure 4 The embodiment shown in Figure 3 Therefore, the following description focuses on this difference.

[0065] Reference Figure 4 In some embodiments, the end of the information storage layer 140 may be located at a level between the lower surface of the protection layer 161 and the upper surface of the supporting insulating layer 162. Figure 4 As shown in FIG, the end portion of the information storage layer 140 may be bent to extend along and overlap at least the end edge of the support insulating layer 162 in the protective layer 161 and the support insulating layer 162. The level of the uppermost end of the common source semiconductor layer 110 may be defined by the end portion of the information storage layer 140. The distance between the gate electrode 130GD connected to the GIDL erase line GEL and the common source semiconductor layer 110 may be determined as T3a according to the position of the end portion of the information storage layer 140.

[0066] exist Figure 4 In the embodiment of FIG, the common source semiconductor layer 110 may be in direct contact with the end portion of the information storage layer 140. Figure 3 In the embodiment, the common source semiconductor layer 110 may be in direct contact with the lower surface of the channel pattern extension 150 p and the end portion of the information storage layer 140 .

[0067] Figure 5 is a lateral cross-sectional view showing a semiconductor device 100A according to another embodiment. Figure 2 Compared with the semiconductor device 100 shown in FIG. Figure 5 The semiconductor device 100A of the embodiment shown in FIG has a great difference in the structure of the lower end portion of the channel pattern 150. Therefore, the following description focuses on this difference.

[0068] Reference Figure 5 , the substrate 101 may include polysilicon doped with a p-type conductivity, and may include an n-type conductivity n-well 101n having a predetermined depth in the upper surface 101M of the substrate 101. The lower end of the channel pattern 150 may extend to a level lower than the upper surface 101M of the substrate 101. The lower end of the channel pattern 150 may include a lower extension 150pn extending a predetermined distance in a lateral direction (x direction, y direction, and / or a combination thereof) at a level lower than the upper surface 101M of the substrate 101. In some embodiments, the sidewalls of the lower extension 150pn may be substantially aligned with the sidewalls of the channel pattern extension 150p.

[0069] The residual information storage layer 240res may be disposed on the sidewalls and lower surface of the lower extension 150pn. Furthermore, the residual information storage layer 240res may partially extend onto the upper surface of the lower extension 150pn. The residual information storage layer 240res may have substantially the same configuration as the information storage layer 140, which will be described in greater detail later. The sidewalls of the residual information storage layer 240res may be substantially aligned with the sidewalls of the information storage layer 140.

[0070] Figure 6 is a diagram showing in detail the Figure 5 A partially enlarged view of region VI of the semiconductor device 100A. Figure 3 Compared with the semiconductor device 100 shown in FIG. Figure 6 The semiconductor device 100A of the embodiment shown in FIG has a great difference in the structure of the lower end portion of the channel pattern 150. Therefore, the following description focuses on this difference.

[0071] Reference Figure 6 , the dimension of the lower extension portion 150pn protruding in the horizontal direction (x direction, y direction, and / or a combination thereof) may be substantially the same as the dimension of the channel pattern extension portion 150p protruding in the horizontal direction. As a result, the sidewalls of the lower extension portion 150pn may be substantially aligned with the sidewalls of the channel pattern extension portion 150p. For example, the extension portions 150p and 150pn may vertically overlap each other.

[0072] The residual information storage layer 240res may include a residual tunneling dielectric layer 142c, a residual charge storage layer 144c, and a residual blocking dielectric layer 146c, and their compositions may be substantially the same as those of the tunneling dielectric layer 142, the charge storage layer 144, and the blocking dielectric layer 146, respectively. In some embodiments, the sidewalls of the information storage layer 140 located on the sidewalls of the channel pattern extensions 150p (i.e., the sidewalls of the support layer 120) may be substantially aligned with the sidewalls of the residual information storage layer 240res.

[0073] The residual tunneling dielectric layer 142c and the residual charge storage layer 144c may conformally extend along the lower surface and side surfaces of the lower extension 150pn. Furthermore, the residual tunneling dielectric layer 142c and the residual charge storage layer 144c may extend a predetermined length along the upper surface of the lower extension 150pn. The residual blocking dielectric layer 146c may conformally extend along the lower surface and side surfaces of the lower extension 150pn. The residual blocking dielectric layer 146c may not extend onto the upper surface of the lower extension 150pn.

[0074] In some embodiments, the thickness T4 of the lower extension portion 150pn in the vertical direction (z direction) may be greater than or equal to the thickness T1 of the channel pattern extension portion 150p in the vertical direction (z direction). Figure 6 Unlike in the embodiment of the present invention, the buried insulating layer 175 may partially extend into the lower extension 150pn.

[0075] In the case where a polycrystalline silicon substrate (i.e., polysilicon) is used as the substrate 101, when the support layer 120 is partially removed so that the sidewalls of the support layer 120 recede (e.g., offset), a space in which the lower extension 150pn will be formed is formed because the substrate 10 is partially removed similarly to the support layer 120. In addition, in a subsequent process, the residual information storage layer 240res and the lower extension 150pn may fill this space.

[0076] 7A to 7I are lateral cross-sectional views of various stages in a method of manufacturing a semiconductor device 100 according to an embodiment.

[0077] Reference Figure 7A A protective insulating layer 103 is formed on the substrate 101 having the n-well 101n formed therein, and a lower sacrificial layer pattern 110s is formed on the protective insulating layer 103. For example, the lower sacrificial layer pattern 110s may be formed by performing a photolithography process after forming the lower sacrificial material layer. The lower sacrificial layer pattern 110s may include, for example, silicon nitride. The protective insulating layer 103 may include any material having an etch selectivity with respect to the lower sacrificial layer pattern 110s, and may include, for example, silicon oxide.

[0078] After forming the lower sacrificial layer pattern 110s, a protective layer 161 and a supporting insulating layer 162 are sequentially and conformally formed on the upper surface and side surfaces of the lower sacrificial layer pattern 110s and the partially exposed protective insulating layer 103. The protective layer 161 may include, for example, polysilicon. In some embodiments, the protective layer 161 may include polysilicon doped with carbon. The supporting insulating layer 162 may include Figure 2 Silicon oxide is not described in detail, so its detailed description is omitted. The protection layer 161 and the supporting insulating layer 162 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), but are not limited thereto.

[0079] Reference Figure 7B A supporting layer material layer 120A may be formed on the supporting insulating layer 162, and an insulating layer 160a may be formed on the supporting layer material layer 120A. The supporting layer material layer 120A may include doped or undoped polysilicon, and the insulating layer 160a may include any insulating layer, for example, silicon nitride, silicon oxide, or silicon oxynitride. The insulating layer 160a may be formed by forming an insulating material layer on polysilicon and then performing chemical mechanical polishing (CMP) to expose the upper surface of the supporting layer material layer 120A.

[0080] Reference Figure 7C , sacrificial layers 130h and interlayer insulating layers 160 may be alternately stacked on the support layer material layer 120A and the insulating layer 160a. According to some embodiments, the interlayer insulating layer 160 and the sacrificial layer 130h may include different materials. According to some embodiments, the interlayer insulating layer 160 and the sacrificial layer 130h may include materials having a high etching selectivity relative to each other. For example, when the sacrificial layer 130h includes silicon oxide, the interlayer insulating layer 160 may include silicon nitride. As another example, when the sacrificial layer 130h includes silicon nitride, the interlayer insulating layer 160 may include silicon oxide. As another example, when the sacrificial layer 130h includes undoped polysilicon, the interlayer insulating layer 160 may include silicon nitride or silicon oxide. The sacrificial layer 130h and the interlayer insulating layer 160 may be formed by CVD, PVD, or ALD.

[0081] Figure 8 It shows in detail Figure 7D A partial enlarged view of area B.

[0082] Reference Figure 7D and Figure 8 A channel hole 150H may be formed sequentially passing through the sacrificial layer 130h and the interlayer insulating layer 160, the supporting layer material layer 120A, the supporting insulating layer 162, the protective layer 161, the lower sacrificial layer pattern 110s, and the protective insulating layer 103. The channel hole 150H may be formed by anisotropic etching.

[0083] Next, the supporting layer recess 120R can be formed by partially removing the supporting layer 120 and causing the sidewalls of the supporting layer 120 to recede (e.g., offset). The sidewalls of the supporting layer 120 can be receded relative to the sidewalls of the channel hole 150H thereover (e.g., arranged away from the sidewalls of the channel hole 150H). The sidewalls of the supporting layer 120 can be further receded (e.g., offset) relative to the sidewalls of the sacrificial layer 130h directly on the supporting layer 120. For example, a portion of the supporting layer 120 can be removed so that the sacrificial layer 130h directly on the supporting layer 120 protrudes relative to the supporting layer 120.

[0084] For example, the support layer 120 can be partially removed by selectively isotropically etching the support layer 120 including polycrystalline silicon. Depending on the choice of etchant, polycrystalline silicon and single-crystalline silicon can have different etching selectivities. In this case, when the substrate 101 is single-crystalline silicon, the support layer 120 can be selectively removed without substantially removing the single-crystalline silicon.

[0085] Figure 9 It shows in detail Figure 7E A partial enlarged view of area B.

[0086] Reference Figure 7E and Figure 9 , the information storage material layer 140m can be substantially conformally formed on the exposed inner surface of the channel hole 150H. In detail, a blocking dielectric material layer 146m, a charge storage material layer 144m, and a tunneling dielectric material layer 142m can be conformally formed from the sidewalls of the channel hole 150H, and they can be formed using, for example, ALD. The blocking dielectric material layer 146m, the charge storage material layer 144m, and the tunneling dielectric material layer 142m can respectively include materials substantially the same as those of the blocking dielectric layer 146, the charge storage layer 144, and the tunneling dielectric layer 142, and therefore their detailed description will be omitted.

[0087] Then, a channel pattern 150 may be formed on the inner surface of the tunnel dielectric material layer 142m. The channel pattern 150 may be formed by, for example, CVD or ALD. The channel pattern 150 may be formed to fill the interior of the support layer recess 120R, thereby forming a channel pattern extension 150p. In an embodiment, the channel pattern 150 may completely fill the interior of the support layer recess 120R. In some embodiments, the channel pattern 150 may be formed to have a greater thickness to completely fill the interior of the support layer recess 120R, and then anisotropically etched to a desired thickness.

[0088] Then, the inner space of the channel pattern 150 may be filled with a buried insulating layer 175. The formation of the buried insulating layer 175 may be performed by, for example, CVD or ALD.

[0089] Figure 10 It shows in detail Figure 7F A partial enlarged view of area B.

[0090] Reference Figure 7F and Figure 10 A mask pattern may be formed on the upper interlayer insulating layer 165, and the mask pattern may be used as an etching mask to form a word line cut opening 180H. The upper surface of the lower sacrificial layer pattern 110s may be exposed at the bottom of the word line cut opening 180H. In some embodiments, the upper surface of the substrate 101 may be exposed at the bottom of the word line cut opening 180H.

[0091] Afterwards, spacers 185 may be formed to cover the upper surface of the upper interlayer insulating layer 165 and the sidewalls of the word line cutting opening 180H. In an exemplary embodiment, the spacers 185 may be selected to have a high etching selectivity relative to the lower sacrificial layer pattern 110s. For example, the spacers 185 may be silicon oxide, silicon oxynitride, or the like.

[0092] Next, the lower sacrificial layer pattern 110s may be removed by selective etching. In some embodiments, the lower sacrificial layer pattern 110s may be removed by wet isotropic etching or dry isotropic etching. When the lower sacrificial layer pattern 110s is selectively removed, the protective insulating layer 103 may prevent damage to the substrate 101. By removing the lower sacrificial layer pattern 110s, the side surface of the information storage material layer 140m having the same level as the lower sacrificial layer pattern 110s may be exposed.

[0093] Figures 11 to 13 The method of removing the exposed portion of the information storage material layer 140m at each stage is shown. Figure 7G The transverse cross-sectional view corresponding to region B.

[0094] Reference Figure 11 , the blocking dielectric material layer 146m can be removed by isotropic etching ( Figure 10) exposed portion. The blocking dielectric layer 146 and the residual blocking dielectric layer 146b can be formed by partially removing the blocking dielectric material layer 146m. In this case, when the etching characteristics of the supporting insulating layer 162 are similar to the etching characteristics of the blocking dielectric material layer 146m, the supporting insulating layer 162 can be partially removed together with the blocking dielectric material layer 146m, for example, to form an opening passing through the blocking dielectric material layer 146m and adjacent to the supporting insulating layer 162 and the residual blocking dielectric layer 146b. In addition, when the etching characteristics of the protective insulating layer 103 are similar to the etching characteristics of the blocking dielectric material layer 146m, the protective insulating layer 103 can be removed together with the blocking dielectric material layer 146m.

[0095] Reference Figure 12 , the charge storage material layer 144m can be removed by isotropic etching ( Figure 10 The charge storage layer 144 and the residual charge storage layer 144b may be formed by partially removing the charge storage material layer 144m, for example, to form an opening through the charge storage material layer 144m and adjacent to the supporting insulating layer 162 and the residual blocking dielectric layer 146b.

[0096] Reference Figure 13 , the tunnel dielectric material layer 142m can be removed by isotropic etching ( Figure 10 The tunneling dielectric layer 142 and the residual tunneling dielectric layer 142b may be formed by partially removing the tunneling dielectric material layer 142m.

[0097] The end of tunneling dielectric layer 142 and the end of blocking dielectric layer 146 are not necessarily aligned with each other. In some embodiments, the end of tunneling dielectric layer 142 may protrude toward channel pattern 150 in a horizontal direction compared to the end of blocking dielectric layer 146.

[0098] By summarizing Figures 11 to 13 The information storage layer 140 may be formed by removing the first portion 140m1 and the second portion 140m2 adjacent to the first portion 140m1, the first portion 140m1 being the exposed portion of the information storage material layer 140m. Furthermore, by removing the first portion 140m1 and the second portion 140m2, a residual information storage layer 140res may be formed adjacent to the lower end of the channel pattern 150.

[0099] exist Figure 13 In the embodiment, the ends of the tunnel dielectric layer 142, the charge storage layer 144, the blocking dielectric layer 146, and the supporting insulating layer 162 are formed as curved surfaces, but the embodiment is not limited thereto. Figure 13In the embodiment, the ends of the tunneling dielectric layer 142, the charge storage layer 144, and the blocking dielectric layer 146 are disposed on the lower surface of the channel pattern extension 150p, but the embodiment is not limited thereto. In some embodiments, the ends of the tunneling dielectric layer 142, the charge storage layer 144, and the blocking dielectric layer 146 may be disposed on the side surface of the protection layer 161.

[0100] Figure 14 It shows in detail Figure 7G A partial enlarged view of area B.

[0101] Reference Figure 7G and Figure 14 The common source semiconductor material layer 110m may be provided to bury the portion where the lower sacrificial layer pattern 110s and the information storage material layer 140m are removed. The common source semiconductor material layer 110m may be formed by diffusing and depositing reactants through the word line cut opening 180H to the portion where the lower sacrificial layer pattern 110s and the information storage material layer 140m are removed.

[0102] A common source semiconductor material layer 110m may be deposited on the surfaces of the exposed sidewalls of the wordline cut opening 180H (i.e., the spacer 185) and the upper interlayer insulating layer 165. The common source semiconductor material layer 110m may be formed by, for example, CVD, ALD, etc. The common source semiconductor material layer 110m may be a polysilicon layer doped with impurities.

[0103] Reference Figure 7H The upper surface of the substrate 101 can be exposed by removing the common source semiconductor material layer 110m deposited on the exposed sidewalls of the word line cut opening 180H and the upper interlayer insulating layer 165. Thereafter, a common source line 103n can be formed by removing the spacers 185 and implanting impurities at a relatively high concentration from the upper surface of the substrate 101 to a predetermined depth.

[0104] Reference Figure 7I , the sacrificial layer 130h can be replaced with the gate electrode 130. Because the sacrificial layer 130h has an etching selectivity with respect to the interlayer insulating layer 160 and the upper interlayer insulating layer 165, the sacrificial layer 130h can be selectively removed. Thereafter, the gate electrode 130 can be formed by forming a conductive material constituting the gate electrode 130 at the position where the sacrificial layer 130h was removed, for example, by CVD or ALD.

[0105] Return to reference Figure 2, an isolation region 180 including a conductive layer 182, a barrier layer 186, and an insulating spacer 184 may be formed in the word line cut opening 180H. Specifically, an insulating spacer 184 may be formed in the word line cut opening 180H, and then the barrier layer 186 and the conductive layer 182 may be formed. The conductive layer 182, the barrier layer 186, and the insulating spacer 184 may be formed by using, for example, CVD, ALD, etc., and their specific materials are described above, so a detailed description thereof will be omitted.

[0106] Next, a conductive capping layer 177 may be formed by partially removing the information storage layer 140, the channel pattern 150, and the upper end portion of the buried insulating layer 175. Thereafter, an upper interlayer insulating layer 192 may be formed, and a contact plug 195 may be formed that passes through the upper interlayer insulating layer 192 and extends in the vertical direction (z direction), and then a bit line 193 may be formed that is conductive and connected to the contact plug 195. The contact plug 195 and the bit line 193 may include at least one of a metal (e.g., tungsten, titanium, tantalum, copper, or aluminum) and a conductive metal nitride (e.g., TiN or TaN).

[0107] Figures 15A to 15F are lateral cross-sectional views showing stages in a method of manufacturing a semiconductor device 100A according to another embodiment. Figure 16 It shows in detail Figure 15A A partial enlarged view of area B. 7A to 7C The corresponding operations are common, so their detailed description is omitted.

[0108] Reference Figure 15A and Figure 16 A channel hole 150H may be formed sequentially passing through the sacrificial layer 130h and the interlayer insulating layer 160, the supporting layer material layer 120A, the supporting insulating layer 162, the protective layer 161, the lower sacrificial layer pattern 110s, and the protective insulating layer 103. The channel hole 150H may be formed by anisotropic etching.

[0109] Next, the supporting layer 120 and the supporting layer recess 120R can be formed by partially removing the supporting layer material layer 120A so that the sidewalls of the supporting layer material layer 120A are receded (e.g., arranged away from the sidewalls of the supporting layer material layer 120A). The sidewalls of the supporting layer 120 can be receded (e.g., offset) relative to the sidewalls of the channel hole 150H thereover. The sidewalls of the supporting layer 120 can be further receded (e.g., offset) relative to the sidewalls of the sacrificial layer 130h directly on the supporting layer 120.

[0110] Alternatively, the substrate 101 may be a polysilicon substrate. In this case, when the sidewalls of the support layer material layer 120A recede (e.g., deflect), the substrate 101 may also be partially removed to form the recessed portion 122R. In some embodiments, the horizontal recessed distance of the support layer recessed portion 120R and the horizontal recessed distance of the recessed portion 122R may be substantially the same.

[0111] Figure 17 It shows in detail Figure 15B A partial enlarged view of area B.

[0112] Reference Figure 15B and Figure 17 The information storage material layer 140m may be substantially conformally formed on the exposed inner surface of the channel hole 150H. Specifically, the blocking dielectric material layer 146m, the charge storage material layer 144m, and the tunneling dielectric material layer 142m may be conformally and sequentially formed from the sidewalls of the channel hole 150H, and may be formed by using, for example, ALD.

[0113] In addition, a channel pattern 150 and a buried insulating layer 175 may be formed on the inner surface of the tunnel dielectric material layer 142m. The channel pattern 150 may be formed to bury the support layer recess 120R, thereby forming a channel pattern extension 150p. In addition, the channel pattern 150 may be formed to bury the lower recess 122R, thereby forming a lower extension 150pn.

[0114] Reference Figure 9 The information storage material layer 140m, the channel pattern 150, and the buried insulating layer 175 are described in detail. Therefore, additional description thereof will be omitted.

[0115] Figure 18 It shows in detail Figure 15C A partial enlarged view of area B.

[0116] Reference Figure 15C and Figure 18 , a mask pattern may be formed on the upper interlayer insulating layer 165 , word line cutting openings 180H may be formed using the mask pattern as an etching mask, spacers 185 may be formed, and then the lower sacrificial layer pattern 110s may be removed by selective etching.

[0117] Figures 19 to 21 is a diagram showing a method of removing the exposed portion of the information storage material layer 140m. Figure 15D The transverse cross-sectional view corresponding to region B.

[0118] Reference Figure 19, the exposed portion of the blocking dielectric material layer 146m can be removed by isotropic etching. The blocking dielectric layer 146 and the residual blocking dielectric layer 146c can be formed by partially removing the blocking dielectric material layer 146m. In this case, when the etching characteristics of the supporting insulating layer 162 are similar to those of the blocking dielectric material layer 146m, the supporting insulating layer 162 can be partially removed together with the blocking dielectric material layer 146m.

[0119] In addition, when the etching characteristics of the protective insulating layer 103 are similar to those of the blocking dielectric material layer 146m, the protective insulating layer 103 can be removed together with the blocking dielectric material layer 146m. In addition, when removing the protective insulating layer 103, the blocking dielectric material layer 146m covering the upper surface of the lower extension 150pn can be completely exposed by isotropic etching. In this case, most of the horizontally extending portion of the blocking dielectric material layer 146m extending in the horizontal direction (x direction, y direction, or a combination thereof) along the upper surface of the lower extension 150pn can be removed.

[0120] Reference Figure 20 The exposed portion of the charge storage material layer 144m may be removed by isotropic etching. The charge storage layer 144 and the residual charge storage layer 144c may be formed by partially removing the charge storage material layer 144m.

[0121] Reference Figure 21 The exposed portion of the tunneling dielectric material layer 142m may be removed by isotropic etching. The tunneling dielectric layer 142 and the residual tunneling dielectric layer 142c may be formed by partially removing the tunneling dielectric material layer 142m.

[0122] Figure 22 It shows in detail Figure 15D A partial enlarged view of area B.

[0123] Reference Figure 15D and Figure 22 The common source semiconductor material layer 110m may be provided to bury the portion where the lower sacrificial layer pattern 110s and the portion where the information storage material layer 140m are removed. The common source semiconductor material layer 110m may be deposited on the surface of the exposed sidewalls (i.e., the spacer 185) of the word line cutting opening 180H and on the upper interlayer insulating layer 165.

[0124] Reference Figure 15EThe upper surface of the substrate 101 can be exposed by removing the common source semiconductor material layer 110m deposited on the exposed sidewalls of the word line cut opening 180H and the upper interlayer insulating layer 165. Thereafter, a common source line 103n can be formed by removing the spacers 185 and implanting impurities at a relatively high concentration from the upper surface of the substrate 101 to a predetermined depth.

[0125] Reference Figure 15F , the sacrificial layer 130h can be replaced with the gate electrode 130. Because the sacrificial layer 130h has an etching selectivity with respect to the interlayer insulating layer 160 and the upper interlayer insulating layer 165, the sacrificial layer 130h can be selectively removed. Thereafter, the gate electrode 130 can be formed by forming a conductive material constituting the gate electrode 130 at the position where the sacrificial layer 130h was removed, for example, by CVD or ALD.

[0126] Reference Figure 5 , an isolation region 180 including a conductive layer 182, a barrier layer 186, and an insulating spacer 184 may be formed in the word line cut opening 180H. Specifically, an insulating spacer 184 may be formed in the word line cut opening 180H, and then the barrier layer 186 and the conductive layer 182 may be formed. The conductive layer 182, the barrier layer 186, and the insulating spacer 184 may be formed by, for example, CVD, ALD, etc., and their specific materials are described above, so a detailed description thereof will be omitted.

[0127] Next, a conductive capping layer 177 may be formed by partially removing the information storage layer 140, the channel pattern 150, and the upper end of the buried insulating layer 175. Figure 2 As described above, the upper interlayer insulating layer 192, the contact plug 195, and the bit line 193 are formed, and thus a detailed description thereof will be omitted.

[0128] Figure 23 1 is a cross-sectional view showing a semiconductor device 100B according to an embodiment. Figure 23 In, with Figures 1 to 22 The same reference numerals as those in the drawings represent the same components.

[0129] Reference Figure 23The peripheral circuit region PERI may be formed at a lower vertical level than the memory cell region MCR. The lower substrate 310 may be disposed at a lower vertical level than the substrate 101, and the upper level of the lower substrate 310 may be lower than the upper level of the substrate 101. An active region may be defined in the lower substrate 310 by a device isolation layer 322, and a plurality of driver transistors 330T may be formed on the active region. The plurality of driver transistors 330T may include a driver circuit gate structure 332 and impurity regions 312 disposed in a portion of the lower substrate 310 on both sides of the driver circuit gate structure 332.

[0130] A plurality of wiring layers 342, a plurality of contact plugs 346, and a lower interlayer insulating layer 350 may be provided on the lower substrate 310. The plurality of contact plugs 346 may be connected between the plurality of wiring layers 342 or between the plurality of wiring layers 342 and the driving transistor 330T. In addition, the lower interlayer insulating layer 350 may cover the plurality of wiring layers 342 and the plurality of contact plugs 246.

[0131] Since the substrate 101 needs to be formed on the lower interlayer insulating layer 350, the substrate 101 may include polysilicon instead of single crystal silicon. Figure 15A and Figure 16 As described above, when the substrate 101 is polysilicon, the lower recess 122R may be formed together with the support layer recess 120R. As a result, the lower extension 150pn may be formed at the lower end of the channel pattern 150.

[0132] According to the embodiment, a vertical semiconductor device having excellent electrical characteristics and high reliability and a method for manufacturing the same are provided. That is, a vertical semiconductor device having excellent electrical characteristics (eg, GIDL erase and high reliability) can be manufactured relatively easily.

[0133] In other words, according to an embodiment, after forming the channel hole, a support layer recess is formed by expanding the sidewalls of the support layer, and the space is filled with oxide-nitride-oxide (ONO) and the channel pattern. When performing an isotropic ONO etch to form an ONO butt contact, the ONO end is confined to the lower portion of the channel pattern extension. As a result, the distance between the gate of the GIDL transistor and the common source semiconductor layer can be maintained constant, wherein the area where the gate of the GIDL transistor and the channel pattern overlap is increased. The channel pattern extension also helps with diffusion control, thereby improving GIDL efficiency and reducing leakage of the ground select transistor.

[0134] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to those skilled in the art by the time this application is filed that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically stated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A vertical semiconductor device comprising: a common source semiconductor layer located on the substrate; a supporting layer, located on the common source semiconductor layer; gate electrodes and interlayer insulating layers alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to the upper surface of the substrate while passing through the gate and the support layer, wherein a sidewall of the support layer facing the channel pattern is offset relative to a sidewall of the gate facing the channel pattern; as well as an information storage layer extending between the gate and the channel pattern, the information storage layer extending at least to a sidewall of the support layer facing the channel pattern, The channel pattern includes a channel pattern extension portion protruding toward the support layer in a lateral direction of the support layer, and in the first direction, the level of the uppermost end of the common source semiconductor layer is equal to or lower than the level of the lower surface of the channel pattern extension portion. The channel pattern extension portion extends in a second direction perpendicular to the first direction, and a thickness of the channel pattern extension portion in the first direction is more than twice a thickness of the channel pattern located at a side of the gate along the second direction. 2 . The vertical semiconductor device according to claim 1 , further comprising a supporting insulating layer and a protection layer located between the common source semiconductor layer and the supporting layer, wherein the protection layer protects the supporting insulating layer.

3. The vertical semiconductor device according to claim 2, wherein: The information storage layer extends at least to the supporting insulating layer.

4. The vertical semiconductor device according to claim 3, wherein: The information storage layer includes a horizontal extending portion extending in a horizontal direction along an upper surface of the supporting insulating layer.

5. The vertical semiconductor device according to claim 1, wherein The substrate has a p-type conductivity and includes an n-well located in a lower portion of the common source semiconductor layer. The vertical semiconductor device according to claim 1 , wherein: The common source semiconductor layer is in direct contact with an end portion of the information storage layer.

7. The vertical semiconductor device according to claim 1, wherein: The substrate includes a polysilicon substrate.

8. The vertical semiconductor device according to claim 7, wherein: The channel pattern includes a horizontal extension portion extending in a horizontal direction under the common source semiconductor layer. 9 . The vertical semiconductor device according to claim 7 , further comprising a lower substrate below the substrate and a peripheral circuit region between the substrate and the lower substrate.

10. A vertical semiconductor device comprising: a common source semiconductor layer located on the n-well of the substrate; a supporting layer, located on the common source semiconductor layer; gate electrodes and interlayer insulating layers alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while passing through the gate and the support layer, the channel pattern including a channel pattern extension protruding toward the support layer in a lateral direction of the support layer, and a sidewall of the support layer facing the channel pattern being offset relative to a sidewall of the gate facing the channel pattern; as well as an information storage layer extending between the gate and the channel pattern, Wherein, in the first direction, the level of the uppermost end of the common source semiconductor layer is equal to or lower than the level of the lower surface of the channel pattern extension portion, The channel pattern extension portion extends in a second direction perpendicular to the first direction, and a thickness of the channel pattern extension portion in the first direction is more than twice a thickness of the channel pattern located at a side of the gate along the second direction.

11. The vertical semiconductor device according to claim 10, further comprising: a channel hole, the channel pattern extending through the channel hole, and a portion of the channel pattern extending in the first direction being integral with the channel pattern extension; as well as A conductive capping layer contacts the channel pattern on an upper portion of the channel hole.

12. The vertical semiconductor device according to claim 10, wherein: The information storage layer extends along a lower surface of the gate electrode closest to the support layer to a sidewall of the support layer.

13. The vertical semiconductor device according to claim 12, wherein: The information storage layer includes a vertical extension portion extending in a vertical direction along a sidewall of the support layer.

14. The vertical semiconductor device of claim 12, wherein: The information storage layer includes a tunneling dielectric layer, a charge storage layer and a blocking dielectric layer, and In an extending direction of the information storage layer, a position of an end portion of the tunnel dielectric layer and a position of an end portion of the blocking dielectric layer are different from each other.

15. A vertical semiconductor device comprising: a common source semiconductor layer located on an n-well of a substrate having a p-type conductivity; a supporting layer, located on the common source semiconductor layer; gate electrodes and interlayer insulating layers alternately stacked on the support layer; a channel pattern extending in a first direction perpendicular to the upper surface of the substrate and passing through the gates and the support layer, wherein the channel pattern extends through the channel hole, and the support layer is in direct contact with a lowermost gate of the gates located in the channel hole; as well as an information storage layer extending between the gate and the channel pattern, wherein the sidewall of the support layer facing the channel hole is offset relative to the sidewall of the gate facing the channel hole, and The information storage layer extends horizontally along the lower surface of the lowest gate among the gates toward the support layer, and then extends in the first direction along the sidewall of the support layer. The channel pattern includes a channel pattern extension portion protruding toward the support layer in a lateral direction of the support layer, and in the first direction, the level of the uppermost end of the common source semiconductor layer is equal to or lower than the level of the lower surface of the channel pattern extension portion. The channel pattern extension portion extends in a second direction perpendicular to the first direction, and a thickness of the channel pattern extension portion in the first direction is more than twice a thickness of the channel pattern located at a side of the gate along the second direction.

Images