Drive device and switching device

Abstract

If a structure for short-circuit protection is provided in a drive device, it will cause the device to become larger. The present invention provides a drive device, comprising: a gate drive circuit that disconnects a first semiconductor element according to a situation where a signal for disconnecting the first semiconductor element among a first semiconductor element and a second semiconductor element connected in series between a positive power supply line and a negative power supply line is input; a measurement circuit that measures a parameter corresponding to the voltage applied to the second semiconductor element; a timing generation circuit that generates a first timing signal when the parameter satisfies a first condition during the disconnection of the first semiconductor element; and a drive condition change circuit that sets the change speed of the gate voltage of the first semiconductor element to a speed lower than a reference speed during the disconnection of the first semiconductor element according to the first timing signal, wherein the gate drive circuit disconnects the first semiconductor element according to a situation where the parameter satisfies a second condition during the conduction period of the first semiconductor element.

Description

Technical Field

[0001] The present invention relates to a driving device and a switching device. Background Art

[0002] Conventionally, in a driving device for driving a semiconductor element, in order to reduce switching loss and suppress a surge voltage during turn-off, an active gate driving method in which the change rate of the gate voltage is changed during the off period has been adopted (for example, refer to Patent Document 1). In addition, various methods for detecting a short circuit to protect an element have been proposed (for example, refer to Patent Documents 2 and 3).

[0003] Patent Document 1: Japanese Patent No. 6168253

[0004] Patent Document 2: Japanese Patent Application Laid-Open No. 2007-259533

[0005] Patent Document 3: Japanese Patent No. 5729472 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] However, if a structure for short-circuit protection is provided in the driving device, the device becomes large-sized.

[0008] Technical Solution for Solving the Technical Problem

[0009] In order to solve the above problems, in a first aspect of the present invention, a driving device is provided. The driving device may include a gate driving circuit that turns off a first semiconductor element according to a signal input that turns off the first semiconductor element among a first semiconductor element and a second semiconductor element connected in series between a positive power supply line and a negative power supply line. The driving device may include a measurement circuit that measures a parameter corresponding to a voltage applied to the second semiconductor element. The driving device may include a timing generation circuit that generates a first timing signal when the parameter satisfies a first condition during the off period of the first semiconductor element. The driving device may include a driving condition changing circuit that, according to the first timing signal, sets the change rate of the gate voltage of the first semiconductor element to a speed lower than a reference speed during the off period of the first semiconductor element. The gate driving circuit may also turn off the first semiconductor element according to a situation where the parameter satisfies a second condition during the on period of the first semiconductor element.

[0010] The gate driving circuit may also turn off the first semiconductor element according to a situation where the parameter satisfies a second condition after a reference time has elapsed since the first semiconductor element started to conduct.

[0011] The timing generation circuit can generate a second timing signal when the parameters satisfy the second condition during the conduction period of the first semiconductor element. The drive condition change circuit can, according to the second timing signal, set the change speed of the gate voltage to a speed lower than the reference speed during the off period of the first semiconductor element.

[0012] The timing generation circuit generates a first timing signal with a predetermined first pulse width.

[0013] The drive condition change circuit can reduce the change speed of the gate voltage during the period from when the first timing signal is received until the first timing signal is generated.

[0014] The timing generation circuit can generate a second timing signal with a predetermined second pulse width that is larger than the first pulse width. The drive condition change circuit can reduce the change speed of the gate voltage during the period from when the second timing signal is received until the second timing signal is generated.

[0015] The second pulse width can be larger than the time width from the start to the end of the off period of the first semiconductor element.

[0016] The drive device can include a first determination circuit that determines whether the parameters satisfy the first condition. The drive device can include a second determination circuit that determines whether the parameters satisfy the second condition.

[0017] The first condition and the second condition can be the same condition. The first determination circuit and the second determination circuit can be the same circuit.

[0018] The parameter can represent the voltage applied to the second semiconductor element.

[0019] The second condition can be that the voltage applied to the second semiconductor element is below a second reference voltage. The second reference voltage can be less than the voltage between the positive power supply line and the negative power supply line.

[0020] The first condition can be that the voltage applied to the second semiconductor element is below a first reference voltage. The second condition can be that the voltage applied to the second semiconductor element is below a second reference voltage. At least one of the first reference voltage and the second reference voltage can be 0V.

[0021] The parameter can represent the voltage applied to the first semiconductor element.

[0022] The second condition can be that the voltage applied to the first semiconductor element is above a fourth reference voltage. The fourth reference voltage can be greater than 0V.

[0023] The first condition may be that the voltage applied to the first semiconductor element is equal to or higher than a third reference voltage. The second condition may be that the voltage applied to the first semiconductor element is equal to or higher than a fourth reference voltage. At least one of the third reference voltage and the fourth reference voltage may be equal to or higher than the voltage between the positive power supply line and the negative power supply line.

[0024] In a second aspect of the present invention, a switching device is provided. The switching device may include two semiconductor elements connected in series between a positive power supply line and a negative power supply line. The switching device may include a driving device of the first type that drives the gate of one of the two semiconductor elements. The switching device may include a driving device of the first type that drives the gate of the other of the two semiconductor elements.

[0025] The two semiconductor elements may be wide bandgap semiconductor elements.

[0026] Furthermore, the above summary of the invention does not enumerate all the essential features of the present invention. Also, variations of these feature groups can also form an invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shows the switching device 1 of the present embodiment.

[0028] Figure 2 Shows the details of the driving device 5.

[0029] Figure 3 Shows the operation waveform of the switching device 1.

[0030] Figure 4 Shows other operation waveforms of the switching device 1. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, the present invention will be described by way of embodiments of the invention. The following embodiments do not limit the invention covered by the scope of the claims. Also, for the solution means of the invention, all combinations of the features described in the embodiments are not necessarily essential.

[0032] [1. Switching Device 1]

[0033] Figure 1 Shows the switching device 1 of the present embodiment. In the figure, a hollow arrow mark indicates voltage.

[0034] Regarding the switching device 1, a case where one phase of a power conversion device for motor drive or power supply is shown as an example is illustrated. By switching the connection between the positive power supply line 101 and the negative power supply line 102 and the power supply output terminal 105, a converted voltage is output from the power supply output terminal 105. The switching device 1 includes semiconductor elements 2, 3 and driving devices 4, 5.

[0035] In addition, a DC voltage Ed of, for example, 600 to 800 V is applied between the positive-side power supply line 101 and the negative-side power supply line 102. In addition, in the positive-side power supply line 101 and the negative-side power supply line 102, there may be wiring inductances 1011 and 1021 corresponding to the wiring lengths, respectively.

[0036] 〔1-1. Semiconductor elements 2, 3〕

[0037] The semiconductor elements 2, 3 are an example of a first semiconductor element and a second semiconductor element, and are connected in series between the negative-side power supply line 102 and the positive-side power supply line 101 in sequence. The power output terminal 105 may be connected to the midpoint of the semiconductor elements 2, 3.

[0038] The semiconductor elements 2, 3 are switching elements that are switched between on and off by the drive devices 4, 5 described later. As an example, the semiconductor elements 2, 3 constitute the upper arm and the lower arm in the power conversion device.

[0039] The semiconductor elements 2, 3 are silicon-based semiconductor elements. The semiconductor elements 2, 3 are not limited to silicon semiconductor elements, and may also be wide-bandgap semiconductor elements. A wide-bandgap semiconductor element is a semiconductor element having a larger bandgap than a silicon semiconductor element, and is, for example, a semiconductor element including SiC, GaN, diamond, gallium nitride-based materials, gallium oxide-based materials, AlN, AlGaN, or ZnO. Compared with a silicon semiconductor element, a wide-bandgap semiconductor element can improve the switching speed.

[0040] In addition, in the present embodiment, as an example, the semiconductor elements 2, 3 are MOSFETs and have parasitic diodes (illustrated in the figure) with the cathode on the positive-side power supply line 101 side. In addition, the semiconductor elements 2, 3 may also be semiconductor elements having other structures such as IGBTs or bipolar transistors, and diodes, Schottky barrier diodes, etc. may be reversely connected in parallel to each semiconductor element as needed.

[0041] 〔1-2. Drive devices 4, 5〕

[0042] The drive devices 4, 5 drive one or the other of the semiconductor elements 2, 3 based on an input signal input from the outside. In the present embodiment, as an example, the positive-side drive device 4 drives the gate of the semiconductor element 2, and the negative-side drive device 5 drives the gate of the semiconductor element 3.

[0043] When the driving devices 4 and 5 alternately turn on the semiconductor elements 2 and 3, after turning off one element to switch it to the off state, the other element can be turned on. The driving devices 4 and 5 reduce the turn-off loss and suppress the surge voltage by switching the change speed of the gate charge amount of the semiconductor elements 2 and 3 to be turned off, that is, by switching the change speed of the gate-source voltage (Vgs), which is the gate voltage, of the semiconductor elements 2 and 3 to be turned off during the turn-off period of the semiconductor elements 2 and 3 (in this embodiment, as an example, the period from the start to the completion of the turn-off execution).

[0044] [2. Details of the driving device 5]

[0045] Figure 2 Shows the details of the driving device 5. In addition, since the driving device 4 has the same structure as the driving device 5, the description thereof is omitted. In addition, in Figure 2 , only the structure related to the turn-off of the semiconductor element 3 in the structure of the driving device 5 is illustrated, and the illustration of the structure related to the turn-on is omitted.

[0046] The driving device 5 includes a measurement circuit 51, a determination circuit 52, an insulation signal transmitter 53, a timing generation circuit 54, a gate drive circuit 55, and a drive condition change circuit 56.

[0047] [2-1. Measurement circuit 51]

[0048] The measurement circuit 51 measures a parameter corresponding to the voltage applied to the semiconductor element 2 on the opposite arm side. Here, the parameter may represent the voltage itself applied to the semiconductor element 2. In this embodiment, as an example, it represents the drain-source voltage Vds(2) of the semiconductor element 2.

[0049] The measurement circuit 51 includes resistors 511 and 512. The resistors 511 and 512 divide the drain-source voltage Vds(2) of the semiconductor element 2. The resistors 511 and 512 are connected in parallel with the semiconductor element 2, and the determination circuit 52 is connected between the resistors 511 and 512.

[0050] [2-2. Determination circuit 52]

[0051] The determination circuit 52 is an example of a first determination circuit and determines whether the parameter satisfies the first condition. In addition, the determination circuit 52 is an example of a second determination circuit and determines whether the parameter satisfies the second condition. The determination circuit 52 can provide the determination result to the timing generation circuit 54 via the insulation signal transmitter 53.

[0052] The first condition may be a switching condition for the rate of change of the gate voltage. For example, the first condition may be that the voltage Vds(2) applied to the semiconductor element 2 on the opposite arm side is equal to or lower than a first reference voltage.

[0053] Here, during the off period of the semiconductor element 3, the drain-source voltage Vds(3) of the semiconductor element 3 rises to the DC voltage Ed between the positive power supply line 101 and the negative power supply line 102, so that the drain-source voltage Vds(2) of the semiconductor element 2 on the opposite arm side decreases accordingly and finally becomes zero. However, since the wiring inductance 1011 of the positive power supply line 101 obstructs the discharge of the parasitic capacitance of the semiconductor element 2 on the opposite arm side at this time, even when the voltage Vds(3) of the semiconductor element 3 reaches the DC voltage Ed, the voltage Vds(3) of the semiconductor element 2 does not become zero. The first reference voltage is set so that even in this case, by appropriately setting the change timing of the driving conditions of the semiconductor element 3, the reduction of both the turn-off loss and the surge voltage can be achieved.

[0054] The first reference voltage may be a voltage smaller than the voltage Vds(2), and the voltage Vds(2) is the voltage applied to the semiconductor element 2 on the opposite arm side at the time when the drain-source voltage Vds(3) of the off semiconductor element 3 reaches a voltage equal to or higher than the DC voltage Ed between the positive power supply line 101 and the negative power supply line 102. For example, the first reference voltage may be the drain-source voltage Vds(2) when the drain current of the semiconductor element 2 on the opposite arm side starts to commutate to the parasitic diode or the anti-parallel diode. Thus, during the off period of the semiconductor element 3 to be switched, according to the timing when the voltage Vds(2) applied to the semiconductor element 2 on the opposite arm side decreases and changes to be equal to or lower than the first reference voltage, it is determined that the parameter satisfies the first condition. In the present embodiment, as an example, the first reference voltage is 0V, or 0V after removing the error. From the perspective of the semiconductor element 3 to be turned off, the first reference voltage becomes a value equal to or higher than the DC voltage Ed.

[0055] The second condition may be a condition for protecting the element from short circuit. For example, the second condition may be that the voltage applied to the semiconductor element 2 on the opposite arm side is equal to or lower than a second reference voltage.

[0056] The second reference voltage may be a voltage smaller than the voltage applied to the semiconductor element 2 during the period when the semiconductor element 3 to be switched is in the on state, that is, during the period when the semiconductor element 2 on the opposite arm side is in the off state. In this case, the parameter satisfying the second condition when the semiconductor element 3 is on means that the semiconductor element 2 on the opposite arm side is not in the off state, and thus a short circuit will occur. The second reference voltage may be smaller than the voltage between the positive power supply line 101 and the negative power supply line 102 (in this embodiment, as an example, it is assumed to be the voltage Ed). In this embodiment, as an example, the second reference voltage is 0V, or 0V after removing the error. That is, in this embodiment, as an example, the second reference voltage is equal to the first reference voltage. In other words, the second condition becomes the same condition as the first condition.

[0057] 〔2-3. Insulation signal transmitter 53〕

[0058] The insulation signal transmitter 53 is provided between the determination circuit 52 and the timing generation circuit 54. The insulation signal transmitter 53 can convert the signal voltage from the determination circuit 52 and provide it to the timing generation circuit 54.

[0059] 〔2-4. Timing generation circuit 54〕

[0060] The timing generation circuit 54 generates a timing signal that determines the control timing of the semiconductor element 3. The timing generation circuit 54 includes a first timing signal generation circuit 541, a short-circuit monitoring circuit 540, and a second timing signal generation circuit 542.

[0061] When the parameter satisfies the first condition during the off period of the semiconductor element 3 to be switched, the first timing signal generation circuit 541 generates a first timing signal. The first timing signal generation circuit 541 can generate the first timing signal according to the situation that the determination circuit 52 determines that the parameter satisfies the first condition during the off period of the semiconductor element 3. The first timing signal generation circuit 541 can detect the start of the off period by receiving an off signal for turning off the semiconductor element 3 from the gate drive circuit 55. The first timing signal may be a pulse signal having a first pulse width determined in advance. The first timing signal generation circuit 541 can provide the first timing signal to the drive condition change circuit 56.

[0062] The short-circuit monitoring circuit 540 monitors whether there is a short circuit between the positive power supply line 101 and the negative power supply line 102. For example, the short-circuit monitoring circuit 540 can detect the occurrence of a short circuit according to the situation that the determination circuit 52 determines that the parameter satisfies the second condition during the on period of the semiconductor element 3 to be switched.

[0063] The short-circuit monitoring circuit 540 can monitor the presence or absence of a short circuit after a reference time (also referred to as a shielding period) has elapsed since the start of conduction of the semiconductor element 3. The short-circuit monitoring circuit 540 can detect the start of conduction of the semiconductor element 3 and the conduction period of the semiconductor element 3 by receiving a conduction command signal that makes the semiconductor element 3 conductive from the gate drive circuit 55. The shielding period can be longer than the time until the current flowing through the semiconductor element 3 (the drain current Id in this embodiment as an example) reaches a peak since the start of conduction of the semiconductor element 3. The short-circuit monitoring circuit 540 can provide a monitoring signal indicating the presence or absence of a short circuit to the second timing signal generation circuit 542 and the gate drive circuit 55.

[0064] The second timing signal generation circuit 542 generates a second timing signal when the period parameter of the semiconductor element 3 to be switched on satisfies the second condition. The second timing signal generation circuit 542 can generate the second timing signal based on the monitoring signal from the short-circuit monitoring circuit 540. The second timing signal can be a pulse signal with a second pulse width that is predetermined and larger than the first pulse width. The second pulse width can be larger than the time width from the start to the end of the disconnection of the semiconductor element 3. The second timing signal generation circuit 542 can provide the second timing signal to the drive condition change circuit 56.

[0065] [2-5. Gate drive circuit 55]

[0066] The gate drive circuit 55 drives the gate of the semiconductor element 3 to be switched on based on the input signal. For example, the gate drive circuit 55 can turn off the semiconductor element 3 when an input signal (also referred to as a turn-off command signal) for turning off the semiconductor element 3 is input. In addition, the gate drive circuit 55 can also turn on the semiconductor element 2 when an input signal (also referred to as a turn-on command signal) for turning on the semiconductor element 3 is input. The gate drive circuit 55 includes an IF circuit 551 and an OR gate 552.

[0067] The IF circuit 551 receives an input signal for the semiconductor element 3 from outside the driving device 5. Depending on the conduction command signal of the received input signal, the IF circuit 551 can supply a conduction signal for turning on the semiconductor element 3 to the gate of the semiconductor element 3 via the driving condition changing circuit 56. The IF circuit 551 can directly supply the conduction command signal included in the input signal to the short-circuit monitoring circuit 540 of the timing generation circuit 54. Depending on the disconnection command signal of the received input signal, the IF circuit 551 can supply a disconnection signal for turning off the semiconductor element 3 to the gate of the semiconductor element 3 via the driving condition changing circuit 56 and supply it to the first timing signal generation circuit 541 of the timing generation circuit 54. The disconnection signal can be supplied to the semiconductor element 3 in the conduction state, and by charging the gate input capacitance Cgs(3) of the semiconductor element 3 in the reverse bias direction (-Vgs), the semiconductor element 3 is switched from the conduction state to the cut-off state.

[0068] The OR gate 552 is provided on the path of the disconnection signal between the IF circuit 551 and the driving condition changing circuit 56. The OR gate 552 supplies, as the disconnection signal for the semiconductor element 3, a signal obtained by taking the logical sum of the disconnection signal from the IF circuit 551 and the monitoring signal indicating a short circuit from the short-circuit monitoring circuit 540 to the driving condition changing circuit 56. Thus, in addition to receiving an input signal for turning off the semiconductor element 2, the gate drive circuit 55 turns off the semiconductor element 3 when the parameters satisfy the second condition during the conduction of the semiconductor element 3. Here, as described above, the short-circuit monitoring circuit 540 monitors the presence or absence of a short circuit after the shielding period has elapsed since the start of conduction of the semiconductor element 3. Therefore, the gate drive circuit 55 turns off the semiconductor element 3 when the parameters satisfy the second condition after the shielding period has elapsed since the start of conduction of the semiconductor element 3.

[0069] 〔2-6. Driving Condition Changing Circuit 56〕

[0070] The driving condition changing circuit 56 changes the conditions for driving the gate of the semiconductor element 3. The driving condition changing circuit 56 can set the changing speed of the gate voltage of the semiconductor element 3 to a speed lower than the first speed during the off period of the semiconductor element 3 according to the first timing signal from the first timing signal generating circuit 541. In the present embodiment, as an example, it can be set to a second speed lower than the first speed. In addition, the driving condition changing circuit 56 can set the changing speed of the gate voltage to a low speed lower than the first speed during the off period of the semiconductor element 3 according to the second timing signal from the second timing signal generating circuit 542. In the present embodiment, as an example, it can be set to a second speed lower than the first speed. The driving condition changing circuit 56 can reduce the changing speed of the gate voltage by reducing the injection speed of the charge injected into the gate. In addition, the first speed is an example of a reference speed. In addition, in the present embodiment, as an example, the changing speed of the gate voltage set according to the first timing signal and the changing speed of the gate voltage set according to the second timing signal are set to the same second speed, but these two changing speeds can be different.

[0071] The driving condition changing circuit 56 includes an OR gate 561, a gate resistor 562, and a switch 563.

[0072] The OR gate 561 supplies a signal obtained by taking the logical sum of the first timing signal from the first timing signal generating circuit 541 and the second timing signal from the second timing signal generating circuit 542 to the switch 563.

[0073] The gate resistor 562 has two resistors 5621 and 5622 with different resistance values. The resistor 5621 has a resistance value such that the changing speed of the gate voltage of the semiconductor element 3 during the off period becomes the first speed. Similarly, the resistor 5622 has a resistance value such that the changing speed of the gate voltage of the semiconductor element 3 during the off period becomes the second speed. One ends of the resistors 5621 and 5622 are connected to the gate via the switch 563 respectively, and the other ends are connected to the gate driving circuit 55. In addition, the gate resistor 562 can have other structures as long as it can change the changing speed of the gate voltage of the semiconductor element 3.

[0074] The switch 563 switches the resistance value of the gate resistor 562. The switch 563 can connect either one of the resistors 5621 and 5622 to the gate of the semiconductor element 3. Thus, the changing speed of the gate voltage is switched between the first speed and the second speed.

[0075] The switch 563 can connect one of the resistors 5621 and 5622 to the gate of the semiconductor element 3 according to the signal from the OR gate 561. In the present embodiment, as an example, the switch 563 can connect the resistor 5622 to the gate during the period of generating the first pulse signal starting from when the first timing signal received as a pulse signal is received and during the period of generating the second pulse signal starting from when the second timing signal received as a pulse signal is received, and connect the resistor 5621 to the gate during other periods. Thus, the drive condition change circuit 56 reduces the change speed of the gate voltage during the period of generating the first timing signal starting from when the first timing signal is received and during the period of generating the second timing signal starting from when the second timing signal is received.

[0076] According to the above-described switching device 1, during the OFF period of the semiconductor element 3 that is the switching object, when the parameter satisfies the first condition, that is, when the voltage Vds(2) applied to the semiconductor element 2 on the opposite arm side decreases and changes below the first reference voltage (for example, 0 V), the first timing signal is generated, and based on this signal, the change speed of the gate voltage of the semiconductor element 3 is reduced from the first speed to the second speed. That is, the change speed of the gate voltage of the semiconductor element 3 that is the switching object is increased until the voltage Vds(2) of the semiconductor element 2 on the opposite arm side becomes the first reference voltage, and when it becomes below the first reference voltage, the change speed is decreased. Therefore, compared with the case where the change speed of the gate voltage is decreased at the time point when the voltage Vds(2) applied to the semiconductor element 2 on the opposite arm side is greater than the first reference voltage, the turn-off loss can be reduced by shortening the turn-off period. In addition, if the voltage Vds(2) of the semiconductor element 2 on the opposite arm side becomes below the reference voltage, the change speed of the gate charge is reduced, so the surge voltage can be reduced.

[0077] In addition, since the semiconductor element 3 is also turned off when the parameter satisfies the second condition during the period when the semiconductor element 3 is conducting, the parameter for changing the change speed of the gate voltage of the semiconductor element 3 can be used to detect a short circuit between the positive power supply line 101 and the negative power supply line 102, thereby turning off the semiconductor element 3. Therefore, compared with the case of separately providing a structure for short-circuit detection, the device can be miniaturized and an increase in manufacturing cost can be suppressed.

[0078] Further, since it is determined whether the parameter satisfies the second condition after the shielding period has elapsed since the start of conduction of the semiconductor element 3, when it is normal that the parameter satisfies the second condition during the shielding period since the start of conduction, unnecessary turning off of the semiconductor element 3 can be prevented.

[0079] In addition, since the second timing signal generated when the parameter satisfies the second condition during the conduction of the semiconductor element 3 causes the change speed of the gate voltage to be a second speed lower than the first speed during the off period of the semiconductor element 3, the surge voltage caused by the disconnection when a short circuit is detected can be reduced.

[0080] In addition, during the period when the first timing signal with the first pulse width is generated, the change speed of the gate voltage is reduced to the second speed. Therefore, after the generation of the first timing signal ends, the change speed of the gate voltage returns to the first speed. Thus, when the semiconductor element 3 is turned off according to the input signal, reducing the change speed of the gate voltage to the second speed during the period when the surge voltage reaches its peak can reduce the surge voltage. In addition, when the first pulse width is smaller than the time width from the start to the end of the turn-off of the semiconductor element 3, since the change speed of the gate voltage returns to the first speed after the generation of the first timing signal ends, the turn-off can be completed earlier, thereby reducing the switching loss.

[0081] In addition, according to the situation where the parameter satisfies the second condition during the conduction of the semiconductor element 3, a second timing signal with the second pulse width is generated. During the generation of this second timing signal, the change speed of the gate voltage of the semiconductor element 3 is reduced. Therefore, after the generation of the second timing signal ends, the change speed of the gate voltage returns to the first speed. Additionally, since the second pulse width is larger than the first pulse width, the change speed of the gate voltage remains at the second speed for a longer period compared to the case where the second pulse width is less than or equal to the first pulse width. Thus, when the semiconductor element 3 is turned off based on the detection of a short circuit, the change speed of the gate voltage can be reliably reduced to the second speed during the period when the surge voltage reaches its peak.

[0082] In addition, since the second pulse width is larger than the time width from the start to the end of the turn-off of the semiconductor element 3, the surge voltage caused by the disconnection when a short circuit is detected can be more reliably reduced.

[0083] In addition, the determination circuit 52 determines whether the parameter satisfies the first condition during the off period of the semiconductor element 3 and generates the first timing signal according to the determination result. Therefore, different from the case of generating the first timing signal according to a predetermined time from the start of the turn-off until the parameter satisfies the first condition, the first timing signal can be generated according to the situation where the parameter truly satisfies the first condition. Thus, during the period when the surge voltage caused by the turn-off of the semiconductor element 3 reaches its peak, the change speed of the gate voltage can be reliably reduced, thereby reducing the surge voltage.

[0084] In addition, since the first reference voltage and the second reference voltage used by the determination circuit 52 are 0V, it is possible to reliably detect the switching timing of the change rate of the gate voltage during the OFF period and the occurrence of a short circuit.

[0085] Furthermore, since the second reference voltage is less than the voltage between the positive power supply line 101 and the negative power supply line 102, when the semiconductor element 3 is turned on, the voltage applied to the semiconductor element 2 on the opposite arm side being below the second reference voltage means that the semiconductor element 2 is not in the cut-off state. Therefore, it is possible to reliably detect a short circuit.

[0086] In addition, since the circuit for determining whether the determination parameter satisfies the first condition and the circuit for determining whether the determination parameter satisfies the second condition are the same determination circuit 52, it is possible to use a single determination circuit 52 to detect the switching timing of the change rate of the gate voltage during the OFF period and the occurrence of a short circuit.

[0087] 〔3. Operating waveforms〕

[0088] Figure 3 Shows the operating waveforms of the switching device 1. In addition, the horizontal axis in the figure represents time, and the vertical axis represents the input signal to the drive device 5, the gate-source voltage Vgs(3) of the semiconductor element 3 to be switched, the gate current Ig(3), the drain-source voltage Vds(3), the drain current Id(3), the monitoring signal from the short-circuit monitoring circuit 540, the timing signal from the timing generation circuit 54, the drain-source voltage Vds(2) of the semiconductor element 2 on the opposite arm side, and the drain current Id(2) (the current flowing through the freewheeling diode), etc. In addition, "Ed" in the figure represents the DC voltage between the positive power supply line 101 and the negative power supply line 102.

[0089] First, at time point t11, if an input signal (turn-on command signal) that turns the semiconductor element 3 on is input to the drive device 5, the shielding period of the short-circuit monitoring by the short-circuit monitoring circuit 540 starts. In addition, a turn-on signal is output from the gate drive circuit 55, and a positive gate current Ig(3) starts to flow through the gate of the semiconductor element 3. In addition, the gate-source voltage Vgs(3) of the semiconductor element 3 starts to increase.

[0090] Next, at time point t13, if the gate-source voltage Vgs(3) of the conductor element 3 exceeds the threshold value Vth, the drain-source voltage Vds(3) of the conductor element 3 starts to decrease, and the drain current Id(3) starts to increase. In addition, the current Id(2) (FWD) flowing through the freewheeling diode of the semiconductor element 2 on the opposite arm side starts to decrease. Next, at time point t15, the drain-source voltage Vds(2) starts to increase from 0V.

[0091] At time point t17, if the shielding period ends, the short-circuit monitoring period of the short-circuit monitoring circuit 540 starts and continues until the falling edge timing of the turn-on command signal, i.e., time point t31. In this operation example, the drain-source voltage Vds(2) of the semiconductor element 2 on the opposite arm side does not become below 0V, and since the parameters do not satisfy the second condition during the monitoring period, the occurrence of a short circuit is not detected.

[0092] Next, at time point t31, if an input signal (turn-off command signal) that makes the semiconductor element 3 in the off state is input to the drive device 5, a disconnection signal is output from the gate drive circuit 55, and a negative gate current Ig(3) starts to flow through the semiconductor element 3. Thereby, gate charge starts to be injected into the semiconductor element 3 in the reverse bias direction. Then, during the period from time point t31 to t32, the gate input capacitance Cgs(3) of the semiconductor element 3 is charged in the reverse bias direction, and the gate-source voltage Vgs(3) decreases.

[0093] Next, at time point t32, if the gate-source voltage Vgs(3) decreases to the mirror voltage, most of the gate charge is used to charge the feedback capacitance (gate-drain capacitance) Cgd(3), the change in the gate-source voltage Vgs(3) becomes flat (so-called mirror period), and the drain-source voltage Vds(3) of the semiconductor element 3 increases.

[0094] Subsequently, in the semiconductor element 2 on the opposite arm side, the drain-source voltage Vds(2) decreases, and a discharge current flows out from the parasitic capacitance Cds(2). Therefore, the drain current Id(3) of the semiconductor element 3 decreases, and a voltage VL corresponding to this current change amount is applied to the wiring inductance 1021 of the negative power supply line 102.

[0095] Next, at time point t33, if the drain-source voltage Vds(2) of the semiconductor element 2 on the opposite arm side becomes zero (refer to the lower dotted box in the figure), the first timing signal generation circuit 541 generates a first timing signal having a first pulse width. Accordingly, the drive condition change circuit 56 corrects the disconnection signal during the period from when the first timing signal is received until the first timing signal is generated, and reduces the change speed of the gate voltage of the semiconductor element 3 (refer to the upper dotted box in the figure). For example, the gate current Ig(3) is controlled to be a negative constant value closer to zero. In addition, in the present embodiment, as an example, the period during which the first timing signal is generated may be the period from time point t33 to t35, and time point t35 may be before a later-described time point t37 at which the disconnection of the semiconductor element 3 ends.

[0096] Here, at time point t33, the voltage Vds(2) between the drain and source in the semiconductor element 2 on the opposite arm side is zero, and in the semiconductor element 2 that is the switching target, the mirror period ends. Therefore, in the semiconductor element 3, the gate-source voltage Vgs(3) starts to decrease again, and at the same time, the drain current Id(3) decreases sharply and becomes zero at time point t37.

[0097] If the voltage Vds(2) between the drain and source in the semiconductor element 2 on the opposite arm side becomes zero, the load current IL commutates to the parasitic diode of the semiconductor element 2. At the same time, in the semiconductor element 3 that is the switching target, the mirror period ends, and the leakage current Id(3) decreases sharply. As a result, the voltage VL across the wiring inductance 1021 of the negative-side power supply line 102 increases instantaneously, and the drain-source voltage Vds(3) of the semiconductor element 3 increases to the peak voltage Vp. Additionally, in this operation example, during the period from time point t33 to t35, the peak voltage Vp reduces the rate of change of the gate voltage. After that, the drain-source voltage Vds(3) becomes the DC voltage Ed at time point t37.

[0098] Then, during the period after time point t37, the charging of the gate input capacitance Cgs(3) of the semiconductor element 3 ends, and the disconnection is completed.

[0099] Figure 4 Other operation waveforms of the switching device 1 are shown. Additionally, in this operation example, the semiconductor element 2 on the opposite arm side becomes conductive due to a fault.

[0100] First, during the period from time point t11 to t13, operations are performed to obtain the same operation waveforms as Figure 3 In this operation example, since the semiconductor element 2 on the opposite arm side becomes conductive due to a fault, the voltage Vds(2) between the drain and source does not start to increase at time point t15 but remains at 0V.

[0101] Next, at time point t17, if the shielding period ends, the short-circuit monitoring period of the short-circuit monitoring circuit 540 starts and continues until the falling edge timing of the conduction command signal, i.e., time point t31. In this operation example, the voltage Vds(2) between the drain and source of the semiconductor element 2 on the opposite arm side becomes below 0V, and the parameters satisfy the second condition during the monitoring period.

[0102] Therefore, at time point t19, the occurrence of a short circuit is detected, the monitoring signal becomes high level, at time point t23, a disconnection signal is output from the gate drive circuit 55, and a negative gate current Ig(3) starts to flow through the semiconductor element 3. The disconnection of the semiconductor element 3 ends at time point t27. As a result, the short-circuit state is eliminated.

[0103] In addition, at time point t21, the second timing signal generation circuit 542 generates a second timing signal having a second pulse width. Accordingly, the drive condition change circuit 56 corrects the turn-off signal output from the gate drive circuit 55 during the period from when the second timing signal is received until the second timing signal is generated, and reduces the change speed of the gate voltage of the semiconductor element 3. Further, in this operation example, during the period after time point t21, the peak voltage Vp reduces the amount of the change speed of the gate voltage. Further, in the present embodiment, as an example, the period during which the second timing signal is generated may be the period from time point t21 to t29, and time point t29 may be after a time point t27 (to be described later) at which the turn-off of the semiconductor element 3 ends. The second timing signal may not fall after rising at time point t21.

[0104] Further, time points t19, t21, and t23 may be the same as time point t17. Further, time point t23 may be before time point t21.

[0105] 〔4. Modification Example〕

[0106] Further, in the above-described embodiment, the first reference voltage for generating the first timing signal has been described as being the drain-source voltage Vds(2) of the semiconductor element 2 on the relative arm side when the drain-source voltage Vds(3) of the semiconductor element 3 reaches a direct current voltage Ed or more, but it may be set to other voltages. For example, the first reference voltage may be the drain-source voltage Vds(2) of the semiconductor element 2 on the relative arm side when the drain current Id(2) starts commutation to the parasitic diode.

[0107] In addition, although the parameter corresponding to the voltage applied to the semiconductor element 2 on the relative arm side has been described as the drain-source voltage Vds(2) of the semiconductor element 2, it may be the voltage applied to the semiconductor element 3 to be switched (set as the drain-source voltage Vds(3) as an example). In this case, the second condition used in the determination circuit 52 may be that the drain-source voltage Vds(3) is equal to or higher than a fourth reference voltage, and the fourth reference voltage may be greater than 0V. Thus, when the parameter satisfies the second condition when the semiconductor element 3 is turned on, it means that the semiconductor element 2 on the relative arm side is not in the cut-off state, and thus a short circuit can be reliably detected. In addition, the first condition may be that the drain-source voltage Vds(3) is equal to or higher than a third reference voltage, the second condition may be that the drain-source voltage Vds(3) is equal to or higher than a fourth reference voltage, and the third reference voltage and the fourth reference voltage may be equal to or higher than the direct current voltage Ed. Thus, the switching timing of the change speed of the gate voltage during the turn-off period and the occurrence of a short circuit can be reliably detected.

[0108] In addition, although the first condition and the second condition are described as the same condition, they can also be different conditions. As an example, one of the first reference voltage and the second reference voltage can be 0V, and the other can be non-0V. When the first condition and the second condition are different, the driving device 5 can also determine whether the parameter satisfies the first condition and whether the parameter satisfies the second condition through different determination circuits. The determination circuit for determining whether the parameter satisfies the first condition can provide the determination result to the first timing signal generation circuit 541, and an insulation signal transmitter 53 can be provided between the determination circuit and the first timing signal generation circuit 541. The determination circuit for determining whether the parameter satisfies the second condition can provide the determination result to the short-circuit monitoring circuit 540, and an insulation signal transmitter 53 can be provided between the determination circuit and the short-circuit monitoring circuit.

[0109] In addition, the case where the switching device 1 is provided with the driving device 4 for driving the semiconductor element 2 and the driving device 5 for driving the semiconductor element 3 is described, but the two can also be integrated to have a single driving device for separately driving the semiconductor elements 2 and 3. In this case, the single driving device can use either the drain-source voltage Vds(2) of the semiconductor element 2 or the drain-source voltage Vds(3) of the semiconductor element 3 as a parameter. Thereby, one of the measurement circuit for measuring the voltage Vds(2) and the measurement circuit for measuring the voltage Vds(3) can be omitted.

[0110] Furthermore, although the case where the driving condition change circuit 56 changes the change speed of the gate voltage by changing the resistance value of the gate resistor 562 is described, the change speed can also be changed by other methods. For example, the driving condition change circuit 56 can reduce the current of the turn-off signal or stop the turn-off signal. To reduce the current of the turn-off signal, for example, the internal path of the turn-off signal toward the gate can be branched to shunt the current.

[0111] The present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made based on the above embodiments. According to the scope of the patent claims, the embodiments with the above various changes or improvements are also included in the technical scope of the present invention.

[0112] It should be noted that for the scope of the patent claims, the devices, systems, programs, and the actions, sequences, steps, and stages of the methods shown in the specification and drawings, as long as there is no specific record of "before...", "prior to...", etc., and the output of the previous process is not used in the subsequent process, they can be implemented in any order. Regarding the action flow in the scope of the patent claims, the specification, and the drawings, even if "first", "next", etc. are used for simplicity in the description, it does not mean that it must be implemented in that order.

[0113] Reference numeral description

[0114] 1 Switch device, 2 Semiconductor element, 3 Semiconductor element, 4 Driving device, 5 Driving device, 51 Measurement circuit, 52 Judgment circuit, 53 Insulation signal transmitter, 54 Timing generation circuit, 55 Gate driving circuit, 56 Driving condition change circuit, 101 Positive side power supply line, 102 Negative side power supply line, 105 Power output terminal, 511 Resistor, 540 Short - circuit monitoring circuit, 541 First timing signal generation circuit, 542 Second timing signal generation circuit, 551 IF circuit, 552 OR gate, 561 OR gate, 562 Gate resistor, 563 Switch, 1011 Wiring inductance, 1021 Wiring inductance, 5621 Resistor, 5622 Resistor.

Claims

1. A driving device, characterized in that, Comprising: A gate drive circuit which, when a signal for turning off the first semiconductor element among a first semiconductor element and a second semiconductor element connected in series between a positive power supply line and a negative power supply line is input, turns off the first semiconductor element; A measurement circuit which measures a parameter corresponding to the voltage applied to the second semiconductor element; A timing generation circuit which generates a first timing signal when the parameter satisfies a first condition during the off period of the first semiconductor element; And A drive condition change circuit which, according to the first timing signal, sets the change speed of the gate voltage of the first semiconductor element to a speed lower than a reference speed during the off period of the first semiconductor element, The gate drive circuit also turns off the first semiconductor element according to the situation where the parameter satisfies a second condition during the on period of the first semiconductor element.

2. The drive device according to claim 1, characterized in that The gate drive circuit turns off the first semiconductor element according to the situation where the parameter satisfies the second condition after a reference time has elapsed since the start of conduction of the first semiconductor element.

3. The drive device according to claim 1 or 2, characterized in that The timing generation circuit generates a second timing signal when the parameter satisfies the second condition during the on period of the first semiconductor element, The drive condition change circuit, according to the second timing signal, sets the change speed of the gate voltage to a speed lower than the reference speed during the off period of the first semiconductor element.

4. The drive device according to claim 3, characterized in that The timing generation circuit generates the first timing signal with a first pulse width determined in advance, The drive condition change circuit reduces the change speed of the gate voltage during the period from receiving the first timing signal to generating the first timing signal.

5. The drive device according to claim 4, characterized in that The timing generation circuit generates the second timing signal with a second pulse width determined in advance and larger than the first pulse width, The drive condition change circuit reduces the change speed of the gate voltage during the period from receiving the second timing signal to generating the second timing signal.

6. The drive device according to claim 5, characterized in that The second pulse width is larger than the time width from the start to the completion of the off of the first semiconductor element.

7. The drive device according to claim 1 or 2, characterized in that, Further comprising: A first determination circuit which determines whether the parameter satisfies the first condition; And A second determination circuit which determines whether the parameter satisfies the second condition.

8. The drive device according to claim 7, characterized in that The first condition and the second condition are the same condition, The first determination circuit and the second determination circuit are the same circuit.

9. The drive device according to claim 1 or 2, characterized in that The parameter represents the voltage applied to the second semiconductor element.

10. The drive device according to claim 9, characterized in that the second condition is that the voltage applied to the second semiconductor element is below a second reference voltage, and the second reference voltage is less than the voltage between the positive power supply line and the negative power supply line.

11. The drive device according to claim 9, characterized in that the first condition is that the voltage applied to the second semiconductor element is below a first reference voltage, the second condition is that the voltage applied to the second semiconductor element is below a second reference voltage, and at least one of the first reference voltage and the second reference voltage is 0V.

12. The drive device according to claim 10, characterized in that the first condition is that the voltage applied to the second semiconductor element is below a first reference voltage, the second condition is that the voltage applied to the second semiconductor element is below a second reference voltage, and at least one of the first reference voltage and the second reference voltage is 0V.

13. The drive device according to claim 1 or 2, characterized in that the parameter represents the voltage applied to the first semiconductor element.

14. The drive device according to claim 13, characterized in that the second condition is that the voltage applied to the first semiconductor element is above a fourth reference voltage, and the fourth reference voltage is greater than 0V.

15. The drive device according to claim 13, characterized in that the first condition is that the voltage applied to the first semiconductor element is above a third reference voltage, the second condition is that the voltage applied to the first semiconductor element is above a fourth reference voltage, and at least one of the third reference voltage and the fourth reference voltage is above the voltage between the positive power supply line and the negative power supply line.

16. The drive device according to claim 14, characterized in that the first condition is that the voltage applied to the first semiconductor element is above a third reference voltage, the second condition is that the voltage applied to the first semiconductor element is above a fourth reference voltage, and at least one of the third reference voltage and the fourth reference voltage is above the voltage between the positive power supply line and the negative power supply line.

17. A switching device, characterized in that, Comprising: two semiconductor elements connected in series between a positive power supply line and a negative power supply line; the drive device according to any one of claims 1 to 16 for driving the gate of one of the two semiconductor elements; and the drive device according to any one of claims 1 to 16 for driving the gate of the other of the two semiconductor elements.

18. The switching device according to claim 17, characterized in that the two semiconductor elements are wide-bandgap semiconductor elements.

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