Semiconductor memory device

Abstract

A semiconductor memory device is provided, including: a third insulating pattern and a first insulating pattern located on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction perpendicular to the substrate, such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other; a gate electrode located between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern; and a second insulating pattern protruding a second width from the first side of the gate electrode in a second direction, the second direction being different from the first direction.

Description

[0001] Korean Patent Application No. 10-2019-0069847 entitled "Semiconductor memory device and method for manufacturing semiconductor memory device" filed in the Korean Intellectual Property Office on June 13, 2019 is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments relate to a semiconductor memory device and a method for manufacturing the same. BACKGROUND

[0003] To meet the demand for excellent performance and low cost, the degree of integration of nonvolatile memory devices has been increasing. However, in the case of two-dimensional or planar memory devices, since their integration density is determined by the area occupied by a unit memory cell, it has become increasingly difficult to increase the integration density. Accordingly, in recent years, three-dimensional memory devices in which unit memory cells are arranged vertically have been developed to increase the integration density without increasing the occupied area. SUMMARY

[0004] Embodiments relate to a semiconductor memory device including a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern protruding a second width from the first side of the gate electrode in a second direction different from the first direction.

[0005] Embodiments also relate to a semiconductor memory device including a semiconductor pattern on a substrate and extending in a first direction perpendicular to the substrate, a tunnel insulating film on the semiconductor pattern, a first charge storage film and a second charge storage film on the tunnel insulating film and spaced apart from each other in the first direction, a blocking insulating film extending on the tunnel insulating film along the first charge storage film and the second charge storage film, a recess between the first charge storage film and the second charge storage film and defined within the blocking insulating film, an insulating pattern filling the recess, and a gate electrode on the insulating pattern and the blocking insulating film.

[0006] The embodiments also relate to a semiconductor memory device, the semiconductor memory device comprising: a barrier insulating film extending in a first direction perpendicular to a substrate; a first recess and a second recess defined within a surface of the barrier insulating film and spaced apart from each other in the first direction; a third recess defined within an opposing surface facing the one surface of the barrier insulating film and located between the first recess and the second recess; a first charge storage film filling the first recess; a second charge storage film filling the second recess; an insulating pattern filling the third recess; and a gate electrode extending along the insulating pattern and the barrier insulating film. Attached Figure Description

[0007] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0008] Figure 1 A schematic circuit diagram is shown for describing a semiconductor memory device according to an example embodiment.

[0009] Figure 2 A cross-sectional view of a semiconductor memory device according to an example embodiment is shown.

[0010] Figure 3 An example embodiment is shown. Figure 2 An enlarged view of region P1 of the semiconductor memory device.

[0011] Figure 4 It shows Figure 3 A magnified view of region R1.

[0012] Figure 5 It shows along Figure 3 The sectional view taken by line A-A' in the middle.

[0013] Figure 6 It shows along Figure 3 The sectional view taken by line B-B' in the figure.

[0014] Figures 7 to 17 An illustration shows a method for manufacturing according to an example embodiment. Figure 2 A view of intermediate processes in a method for developing a semiconductor memory device.

[0015] Figure 18 This is an example cross-sectional view of a semiconductor memory device according to another example embodiment.

[0016] Figure 19 An example embodiment is shown. Figure 18 An enlarged view of region P2 of the semiconductor memory device.

[0017] Figure 20 It shows Figure 19A magnified view of region R2.

[0018] Figures 21 to 24 An illustration shows a method for manufacturing according to an example embodiment. Figure 18 A view of intermediate processes in a method for developing a semiconductor memory device. Detailed Implementation

[0019] Figure 1 This is a schematic circuit diagram used to describe a semiconductor memory device according to an example embodiment.

[0020] Reference Figure 1 The semiconductor memory device according to the example embodiment may include multiple word lines WL0 to WLn, a common source line CSL, multiple bit lines BL1 to BL3, and multiple cell strings CSTR.

[0021] Word lines WL0 to WLn can be spaced apart from each other in the first direction Z. Bit lines BL1 to BL3 can be arranged in two dimensions. For example, bit lines BL1 to BL3 can be spaced apart from each other in the second direction Y and can extend in the third direction X. Cell strings CSTR can be connected in parallel to each of the bit lines BL1 to BL3. Cell strings CSTR can be connected together to the common source line CSL. Therefore, cell strings CSTR can be located between bit lines BL1 to BL3 and the common source line CSL.

[0022] In the example embodiment, multiple common source lines (CSLs) can be arranged in two dimensions. For example, the common source lines (CSLs) can extend in the second direction Y while being spaced apart from each other. The same voltage can be applied to the common source lines (CSLs), or different voltages can be applied to the common source lines (CSLs) to control them individually.

[0023] Each cell string CSTR may include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to each of the bit lines BL1 to BL3, and a plurality of memory cell transistors MCTs between the ground select transistor GST and the string select transistor SST. Each memory cell transistor MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistor MCT may be connected in series.

[0024] The common-source line CSL can be connected to the source of the ground-select transistor GST. The ground-select line GSL, multiple word lines WL0 to WLn, and the serial-select line SSL can be connected between the common-source line CSL and each of the bit lines BL1 to BL3. The ground-select line GSL can be used as the gate electrode of the ground-select transistor GST. The word lines WL0 to WLn can be used as the gate electrodes of the memory cell transistor MCT. The serial-select line SSL can be used as the gate electrode of the serial-select transistor SST.

[0025] Figure 2 This is a cross-sectional view of a semiconductor memory device according to an example embodiment.

[0026] Reference Figure 2 The diagram shows multiple gate electrodes GSL, WL0 to WLn, SSL, and 150. The gate electrodes GSL, WL0 to WLn, and SSL can have the same thickness or can have different thicknesses from each other.

[0027] For ease of explanation, bit lines BL1 to BL3 can be collectively referred to as bit lines BL and are shown as bit lines BL in the attached figures.

[0028] In an example embodiment, the plurality of gate electrodes GSL, WL0 to WLn, SSL, and 150 may include a ground select line GSL, word lines WL0 to WLn, and a serial select line SSL. The ground select line GSL, word lines WL0 to WLn, and serial select line SSL may be stacked sequentially on the substrate 100.

[0029] As an example, in Figure 2 Four word lines are shown between the ground select line (GSL) and the serial select line (SSL), but eight, sixteen, 32, sixty-four, or more word lines can be stacked between the ground select line (GSL) and the serial select line (SSL).

[0030] Each of the gate electrodes GSL, WL0 to WLn, SSL, and 150 may include a conductive material. For example, each of the gate electrodes GSL, WL0 to WLn, SSL, and 150 may include a metal such as tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon.

[0031] Each of the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 may include an insulating material. For example, each of the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 may include silicon oxide.

[0032] In an example embodiment, the gate electrodes GSL, WL0 to WLn, SSL and 150, and the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 can be separated by a word line cutting region WLC. For example, the word line cutting region WLC can extend in the second direction Y to cut the gate electrodes GSL, WL0 to WLn, SSL and 150, and the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166.

[0033] In an example embodiment, the separation structure 300 can be formed in the word line cutting region WLC. For example... Figure 2As shown, the separator structure 300 may extend through the gate electrodes GSL, WL0 to WLn, SSL and 150, and the first insulating pattern 162, the second insulating pattern 164 and the third insulating pattern 166 to the substrate 100. In an example embodiment, the separator structure 300 may include a plug pattern 302 and a spacer 304.

[0034] Plug pattern 302 may pass through gate electrodes GSL, WL0 to WLn, SSL and 150, and insulating patterns 162, 164 and 166 to connect to substrate 100. In an example embodiment, plug pattern 302 may be configured as a common source line of a semiconductor memory device according to an example embodiment (e.g., Figure 1 (CSL). For example, plug pattern 302 may include a conductive material. Plug pattern 302 may be connected to impurity region 105 in substrate 100. Impurity region 105 may extend, for example, in a second direction Y.

[0035] Spacer 304 may be disposed between plug pattern 302 and gate electrodes GSL, WL0 to WLn, SSL and 150, and first insulating pattern 162, second insulating pattern 164 and third insulating pattern 166. For example, spacer 304 may extend along a side surface of plug pattern 302. Spacer 304 may include insulating material. Therefore, spacer 304 may electrically isolate plug pattern 302 from gate electrodes GSL, WL0 to WLn, SSL and 150, and first insulating pattern 162, second insulating pattern 164 and third insulating pattern 166.

[0036] Multiple channel structures CS1 to CS3 may extend through gate electrodes GSL, WL0 to WLn, SSL, and 150, and insulating patterns 162, 164, and 166 to connect to substrate 100. Channel structures CS1 to CS3 may extend in a first direction Z intersecting gate electrodes GSL, WL0 to WLn, SSL, and 150, and the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166. For example, each of channel structures CS1 to CS3 may have a pillar shape extending in the first direction Z. Each of channel structures CS1 to CS3 may include a semiconductor pattern 106 and multiple charge storage films, such as a first charge storage film 110a and a second charge storage film 110b.

[0037] Semiconductor pattern 106 may extend through gate electrodes GSL, WL0 to WLn, SSL, and 150, and insulating patterns 162, 164, and 166, to connect to substrate 100. For example, semiconductor pattern 106 may extend in a first direction Z to connect to substrate 100. Semiconductor pattern 106 in Figure 2The semiconductor pattern 106 is shown as having a cup shape, but it can have various shapes, such as cylindrical, rectangular prism, and filled column shapes.

[0038] For example, semiconductor pattern 106 may include at least one of semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0039] The first charge storage film 110a and the second charge storage film 110b may be disposed between the semiconductor pattern 106 and the gate electrodes GSL, WL0 to WLn, SSL, and 150. The first charge storage film 110a and the second charge storage film 110b may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-dielectric-constant material having a dielectric constant higher than that of silicon oxide. The high-dielectric-constant material may include at least one of, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0040] In an example embodiment, a first charge storage film 110a and a second charge storage film 110b may be disposed between multiple films. For example, the first charge storage film 110a and the second charge storage film 110b may be located on a tunnel insulating film 104 stacked on a semiconductor pattern 106. A barrier insulating film 102 may be conformally formed on the tunnel insulating film 104 and the first charge storage film 110a and the second charge storage film 110b. The tunnel insulating film 104 may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)). The first charge storage film 110a and the second charge storage film 110b may include, for example, silicon nitride. The barrier insulating film 102 may include, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3), hafnium oxide (HfO2)).

[0041] Each of the channel structures CS1 to CS3 may further include a fill insulating pattern 108. The fill insulating pattern 108 may fill a cup-shaped semiconductor pattern 106. For example, the semiconductor pattern 106 may extend conformally along the side and bottom surfaces of the fill insulating pattern 108. The fill insulating pattern 108 may include, for example, silicon oxide.

[0042] In an example embodiment, each of the channel structures CS1 to CS3 may further include a channel pad 160. The channel pad 160 may be attached to the top of the barrier insulating film 102, the tunnel insulating film 104, the semiconductor pattern 106, and the filling insulating pattern 108. For example, the channel pad 160 may be formed within the first interlayer insulating film 210, or it may be formed such that the semiconductor pattern 106 extends along the side surface of the channel pad 160. The channel pad 160 may comprise, for example, polysilicon doped with impurities.

[0043] Bit lines BL1 to BL3 can be connected to channel structures CS1 to CS3. For example, each of the bit lines BL1 to BL3 can be connected to each of the channel structures CS1 to CS3 via bit line contact 320. Bit line contact 320 can, for example, pass through the second interlayer insulating film 310, so that each of the channel structures CS1 to CS3 is electrically connected to each of the bit lines BL1 to BL3.

[0044] In the case of region P1 used as a memory cell, one gate electrode 150 can control one memory cell. Therefore, since the first charge storage film 110a and the second charge storage film 110b are formed in one memory cell, charge is stored in the desired charge storage film. Structurally, this memory cell can be used as one memory cell, but it can operate as two memory cells, thereby increasing the cell integration density. That is, assuming the word line in region P1 is the third word line WL3, the effect that can be obtained from two memory cells can be achieved at the third word line WL3 using one gate electrode 150. The detailed effects, process, and operation will be described below.

[0045] Figure 3 According to the example embodiment Figure 2 An enlarged view of region P1 of the semiconductor memory device.

[0046] Reference Figure 3 The semiconductor memory device includes a first insulating pattern 162, a second insulating pattern 164, a third insulating pattern 166, a first channel structure CS1, a second channel structure CS2, a third channel structure CS3, and a gate electrode 150. The first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 can be collectively referred to as multiple insulating patterns 162, 164, and 166, and the first channel structure CS1, the second channel structure CS2, and the third channel structure CS3 can be collectively referred to as multiple channel structures CS1, CS2, and CS3.

[0047] The first insulating pattern 162, the gate electrode 150, and the third insulating pattern 166 may be stacked in a first direction Z perpendicular to the substrate. The second insulating pattern 164 may protrude from the gate electrode 150 in a third direction X parallel to the substrate 100. The first insulating pattern 162, the second insulating pattern 164, the third insulating pattern 166, and the gate electrode 150 may extend in the third direction X.

[0048] The first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 may include, for example, silicon oxide (such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetraethyl orthosilicate glass (TEOS), or high-density plasma-CVD (HDP-CVD)).

[0049] The slit region 190 can be formed in a semiconductor memory device according to an example embodiment. The slit region 190 can divide multiple stacked structures.

[0050] Although not shown, substrate 100 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In another embodiment, the substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0051] Although the first insulating pattern 162 and the third insulating pattern 166 are shown to have the same thickness, the first insulating pattern 162 and the third insulating pattern 166 may have different thicknesses from each other.

[0052] The gate electrode 150 may be located between the first insulating pattern 162 and the third insulating pattern 166, and may include a second insulating pattern 164 configured to protrude from the gate electrode 150 in a third direction X.

[0053] exist Figure 3 Only one of the multiple gate electrodes 150 is shown in the example. Therefore, multiple gate electrodes 150 can be provided. In the example embodiment, the lowermost gate electrode 150 can be set as... Figure 1 The ground selection line GSL. In the example embodiment, the uppermost gate electrode 150 can be set to Figure 1 The string selection line SSL. In an example embodiment, the gate electrode 150 located between the lowermost gate electrode 150 and the uppermost gate electrode 150 in the first direction Z can be set to Figure 1 The word lines WL0 to WLn are between the ground selection line GSL and the serial selection line SSL.

[0054] The gate electrode 150 may include a conductive material. The gate electrode 150 may include, for example, a metal (such as tungsten (W), cobalt (Co), nickel (Ni)) or a semiconductor material such as silicon.

[0055] The first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 may include insulating material. The first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 may include, for example, silicon oxide.

[0056] The channel structures CS1, CS2, and CS3 can extend in the first direction Z through the first insulating pattern 162, the second insulating pattern 164, the third insulating pattern 166, and the gate electrode 150. For example, the channel structures CS1, CS2, and CS3 can be formed in a pillar shape on the substrate 100 to pass through the first insulating pattern 162, the second insulating pattern 164, the third insulating pattern 166, and the gate electrode 150. Therefore, the gate electrode 150 can intersect with the channel structures CS1, CS2, and CS3.

[0057] Each of the channel structures CS1, CS2, and CS3 may include a semiconductor pattern 106. The semiconductor pattern 106 may extend through a first insulating pattern 162, a second insulating pattern 164, and a third insulating pattern 166, as well as a gate electrode 150, to connect to the substrate 100. For example, the semiconductor pattern 106 may extend in a first direction Z. The semiconductor pattern 106 may have, for example, a cup shape. For example, each of the channel structures CS1, CS2, and CS3 may include a columnar filled insulating pattern 108 and a semiconductor pattern 106 configured to conformally extend along the bottom surface and sidewalls of the filled insulating pattern 108. The filled insulating pattern 108 may include, for example, silicon oxide. In other example embodiments, the semiconductor pattern 106 may have various shapes, such as cylindrical, rectangular prism, and filled column shapes.

[0058] Semiconductor pattern 106 may include, for example, semiconductor materials, such as single-crystal silicon.

[0059] Each of the channel structures CS1, CS2, and CS3 may include a tunnel insulating film 104. The tunnel insulating film 104 may include, for example, silicon oxide or silicon oxynitride. In another embodiment, for example, the tunnel insulating film 104 may be configured as a bilayer comprising a silicon oxide film and a silicon oxynitride film, etc. For ease of explanation, the tunnel insulating film 104 will be described below as comprising silicon oxide.

[0060] Each of the channel structures CS1, CS2, and CS3 may include a first charge storage film 110a and a second charge storage film 110b. The first charge storage film 110a and the second charge storage film 110b may be collectively referred to as a plurality of charge storage films 110a and 110b.

[0061] The first charge storage film 110a and the second charge storage film 110b can be formed on the sidewalls of the tunnel insulating film 104. Therefore, the tunnel insulating film 104 can be formed between the semiconductor pattern 106 and the first charge storage film 110a and the second charge storage film 110b. Furthermore, each of the first charge storage film 110a and the second charge storage film 110b can extend in a second direction Y (e.g., the +Y direction).

[0062] The second insulating pattern 164 can be formed between the first charge storage film 110a and the second charge storage film 110b, and the second insulating pattern 164 can extend in the second direction Y while protruding from the gate electrode 150 in the third direction X.

[0063] The first charge storage film 110a and the second charge storage film 110b may include at least one of, for example, silicon nitride, silicon oxynitride, silicon-rich nitride (Si-rich nitride), and nanocrystalline silicon (nanocrystalline Si). For ease of explanation, the first charge storage film 110a and the second charge storage film 110b will be described below as including silicon nitride.

[0064] Each of the channel structures CS1, CS2, and CS3 may include a barrier insulating film 102. The barrier insulating film 102 may extend along the first charge storage film 110a, the second charge storage film 110b, and the tunnel insulating film 104 in a first direction Z.

[0065] The first recess 118a and the second recess 118b formed in one surface of the barrier insulating film 102 may be filled with silicon nitride to form the first charge storage film 110a and the second charge storage film 110b, respectively.

[0066] The third recess 168 can be formed in another surface of the barrier insulating film 102 and can be filled with insulating material to form a second insulating pattern 164.

[0067] The barrier insulating film 102 can be formed on the sidewalls, top surface, and bottom surface of the first charge storage film 110a and the second charge storage film 110b. Therefore, the barrier insulating film 102 can be formed between the gate electrode 150 and the first charge storage film 110a and the second charge storage film 110b.

[0068] The barrier insulating film 102 can be configured to surround the gate electrode 150. For example, the barrier insulating film 102 can extend along the bottom surface, sidewalls, and top surface of the gate electrode 15. Thus, the lower portion of the barrier insulating film 102 can be formed between the gate electrode 150 and the first insulating pattern 162, the side portion of the barrier insulating film 102 can be formed between the gate electrode 150 and the first charge storage film 110a and the second charge storage film 110b, and the upper portion of the barrier insulating film 102 can be formed between the gate electrode 150 and the third insulating pattern 166.

[0069] The barrier insulating film 102 may comprise, for example, silicon oxide or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof. For ease of explanation, the barrier insulating film 102 will be described below as comprising silicon oxide.

[0070] In the semiconductor memory device according to the example embodiment, the first charge storage film 110a and the second charge storage film 110b can be controlled by a gate electrode 150. Therefore, two transistors can be formed in one cell, thereby increasing the integration density of the semiconductor memory device.

[0071] In the semiconductor memory device according to the example embodiment, when electrons in the semiconductor pattern 106 are injected into the first charge storage film 110a and / or the second charge storage film 110b via the tunnel insulating film 104, the electrons can be injected via hot carrier injection rather than via Fowler-Nordheim tunneling. Therefore, establishing a strong potential difference within the semiconductor memory device to accelerate the electrons in the semiconductor pattern 106 allows the electrons to possess high kinetic energy, which can be trapped in the first charge storage film 110a and / or the second charge storage film 110b.

[0072] In a semiconductor memory device according to an example embodiment, for example, when electrons are injected into the first charge storage film 110a of the first channel structure CS1, a voltage of +V can be applied to the top of the first channel structure CS1 and the gate electrode 150, while a voltage of 0 (or below +V) can be applied to the bottom of the first channel structure CS1. The difference between the voltage applied to the top of the first channel structure CS1 and the gate electrode 150 and the voltage applied to the bottom of the first channel structure CS1 can be greater at the first charge storage film 110a than at the second charge storage film 110b. Therefore, electrons of the semiconductor pattern 106 can be trapped in the first charge storage film 110a.

[0073] In the semiconductor memory device according to the example embodiment, for example, when electrons are injected into the second charge storage film 110b of the first channel structure CS1, a voltage of +V can be applied to the bottom of the first channel structure CS1 and the gate electrode 150, while a voltage of 0 (or below +V) can be applied to the top of the first channel structure CS1. The difference between the voltage applied to the bottom of the first channel structure CS1 and the gate electrode 150 and the voltage applied to the top of the first channel structure CS1 can be greater at the second charge storage film 110b than at the first charge storage film 110a. Therefore, electrons of the semiconductor pattern 106 can be trapped in the second charge storage film 110b.

[0074] In a semiconductor memory device according to an example embodiment, in order to help control the first charge storage film 110a and the second charge storage film 110b as separate transistors via the gate electrode 150, a second insulating pattern 164, configured to protrude from the gate electrode 150 in a third direction X, may be formed between the first charge storage film 110a and the second charge storage film 110b.

[0075] Therefore, it is possible to prevent the charge trapped in the first charge storage film 110a from being trapped in the second charge storage film 110b through the second insulating pattern 164. Conversely, it is possible to prevent the charge trapped in the second charge storage film 110b from being trapped in the first charge storage film 110a through the second insulating pattern 164. Therefore, the performance of the semiconductor memory device can be improved while increasing the integration density of the semiconductor memory device.

[0076] In the following description, reference will be made to Figure 4 The internal workings of a semiconductor memory device according to an example embodiment are described in detail.

[0077] Figure 4 yes Figure 3 A magnified view of region R1.

[0078] Reference Figure 4 The gate electrode 150 can be formed between the top surface G2 of the first insulating pattern 162 and the bottom surface G1 of the third insulating pattern 166. The first insulating pattern 162 can have a first width W1 in the third direction X, and the third insulating pattern 166 can have a third width W3 in the third direction X.

[0079] The gate electrode 150 may include a first side M1 and a second side M2 ​​extending between the first insulating pattern 162 and the third insulating pattern 166. The gate electrode 150 may have a sixth width W6 defined in a third direction X between the first side M1 and the second side M2.

[0080] The second insulating pattern 164 may protrude a second width W2 from the first side M1 of the gate electrode 150 in the third direction X. The second insulating pattern 164 may have a third length L3 in the first direction Z. The second insulating pattern 164 may include a sixth side M6 where the second insulating pattern 164 intersects with the gate electrode 150 and a fifth side M5 where the second insulating pattern 164 intersects with the barrier insulating film 102. The second insulating pattern 164 may have a tenth width W10 defined from the sixth side M6 to the fifth side M5, and the second width W2 may be the same as the tenth width W10. The gate electrode 150 may have a ninth width W9 defined in the third direction X from the second side M2 ​​to the sixth side M6.

[0081] A first charge storage film 110a may be formed in the first direction Z at the upper portion of the second insulating pattern 164, and a second charge storage film 110b may be formed in the first direction Z at the lower portion of the second insulating pattern 164, with the second insulating pattern 164 positioned between the first charge storage film 110a and the second charge storage film 110b. The first charge storage film 110a may have a first length L1 in the first direction Z. The first charge storage film 110a may have a seventh width W7 in the third direction X. The second charge storage film 110b may have a second length L2 in the first direction Z. The second charge storage film 110b may have an eighth width W8 in the third direction X. The seventh width W7 may be the same as the eighth width W8.

[0082] In the semiconductor memory device according to the example embodiment, the third length L3 of the second insulating pattern 164 may be smaller than the first length L1 and / or the second length L2. For example, the third length L3 of the second insulating pattern 164 may be larger than half of the first length L1 and / or half of the second length L2. When the third length L3 of the second insulating pattern 164 becomes longer, the charge trapped between the first charge storage film 110a and the second charge storage film 110b can be separated more effectively, or the charge trapped in the first charge storage film 110a and / or the second charge storage film 110b can be separated more effectively.

[0083] The first length L1 of the first charge storage film 110a and the second length L2 of the second charge storage film 110b are shown to be the same, but the first length L1 of the first charge storage film 110a and the second length L2 of the second charge storage film 110b may be different from each other.

[0084] The first charge storage film 110a may be spaced apart from the first side M1 by a fourth width W4. The second charge storage film 110b may be spaced apart from the first side M1 by a fifth width W5. The fourth width W4 and the fifth width W5 are shown as the same, but the fourth width W4 and the fifth width W5 may be different from each other. The sum of the fourth width W4 and the seventh width W7 of the first charge storage film 110a in the third direction X may be longer than the second width W2.

[0085] The first charge storage film 110a includes a third side M3 where the first charge storage film 110a and the barrier insulating film 102 meet, and the second charge storage film 110b includes a fourth side M4 where the second charge storage film 110b and the barrier insulating film 102 meet. The barrier insulating film 102 may conformally extend along the first insulating pattern 162, the second insulating pattern 164 and the third insulating pattern 166, the gate electrode 150, the first charge storage film 110a and the second charge storage film 110b, and the tunnel insulating film 104 in a first direction Z.

[0086] The first charge storage film 110a and the second charge storage film 110b can be formed, for example, by filling the first recess 118a and the second recess 118b with silicon nitride films, respectively, in one surface of the barrier insulating film 102. The second insulating pattern 164 can be formed by filling the third recess 168 with an insulating material, in the other surface of the barrier insulating film 102 opposite to said one surface of the barrier insulating film 102.

[0087] For example, the first width W1 of the first insulating pattern 162 and the third width W3 of the third insulating pattern 166 can be the same. The distance from the first side M1 to the second side M2 ​​(i.e., the sixth width W6 of the gate electrode 150 in the third direction X) can be smaller than the first width W1 and / or the third width W3.

[0088] The length from the second side M2 ​​to the fifth side M5 is equal to the sum of the ninth width W9 and the second width W2 of the protruding portion of the second insulating pattern 162. The ninth width W9 may be the same as the sixth width W6, or it may be smaller than the sixth width W6 (see...). Figure 20 ).

[0089] The length from the second side M2 ​​to the third side M3 is equal to the sum of the sixth width W6 and the fourth width W4. The length from the second side M2 ​​to the fourth side M4 is equal to the sum of the sixth width W6 and the fifth width W5.

[0090] Although the sum of the sixth width W6 and the fourth width W4, as shown in the attached diagram, can be the same as the sum of the sixth width W6 and the fifth width W5, the sum of the sixth width W6 and the fourth width W4 can be different from the sum of the sixth width W6 and the fifth width W5.

[0091] In a semiconductor memory device according to an example embodiment, the sum of the sixth width W6 and the second width W2 may be greater than the sum of the sixth width W6 and the fourth width W4. The sum of the sixth width W6 and the second width W2 may be greater than the sum of the sixth width W6 and the fifth width W5.

[0092] As described above, the semiconductor memory device according to the example embodiment can independently store charge in a first charge storage film 110a and a second charge storage film 110b through a gate electrode 150.

[0093] For example, referencing along Figure 4 The direction of the arrow drawn between the two dots in D2 indicates the gate voltage V. G It can be applied to the gate electrode 150. Gate voltage V G This can be, for example, a positive voltage. A first voltage V1 can be applied to the top of the semiconductor pattern 106, and a second voltage V2, different from the first voltage V1, can be applied to the bottom of the semiconductor pattern 106. In one example, the first voltage V1 can be a ground voltage, while the second voltage V2 can be a positive voltage. In this case, the charge (electrons) supplied from the top of the semiconductor pattern 106 can be selectively trapped in the second charge storage film 110b.

[0094] As another example, refer to along Figure 4 The direction of the arrow drawn between the two dots in D1, and the gate voltage V G It can be applied to the gate electrode 150. Gate voltage V G This can be, for example, a positive voltage. A first voltage V1 can be applied to the top of the semiconductor pattern 106, while a second voltage V2, different from the first voltage V1, can be applied to the bottom of the semiconductor pattern 106. In one example, the first voltage V1 can be a positive voltage, while the second voltage V2 can be a ground voltage. In this case, the charge (electrons) supplied from the bottom of the semiconductor pattern 106 can be selectively trapped in the first charge storage film 110a.

[0095] Therefore, the semiconductor memory device according to the example embodiment can implement two data storage elements via each gate electrode 150. Thus, a semiconductor memory device with improved integration density can be provided.

[0096] Figure 5 It is along Figure 3 The sectional view taken by line A-A' in the middle.

[0097] Reference Figure 5The semiconductor memory device according to the example embodiment can be separated by a slit region 190. The semiconductor memory device according to the example embodiment includes a first channel structure CS1, a second channel structure CS2, a third channel structure CS3, a fourth channel structure CS4, and a fifth channel structure CS5 connected to a gate electrode 150. In each of the first channel structure CS1, the second channel structure CS2, the third channel structure CS3, the fourth channel structure CS4, and the fifth channel structure CS5, a filling insulating pattern 108, a semiconductor pattern 106, a tunnel insulating film 104, a first charge storage film 110a, and a barrier insulating film 102 can be sequentially formed.

[0098] In the following description, reference will be made to Figure 6 Describes a portion of a semiconductor memory device according to an example embodiment, formed by an insulating pattern between a first charge storage film 110a and a second charge storage film 110b.

[0099] Figure 6 It is along Figure 3 The sectional view taken by line B-B' in the figure.

[0100] Reference Figure 6 The semiconductor memory device according to the example embodiment can be separated by a slit region 190. The semiconductor memory device according to the example embodiment includes a first channel structure CS1, a second channel structure CS2, a third channel structure CS3, a fourth channel structure CS4, and a fifth channel structure CS5 insulated by a second insulating pattern 164. In each of the first channel structure CS1, the second channel structure CS2, the third channel structure CS3, the fourth channel structure CS4, and the fifth channel structure CS5, a filling insulating pattern 108, a semiconductor pattern 106, a tunnel insulating film 104, and a barrier insulating film 102 can be sequentially formed.

[0101] In a semiconductor memory device according to an example embodiment, a first charge storage film 110a is connected to a second insulating pattern 164. Figure 3 The second charge storage film 110b is isolated, which prevents charge trapping interference between the first charge storage film 110a and the second charge storage film 110b.

[0102] Figures 7 to 17 This illustrates a method for describing the manufacture according to an example embodiment. Figure 2 A view of the intermediate process of a method for making a semiconductor memory device.

[0103] Reference Figure 7 A first insulating pattern 162, a first sacrificial film 152, a second insulating pattern 164, a second sacrificial film 154 and a third insulating pattern 166 are sequentially stacked on a substrate 100.

[0104] Although the first sacrificial membrane 152 and the second sacrificial membrane 154 are shown to have the same thickness, the first sacrificial membrane 152 and the second sacrificial membrane 154 may have different thicknesses from each other.

[0105] The first sacrificial film 152 and the second sacrificial film 154 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon-rich nitride (Si-rich nitride), and nanocrystalline silicon (nanocrystalline Si). For ease of explanation, the first sacrificial film 152 and the second sacrificial film 154 will be described below as including silicon nitride. The first sacrificial film 152 and the second sacrificial film 154 may define the region where the gate electrode 150 is formed.

[0106] Reference Figure 8 A first channel hole CH1, a second channel hole CH2, and a third channel hole CH3 can be formed in the stacked first insulating pattern 162, first sacrificial film 152, second insulating pattern 164, second sacrificial film 154, and third insulating pattern 166.

[0107] In the following description, a first channel via CH1 will be described as an example. A stacked first insulating pattern 162, a first sacrificial film 152, a second insulating pattern 164, a second sacrificial film 154, and a third insulating pattern 166 may be etched to form a first channel via CH1 configured to pass through the stacked first insulating pattern 162, first sacrificial film 152, second insulating pattern 164, second sacrificial film 154, and third insulating pattern 166. The first channel via CH1 may be configured to expose a portion of the substrate 100 by passing through the stacked first insulating pattern 162, first sacrificial film 152, second insulating pattern 164, second sacrificial film 154, and third insulating pattern 166. In an example embodiment, forming the first channel via CH1 may include etching a portion of the top portion of the substrate 100.

[0108] In an example embodiment, the first channel hole CH1 may have a tapered shape. For example, the width of the first channel hole CH1 may become narrower towards the bottom in the first direction Z. This shape of the first channel hole CH1 may be caused by the characteristics of the etching process used to form the first channel hole CH1.

[0109] Reference Figure 9 The portions of the first sacrificial film 152 and the second sacrificial film 154 exposed by the first channel hole CH1, the second channel hole CH2, and the third channel hole CH3 can be removed. For example, an etch-back process can be performed on the first sacrificial film 152 and the second sacrificial film 154 to form recesses in the first sacrificial film 152 and the second sacrificial film 154.

[0110] Reference Figure 10A barrier insulating film 102 and an initial charge storage film 110 may be sequentially formed in each of the channel holes CH1 to CH3. In the following description, the first channel hole CH1 will be described as an example.

[0111] First, a barrier insulating film 102 extending along the contour of the first channel hole CH1 can be formed. The barrier insulating film 102 can extend along the side surfaces of the first sacrificial film 152, the second sacrificial film 154, the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166.

[0112] Next, an initial charge storage film 110 can be formed on the barrier insulating film 102. The initial charge storage film 110 can extend along the contour of the barrier insulating film 102.

[0113] Reference Figure 11 An etch-back process can be performed on the initial charge storage film 110. The etch-back process according to the example embodiment can be performed by wet etching. In the example embodiment, the etch-back process can be performed until the side surfaces of the barrier insulating film 102 are exposed. Therefore, multiple charge storage films (e.g., the first charge storage film 110a and the second charge storage film 110b) can be formed spaced apart from each other between the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166.

[0114] The first charge storage film 110a and the second charge storage film 110b can be embedded in the sacrificial films 154 and 152, respectively. For example, the first charge storage film 110a can fill at least a portion of the first recess 118a formed in the second sacrificial film 154, and the second charge storage film 110b can fill at least a portion of the second recess 118b formed in the first sacrificial film 152.

[0115] As an example, the width of the first charge storage film 110a and the width of the second charge storage film 110b are shown to be equal to each other. As an example, the depth of the first charge storage film 110a and the depth of the second charge storage film 110b are shown to be equal to each other.

[0116] Reference Figure 12 A tunnel insulating film 104, a semiconductor pattern 106, and a filling insulating pattern 108 can be sequentially formed in each of the channel holes CH1 to CH3. A first interlayer insulating film 210 and a channel pad 160 can be formed on the channel structures CS1 to CS3.

[0117] Reference Figure 13A slit region 190 may be formed in the first insulating pattern 162, the second insulating pattern 164, the third insulating pattern 166, and the sacrificial films 152 and 154. The slit region 190 may be configured to expose the substrate 100 by passing through the first insulating pattern 162, the second insulating pattern 164, the third insulating pattern 166, and the sacrificial films 152 and 154. Therefore, the slit region 190 may cut through the first insulating pattern 162, the second insulating pattern 164, the third insulating pattern 166, and the sacrificial films 152 and 154. In an example embodiment, the slit region 190 may extend in the second direction Y.

[0118] In an example embodiment, an impurity region 105 may be formed in the substrate 100 exposed by the slit region 190.

[0119] Reference Figure 14 It can remove the portions of the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 that are exposed by the slit area 190.

[0120] Reference Figure 15 The sacrificial films 152 and 154 exposed by the slit region 190 can be removed. The removal of the sacrificial films 152 and 154 can be performed, for example, by an anisotropic etching process. Therefore, in some embodiments, a portion of the side surface of the barrier insulating film 102 can be exposed.

[0121] Reference Figure 16 The gate electrode 150 can be formed by filling the regions from which the sacrificial films 152 and 154 have been removed with a conductive material.

[0122] Reference Figure 17 A separation structure 300 can be formed in the slit region 190 to form the word line cutting region WLC. For example, a spacer 304 extending along the contour of the word line cutting region WLC can be formed. Then, a plug pattern 302 filling the word line cutting region WLC can be formed on the spacer 304.

[0123] Then, refer to again Figure 2 A second interlayer insulating film 310 can be formed on the word line cutting region WLC, the first interlayer insulating film 210, and the channel pad 160. A bit line contact 320 that contacts the channel pad 160 can be formed inside the second interlayer insulating film 310. A bit line BL can be formed on the bit line contact 320 and the second interlayer insulating film 310, enabling the formation of a bit line according to the example embodiment. Figure 2 Semiconductor memory devices.

[0124] Figure 18 This is an example cross-sectional view of a semiconductor memory device according to another example embodiment. The focus will be on... Figure 2The differences are described below, and references can be omitted. Figure 2 The repetitive description in the exposition.

[0125] Reference Figure 18 ,and Figure 2 The difference lies in that the second insulating pattern 164 further penetrates into the gate electrode 150 in the third direction X of the word lines WL0 to WLn.

[0126] When region P2 is used as a memory cell, one gate electrode 150 can control one memory cell. Therefore, since the first charge storage film 110a and the second charge storage film 110b are formed in one memory cell, charge is stored in the desired charge storage film. Structurally, this memory cell can be used as one memory cell, but it can operate as two memory cells, thereby increasing the cell integration density. That is, assuming the word line in region P2 is the third word line WL3, the effect obtainable from two memory cells can be achieved at the third word line WL3 using one gate electrode 150. The detailed effects, process, and operation will be described below.

[0127] Figure 19 According to the example embodiment Figure 18 An enlarged view of region P2 of the semiconductor memory device. (Except for the reference...) Figure 3 Apart from the repeated parts of the description, the following description will be provided.

[0128] Reference Figure 19 At least a portion of the second insulating pattern 164 may be formed within the gate electrode 150.

[0129] In the semiconductor memory device according to the example embodiment, the first charge storage film 110a and the second charge storage film 110b can be controlled by a gate electrode 150. Therefore, forming two transistors in one cell allows for an increase in the integration density of the semiconductor memory device.

[0130] In the semiconductor memory device according to the example embodiment, when electrons in the semiconductor pattern 106 are injected into the first charge storage film 110a and / or the second charge storage film 110b via the tunnel insulating film 104, the electrons can be injected via hot carrier injection rather than via Fowler-Nordheim tunneling. Therefore, a strong potential difference can be established within the semiconductor memory device to accelerate the electrons in the semiconductor pattern 106, allowing the electrons to possess high kinetic energy. Electrons with high kinetic energy (i.e., hot carriers) can be trapped in the first charge storage film 110a and / or the second charge storage film 110b.

[0131] In a semiconductor memory device according to an example embodiment, for example, when electrons are injected into the first charge storage film 110a of the first channel structure CS1, a voltage of +V can be applied to the top of the first channel structure CS1 and the gate electrode 150, while a voltage of 0 (or below +V) can be applied to the bottom of the first channel structure CS1. The difference between the voltage applied to the top of the first channel structure CS1 and the gate electrode 150 and the voltage applied to the bottom of the first channel structure CS1 can be greater at the first charge storage film 110a than at the second charge storage film 110b. Therefore, electrons of the semiconductor pattern 106 can be trapped in the first charge storage film 110a.

[0132] In the semiconductor memory device according to the example embodiment, for example, when electrons are injected into the second charge storage film 110b of the first channel structure CS1, a voltage of +V can be applied to the bottom of the first channel structure CS1 and the gate electrode 150, while a voltage of 0 (or below +V) can be applied to the top of the first channel structure CS1. The difference between the voltage applied to the bottom of the first channel structure CS1 and the gate electrode 150 and the voltage applied to the top of the first channel structure CS1 can be greater at the second charge storage film 110b than at the first charge storage film 110a. Therefore, electrons of the semiconductor pattern 106 can be trapped in the second charge storage film 110b.

[0133] In a semiconductor memory device according to an example embodiment, in order to help control the first charge storage film 110a and the second charge storage film 110b as separate transistors via the gate electrode 150, a second insulating pattern 164 extending from the interior of the gate electrode 150 in a third direction X can be formed between the first charge storage film 110a and the second charge storage film 110b. Therefore, it is possible to prevent charge trapped in the first charge storage film 110a from being trapped in the second charge storage film 110b via the second insulating pattern 164. Conversely, it is possible to prevent charge trapped in the second charge storage film 110b from being trapped in the first charge storage film 110a via the second insulating pattern 164. Therefore, the performance of the semiconductor memory device can be improved while increasing the integration density of the semiconductor memory device.

[0134] It can prevent the voltage of the gate electrode 150 on the third-direction X-line of the first charge storage film 110a from reaching the second charge storage film 110b, and it can also prevent the voltage of the gate electrode 150 on the third-direction X-line of the second charge storage film 110b from reaching the first charge storage film 110a. Therefore, the first charge storage film 110a and the second charge storage film 110b can be controlled as separate transistors by a single gate electrode 150, thereby improving the performance of the semiconductor memory device while increasing the integration density of the semiconductor memory device.

[0135] Figure 20 yes Figure 19 A magnified view of region R2. For reference, the focus will be on... Figure 4 The differences will be described below, and references will be omitted. Figure 4 The repeated parts of the description.

[0136] Reference Figure 20 At least a portion of the second insulating pattern 164 may be formed inside the gate electrode 150. For example... Figure 20 As shown, the second insulating pattern 164 may have a tenth width W10 defined from the sixth side M6 to the fifth side M5 where the second insulating pattern 164 intersects with the barrier insulating film 102.

[0137] In the semiconductor memory device according to the example embodiment, the third length L3 of the second insulating pattern 164 may be smaller than the first length L1 and / or the second length L2, or for example, the third length L3 of the second insulating pattern 164 may be larger than half of the first length L1 and / or half of the second length L2. When the third length L3 of the second insulating pattern 164 becomes longer, the charge trapped between the first charge storage film 110a and the second charge storage film 110b can be separated more effectively.

[0138] Although the first length L1 of the first charge storage film 110a and the second length L2 of the second charge storage film 110b are shown to be the same, the first length L1 of the first charge storage film 110a and the second length L2 of the second charge storage film 110b may be different from each other. Although the fourth width W4 and the fifth width W5 are shown to be the same, the fourth width W4 and the fifth width W5 may be different from each other.

[0139] As an example, the first width W1 of the first insulating pattern 162 and the third width W3 of the third insulating pattern 166 are shown to be the same. The distance from the first side M1 to the second side M2 ​​(i.e., the sixth width W6 of the gate electrode 150 in the third direction X) may be smaller than the first width W1 and / or the third width W3.

[0140] The length from the second side M2 ​​to the fifth side M5 is equal to the sum of the sixth width W6 and the second width W2, equal to the sum of the ninth width W9 and the tenth width W10, and may be equal to or less than the third width W3 and / or the first width W1. The length from the second side M2 ​​to the third side M3 is equal to the sum of the sixth width W6 and the fourth width W4. The length from the second side M2 ​​to the fourth side M4 is equal to the sum of the sixth width W6 and the fifth width W5.

[0141] Although the sum of the sixth width W6 and the fourth width W4, as shown in the attached diagram, can be the same as the sum of the sixth width W6 and the fifth width W5, the sum of the sixth width W6 and the fourth width W4 can be different from the sum of the sixth width W6 and the fifth width W5.

[0142] In the semiconductor memory device according to the example embodiment, the length from the second side M2 ​​to the fifth side M5 may be greater than the sum of the sixth width W6 and the fourth width W4.

[0143] As described above, the semiconductor memory device according to the example embodiment can independently store charge in a first charge storage film 110a and a second charge storage film 110b through a gate electrode 150.

[0144] For example, referencing along Figure 20 The direction of the arrow drawn between the two dots in D2, and the gate voltage V G It can be applied to the gate electrode 150. Gate voltage V G This could be, for example, a positive voltage. A first voltage V1 can be applied to the top of the semiconductor pattern 106, while a second voltage V2, different from the first voltage V1, can be applied to the bottom of the semiconductor pattern 106. In one example, the first voltage V1 could be a ground voltage, while the second voltage V2 could be a positive voltage. In this case, the charge (electrons) supplied from the top of the semiconductor pattern 106 can be selectively trapped in the second charge storage film 110b.

[0145] As another example, refer to along Figure 20 The direction of the arrow drawn between the two dots in D1, and the gate voltage V G It can be applied to the gate electrode 150. Gate voltage V G This can be, for example, a positive voltage. A first voltage V1 can be applied to the top of the semiconductor pattern 106, while a second voltage V2, different from the first voltage V1, can be applied to the bottom of the semiconductor pattern 106. In one example, the first voltage V1 can be a positive voltage, while the second voltage V2 can be a ground voltage. In this case, the charge (electrons) supplied from the bottom of the semiconductor pattern 106 can be selectively trapped in the first charge storage film 110a.

[0146] Therefore, the semiconductor memory device according to the example embodiment can implement two data storage elements via each gate electrode 150. Thus, a semiconductor memory device with improved integration density can be provided.

[0147] According to the example embodiment Figure 20In the semiconductor memory device, because the second insulating pattern 164 further penetrates into the gate electrode 150, the first charge storage film 110a and the second charge storage film 110b can be more insulating, allowing the first charge storage film 110a and the second charge storage film 110b to be better controlled separately from each other under the control of the gate electrode 150. Therefore, the second insulating pattern 164, which further protrudes into the gate electrode 150, can effectively help to individually control the voltage applied to the first charge storage film 110a and the second charge storage film 110b.

[0148] Figures 21 to 24 This illustrates a method for describing the manufacture according to an example embodiment. Figure 18 A view of an intermediate process of a method for constructing a semiconductor memory device. In these embodiments, reference is used. Figures 7 to 13 The same manufacturing process is described, so the following description will focus on subsequent processes. Figures 14 to 17 The differences will be described below, and references will be omitted. Figures 14 to 17 The repeated parts of the description.

[0149] Reference Figure 21 The portions of the first insulating pattern 162, the second insulating pattern 164, and the third insulating pattern 166 exposed by the slit region 190 can be etched. At this time, the etching speed of the first insulating pattern 162 and the third insulating pattern 166 can be different from the etching speed of the second insulating pattern 164. Therefore, the etching speed of the second insulating pattern 164 can be faster than the etching speed of the first insulating pattern 162 and the third insulating pattern 166.

[0150] In a method for manufacturing a semiconductor memory device according to an example embodiment, at least a portion of a second insulating pattern 164 may be retained between a first sacrificial film 152 and a second sacrificial film 154.

[0151] Reference Figure 22 The first sacrificial film 152 and the second sacrificial film 154 exposed by the slit region 190 can be removed. For example, a wet etching process with an etch selectivity ratio for the first insulating pattern 162, the second insulating pattern 164 and the third insulating pattern 166 can be performed to remove the first sacrificial film 152 and the second sacrificial film 154.

[0152] In a method for manufacturing a semiconductor memory device according to an example embodiment, a second insulating pattern 164 may extend from a barrier insulating film 102 in a third direction X to protrude from a side surface of the barrier insulating film 102 in a direction opposite to the third direction X (-X direction).

[0153] Reference Figure 23 This can form a gate electrode 150 to occupy the removedFigure 22 The space between the first sacrificial film 152 and the second sacrificial film 154. The gate electrode 150 can be formed by depositing a conductive material such as a metal by atomic layer deposition (ALD) or chemical vapor deposition (CVD), or, for example, by generating a tungsten (W) core and depositing bulk tungsten.

[0154] Reference Figure 24 A separation structure 300 can be formed in the slit region 190 to form the word line cutting region WLC. For example, a spacer 304 extending along the contour of the word line cutting region WLC can be formed. Then, a plug pattern 302 filling the word line cutting region WLC can be formed on the spacer 304.

[0155] Refer again Figure 18 A second interlayer insulating film 310 can be formed on the word line cutting region WLC, the first interlayer insulating film 210, and the channel pad 160. A bit line contact 320 that contacts the channel pad 160 can be formed inside the interlayer insulating film 310. A bit line BL can be formed on the bit line contact 320 and the second interlayer insulating film 310, enabling the formation of a bit line according to the example embodiment. Figure 18 Semiconductor memory devices.

[0156] As described above, the embodiments relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device, the semiconductor memory device including an insulating pattern configured to protrude from a gate electrode and lie between charge storage films. The embodiments can provide a semiconductor memory device with improved reliability by providing an insulating pattern configured to protrude from a gate electrode and lie between charge storage films. The embodiments can also provide a method for manufacturing a semiconductor memory device including an insulating pattern configured to protrude from a gate electrode and lie between charge storage films.

[0157] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, unless specifically instructed otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A third insulating pattern and a first insulating pattern are located on a substrate, and the third insulating pattern and the first insulating pattern are spaced apart from each other in a first direction perpendicular to the substrate, such that the bottom surface of the third insulating pattern and the top surface of the first insulating pattern face each other. The gate electrode is located between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and includes a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern. The second insulating pattern protrudes a second width from the first side of the gate electrode in a second direction, which is different from the first direction. as well as A barrier insulating film extends along the second insulating pattern and is located on the third insulating pattern, the first insulating pattern, and the gate electrode. The barrier insulating film includes a first charge storage film and a second charge storage film spaced apart from each other in a first direction. The second insulating pattern is located between the first charge storage film and the second charge storage film in the first direction.

2. The semiconductor memory device according to claim 1, wherein, At least a portion of the second insulating pattern is formed within the gate electrode.

3. The semiconductor memory device according to claim 2, wherein: The gate electrode includes a second side facing the first side. The gate electrode includes a sixth side where the gate electrode and the second insulating pattern intersect, and The sixth width of the gate electrode, defined from the second side to the first side, is longer than the ninth width of the gate electrode, defined from the second side to the sixth side.

4. The semiconductor memory device according to claim 3, wherein: The third insulating pattern has a third width in the second direction. The first insulating pattern has a first width in the second direction. The second insulating pattern has a tenth width defined from the sixth side to the fifth side where the second insulating pattern intersects with the barrier insulating film, and In the second direction, the sum of the ninth width of the gate electrode and the tenth width of the second insulating pattern is smaller than the third width and smaller than the first width.

5. The semiconductor memory device according to claim 1, wherein: The third insulating pattern has a third width in the second direction. The first insulating pattern has a first width in the second direction, and In the second direction, the sixth width of the gate electrode is smaller than the third width and smaller than the first width.

6. The semiconductor memory device according to claim 5, wherein, The third width of the third insulating pattern is the same as the first width of the first insulating pattern.

7. The semiconductor memory device according to claim 1, wherein, The fourth width defined from the first side to the first charge storage film and the fifth width defined from the first side to the second charge storage film are shorter than the second width.

8. The semiconductor memory device according to claim 7, wherein, The seventh width of the first charge storage film in the second direction is the same as the eighth width of the second charge storage film in the second direction.

9. The semiconductor memory device according to claim 8, wherein, The sum of the fourth width and the seventh width of the first charge storage film in the second direction is longer than the second width.

10. A semiconductor memory device, the semiconductor memory device comprising: A semiconductor pattern is located on a substrate and extends in a first direction perpendicular to the substrate; A tunnel insulating film is located on a semiconductor pattern; The first charge storage film and the second charge storage film are located on the tunnel insulating film and are spaced apart from each other in the first direction; The blocking insulating film extends along the first charge storage film and the second charge storage film on the tunnel insulating film; The recess is located between the first charge storage film and the second charge storage film, and is confined within the barrier insulating film; Insulating pattern, filling in the depressions; as well as The gate electrode is located on the insulating pattern and the barrier insulating film.

11. The semiconductor memory device of claim 10, wherein: The first charge storage film has a first length in a first direction. The second charge storage film has a second length in the first direction, and The first length is the same as the second length.

12. The semiconductor memory device of claim 11, wherein: The insulating pattern has a third length in the first direction. The third length is smaller than the first length and smaller than the second length.

13. The semiconductor memory device according to claim 10, wherein, The insulating pattern extends into the gate electrode.

14. The semiconductor memory device according to claim 13, wherein: The gate electrode includes a first side where the gate electrode and the barrier insulating film meet thereon, a second side facing the first side, and a sixth side where the gate electrode and the insulating pattern meet thereon; and In the second direction intersecting the first direction, the sixth width of the gate electrode defined from the first side to the second side is smaller than the sum of the ninth width of the gate electrode defined from the second side to the sixth side and the tenth width of the insulating pattern, the tenth width of which is the width defined from the sixth side to the fifth side where the insulating pattern and the blocking insulating film intersect.

15. A semiconductor memory device, the semiconductor memory device comprising: A barrier insulating film extends in a first direction perpendicular to the substrate; The first and second recesses are defined within a surface of the barrier insulating film and are spaced apart from each other in a first direction; The third recess is defined within the opposing surface of the one surface facing the barrier insulating film and is located between the first recess and the second recess. A first charge storage film fills the first depression; A second charge storage film fills the second depression; Insulating pattern, filling the third depression; as well as The gate electrode extends along the insulating pattern and the barrier insulating film.

16. The semiconductor memory device according to claim 15, wherein, The insulating pattern extends into the gate electrode.

17. The semiconductor memory device of claim 16, wherein: The gate electrode includes a first side where the gate electrode and the barrier insulating film meet, a second side facing the first side, and a sixth side where the gate electrode and the insulating pattern meet. In the second direction intersecting the first direction, the sixth width defined from the first side to the second side is smaller than the sum of the ninth width defined from the second side to the sixth side and the tenth width of the insulating pattern, the tenth width of which is the width defined from the sixth side to the fifth side where the insulating pattern and the barrier insulating film intersect.

18. The semiconductor memory device according to claim 15, wherein: The first charge storage film has a first length in a first direction. The second charge storage film has a second length in the first direction. The first length is the same as the second length. The insulating pattern has a third length in the first direction, and The third length is smaller than the first length and smaller than the second length.

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