Display Devices

Abstract

A display device is disclosed, comprising: a sensor layer including a sensor; a pixel layer provided on the sensor layer and including a pixel region and pixels located in the pixel region; and an opaque layer provided between the sensor layer and the pixel layer and having holes corresponding to light-transmitting regions of specific pixel regions provided with specific pixels emitting light of a specific color.

Description

Technical Field

[0001] One or more embodiments are directed to a display device having a fingerprint sensing function. Background Art

[0002] Various display devices used in multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles have been developed. Recently, a display device having a function for sensing a user's fingerprint has been developed. Examples of fingerprint recognition methods include an electrostatic capacitance method based on a change in capacitance of a capacitor formed between electrodes, an optical method using an optical sensor, and an ultrasonic method using a piezoelectric material.

[0003] It should be understood that the background of the technology section is intended, in part, to provide a useful background for understanding the technology. However, the background of the technology section may also include ideas, concepts or understandings of the part that were not known or appreciated by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0004] One or more embodiments may include a display device for configuring a fingerprint sensor without a separate external light source and increasing the amount of light received by the fingerprint sensor.

[0005] The technical problems to be solved by the present disclosure are not limited to the above contents, and according to the description of the present disclosure, a person of ordinary skill in the art will clearly appreciate and understand other technical problems to be solved by the present disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a display device may include: a sensor layer including a plurality of sensors; a pixel layer disposed on the sensor layer and including a plurality of pixel regions and a plurality of pixels located in the pixel regions; and an opaque layer disposed between the sensor layer and the pixel layer and including a hole corresponding to a light-transmitting region of a specific pixel region in which a specific pixel emitting light of a specific color is disposed.

[0008] The holes of the opaque layer may be repeatedly formed in a predetermined pattern and in a predetermined direction in the display area.

[0009] The light-transmitting region may be a region corresponding to a gap between a wiring in a specific pixel region where the specific pixel is provided and a circuit device constituting the specific pixel.

[0010] Each of the plurality of pixels may include a pixel circuit disposed in a pixel region and a pixel electrode connected to the pixel circuit, wherein the display device may further include an insulating layer including an opening exposing a portion of the pixel electrode and covering an edge of the pixel electrode.

[0011] The openings of the insulating layer may be offset from the holes of the opaque layer.

[0012] The specific pixel that emits light of a specific color may be a red pixel.

[0013] The specific pixel that emits light of a specific color may be a green pixel.

[0014] The specific pixel that emits light of a specific color may be a blue pixel.

[0015] The display device may further include a substrate located between the opaque layer and the sensor layer.

[0016] The display device may include a substrate having a plurality of layers, and the opaque layer may be disposed between the plurality of layers of the substrate.

[0017] The opaque layer may be a single layer structure including molybdenum (Mo).

[0018] The opaque layer may be a sequentially stacked three-layer structure including a first layer having titanium (Ti), a second layer having aluminum (Al), and a third layer having titanium (Ti).

[0019] The pixel may include a first pixel, a second pixel, and a third pixel, and the first pixel, the second pixel, and the third pixel include a first light-emitting area, a second light-emitting area, and a third light-emitting area, respectively. The first light-emitting area of ​​the first pixel and the third light-emitting area of ​​the third pixel may be alternately arranged in a first sub-row of each row in a row in a first direction, and the second light-emitting area of ​​the second pixel may be repeatedly arranged in the first direction in a second sub-row and the first light-emitting area, the second light-emitting area, the third light-emitting area, and the second light-emitting area may be repeatedly arranged in a zigzag pattern.

[0020] The hole may be offset from the first light emitting area, the second light emitting area, and the third light emitting area.

[0021] The pixel layer may include: a circuit layer including pixel circuits of a plurality of pixels; and a display element layer disposed on the pixel circuit layer and including display elements of a plurality of pixels, wherein an opaque layer may be disposed between the substrate and the circuit layer.

[0022] According to one or more embodiments, a display device may include: a substrate including a plurality of pixel regions in a display area; an opaque layer disposed on the substrate; and a plurality of pixels disposed on the opaque layer and respectively disposed in the plurality of pixel regions, wherein the opaque layer may have holes corresponding to light-transmitting regions of specific pixel regions in which specific pixels emitting light of a specific color are disposed.

[0023] Each of the light-transmitting regions may be a region corresponding to a gap between a wiring in a specific pixel region and a circuit device constituting the specific pixel.

[0024] The plurality of pixels may include a first pixel emitting red light, a second pixel emitting green light, and a third pixel emitting blue light.

[0025] Each of the first pixels may include a first pixel circuit arranged in a first pixel area and a first pixel electrode connected to the first pixel circuit, each of the second pixels may include a second pixel circuit arranged in a second pixel area and a second pixel electrode connected to the second pixel circuit, and each of the third pixels may include a third pixel circuit arranged in a third pixel area and a third pixel electrode connected to the third pixel circuit.

[0026] The opaque layer may include holes corresponding to light-transmitting areas of the first pixel area among the first to third pixel areas, respectively.

[0027] The opaque layer may include a hole corresponding to a light-transmitting area of ​​a second pixel area among the first to third pixel areas.

[0028] The opaque layer may include a hole corresponding to a light-transmitting area of ​​a third pixel area among the first to third pixel areas.

[0029] The display device may further include an insulating layer including an opening exposing a portion of each of the first to third pixel electrodes, and the insulating layer covers edges of the first to third pixel electrodes.

[0030] The openings of the insulating layer may be offset from the holes of the opaque layer.

[0031] The display device may further include a plurality of sensors disposed on a surface of the substrate opposite to a surface on which the plurality of pixels are disposed and in a sensing region overlapping at least a portion of the display region.

[0032] Each of the plurality of sensors may overlap with at least one pixel in the sensing area.

[0033] Each of the plurality of sensors may be disposed in a non-light emitting region between adjacent pixels and offset from the adjacent pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other aspects, features and advantages of the embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0035] Figure 1 and Figure 2 is a plan view showing a display device according to an embodiment of the present disclosure;

[0036] FIG. 3A to FIG. 3H is a plan view showing the size and / or arrangement of pixels and sensors according to an embodiment of the present disclosure;

[0037] Figure 4 is shown for use by Figure 1 a display device configured to sense biometric information;

[0038] Figure 5 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure;

[0039] Fig. 6A and Figure 6B is an equivalent circuit showing one pixel of a display panel according to an embodiment of the present disclosure;

[0040] 7A to 9B is a view showing the arrangement of a pixel circuit according to an embodiment of the present disclosure;

[0041] Fig.10 is a view showing an arrangement of light emitting regions of pixels of a display device according to an embodiment of the present disclosure;

[0042] Fig.11 is a view showing positions of transistors and capacitors in a pixel circuit according to an embodiment of the present disclosure; and

[0043] Fig.12 and Fig.13 is a plan view showing the positions of holes of an opaque layer and light emitting areas according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Although the present invention can be modified in various ways and has other embodiments, the embodiments are shown in the drawings and will be mainly described in the specification. However, the scope of the present invention is not limited to the embodiments in the drawings and the specification, and should be interpreted as including all changes, equivalents and substitutions included in the spirit and scope of the present invention.

[0045] In order to describe the embodiments of the present invention, some of parts that are not related to the description may not be provided, and the same reference numerals denote the same elements throughout the specification.

[0046] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate the description and interpretation of terms. For example, when discussing "first element" in the description, it can be named "second element" or "third element", and without departing from the teachings herein, "second element" and "third element" can be named in a similar manner. As used herein, "about" or "approximately" includes the value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art in consideration of the measurement discussed and the error (i.e., the limitation of the measurement system) associated with the measurement of a specific amount. For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 5% of the value.

[0047] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element with one or more intervening elements interposed between the element and the other element. It will also be understood that when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components and / or any combination thereof.

[0049] When a layer, film, zone, substrate or region is referred to as being "on" another layer, film, zone, substrate or region, it may be directly on the other layer, film, zone, substrate or region, or there may be an intermediate layer, film, zone, substrate or region between them. On the contrary, when a layer, film, zone, substrate or region is referred to as being "directly on" another layer, film, zone, substrate or region, there may not be an intermediate layer, film, zone, substrate or region between them. In addition, when a layer, film, zone, substrate or region is referred to as being "below" another layer, film, zone, substrate or region, it may be directly below another layer, film, zone, substrate or region, or there may be an intermediate layer, film, zone, substrate or region between them. On the contrary, when a layer, film, zone, substrate or region is referred to as being "directly on" another layer, film, zone, substrate or region, there may not be an intermediate layer, film, zone, substrate or region between them. Furthermore, "on" or "over" may include positioning on an object or positioning below an object and does not necessarily mean a direction based on gravity.

[0050] For ease of description, spatially relative terms "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Therefore, the illustrative term "below" may include both lower and upper positions. The device may also be oriented in other directions, and therefore spatially relative terms may be interpreted differently depending on the orientation.

[0051] In the accompanying drawings, the size and thickness of the elements may be exaggerated for clarity and ease of description. However, the present invention is not limited to the sizes and thicknesses shown. In the accompanying drawings, the thickness of layers, films, panels, regions and other elements may be exaggerated for clarity. In the accompanying drawings, the thickness of some layers and regions may be exaggerated for better understanding and ease of description.

[0052] In the following embodiments, a “plan view of an object” means a “view of an object viewed from above”, and a “cross-sectional view of an object” means a “view of an object viewed from the side and cut vertically”. In the following embodiments, when elements “overlap”, it may mean that the elements overlap in a “plan view” and / or a “cross-sectional view”.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0054] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the disclosure are shown.

[0055] Figure 1 and Figure 2 is a plan view showing a display device according to an embodiment of the present disclosure.

[0056] Although an organic light-emitting display device is described as a display device according to an embodiment of the present disclosure, the display device of the present disclosure is not limited thereto. In an embodiment, the display device of the present disclosure may be any of various display devices such as an inorganic light-emitting display (or an inorganic electroluminescent (EL) display), a nano-luminescent display, or a quantum dot light-emitting display.

[0057] Reference Figure 1 The display device according to the embodiment includes a display area DA that displays an image and a peripheral area PPA that is a non-display area and surrounds the display area DA. The substrate 100 of the display panel 10 of the display device may include the display area DA and the peripheral area PPA.

[0058] The display area DA may have a shape similar to a rectangular shape or a square shape. The display area DA may have a shape with rounded corners. The pixels PX and the wiring for applying the electrical signal to the pixels PX may be positioned or arranged in the display area DA. The pixels PX may be arranged in a predetermined pattern in a first direction D1 and a second direction D2 intersecting the first direction D1. Each of the pixels PX may include a display element and a pixel circuit for driving the display element. For example, the display element may include an organic light emitting diode (OLED), an inorganic light emitting diode (LED), a micro LED, a nano light emitting diode (NED), or a quantum dot (QD)-LED. The pixel circuit may include a transistor and a capacitor.

[0059] The signal line for applying an electrical signal to the pixel PX may include a scan line and a data line. Each of the scan lines may extend in a first direction D1, and each of the data lines may extend in a second direction D2. The scan lines may be arranged in rows and may transmit scan signals to the pixels PX, and the data lines may be arranged in columns and may transmit data signals to the pixels PX. Each of the pixels PX may be connected to at least one corresponding scan line among the scan lines and at least one corresponding data line among the data lines.

[0060] The display area DA may include the sensing area SA. The display area DA and the sensing area SA may overlap each other, and at least a portion of the display area DA may be configured as the sensing area SA. The term overlap may include layer, stack, facing or facing, extending across, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The term "non-overlapping" may include "separated from" or "separately disposed from" or "deviation from", as well as any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art.

[0061] like Figure 1 As shown in , a portion of the display area DA may be set as the sensing area SA, or only a portion of the display area DA may be set as the sensing area SA. Figure 2 As shown in , the entire display area DA can be set as the sensing area SA. In an embodiment, the display area DA and the sensing area SA can be positioned or arranged substantially adjacent to each other, so that some parts of the display area DA and the sensing area SA can overlap with each other, or only parts of the display area DA and the sensing area SA can overlap with each other. The pixels PX and the sensors SU can be positioned or arranged in the sensing area SA. Each of the sensors SU can be a sensor for sensing biometric information of a human body related to at least one of, for example, a user's heartbeat, stress, fingerprint, oxygen saturation, blood pressure, blood sugar level, temperature, and skin color. The following description will be made assuming that the sensor SU senses a fingerprint. The sensor SU can be an optical sensor including a light receiving device.

[0062] The sensor SU may be disposed on a surface (e.g., a rear surface) opposite to a surface (e.g., a front surface) of the display panel 10 on which an image is displayed, among the two surfaces of the display panel 10. The sensor SU may use a display element of at least one pixel PX substantially positioned or disposed around the sensor SU as a light source. For example, the sensor SU may overlap with at least some of the pixels PX positioned or disposed in the sensing area SA, or may be positioned or disposed around the pixels PX. For example, at least some of the sensors SU may be positioned or disposed to overlap with a non-luminous area between adjacent pixels PX positioned or disposed in the sensing area SA. The pixels PX and the sensors SU may be arranged at a predetermined ratio according to the sensing resolution. For example, the resolution of the sensor SU may be smaller than the resolution of the pixel PX.

[0063] The peripheral area PPA where no image is displayed may surround the display area DA. The peripheral area PPA where the pixel PX may not be located or disposed may include a pad area to which various electronic devices (eg, a printed circuit board) may be electrically attached.

[0064] A driver for applying an electrical signal to the pixels PX of the display area DA may be positioned or disposed in the peripheral area PPA. The driver may be formed as a separate integrated circuit chip or one integrated circuit chip and may be directly mounted in the peripheral area PPA, may be mounted on a flexible printed circuit film, may be attached to the substrate 100 as a tape carrier package (TCP), or may be directly formed on the substrate 100. The peripheral area PPA may include a power line that provides power such as a driving voltage and a common voltage.

[0065] Despite Figure 1 and Figure 2 Although not shown in the drawings, the display panel 10 may include a bending area and may be bent at the bending area, wherein the bending area is a part of the peripheral area PPA.

[0066] FIG. 3A to FIG. 3H is a plan view showing the size and / or arrangement of pixels and sensors according to an embodiment of the present disclosure. The resolution may be a function of the ratio and arrangement of the sensors SU relative to the pixels PX. FIG. 3A to FIG. 3H In the embodiment, the arrangement of the pixels PX may correspond to an arrangement of pixel regions of the pixels PX being positioned or arranged or an arrangement of light emitting regions of display elements of the pixels PX being positioned or arranged.

[0067] Reference Figure 3A, the sensors SU in the sensing area SA may be positioned or arranged to have the same resolution as the resolution of the pixels PX. For example, in the sensing area SA, the same number of sensors SU as the pixels PX may be arranged. According to an embodiment, at least a portion of each of the sensors SU may overlap with at least one pixel PX. For example, each of the sensors SU may be positioned or arranged in one pixel area where one pixel PX may be positioned or arranged.

[0068] The pixel area can be Figure 3A substantially adjacent to each other as shown in , or may be as shown in FIG. 3B to FIG. 3H As shown in FIG. Figure 3A As shown in FIG, the pixel area can be divided by the scan line SL and the data line DL. FIG. 3B to FIG. 3H The scan lines SL and the data lines DL are not shown in the figure, but the scan lines SL and the data lines DL may be positioned or disposed in each pixel region.

[0069] Reference Figure 3B , the pixels PX may be spaced apart from each other, and the sensors SU may be positioned or arranged in the sensing area SA to have the same resolution as that of the pixels PX. For example, in the sensing area SA, the same number of sensors SU as the number of pixels PX may be arranged. According to an embodiment, at least a portion of each of the sensors SU may overlap with at least one pixel PX. For example, each of the sensors SU may be positioned or arranged in one pixel area.

[0070] Reference Figure 3C , a greater number of sensors SU than the number of pixels PX disposed in the sensing area SA may be disposed, and a greater number of sensors SU than the number of pixels PX disposed in the sensing area SA may be positioned or disposed in the sensing area SA to have a higher resolution than the resolution of the pixels PX. For example, each of the sensors SU may have a size smaller than that of each of the pixels PX.

[0071] Reference Figure 3D , a smaller number of sensors SU than pixels PX (i.e., fewer sensors SU than pixels PX) may be provided, and a smaller number of sensors SU than pixels PX may be arranged at predetermined intervals in the sensing area SA. For example, the sensors SU may be positioned or provided in an area that may form some pixels PX among the pixels PX positioned or provided in the sensing area SA. Figure 3D In the embodiment, one sensor SU may be positioned or arranged for every four pixels PX positioned or arranged in the sensing area SA, but the present disclosure is not limited thereto. That is, the number (or resolution) of sensors SU positioned or arranged in the sensing area SA may be modified in various ways.

[0072] Reference Figure 3E Each of the sensors SU may have a size substantially larger than that of each of the pixels PX, and may be positioned or arranged to cover an area where pixels PX corresponding to each of the sensors SU may be formed. For example, a smaller number of sensors SU than pixels PX or fewer sensors SU may be provided, and a smaller number of sensors SU than pixels PX or fewer sensors SU may be positioned or arranged in the sensing area SA at predetermined intervals.

[0073] Reference Figure 3F , each of the sensors SU may have a size substantially large enough to cover several pixels PX, and may be positioned or arranged to overlap several pixels PX.

[0074] Reference Figure 3G , each of the sensors SU may be positioned or disposed in a region substantially between adjacent pixels PX, and may be positioned or disposed such that at least a portion of the sensor SU overlaps the adjacent pixel PX.

[0075] Reference Figure 3H , each of the sensors SU may be positioned or disposed in a non-light emitting region substantially between adjacent pixels PX, and may not overlap with or be offset from the pixel PX.

[0076] The embodiments of the present disclosure are not limited to FIG. 3A to FIG. 3H In the embodiment of the present invention, the size, number, resolution and position, arrangement and / or placement of the sensors SU located or arranged in the sensing area SA, and / or the placement of the sensors SU relative to the pixels PX may be modified in various ways. For example, the size, number, resolution and position of the sensors SU and the placement of the sensors SU relative to the pixels PX may be determined in consideration of various factors such as the amount of received light required to sense biometric information, resolution and / or crosstalk.

[0077] Despite Figures 3A to 3H The sensors SU may be arranged in a regular array in the sensing area SA, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the sensors SU may be irregularly distributed in the sensing area SA.

[0078] Figure 4 is shown for use by Figure 1 A view of a configuration of a display device to sense biometric information.

[0079] The display device may include a sensor layer 200, an opaque layer 300, and a pixel layer 400. The pixel layer 400 may be positioned or disposed on a first surface (e.g., a front surface) of the substrate 100, and the sensor layer 200 may be positioned or disposed on a second surface (e.g., a rear surface) of the substrate 100 opposite to the first surface. The opaque layer 300 may be positioned or disposed between the sensor layer 200 and the pixel layer 400. The opaque layer 300 may be positioned or disposed between the substrate 100 and the pixel layer 400. The display device may include a functional layer 500 positioned or disposed on the pixel layer 400. The functional layer 500 may include one or more layers.

[0080] The sensor layer 200 may include a sensor SU. The pixel layer 400 may include a pixel PX and may include a circuit layer and a display element layer, the circuit layer including a pixel circuit of the pixel PX, and the display element layer being positioned or disposed on the circuit layer and including a display element. The opaque layer 300 may have a hole 310. The hole 310 of the opaque layer 300 may correspond to a light-transmitting area of ​​a pixel PX emitting light of a specific color. Such a pixel PX may be among pixels PX emitting light of different colors.

[0081] When the object OB contacts the top surface of the display device or is adjacent to the top surface of the display device, the light L emitted from the pixel PX of the pixel layer 400 may be reflected by the object OB, and the reflected light RL may pass through the hole 310 of the opaque layer 300 and may be sensed by the sensor SU of the sensor layer 200. The object OB may be a body part such as a hand or a finger. The display device may obtain biometric information based on a sensing signal from the sensor SU. The display device may display the biometric information as an image by using the pixel PX.

[0082] Figure 5 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0083] Figure 5 1 is a schematic cross-sectional view showing a pixel PX and a sensor SU positioned or disposed in a sensing area SA overlapping with a display area DA of a display panel 10. Figure 4 and Figure 5 , the opaque layer 300 and the pixel layer 400 may be disposed on the front surface of the substrate 100 .

[0084] The substrate 100 may be formed of any of various materials such as a glass material, a metal material, or a plastic material. According to an embodiment, the substrate 100 may be a flexible substrate and may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 may include a plurality of layers. For example, the substrate 100 may have a multilayer structure including a base layer and an inorganic layer, and the base layer includes the above-mentioned polymer resin. For example, the substrate 100 may include a first base layer, a first inorganic layer, a second base layer, and a second inorganic layer that may be stacked sequentially. Each of the first base layer and the second base layer may include the above-mentioned polymer resin. Each of the first inorganic layer and the second inorganic layer may have a single-layer or multilayer structure including an inorganic material, and the inorganic material may be silicon nitride (SiN x ) and / or silicon oxide (SiO x ), wherein each of the first inorganic layer and the second inorganic layer is a barrier layer that can prevent penetration of foreign materials.

[0085] The buffer layer 101 may be positioned or disposed on the substrate 100. The buffer layer 101 may include an inorganic material (such as silicon nitride or silicon oxide), an organic material, or a combination of an organic material and an inorganic material, and may have a single-layer or multi-layer structure including an inorganic material and an organic material. In some embodiments, the second inorganic material of the substrate 100 may be a part of the buffer layer 101 having a multi-layer structure. The buffer layer 101 may be omitted. The opaque layer 300 may be positioned or disposed on the buffer layer 101.

[0086] The opaque layer 300 may be positioned or arranged to correspond to at least the sensing area SA. The opaque layer 300 may be positioned or arranged to cover the entire display area DA. The opaque layer 300 may extend to the peripheral area PPA. The opaque layer 300 may prevent light incident from outside the display device and light emitted from the display element from reaching the sensor SU. The opaque layer 300 may have a hole 310 passing through the opaque layer 300. The hole 310 may be a transmissor through which the reflected light RL from the pixel PX passes and reaches the sensor SU. The hole 310 may be formed in a predetermined pattern according to the arrangement of the pixel PX.

[0087] The opaque layer 300 may include a light-shielding material. The opaque layer 300 may include a light-shielding metal. For example, the opaque layer 300 may include at least one of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti) and alloys thereof, and may have a single-layer or multi-layer structure. In an embodiment, the opaque layer 300 may have a single-layer structure including Mo. In another embodiment, the opaque layer 300 may have a three-layer structure including a first layer formed of Ti, a second layer formed of Al, and a third layer formed of Ti that may be sequentially stacked on the buffer layer 101. The opaque layer 300 may include any other suitable material as will be appreciated and understood by those of ordinary skill in the art.

[0088] The transparent insulating material may be positioned or disposed in the hole 310 of the opaque layer 300. In an embodiment, the hole 310 of the opaque layer 300 may be filled with the first insulating layer 111 and / or the second insulating layer 112. In another embodiment, the hole 310 of the opaque layer 300 may be filled with a transparent insulating material separate from the first insulating layer 111 and / or the second insulating layer 112.

[0089] Despite Figure 5 The opaque layer 300 may be positioned or disposed on the buffer layer 101, but the present disclosure is not limited thereto. For example, the opaque layer 300 may be positioned or disposed between layers of the substrate 100 or between the substrate 100 and the buffer layer 101, or may have a multilayer structure including layers positioned or disposed at different positions.

[0090] Return to reference Figure 5 , the first insulating layer 111 may be positioned or disposed on the opaque layer 300. The first insulating layer 111 may include an inorganic material such as an oxide or a nitride or an organic material or a combination of an inorganic material and an organic material, and may have a single layer or multilayer structure including the inorganic material and the organic material.

[0091] A pixel PX including a pixel circuit PC including a thin film transistor (TFT) 430 and a capacitor 470 and a display element 450 connected to the pixel circuit PC may be disposed on the first insulating layer 111. The display element 450 may be an organic light emitting diode (OLED).

[0092] The TFT 430 may include a semiconductor layer 431, a gate electrode 432, a source electrode 433, and a drain electrode 434. The semiconductor layer 431 may include a source region, a drain region, and a channel region between the source region and the drain region. The source electrode 433 and the drain electrode 434 may contact the source region and the drain region of the semiconductor layer 431, respectively. The second insulating layer 112 may be positioned or disposed between the semiconductor layer 431 and the gate electrode 432. The third insulating layer 113 and the fourth insulating layer 114 may be positioned or disposed between the gate electrode 432 and the source electrode 433 and between the gate electrode 432 and the drain electrode 434. Each of the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. Each of the second insulating layer 112 , the third insulating layer 113 , and the fourth insulating layer 114 including the inorganic insulating material may have a single-layer or multi-layer structure including one or more of the above-mentioned materials.

[0093] The capacitor 470 may include a lower electrode 471 positioned or disposed on the same layer as that of the gate electrode 432 of the TFT 430 and an upper electrode 472 covering the lower electrode 471 .

[0094] The lower electrode 471 of the capacitor 470 may be integrally formed with the gate electrode 432 of the TFT 430. For example, the gate electrode 432 of the TFT 430 may be used as the lower electrode 471 of the capacitor 470. The lower electrode 471 of the capacitor 470 may overlap with the upper electrode 472 with the third insulating layer 113 therebetween. For example, the third insulating layer 113 may be used as a dielectric layer of the capacitor 470.

[0095] Despite Figure 5 The capacitor 470 overlaps with the TFT 430, but the present disclosure is not limited thereto. Various modifications may be made; for example, the capacitor 470 may be positioned or disposed so as not to overlap with the TFT 430. The fourth insulating layer 114 may be positioned or disposed on the capacitor 470.

[0096] The fifth insulating layer 115 covering the TFT 430 may include a planarizing insulating layer, and may have a single-layer or multi-layer structure including an organic insulating material. The fifth insulating layer 115 may include an organic insulating material, such as a general polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof. In an embodiment, the fifth insulating layer 115 may include polyimide (PI). In an embodiment, the fifth insulating layer 115 may have a single-layer or multi-layer structure including an inorganic insulating material.

[0097] The pixel electrode 451 may be electrically connected to the source electrode 433 or the drain electrode 434 of the TFT 430. The pixel electrode 451 may include a reflective film including a reflective conductive material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an embodiment, the pixel electrode 451 may include a transparent conductive film including a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one transparent conductive oxide selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an implementation, the pixel electrode 451 may have a structure in which a reflective film and a transparent conductive film may be stacked.

[0098] The edge of the pixel electrode 451 may be covered by the sixth insulating layer 116 positioned or disposed on the fifth insulating layer 115. For example, the sixth insulating layer 116 may be a pixel defining layer that defines a light emitting region by having an opening OP, wherein a portion of the pixel electrode 451 may be exposed through the opening OP. The opening OP of the sixth insulating layer 116 where the light emitting layer is positioned or disposed may correspond to the light emitting region of the pixel PX. The sixth insulating layer 116 may include an organic insulating film. The sixth insulating layer 116 may include a polyacrylic compound, a PI-based compound, a Teflon-based compound, or a polyimide such as polyimide. TM of fluorocarbons or benzocyclobutene compounds.

[0099] The intermediate layer 452 may be positioned or disposed on the pixel electrode 451, and may include at least a light emitting layer (EML). In an embodiment, the intermediate layer 452 may include at least one EML, and may include one or more functional layers of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). The EML may be a red EML, a green EML, or a blue EML. The EML may have a multilayer structure in which a red EML, a green EML, and a blue EML may be stacked to emit white light, or may have a single-layer structure including a red light emitting material, a green light emitting material, and a blue light emitting material. The functional layer may include a layer integrally formed on the pixel electrode 451, or may include a layer patterned to correspond to each of the pixel electrodes 451.

[0100] The opposing electrode 453 may be positioned or disposed on the intermediate layer 452, and may be formed of any of various conductive materials. For example, the opposing electrode 453 may include a semi-transmissive reflective film including at least one selected from the group consisting of lithium (Li), calcium (Ca), lithium fluoride (LiF), Al, Mg, and Ag, or may include a transparent metal oxide such as ITO, IZO, or ZnO, and may have a single-layer or multi-layer structure.

[0101] The encapsulation layer 410 may be positioned or disposed on the opposite electrode 453, and may protect the display device from external materials, moisture, etc. In an embodiment, the encapsulation layer 410 may include an encapsulation substrate attached to the substrate 100. The encapsulation substrate may be formed of any of various materials such as a glass material, a metal material, or a plastic material. In an embodiment, the encapsulation layer 410 may include a thin film encapsulation layer including at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0102] The functional layer 500 may be positioned or disposed on the encapsulation layer 410. The functional layer 500 may include: an input sensing member for sensing a touch input; an anti-reflection member including a polarizer, a retarder, a color filter, or a black matrix; and a transparent window.

[0103] The sensor layer 200 may be positioned or disposed on the rear surface of the substrate 100. The sensor layer 200 may be formed as a unit separate from the pixel layer 400, and may be coupled to the rear surface of the substrate 100.

[0104] The sensor layer 200 may include sensors SU disposed on a base layer 201 .

[0105] The base layer 201 may correspond to the shape of the substrate 100 of the display panel 10 and may be provided to have substantially the same shape as the substrate 100. The base layer 201 may include a substrate or a film formed of an insulating material such as a polymer resin, a metal material, or a glass material.

[0106] The buffer layer 210 may be disposed on the base layer 201. The buffer layer 210 may include an inorganic material (such as silicon nitride or silicon oxide) or an organic material or a combination of an inorganic material and an organic material, and may have a single layer or multilayer structure including an inorganic material and an organic material. The buffer layer 210 may be omitted.

[0107] A sensor SU including a TFT 230, a photodiode 250 as a light receiving device, and a capacitor 270 may be disposed on the buffer layer 210. The sensor SU may be an optical sensor that senses biometric information by receiving reflected light RL obtained when light L emitted from a display element 450 of a pixel PX is reflected by an object OB.

[0108] The TFT 230 may include a semiconductor layer 231, a gate electrode 232, a source electrode 233, and a drain electrode 234. The semiconductor layer 231 may include a source region, a drain region, and a channel region between the source region and the drain region. The source electrode 233 and the drain electrode 234 may contact the source region and the drain region of the semiconductor layer 231, respectively. The seventh insulating layer 211 may be positioned or disposed between the semiconductor layer 231 and the gate electrode 232. The eighth insulating layer 212 and the ninth insulating layer 213 may be positioned or disposed between the gate electrode 232 and the source electrode 233 and between the gate electrode 232 and the drain electrode 234. Each of the seventh insulating layer 211, the eighth insulating layer 212, and the ninth insulating layer 213 may have a single-layer or multi-layer structure including an inorganic insulating material.

[0109] The photodiode 250 may obtain biometric information by sensing the reflected light RL reflected from the object OB and passing through the hole 310 of the opaque layer 300. The photodiode 250 may include a first electrode 251, a semiconductor layer 252, a second electrode 253, and a bias electrode 254. The first electrode 251 may be electrically connected to the drain electrode 234 of the TFT 230. The second electrode 253 may include a transparent electrode. The bias electrode 254 may be connected to the second electrode 253 and may be electrically connected to the second electrode 253 through a contact hole in the ninth insulating layer 213 covering the second electrode 253.

[0110] The capacitor 270 may include a lower electrode 271 positioned or disposed on the same layer as the gate electrode 232 of the TFT 230 and an upper electrode 272 positioned or disposed on the same layer as the first electrode 251 of the photodiode 250 .

[0111] The tenth insulating layer 214 as a planarization insulating layer covering the TFT 230 and the photodiode 250 may have a single layer or a multilayer structure including an organic insulating material. In an embodiment, the tenth insulating layer 214 may have a single layer or a multilayer structure including an inorganic insulating material. An adhesive layer (not shown) for attaching the sensor layer 200 to the substrate 100 may be provided between the tenth insulating layer 214 and the rear surface of the substrate 100.

[0112] Fig. 6A and Figure 6B is a schematic diagram showing an equivalent circuit of one pixel of a display panel according to an embodiment of the present disclosure.

[0113] Reference Fig. 6A , the pixel PX includes a pixel circuit PC and an organic light emitting diode OLED, which is a display element connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel PX may emit red light, green light, blue light, or white light from the organic light emitting diode OLED.

[0114] The second transistor T2, which may be a switching transistor, may be connected to the scan line SL and the data line DL, and may transmit a data signal input from the data line DL to the first transistor T1 according to a switching voltage input from the scan line SL. The capacitor Cst may be connected to the second transistor T2 and the power supply voltage line PL, and may store a voltage corresponding to a difference between a voltage corresponding to the data signal received from the second transistor T2 and a first power supply voltage ELVDD supplied to the power supply voltage line PL. The power supply voltage line PL may be spaced apart from the scan line SL or the data line DL to be parallel to the scan line SL or the data line DL.

[0115] The first transistor T1, which may be a driving transistor, may be connected to the power supply voltage line PL and the capacitor Cst, and may control a driving current I flowing from the power supply voltage line PL through the organic light emitting diode OLED according to the value of a voltage stored in the capacitor Cst. oled . Since the driving current I oled , the organic light emitting diode OLED may emit light having a predetermined brightness. An opposite electrode (eg, a cathode) of the organic light emitting diode OLED may receive a second power voltage ELVSS.

[0116] Despite Fig. 6A The pixel circuit PC includes two transistors and one capacitor, but the present disclosure is not limited thereto. The number of transistors and the number of capacitors may be modified in various ways according to the design of the pixel circuit PC.

[0117] Reference Figure 6BAlthough signal lines (e.g., SL1, SL2, EL, and DL), initialization voltage lines VIL, and power supply voltage lines PL are provided for each pixel PX, the present disclosure is not limited thereto. In an embodiment, at least one of the signal lines (e.g., SL1, SL2, EL, and DL), the initialization voltage lines VIL, and / or the power supply voltage lines PL may be shared by adjacent pixels PX.

[0118] The signal line may include a first scan line SL1 transmitting a first scan signal GW, a second scan line SL2 transmitting a second scan signal GI, an emission control line EL transmitting an emission control signal EM, and a data line DL intersecting the first scan line SL1 and transmitting a data signal DATA. The second scan line SL2 may be connected to the first scan line SL1 of a next or previous row, and the second scan signal GI may be the first scan signal GW of the next or previous row.

[0119] The power supply voltage line PL may transmit the first power supply voltage ELVDD to the first transistor T1, and the initialization voltage line VIL may transmit the first power supply voltage ELVDD to the first transistor T1. Figure 5 The pixel electrode 451 in FIG. 4 and the initialization voltage VINT of the first transistor T1 are transmitted to the pixel PX.

[0120] The first scan line SL1, the second scan line SL2, the emission control line EL, and the initialization voltage line VIL may extend in the first direction D1 and may be spaced apart from each other in each row. The data line DL and the power supply voltage line PL may extend in the second direction D2 and may be spaced apart from each other in each column.

[0121] The pixel circuit PC of the pixel PX may include first to seventh transistors T1 to T7 and a capacitor Cst.

[0122] The first transistor T1 may be connected to the power supply voltage line PL through the fifth transistor T5, and may be electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 may be used as a driving transistor, and may receive a data signal DATA according to a switching operation of the second transistor T2, and drive a current I oled Provided to the organic light emitting diode OLED.

[0123] The second transistor T2 may be connected to the first scan line SL1 and the data line DL, may be turned on by the first scan signal GW received through the first scan line SL1 , and may perform a switching operation of transmitting a data signal DATA transmitted through the data line DL to the node N.

[0124] The third transistor T3 may be connected to the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 may be turned on by the first scan signal GW received through the first scan line SL1 and diode-connect the first transistor T1.

[0125] The fourth transistor T4 may be turned on by the second scan signal GI received through the second scan line SL2 , and may transfer the initialization voltage VINT from the initialization voltage line VIL to the gate electrode of the first transistor T1 and initialize the gate voltage of the first transistor T1 .

[0126] The fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously by the emission control signal EM received through the emission control line EL, and form a current path to drive the current I oled Current may flow from the power voltage line PL to the organic light emitting diode OLED through this path.

[0127] The seventh transistor T7 may be turned on by the second scan signal GI received through the second scan line SL2 and may transfer the initialization voltage VINT from the initialization voltage line VIL to the organic light emitting diode OLED and may initialize the organic light emitting diode OLED. The seventh transistor T7 may be omitted.

[0128] Despite Figure 6B The fourth transistor T4 and the seventh transistor T7 may be connected to the second scan line SL2, but the present disclosure is not limited thereto. In another embodiment, the fourth transistor T4 may be connected to the second scan line SL2, and the seventh transistor T7 may be connected to a separate wiring and may operate according to a signal transmitted to the wiring.

[0129] The capacitor Cst may be connected to the power voltage line PL and the gate electrode of the first transistor T1 , and may store or maintain a voltage corresponding to a difference between voltages of two terminals thereof to maintain a voltage applied to the gate electrode of the first transistor T1 .

[0130] The pixel electrode can receive the driving current I from the first transistor T1. oled The common electrode may receive a second power voltage ELVSS and may be used as a second electrode of the organic light emitting diode OLED.

[0131] Fig. 6A and Figure 6B The transistor, capacitor Cst and organic light emitting diode OLED can be realized as Figure 5 TFT 430, capacitor 470 and display element 450.

[0132] Despite Fig. 6A and Figure 6B The organic light emitting diode OLED is a display element, but the embodiments of the present disclosure are not limited thereto. Fig. 6A and Figure 6B Examples of display elements in may include light emitting diodes (LEDs), micro-LEDs, nano-light emitting diodes (NEDs), and quantum dot (QD)-LEDs.

[0133] 7A to 9B is a view showing the arrangement of a pixel circuit according to an embodiment of the present disclosure.

[0134] The pixels PX positioned or disposed in the display area DA of the substrate 100 may include a first pixel PX1 (see FIG. 1 ) that emits light of a first color. Fig.10 ), a second pixel PX2 emitting light of a second color (see Fig.10 ) and a third pixel PX3 emitting light of a third color (see Fig.10 ). The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeatedly arranged in a predetermined pattern in the first direction D1 and the second direction D2. In an embodiment, the first pixel PX1 may be a red pixel R, the second pixel PX2 may be a green pixel G, and the third pixel PX3 may be a blue pixel B (eg, Fig.10 In another embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a blue pixel, and the third pixel PX3 may be a green pixel.

[0135] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include Fig. 6A and Figure 6B The pixel circuit PC and the organic light emitting diode OLED shown in FIG. 1 , wherein the organic light emitting diode OLED is a display element electrically connected to the pixel circuit PC.

[0136] The display area DA of the substrate 100 may include a pixel area where the pixel PX is located or arranged. The pixel area may include a first pixel area PA1, a second pixel area PA2, and a third pixel area PA3. The first pixel circuit PC1 of the first pixel PX1 may be located or arranged in the first pixel area PA1. The second pixel circuit PC2 of the second pixel PX2 may be located or arranged in the second pixel area PA2. The third pixel circuit PC3 of the third pixel PX3 may be located or arranged in the third pixel area PA3.

[0137] In an embodiment, if Fig. 7AAs shown in FIG. 1 , in row iN, a first pixel region PA1 of a first column 1M, a second pixel region PA2 of a second column 2M substantially adjacent to the first pixel region PA1, and a third pixel region PA3 of a third column 3M substantially adjacent to the second pixel region PA2 may be repeatedly arranged in a first direction D1 (row direction). A first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 may be repeatedly arranged in the first pixel region PA1, the second pixel region PA2, and the third pixel region PA3.

[0138] In an embodiment, if Figure 7B As shown in FIG. 1 , in row iN, a first pixel region PA1 of a first column 1M, a second pixel region PA2 of a second column 2M substantially adjacent to the first pixel region PA1, a third pixel region PA3 of a third column 3M substantially adjacent to the second pixel region PA2, and a second pixel region PA2 of a fourth column 4M substantially adjacent to the third pixel region PA3 may be repeatedly arranged in the first direction D1. A first pixel circuit PC1, a second pixel circuit PC2, a third pixel circuit PC3, and a second pixel circuit PC2 may be repeatedly arranged in the first pixel region PA1, the second pixel region PA2, the third pixel region PA3, and the second pixel region PA2.

[0139] Each of the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3 may include at least one light-transmitting area 310'. The light-transmitting area 310' may be an area corresponding to a gap between circuit devices constituting the pixel PX and / or wiring connected to the circuit devices in the pixel area. For example, the light-transmitting area 310' may be an area in the pixel area where no light-shielding element is positioned or provided, such as a circuit device constituting the pixel PX and / or wiring connected to the circuit device.

[0140] In an embodiment of the present disclosure, the opaque layer 300 may be positioned or disposed on the substrate 100, and may be positioned or disposed under the circuit layer including the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The opaque layer 300 may have a hole 310. The position of the hole 310 of the opaque layer 300 may correspond to the position of the light-transmitting area 310' of the pixel area of ​​the pixel PX emitting light of a specific color positioned or disposed among the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3. The hole 310 of the opaque layer 300 may overlap with the light-transmitting area 310' of the pixel area of ​​the pixel PX emitting light of a specific color positioned or disposed, and may not overlap with the light-transmitting area 310' of the remaining pixel area. That is, the opaque layer 300 may have a hole pattern corresponding to the arrangement pattern of the pixel area of ​​the pixel PX emitting light of a specific color positioned or disposed. For example, the hole 310 of the opaque layer 300 may be repeatedly formed in a predetermined pattern and regular intervals in the first direction D1 and the second direction D2 in the display area DA.

[0141] In an embodiment, if Fig. 7A and Figure 7B As shown in FIG. 1 , the opaque layer 300 may have a hole 310 at a position corresponding to the light-transmitting region 310 ′ of the first pixel region PA1. Fig. 8A and Figure 8B As shown in , the opaque layer 300 may have a hole 310 at a position corresponding to the light-transmitting area 310' of the second pixel area PA2. Fig.9A and Fig. 9B As shown in FIG. 1 , the opaque layer 300 may have a hole 310 at a position corresponding to the light-transmitting region 310 ′ of the third pixel region PA3 .

[0142] When the holes 310 of the opaque layer 300 are formed at regular intervals, the holes 310 of the opaque layer 300 may correspond to light-transmitting areas of pixels PX that emit light of different colors. For example, some of the holes 310 of the opaque layer 300 may correspond to light-transmitting areas of the first pixel area PA1, some of the holes 310 may correspond to light-transmitting areas of the second pixel area PA2, and other holes 310 of the holes 310 may correspond to light-transmitting areas of the third pixel area PA3. Brightness deviation and color deviation may occur between the pixel PX having a light-transmitting area corresponding to the hole 310 and the adjacent pixel PX having a light-transmitting area not corresponding to the hole 310. This is because the influence of the opaque layer 300 on the electrode layer connected to the TFT (e.g., the driving TFT) may change due to the holes 310 of the opaque layer 300.

[0143] However, according to an embodiment of the present disclosure, since the holes 310 of the opaque layer 300 are formed at regular intervals and at positions corresponding to light-transmitting regions of a specific or predetermined pixel region, brightness deviation and color deviation between pixels PX may be prevented or minimized.

[0144] Each of the display elements of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be positioned or arranged on the pixel circuit. The display element can be directly positioned or arranged on the pixel circuit of the corresponding pixel to overlap with the pixel circuit, or can be positioned or arranged to overlap with the pixel circuit of another pixel, and the pixel circuit of the other pixel can deviate from the pixel circuit of the corresponding pixel and can be positioned or arranged in an adjacent row or column. That is, the display element can be positioned or arranged in the corresponding pixel area, or a part of the display element can be positioned or arranged in another pixel area substantially adjacent to the corresponding pixel area.

[0145] Fig.10 is a view showing the arrangement of light emitting regions of pixels of a display device according to an embodiment of the present disclosure.

[0146] Fig.10 The light emitting area of ​​each of the first pixel PX1, the second pixel PX2 and the third pixel PX3 is shown. The light emitting area is an area where the light emitting layer (EML) of the display element is positioned or disposed. The opening of the pixel defining layer or the portion of the pixel electrode exposed by the opening of the pixel defining layer can be defined as the light emitting area.

[0147] The first pixel PX1 may include a first light emitting region EA1, the second pixel PX2 may include a second light emitting region EA2, and the third pixel PX3 may include a third light emitting region EA3.

[0148] The first light emitting area EA1 of the first pixel PX1 and the third light emitting area EA3 of the third pixel PX3 may be alternately arranged in the first sub-row 1SN of each row in rows 1N, 2N, ... in the first direction D1, and the second light emitting area EA2 of the second pixel PX2 may be repeatedly arranged in the second sub-row 2SN in the first direction D1. The first light emitting area EA1 of the first pixel PX1, the second light emitting area EA2 of the second pixel PX2, the third light emitting area EA3 of the third pixel PX3, and the second light emitting area EA2 of the second pixel PX2 may be repeatedly arranged in each row in rows 1N, 2N, ... in a zigzag manner or pattern. Such manner or pattern may be other arrangements as will be appreciated and understood by those of ordinary skill in the art.

[0149] In odd columns, the first light emitting area EA1 of the first pixel PX1 and the third light emitting area EA3 of the third pixel PX3 may be alternately arranged in the second direction D2. In even columns, the second light emitting area EA2 of the second pixel PX2 may be repeatedly arranged in the second direction D2. For example, in the first column 1M, the first light emitting area EA1 of the first pixel PX1 and the third light emitting area EA3 of the third pixel PX3 may be alternately arranged in the second direction D2. In the second column 2M substantially adjacent to the first column 1M, the second light emitting area EA2 of the second pixel PX2 may be repeatedly arranged in the second direction D2. In the third column 3M substantially adjacent to the second column 2M, the third light emitting area EA3 of the third pixel PX3 and the first light emitting area EA1 of the first pixel PX1 may be alternately arranged in the second direction D2 in a manner opposite to that of the first column 1M.

[0150] The first light emitting area EA1 of the first pixel PX1, the second light emitting area EA2 of the second pixel PX2, and the third light emitting area EA3 of the third pixel PX3 may have different sizes. In an embodiment, the third light emitting area EA3 of the third pixel PX3 may have a size larger than the size of the first light emitting area EA1 of the first pixel PX1. The third light emitting area EA3 of the third pixel PX3 may have a size larger than the size of the second light emitting area EA2 of the second pixel PX2. The first light emitting area EA1 of the first pixel PX1 may have a size larger than the size of the second light emitting area EA2 of the second pixel PX2. In an embodiment, the third light emitting area EA3 of the third pixel PX3 may have a size that is the same as or similar to the size of the first light emitting area EA1 of the first pixel PX1. The present disclosure is not limited thereto. For example, various modifications may be made; for example, the first light emitting area EA1 of the first pixel PX1 may be larger than each of the second light emitting area EA2 of the second pixel PX2 and the third light emitting area EA3 of the third pixel PX3.

[0151] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a polygonal shape (such as a quadrilateral shape or an octagonal shape), a circular shape, or an elliptical shape, and examples of polygonal shapes may include shapes with rounded corners. Other shapes are also feasible as will be appreciated and understood by those of ordinary skill in the art, while being consistent with the spirit and scope of the present invention.

[0152] The first light emitting area EA1 of the first pixel PX1 may be positioned or disposed in the first pixel area PA1, or a portion of the first light emitting area EA1 may be positioned or disposed in the second pixel area PA2 or the third pixel area PA3 substantially adjacent to the first pixel area PA1. The second light emitting area EA2 of the second pixel PX2 may be positioned or disposed in the second pixel area PA2, or a portion of the second light emitting area EA2 may be positioned or disposed in the first pixel area PA1 or the third pixel area PA3 substantially adjacent to the second pixel area PA2. The third light emitting area EA3 of the third pixel PX3 may be positioned or disposed in the third pixel area PA3, or a portion of the third light emitting area EA3 may be positioned or disposed in the first pixel area PA1 or the second pixel area PA2 substantially adjacent to the third pixel area PA3.

[0153] Fig.11 is a view showing the positions of transistors and capacitors in a pixel circuit according to an embodiment of the present disclosure. Fig.12 and Fig.13 is a plan view showing the positions of holes of an opaque layer and light emitting areas according to an embodiment of the present disclosure.

[0154] Fig.11 is a view showing a pixel circuit PC positioned or arranged in a pixel region. Fig.11 The pixel circuit PC of FIG. 1 may be applied to each of the first pixel circuit PC1 , the second pixel circuit PC2 , and the third pixel circuit PC3 of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 . Fig.11 The display elements located above the pixel circuit PC are not shown.

[0155] The pixel circuit PC of the pixel PX may include a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Each of the first transistor T1 to the seventh transistor T7 may include a semiconductor layer and a gate electrode, and the gate electrode is positioned or disposed at a position corresponding to the channel region of the semiconductor layer and insulated from the semiconductor layer. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be arranged along the semiconductor layer 1130. That is, the semiconductor layers of the first transistor T1 to the seventh transistor T7 may be connected to each other and may be bent in any of various shapes.

[0156] The semiconductor layer 1130 may include a channel region and a source region and a drain region located at both sides of the channel region, and the source region and the drain region may correspond to a source electrode and a drain electrode of a corresponding transistor, respectively.

[0157] The first transistor T1 may include a gate electrode G1 overlapping a channel region, and first and second electrodes E11 and E12 located at both sides of the gate electrode G1. The channel region overlapping the gate electrode G1 may have a bent shape to form a long channel in a narrow space.

[0158] The second transistor T2 may include a gate electrode G2 overlapping a channel region, and first and second electrodes E21 and E22 located at both sides of the channel region. The second electrode E22 may be connected to the first electrode E11 of the first transistor T1.

[0159] The third transistor T3 may be a double transistor and may include a gate electrode G3 overlapping two channel regions and may include a first electrode E31 and a second electrode E32 positioned or disposed at both sides of the channel region. The third transistor T3 may be connected to the gate electrode G1 of the first transistor T1 through a node connection line 1174 .

[0160] The fourth transistor T4 , which may be a double transistor, may include a gate electrode G4 overlapping two channel regions, and first and second electrodes E41 and E42 positioned or disposed at both sides.

[0161] The fifth transistor T5 may include a gate electrode G5 overlapping a channel region, and first and second electrodes E51 and E52 positioned or disposed at both sides of the channel region. The second electrode E52 may be connected to the first electrode E11 of the first transistor T1.

[0162] The sixth transistor T6 may include a gate electrode G6 overlapping a channel region, and first and second electrodes E61 and E62 positioned or disposed at both sides of the channel region. The first electrode E61 may be connected to the second electrode E12 of the first transistor T1.

[0163] The seventh transistor T7 may include a gate electrode G7 overlapping a channel region, and first and second electrodes E71 and E72 positioned or disposed at both sides of the channel region.

[0164] The first scan line SL1, the second scan line SL2, the emission control line EL, and the gate electrode G1 of the first transistor T1 may be positioned or disposed on the semiconductor layer 1130 with an insulating layer (or insulating layers) therebetween.

[0165] Each of the first scan line SL1, the second scan line SL2, and the emission control line EL may extend in the first direction D1. Portions of the first scan line SL1 may correspond to the gate electrode G2 of the second transistor T2 and the gate electrode G3 of the third transistor T3. Portions of the second scan line SL2 may correspond to the gate electrode G4 of the fourth transistor T4 and the gate electrode G7 of the seventh transistor T7. Portions of the emission control line EL may correspond to the gate electrode G5 of the fifth transistor T5 and the gate electrode G6 of the sixth transistor T6.

[0166] The gate electrode G1 of the first transistor T1 , which may be an island electrode, may be connected to the third transistor T3 through a node connection line 1174 .

[0167] The electrode voltage line HL may be positioned or disposed on the first scan line SL1, the second scan line SL2, the emission control line EL, and the gate electrode G2 of the first transistor T1 with an insulating layer (or insulating layers) therebetween.

[0168] The electrode voltage line HL may extend in the first direction D1 to intersect the data line DL and the power supply voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the gate electrode G1 of the first transistor T1 and may form a capacitor Cst together with the gate electrode G1 of the first transistor T1. For example, the gate electrode G1 of the first transistor T1 may become a first electrode CE1 of the capacitor Cst, and a portion of the electrode voltage line HL may become a second electrode CE2 of the capacitor Cst.

[0169] The second electrode CE2 of the capacitor Cst may be electrically connected to the power supply voltage line PL. The electrode voltage line HL may be connected to the power supply voltage line PL positioned or disposed on the electrode voltage line HL through the contact hole CNT. The electrode voltage line HL may have the same voltage level as that of the power supply voltage line PL. The power supply voltage line PL may be a power supply voltage line in the second direction D2, and the electrode voltage line HL may be a power supply voltage line in the first direction D1.

[0170] The initialization voltage line VIL may extend in the first direction D1 . The initialization voltage line VIL may be connected to the fourth transistor T4 and the seventh transistor T7 through an initialization connection line 1173 .

[0171] The initialization voltage line VIL and the electrode voltage line HL may be positioned or disposed on the same layer and may include the same material. Fig.11 The initialization voltage line VIL and the electrode voltage line HL may be positioned or disposed on the same layer, but in an embodiment, the initialization voltage line VIL and the pixel electrode (eg, Figure 5 The pixel electrode 451) can be positioned or arranged on the same layer.

[0172] The data line DL, the power voltage line PL, the initialization connection line 1173, and the node connection line 1174 may be positioned or disposed on the electrode voltage line HL with an insulating layer (or insulating layers) therebetween.

[0173] Each of the data line DL and the power voltage line PL may extend in the second direction D2.

[0174] The data line DL may be connected to the first electrode E21 of the second transistor T2 through the contact hole 1154. A portion of the data line DL may correspond to the first electrode E21 of the second transistor T2.

[0175] The power supply voltage line PL may be connected to the electrode voltage line HL through the contact hole CNT. The power supply voltage line PL may be connected to the fifth transistor T5 through the contact hole 1155. The power supply voltage line PL may be connected to the first electrode E51 of the fifth transistor T5 through the contact hole 1155. Fig.11 The middle power supply voltage line PL has a single-layer structure and can be positioned or disposed on the same layer as the data line DL, but in an embodiment, the power supply voltage line PL can have a two-layer structure, which includes a lower power supply voltage line positioned or disposed on the same layer as the data line DL and an upper power supply voltage line positioned or disposed above the lower power supply voltage line. An insulating layer (or multiple insulating layers) can be positioned or disposed between the lower power supply voltage line and the upper power supply voltage line. For example, the insulating layer (or multiple insulating layers) can be positioned or disposed between the upper power supply voltage line and the pixel electrode.

[0176] One end of the initialization connection line 1173 may be connected to the fourth transistor T4 and the seventh transistor T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VIL through the contact hole 1151 .

[0177] One end of the node connection line 1174 may be connected to the second electrode E32 of the third transistor T3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the gate electrode G1 of the first transistor T1 through the contact hole 1157 .

[0178] Display element 450 (see Figure 5) can be positioned or arranged on the data line DL, the power supply voltage line PL, the initialization connection line 1173 and the node connection line 1174, and the insulating layer (or multiple insulating layers) are located between them. The pixel electrode 451 can be connected to the sixth transistor T6 and can be connected to the first transistor T1. The pixel electrode 451 can be connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 can be connected to the second electrode E62 of the sixth transistor T6 through the contact hole 1153. The pixel electrode 451 can overlap with at least one of the first transistor T1 to the seventh transistor T7 and the capacitor Cst. The intermediate layer 452 including the EML can be positioned or arranged on the pixel electrode 451. As described above, the opening of the pixel defining layer or the pixel electrode 451 is positioned or the portion of the light emitting layer is set to be defined as a light emitting area, wherein the pixel defining layer exposes a portion of the pixel electrode 451 and covers the edge of the pixel electrode 451.

[0179] exist Fig.11 In the embodiment, the seventh transistor T7 provided in the pixel circuit PC of the pixel PX in the previous row can be electrically connected to the second scan line SL2 of the pixel PX in the current row. That is, the seventh transistor T7 of the pixel PX in the current row can be connected to the second scan line provided in the pixel circuit PC of the pixel PX in the next row. Figure 6B As shown in FIG. 1 , the seventh transistor T7 may be connected to the second scan line SL2 provided in the pixel circuit PC of the pixel PX of the current row.

[0180] In the pixel area, there may be gaps between elements of the pixel (e.g., first to seventh transistors, capacitors, and wiring (e.g., scan lines, emission control lines, electrode voltage lines, data lines, initialization voltage lines, power supply voltage lines, and connection lines). Elements of the pixel may not be positioned or disposed in the gaps. The light-transmitting area may represent an area having a predetermined size and allowing a sufficient amount of light to pass through it to the sensor in the gap. One or more light-transmitting areas may exist in the pixel area. The position, size, shape, and number of the light-transmitting areas may be modified according to the arrangement of transistors, capacitors, and wiring in the pixel area. Fig.11 A first light-transmitting region 310 a , a second light-transmitting region 310 b , a third light-transmitting region 310 c , and a fourth light-transmitting region 310 d , each having a predetermined size in a gap in a pixel region, are shown.

[0181] The opaque layer 300 according to an embodiment of the present disclosure may have a hole 310 corresponding to a light-transmitting area in a pixel area. The hole 310 of the opaque layer 300 may overlap with at least one light-transmitting area in a pixel area. The holes 310 of the opaque layer 300 may not overlap with the light-emitting area, and may be spaced apart from each other, or may be set separately from each other or deviate from each other. The position, size, shape, and number of the holes 310 of the opaque layer 300 according to an embodiment of the present disclosure may be determined according to the position, size, and number of the light-transmitting area in the pixel area. The position, size, shape, and number of the holes and the light-transmitting area are not limited to the illustrations of the accompanying drawings, but may include any position, size, shape, and number as will be appreciated and understood by those of ordinary skill in the art.

[0182] In an embodiment, the opaque layer 300 may have a hole 310 corresponding to the position of one light-transmitting region of each of the pixels PX emitting light of a specific color. Fig.12 As shown in , the opaque layer 300 may have holes 310 overlapping the first light-transmitting area 310a of the first pixel area PA1 or overlapping the first light-transmitting area 310a of only the first pixel area PA1. The holes 310 may be positioned or disposed in a non-light-emitting area around the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, and may not overlap with the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 or may deviate from the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3. The opaque layer 300 may have holes 310 arranged in a predetermined pattern at regular intervals to correspond to the first light-transmitting area 310a of the first pixel area PA1.

[0183] In an embodiment, the opaque layer 300 may have holes 310 corresponding to the positions of the light-transmitting regions of the pixels PX that emit light of a specific color. Fig.13 As shown in , the opaque layer 300 may have a hole 310 overlapping the second light-transmitting area 310b, the third light-transmitting area 310c, and the fourth light-transmitting area 310d of the second pixel area PA2. In this example and other examples, the hole 310 may overlap the second light-transmitting area 310b, the third light-transmitting area 310c, and the fourth light-transmitting area 310d of only the second pixel area PA2. The hole 310 may be positioned or disposed in a non-light-emitting area around the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, and may not overlap the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3. The opaque layer 300 may have holes 310 arranged in a predetermined pattern at regular intervals to correspond to the second light-transmitting area 310b, the third light-transmitting area 310c, and the fourth light-transmitting area 310d of the second pixel area PA2.

[0184] The display device according to an embodiment of the present disclosure can provide a fingerprint sensing function on the front surface of the display device by using a sensor SU disposed in a sensing area SA overlapping the display area DA. The display device according to an embodiment of the present disclosure senses the fingerprint of the user by using light emitted from the pixel PX. Therefore, the display device in which the fingerprint sensor is embedded can be implemented by using the pixel PX in the sensing area SA as a light source without using an external light source. Therefore, the thickness and manufacturing cost of the display device in which the fingerprint sensor is embedded can be reduced.

[0185] The display device according to an embodiment of the present disclosure can maximize the transmittance by positioning an opaque layer having holes in the display panel, and can reduce the brightness deviation and color deviation between pixels emitting light of different colors by making the holes of the opaque layer correspond to the light-transmitting areas of the pixels emitting light of a specific color. The display device according to an embodiment of the present disclosure can prevent the user from observing the sensor layer, etc. by positioning the sensor layer on the rear surface of the display panel, thereby preventing the image quality of the display device from being degraded. The display device according to an embodiment of the present disclosure can reduce the noise of the sensor and ensure the reliability of the sensor by preventing the light emitted directly from the display element of the pixel from being incident on the sensor and causing the sensor to react to the light reflected from the human body due to the holes of the opaque layer positioned or set on the entire surface of the display panel.

[0186] The display device according to an embodiment of the present disclosure may be an electronic device such as a smart phone, a mobile phone, a navigation system, a game console, a TV, a main unit for a vehicle, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), or a personal digital assistant (PDA). Moreover, the electronic device may be a flexible device.

[0187] The display device according to an embodiment of the present disclosure can reduce thickness and manufacturing cost by configuring a fingerprint sensor without an external light source.

[0188] While the invention has been shown and described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising: A sensor layer, including multiple sensors; a pixel layer disposed on the sensor layer and including a plurality of pixel regions and a plurality of pixels located in the plurality of pixel regions and emitting light of a plurality of colors, each of the plurality of pixels including a pixel circuit disposed in the pixel region and a pixel electrode connected to the pixel circuit; as well as An opaque layer is disposed between the sensor layer and the pixel layer and includes a hole corresponding to a light-transmitting area of ​​a specific pixel area where a specific pixel emitting light of a specific color is disposed.

2. The display device according to claim 1, wherein: The holes of the opaque layer are repeatedly formed in a predetermined pattern and in a predetermined direction in a display area.

3. The display device according to claim 1, wherein: Each of the light-transmitting regions is a region corresponding to a gap between a wiring in the specific pixel region and a circuit device constituting the specific pixel.

4. The display device according to claim 3, wherein: The display device further includes an insulating layer including an opening exposing a portion of the pixel electrode, and the insulating layer covers an edge of the pixel electrode.

5. The display device according to claim 4, wherein: The opening of the insulating layer is offset from the hole of the opaque layer.

6. The display device according to claim 1, wherein: The specific pixel that emits the light of the specific color is one of a red pixel, a green pixel, and a blue pixel. 7 . The display device of claim 1 , further comprising a substrate located between the opaque layer and the sensor layer.

8. The display device according to claim 1, further comprising a substrate having a plurality of layers, wherein The opaque layer is disposed between the plurality of layers of the substrate.

9. The display device according to claim 7, wherein: The pixel layer comprises: a circuit layer, comprising the pixel circuits of the plurality of pixels; and A display element layer, which is disposed on the circuit layer and includes display elements of the plurality of pixels, Wherein, the opaque layer is arranged between the substrate and the circuit layer.

10. A display device, comprising: A substrate including a plurality of pixel regions located in a display area; an opaque layer disposed on the substrate; as well as a plurality of pixels emitting light of a plurality of colors, disposed on the opaque layer and respectively disposed in the plurality of pixel regions, each of the plurality of pixels comprising a pixel circuit disposed in the pixel region and a pixel electrode connected to the pixel circuit, The opaque layer includes a hole, and the hole corresponds to a light-transmitting area of ​​a specific pixel area where a specific pixel emitting light of a specific color is arranged.

11. The display device according to claim 10, wherein: Each of the light-transmitting regions is a region corresponding to a gap between a wiring in the specific pixel region and a circuit device constituting the specific pixel.

12. The display device according to claim 10, wherein: The plurality of pixels include a first pixel emitting red light, a second pixel emitting green light, and a third pixel emitting blue light.

13. The display device according to claim 10, wherein: The opaque layer includes holes respectively corresponding to light-transmitting regions of one of the first pixel region, the second pixel region, and the third pixel region among the plurality of pixel regions.

14. The display device according to claim 12, wherein: The display device further includes an insulating layer including an opening exposing a portion of the pixel electrode of each of the plurality of pixels, the opening of the insulating layer being offset from the hole of the opaque layer.

15. The display device according to claim 10, further comprising a plurality of sensors disposed on a surface of the substrate opposite to a surface on which the plurality of pixels are disposed, and the plurality of sensors are disposed in a sensing area overlapping at least a portion of the display area.

16. The display device according to claim 15, wherein: Each of the plurality of sensors overlaps with at least one pixel in the sensing area.

17. The display device according to claim 16, wherein: Each of the plurality of sensors is disposed in a non-light emitting region between adjacent pixels among the plurality of pixels and is offset from the adjacent pixels.

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