Semiconductor device with stacked structure

Abstract

A semiconductor device having a stacked structure is provided. The semiconductor device includes: a substrate having a cell array region and a pad region; a stacked structure including gate electrodes and molding insulating layers alternately stacked on the substrate and having a stepped shape in the pad region; a first separation region penetrating the stacked structure in the pad region, extending in a first direction, and including a first dummy insulating layer and a second dummy insulating layer, the first dummy insulating layer covering a sidewall of the first separation region and including a horizontal portion covering a portion of the gate electrode, and the second dummy insulating layer being disposed between the first dummy insulating layers; an extension portion extending from the first dummy insulating layer toward the molding insulating layer in a second direction perpendicular to the first direction; a second separation region dividing the stacked structure and extending in the first direction; and a cell contact plug penetrating the horizontal portion and connected to the gate electrode.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0073505 filed on June 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the inventive concept relate to a semiconductor device having a stack structure. Background Art

[0003] There is an increasing demand for semiconductor devices with reduced size that can process high-capacity data. Consequently, there is a need to increase the integration density of semiconductor elements included in semiconductor devices. To improve the integration density of semiconductor devices, vertical transistor structures may be used instead of planar transistor structures. Summary of the Invention

[0004] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a cell array region and a pad region; a stack structure including gate electrodes and a molding insulating layer alternately stacked on the substrate and having a stepped shape in the pad region; a plurality of first separation regions vertically penetrating the stack structure in the pad region, extending in a first direction, and including a first dummy insulating layer and a second dummy insulating layer, wherein the first dummy insulating layer covers the inner side walls of the plurality of first separation regions and includes a horizontal portion covering a portion of the upper surface of an upper gate electrode in the gate electrode, and the second dummy insulating layer is arranged between the first dummy insulating layers; an extension portion extending from the first dummy insulating layer toward the molding insulating layer in a second direction perpendicular to the first direction; a plurality of second separation regions dividing the stack structure into a plurality of regions and extending in the first direction; and a cell contact plug penetrating the horizontal portion and being located in the second dummy insulating layer and connected to the gate electrode.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a cell array region and a pad region; a stack structure including a gate electrode having a stepped shape in the pad region and a molded insulating layer; an interlayer insulating layer covering the stack structure in the pad region; a plurality of first separation regions penetrating the stack structure and the interlayer insulating layer in the pad region, wherein the plurality of first separation regions include a first insulating layer and a second insulating layer, the first insulating layer covering one end of the gate electrode and extending in a direction substantially perpendicular to an upper surface of the substrate, and the second insulating layer being arranged between the first insulating layers; a plurality of second separation regions dividing the stack structure into a plurality of regions on the substrate and extending in a first direction; at least one dummy channel arranged between the plurality of first separation regions and the plurality of second separation regions; and a cell contact plug penetrating the first insulating layer in the plurality of first separation regions and connected to the gate electrode.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a cell array region and a pad region; a stack structure including gate electrodes and a molded insulating layer alternately stacked on the substrate and having a stepped shape in the pad region; an interlayer insulating layer covering the stack structure in the pad region; a dummy insulating layer dividing the stack structure and the interlayer insulating layer into a plurality of regions and including a material different from that of the interlayer insulating layer; an extension portion contacting the dummy insulating layer in the stack structure and spaced apart from each other between the gate electrodes in a direction substantially perpendicular to an upper surface of the substrate; and a cell contact plug disposed in the dummy insulating layer and connected to the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings.

[0008] Figure 1 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0009] Figure 2 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 1 An equivalent circuit diagram of a unit array of a semiconductor device.

[0010] Figure 3 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0011] Figure 4 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 3 Magnified view of area A.

[0012] Figure 5A is a diagram showing an exemplary embodiment according to the present inventive concept Figure 4 1 is a cross-sectional view of a cross-sectional surface of a semiconductor device taken along line II'.

[0013] Figure 5B is a diagram showing an exemplary embodiment according to the present inventive concept Figure 4 sectional view of a cross-sectional surface of the semiconductor device taken along line II-II'.

[0014] Figure 5C is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region B.

[0015] Figure 5D is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region C.

[0016] Figure 5Eis a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region D.

[0017] Figure 5F is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region E.

[0018] Figure 6A is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0019] Figure 6B is a diagram showing an exemplary embodiment according to the present inventive concept Figure 6A Magnified view of region B'.

[0020] Figure 7A is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0021] Figure 7B is a diagram showing an exemplary embodiment according to the present inventive concept Figure 7A Magnified view of area B".

[0022] Figure 8A and Figure 8B is a plan view illustrating an arrangement relationship between dummy channels and cell contact plugs of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0023] Figure 9 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0024] Figure 10 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 9 The plan view of area F.

[0025] Figure 11 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 10 sectional view of the semiconductor device taken along line III-III'.

[0026] Figures 12 to 24 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the inventive concept provide a semiconductor device having improved reliability.

[0028] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application.

[0029] Figure 1 is a block diagram illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0030] Reference Figure 1 , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30 . The peripheral circuit 30 may include a row decoder 32 , a page buffer 34 , input and output buffers 35 , a control logic 36 , and a voltage generator 37 .

[0031] The memory cell array 20 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells. The plurality of memory cells may be connected to a row decoder 32 via a string select line SSL, a word line WL, and a ground select line GSL, and may be connected to a page buffer 34 via a bit line BL. In an exemplary embodiment of the present inventive concept, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

[0032] The row decoder 32 may decode the input address ADDR from the control logic 36 and may generate and transmit a driving signal of the word line WL. The row decoder 32 may provide a word line voltage generated by the voltage generator 37 to each of the selected word line WL and the non-selected word line WL in response to the control of the control logic 36.

[0033] The page buffer 34 can be connected to the memory cell array 20 via the bit lines BL and can read out information stored in the memory cells. The page buffer 34 can temporarily store data to be stored in the memory cells or can sense data stored in the memory cells. The page buffer 34 can include a column decoder and a sense amplifier. The column decoder can selectively activate the bit lines BL of the memory cell array 20, and the sense amplifier can sense the voltage of the bit line BL selected by the column decoder in a read operation and can read out the data stored in the selected memory cell.

[0034] The input and output buffer 35 may receive data DATA during a program operation and may transmit the data DATA to the page buffer 34, and may output the data DATA received from the page buffer 34 to an external entity during a read operation. The input and output buffer 35 may transmit an input address or an input command to the control logic 36.

[0035] The control logic 36 may control the operation of the row decoder 32 and the page buffer 34. The control logic 36 may receive a control signal and an external voltage transmitted from an external entity and may operate in response to the received control signal. The control logic 36 may control a read operation, a write operation, and / or an erase operation in response to the control signal.

[0036] The voltage generator 37 may use an external voltage to generate, for example, a program voltage, a read voltage, an erase voltage, etc. required for internal operations. The voltage generated by the voltage generator 37 may be transmitted to the memory cell array 20 through the row decoder 32 .

[0037] Figure 2 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 1 An equivalent circuit diagram of a unit array of a semiconductor device.

[0038] Reference Figure 2 , the memory cell array 20 may include: a plurality of memory cell strings S, including memory cells MC connected in series with each other; and a ground selection transistor GST and string selection transistors SST1 and SST2, connected in series to both ends of the memory cells MC. The plurality of memory cell strings S may be connected in parallel to the bit lines BL0 to BL2. The plurality of memory cell strings S may be commonly connected to a common source line CSL. Therefore, the plurality of memory cell strings S may be arranged between the plurality of bit lines BL0 to BL2 and a single common source line CSL. In an exemplary embodiment of the present inventive concept, the plurality of common source lines may be arranged two-dimensionally.

[0039] Memory cells MC connected in series can be controlled by word lines WL0 to WLn for selecting the memory cells MC. Each memory cell MC can include a data storage element. The gate electrodes of memory cells MC arranged at substantially the same distance from a common source line CSL can be connected to one of the word lines WL0 to WLn and can be in an equipotential state. Alternatively, even when the gate electrodes of memory cells MC are arranged at substantially the same distance from a common source line CSL, gate electrodes arranged in different rows or columns can be independently controlled.

[0040] The ground selection transistor GST may be controlled by a ground selection line GSL and may be connected to a common source line CSL. The string selection transistors SST1 and SST2 may be controlled by string selection lines SSL1 and SSL2 and may be connected to the bit lines BL0 to BL2. Figure 2An example is shown in which a single ground selection transistor GST and two string selection transistors SST1 and SST2 are connected to each of a plurality of memory cells MC connected in series, but the inventive concept is not limited thereto. A single string selection transistor may be connected to each memory cell MC, or multiple ground selection transistors may be connected to each memory cell MC. One or more dummy lines DWL or buffer lines may also be provided between the uppermost word line WLn of the word lines WL0 to WLn and the string selection lines SSL1 and SSL2. In an exemplary embodiment of the inventive concept, one or more dummy lines DWL may also be provided between the lowermost word line WL0 and the ground selection line GSL.

[0041] When a signal is applied to string select transistors SST1 and SST2 via string select lines SSL1 and SSL2, the signal applied via bit lines BL0 to BL2 can be transmitted to memory cells MC connected in series, thereby enabling data read and write operations. Furthermore, by applying an erase voltage of a specific level via the substrate, an erase operation for erasing data written in memory cells MC can be performed. In an exemplary embodiment of the present inventive concept, memory cell array 20 may further include at least one dummy memory cell string electrically separated from bit lines BL0 to BL2.

[0042] Figure 3 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept. Figure 3 , some configurations of the semiconductor device 100 are shown for the sake of understanding. Figure 4 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 3 Magnified view of area A. Figure 5A is a diagram showing an exemplary embodiment according to the present inventive concept Figure 4 1 is a cross-sectional view of a cross-sectional surface of a semiconductor device taken along line II'. Figure 5B is a diagram showing an exemplary embodiment according to the present inventive concept Figure 4 sectional view of a cross-sectional surface of the semiconductor device taken along line II-II'. Figure 5C is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region B. Figure 5D is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region C. Figure 5E is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region D. Figure 5F is a diagram showing an exemplary embodiment according to the present inventive concept Figure 5A An enlarged cross-sectional view of region E.

[0043] Reference Figures 3 to 5B The semiconductor device 100 may include: a substrate 101 having a cell array region CAR and a pad (also referred to as a "pad" or "solder pad") region PAD; a stacked structure GS including gate electrodes 130 and a molding insulating layer 120 alternately stacked on the substrate 101; a channel CH penetrating the stacked structure GS; a first separation region MS1 ​​and a second separation region MS2 penetrating the stacked structure GS; and a cell contact plug CCP penetrating the first separation region MS1.

[0044] The first separation region MS1 ​​and the second separation region MS2 may extend in a first direction (x direction), may be arranged side by side, and may be spaced apart from each other in a second direction (y direction). The first separation region MS1 ​​and the second separation region MS2 may be arranged parallel to each other. The second separation region MS2 may include: a second central separation region MS2a extending from the cell array region CAR to the pad region PAD; and second auxiliary separation regions MS2b extending in the cell array region CAR and partially spaced apart from each other in the first direction in the pad region PAD. Portions of the first separation region MS1 ​​may be arranged between the second auxiliary separation regions MS2b in the pad region PAD. The first separation region MS1 ​​may be arranged only in the pad region PAD, and each first separation region MS1 ​​may have a length shorter than that of each second central separation region MS2a in the first direction, but the inventive concept is not limited thereto.

[0045] The cell array region CAR may be divided into a plurality of memory blocks by the second central separation region MS2a. The stack structure GS may be divided into a plurality of regions by the second separation region MS2.

[0046] The second auxiliary separation region MS2b may be disposed between the second central separation region MS2a in the cell array region CAR. The first separation region MS1 ​​and the second auxiliary separation region MS2b may be alternately disposed and arranged side by side in the second direction in the pad region PAD with a certain gap therebetween. The gap between the first separation region MS1 ​​and the second separation region MS2 and the arrangement order and number of the first separation region MS1 ​​and the second separation region MS2 are not limited to Figure 3 The example shown in FIG. 1 may be changed. For example, the gap between the first separation region MS1 ​​and the second separation region MS2 may not be constant, and the first separation region MS1 ​​and the second separation region MS2 may not be alternately arranged. The number of first separation regions MS1 may be the same as the number of second separation regions MS2, or the number of first separation regions MS1 may be greater than or less than the number of second separation regions MS2.

[0047] Reference Figure 5A and Figure 5BThe semiconductor device 100 may include a stacked structure GS in which mold insulating layers 120 and gate electrodes 130 are alternately stacked on a substrate 101, a first separation region MS1 ​​and a second separation region MS2 that divide the stacked structure GS into a plurality of regions, a channel CH, a dummy channel DCH, a cell contact plug CCP, and a wiring layer 190. The semiconductor device 100 may also include an interlayer insulating layer 60 covering the stacked structure GS, a first cap insulating layer 70 covering the interlayer insulating layer 60, and a second cap insulating layer 80 covering the first cap insulating layer 70. The channel CH may include a channel region 140, a channel insulating layer 145, a gate dielectric layer, and the like. The wiring layer 190 may include a lower wiring layer 150, an intermediate wiring layer 160, and an upper wiring layer 170, which will be described in more detail below.

[0048] The substrate 101 may have an upper surface extending in a first direction and a second direction. The substrate 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include, for example, silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer or an epitaxial layer.

[0049] The cell array region CAR of the substrate 101 may be a region where the gate electrodes 130 may be vertically stacked and the channels CH may be provided, and the cell array region CAR may correspond to Figure 1 The memory cell array 20 shown in FIG. The pad area PAD may be a region where the gate electrode 130 may extend in different lengths, and the pad area PAD may be Figure 1 The memory cell array 20 shown in FIG is electrically connected to the peripheral circuit 30. The pad region PAD may be provided on at least one end of the cell array region CAR in one direction.

[0050] The gate electrodes 130 may be stacked and spaced apart from each other in the third direction (z direction), and the gate electrodes 130 may extend from the cell array region CAR to the pad region PAD at different lengths. The gate electrodes 130 may include: Figure 2, a lower gate electrode included in the gate electrode of the ground selection transistor GST shown in FIG, a memory gate electrode included in a plurality of memory cells MC, and an upper gate electrode included in the gate electrodes of the string selection transistors SST1 and SST2. The number of memory gate electrodes included in the memory cells MC can be determined according to the capacity of the semiconductor device 100. In an exemplary embodiment of the present inventive concept, the number of upper gate electrodes and lower gate electrodes of each of the string selection transistors SST1 and SST2 and the ground selection transistor GST can be one or two, and the upper gate electrodes and the lower gate electrodes can have a structure that is the same as or different from that of the memory gate electrodes of the memory cells MC. Some of the gate electrodes 130 (for example, the memory gate electrodes adjacent to the upper gate electrode or the lower gate electrode) can be dummy gate electrodes.

[0051] The mold insulating layer 120 may be disposed between the gate electrodes 130. The mold insulating layers 120 may be stacked and spaced apart from each other in the third direction of the substrate 101, and may extend in the second direction.

[0052] The molded insulating layer 120 and the gate electrode 130 may extend to different lengths in the first direction and may form a stepped portion in a staircase shape in the pad area PAD of the substrate 101. Portions of the stacked structure GS may extend to different lengths in the first and second directions and may form a pad having a stepped portion in the form of a pyramid in the pad area PAD of the substrate 101. The number of stepped portions of the pad is not limited to the example shown in the drawings and may be varied.

[0053] The portion of the gate electrode 130 included in the pad may be a dummy gate electrode 130 a. The dummy gate electrode 130 a does not contact the channel CH. In the pad region PAD, the gate electrode 130 and the dummy gate electrode 130 a may be connected to the cell contact plug CCP, and thus the gate electrode 130 may be connected to the wiring layer 190.

[0054] The gate electrode 130 may include a metal material such as tungsten (W). In an exemplary embodiment of the present invention, the gate electrode 130 may include a polysilicon material or a metal silicide material. In an exemplary embodiment of the present invention, the gate electrode 130 may further include a diffusion barrier, which may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. The molded insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride.

[0055] The interlayer insulating layer 60 may cover the substrate 101 and the stacked structure GS on the substrate 101. The interlayer insulating layer 60 may include an insulating material such as silicon oxide or silicon nitride.

[0056] The channels CH may be formed in rows and columns on the cell array area CAR and may be spaced apart from each other. The channels CH may be arranged in a grid form, or may be arranged in a zigzag form along one direction. Each channel CH may have a cylindrical shape and may have an inclined side surface, the width of which decreases toward the substrate 101 according to the aspect ratio. In an exemplary embodiment of the present invention, the channel CH may have a "U" shape in which the lower portions of the channels CH are connected to each other. In an exemplary embodiment of the present invention, the dummy channel DCH may also be provided on the end of the cell array area CAR adjacent to the pad area PAD and in the pad area PAD. The dummy channel DCH may have a structure that is the same as or similar to that of the channel CH and may not perform any substantial function in the semiconductor device 100.

[0057] The channel region 140 may be provided in the channel CH. The channel region 140 in the channel CH may have a ring-shaped form surrounding the channel insulating layer 145, but the inventive concept is not limited thereto. In an exemplary embodiment of the present inventive concept, the channel region 140 may have a columnar shape such as a cylindrical shape or a prismatic shape. The channel region 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material including p-type or n-type impurities.

[0058] A channel pad 146 may be disposed on the channel region 140 in the channel CH. The channel pad 146 may cover an upper surface of the channel insulating layer 145 and may be electrically connected to the channel region 140. The channel pad 146 may include, for example, doped polysilicon.

[0059] The gate dielectric layer may be disposed between the gate electrode 130 and the channel region 140. The gate dielectric layer may include a tunnel layer, a charge storage layer, and a blocking layer stacked sequentially from the channel region 140. The tunnel layer may tunnel charges to the charge storage layer and may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, or a combination thereof. In an exemplary embodiment of the present inventive concept, at least a portion of the gate dielectric layer may extend in a horizontal direction along the gate electrode 130.

[0060] like Figure 5AAs shown in FIG, the first separation region MS1 ​​and the second separation region MS2 may penetrate the gate electrode 130, the molded insulating layer 120, and the interlayer insulating layer 60 stacked on the substrate 101 in a third direction perpendicular to the upper surface of the substrate 101 and may be in contact with the substrate 101. Therefore, the first separation region MS1 ​​and the second separation region MS2 may penetrate the stacked structure GS and may be in contact with the substrate 101.

[0061] Each of the first and second separation regions MS1 and MS2 may have an inclined side surface whose lower portion width decreases more than the upper portion width toward the substrate 101 according to the aspect ratio. Figure 5F , an upper portion of each first separation region MS1 ​​may have a first width W1, and a lower portion of each first separation region MS1 ​​may have a second width W2. The first width W1 may be greater than the second width W2.

[0062] The first separation regions MS1 may be arranged side by side and may be spaced apart from each other between the second separation regions MS2. In the second direction, each first separation region MS1 ​​may have a width greater than the width of each second separation region MS2. The internal space of each first separation region MS1 ​​may be filled with a first dummy insulating layer DIL1 and a second dummy insulating layer DIL2, but the inventive concept is not limited thereto. For example, the internal space of each first separation region MS1 ​​may include a single layer containing an insulating material different from the material of the interlayer insulating layer 60. The first dummy insulating layer DIL1 may be arranged on both inclined sidewalls of the first separation region MS1 ​​and on the bottom surface of the first separation region MS1, may extend in a third direction, may contact the substrate 101, and may also extend in the first direction. The second dummy insulating layer DIL2 may be arranged between the first dummy insulating layers DIL1, may extend in the third direction, and may also extend in the first direction. The first dummy insulating layer DIL1 and the second dummy insulating layer DIL2 may include different materials.

[0063] The upper surfaces of the second separation region MS2, the first separation region MS1, and the dummy channel DCH may have the same level. Alternatively, the upper surface of the second separation region MS2 may be set at a higher level than the upper surface of the first separation region MS1 ​​and may be set at a higher level than the upper surface of the dummy channel DCH.

[0064] Reference Figure 5B The line II-II′ may cut the semiconductor device 100 along the first direction along which the first separation region MS1 ​​extends in the pad region PAD, and may penetrate and cut the channel CH in the cell array region CAR.

[0065] like Figure 5BAs shown in FIG, the semiconductor device 100 may include gate electrodes 130, a mold insulating layer 120, a horizontal portion 124, an extension portion 125, an interlayer insulating layer 60, a cell contact plug CCP, a second dummy insulating layer DIL2, etc. In a portion of the pad region PAD where the first separation region MS1 ​​is provided, a space between the gate electrodes 130 may be filled with the extension portion 125 instead of the mold insulating layer 120. The extension portion 125 may be connected to the horizontal portion 124 covering a portion of the upper surface of each gate electrode 130.

[0066] The cell contact plug CCP may penetrate the horizontal portion 124 and may make contact with the gate electrode 130 on an end portion of the gate electrode 130 .

[0067] Figure 5C The arrangement of the extension portion 125 is shown.

[0068] Reference Figure 5C The extension portion 125 may be disposed adjacent to the first separation region MS1. One end of the extension portion 125 may contact the outer surface of the first dummy insulating layer DIL1 in the second direction, and the other end of the extension portion 125 may contact the mold insulating layer 120 in the second direction. The thickness of each extension portion 125 in the third direction may be substantially the same as the thickness of each mold insulating layer 120 in the third direction. The first dummy insulating layer DIL1 may extend in the third direction and may contact the interlayer insulating layer 60. The extension portion 125 may be a layer covering the region between the gate electrode 130 and the sidewalls of the mold insulating layer 120 and contacting the first dummy insulating layer DIL1. The horizontal portion 124 may be a layer located on the upper surface of the uppermost gate electrode 130 and may be part of the first dummy insulating layer DIL1.

[0069] The extension portions 125 may be spaced apart from each other in the second direction with the first separation region MS1 ​​interposed between the extension portions 125, and partial regions of the extension portions 125 may be spaced apart from each other in the third direction with the gate electrode 130 interposed between partial regions of the extension portions 125. The extension portions 125 may be configured to be surrounded by the first dummy insulating layer DIL1, the mold insulating layer 120, the gate electrode 130, and the second dummy insulating layer DIL2.

[0070] The extension portion 125 may extend from the first dummy insulating layer DIL1 toward the mold insulating layer 120 in the second direction. Therefore, the first dummy insulating layer DIL1 and the extension portion 125 may have a sawtooth or fishbone shape. The first dummy insulating layer DIL1 and the extension portion 125 may serve as a support to prevent the mold insulating layer 120 from collapsing.

[0071] The positions of one end of the extension portion 125 in the second direction may differ from each other. As the width of each first separation region MS1 ​​in the second direction decreases toward the substrate 101, the closer the extension portion 125 is to the substrate 101, the shorter the distance between the extension portions 125 in the second direction. Therefore, the width of each extension portion 125 in the second direction may decrease. For example, the extension portion 125 may include a first extension portion 125-1 and a second extension portion 125-2, and the second extension portion 125-2 may be positioned closer to the substrate 101 than the first extension portion 125-1, and the end of the second extension portion 125-2 opposite the mold insulation layer 120 in the second direction may be different from the end of the first extension portion 125-1 opposite the mold insulation layer 120 in the second direction.

[0072] The extension portion 125 may be formed of a material different from that of the mold insulation layer 120 and the gate electrode 130, and may be formed of the same material as that of the first dummy insulation layer DIL1. For example, the first dummy insulation layer DIL1 and the extension portion 125 may include aluminum oxide (Al2O3), but the inventive concept is not limited thereto.

[0073] In an exemplary embodiment of the present inventive concept, since the extension portion 125 is provided on the etched end of the mold insulating layer 120, the length of each mold insulating layer 120 in the second direction is reduced. Therefore, during the gate replacement process, the support force of the dummy channel DCH in contact with the mold insulating layer 120 can be improved, so that the collapse of the mold insulating layer 120 can be prevented and bridging defects can be reduced.

[0074] A portion of the stacked structure GS may include an area that is not connected to the second separation region MS2. Therefore, during the gate replacement process, portions of the sacrificial layer 180 may not be selectively removed relative to the mold insulation layer 120, and at least one area in which the sacrificial layer 180 remains may exist in the semiconductor structure. For example, the sacrificial layer 180 disposed on the uppermost end between the first separation region MS1 ​​and the second separation region MS2 and not penetrated by the second separation region MS2 may remain.

[0075] The sacrificial layer 180 may be disposed at substantially the same level as that of the upper gate electrode of the gate electrode 130 connected to the cell contact plug CCP, and one end of the sacrificial layer 180 may be surrounded by the first dummy insulating layer DIL1, the second dummy insulating layer DIL2, and the extension portion 125. The sacrificial layer 180 may be disposed between the horizontal portion 124 and the extension portion 125, and may include a material different from that of the gate electrode 130.

[0076] Figure 5DA region C in which the cell contact plug CCP of the semiconductor device 100 according to an exemplary embodiment of the inventive concept contacts the gate electrode 130 is illustrated.

[0077] An upper gate electrode among the gate electrodes 130 may make contact with the cell contact plug CCP and may serve to electrically connect the wiring layer 190 to the memory cell MC. An extension portion 125 may be disposed under the upper gate electrode.

[0078] The first dummy insulating layer DIL1 may include a horizontal portion 124 covering the upper surface of the upper gate electrode. Thus, a portion of the first dummy insulating layer DIL1 may include the horizontal portion 124 disposed substantially parallel to the upper surface of the substrate 101. The horizontal portion 124 may contact the second dummy insulating layer DIL2. The horizontal portion 124 may provide a contact region connecting the upper wiring to the gate electrode 130 and may be penetrated by a cell contact plug CCP in the third direction. The cell contact plug CCP may be disposed in the first separation region MS1, may penetrate the second dummy insulating layer DIL2 in the third direction, may penetrate the horizontal portion 124 in the third direction, and may contact the upper gate electrode.

[0079] The horizontal portion 124 may include a material different from that of the mold insulation layer 120 and may include the same material as that of the extension portion 125. As the material of the horizontal portion 124, an insulating material having an etching selectivity different from that of the second dummy insulation layer DIL2 and the mold insulation layer 120 may be selected under certain conditions. For example, the horizontal portion 124 may include aluminum oxide (Al2O3), but the inventive concept is not limited thereto. Since the horizontal portion 124 includes a material that takes etching selectivity into consideration, the etching rate in the horizontal portion 124 may be slower than the etching rate in the second dummy insulation layer DIL2 during the etching process for forming the cell contact plug CCP. Therefore, the depth of the contact area of ​​the cell contact plug CCP can be adjusted. Since the depth of the contact area of ​​the cell contact plug CCP is adjusted, the cell contact plug CCP and the through wiring can be formed in the same process.

[0080] Since the semiconductor device 100 includes the extension portion 125 and the horizontal portion 124 , a punching defect in which the cell contact plug CCP contacts a lower gate electrode disposed under an upper gate electrode in the gate electrode 130 may be prevented.

[0081] The horizontal portion 124 and the extension portion 125 may be configured to surround one end of the upper gate electrode, and the extension portion 125 may be in contact with the outer side surface of the first dummy insulating layer DIL1. In an exemplary embodiment of the present inventive concept, when the first dummy insulating layer DIL1 extending in the third direction, the horizontal portion 124 as a portion of the first dummy insulating layer DIL1, and the extension portion 125 extending from the outer side surface of the first dummy insulating layer DIL1 toward the mold insulating layer 120 are formed of the same material, the first dummy insulating layer DIL1, the horizontal portion 124, and the extension portion 125 may be included in the first insulating layer and referred to as the first insulating layer.

[0082] Figure 5E A region D of the semiconductor device 100 is shown in which a plurality of cell contact plugs CCP are in contact with a plurality of gate electrodes 130 , respectively. Figure 5E Particularly, a cross-sectional surface of the first separation region MS1 ​​in the pad region PAD including a boundary surface of a stepped portion on which a pad exists is shown.

[0083] Due to the presence of the stepped portion of the upper gate electrode in the pad area PAD, a height difference may exist between the horizontal portions 124 covering the upper gate electrode. The height difference H1 of the horizontal portions 124 in the third direction may be substantially the same as the height of each stepped portion of the gate electrode 130. Therefore, the height difference H1 may be substantially the same as the sum of the first thickness of a single gate electrode 130 in the third direction and the second thickness of a single mold insulation layer 120 in the third direction.

[0084] The semiconductor device 100 may include at least one first separation region MS1 ​​including two cell contact plugs CCP. Each cell contact plug CCP may penetrate the second dummy insulating layer DIL2, may penetrate the horizontal portion 124, and may be electrically connected to the gate electrode 130. For example, the cell contact plug CCP may penetrate one of the second dummy insulating layers DIL2, may include a first cell contact plug and a second cell contact plug having different heights in the third direction, and may be electrically connected to the gate electrode 130, respectively. The height difference between the first cell contact plug and the second cell contact plug may be substantially the same as the sum of a first thickness of a single gate electrode 130 taken in the third direction and a second thickness of a single mold insulating layer 120 taken in the third direction.

[0085] Reference Figure 5FThe first separation region MS1 ​​may include an upper first separation region in contact with the interlayer insulating layer 60 and a lower first separation region in contact with the stacked structure GS. Each upper first separation region may have a first width W1 in the second direction, and the lower first separation region may have a second width W2 in the second direction. The first width W1 may be greater than the second width W2. The minimum value of the first width W1 may be greater than the maximum value of the second width W2.

[0086] Figure 6A is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0087] Figure 6B is a diagram showing an exemplary embodiment according to the present inventive concept Figure 6A Magnified view of region B'.

[0088] Reference Figure 6A and Figure 6B In the semiconductor device 100a, the inner space of the first separation region MS1 ​​may be filled with the second dummy insulating layer DIL2. Figure 5A In contrast, since the first separation region MS1 ​​does not include the first dummy insulation layer DIL1 , the configuration of the insulation layer may be different. Each second separation region MS2 may have an inclined side surface having a lower width smaller than an upper width according to an aspect ratio.

[0089] The extension portion 125a may be disposed adjacent to the first separation region MS1. One end of the extension portion 125a may contact the second dummy insulation layer DIL2 in the second direction, and the other end of the extension portion 125a may contact the mold insulation layer 120 in the second direction. The thickness of each extension portion 125a in the third direction may be substantially the same as the thickness of each mold insulation layer 120 in the third direction. The extension portions 125a may be spaced apart from each other in the second direction with the first separation region MS1 ​​interposed therebetween, and may be spaced apart from each other in the third direction with the gate electrode 130 interposed therebetween. The extension portion 125a may be configured to be surrounded by the second dummy insulation layer DIL2, the mold insulation layer 120, and the gate electrode 130.

[0090] The extension portion 125a may include a material different from that of the mold insulation layer 120, and may include the same material as that of the horizontal portion 124. As the material of the extension portion 125a, an insulating material having an etching selectivity different from that of the second dummy insulation layer DIL2 and the mold insulation layer 120 may be selected under certain conditions. For example, the extension portion 125a may include aluminum oxide (Al2O3), but the inventive concept is not limited thereto.

[0091] The semiconductor device 100a may further include a horizontal portion 124 covering a portion of the upper surface of each upper gate electrode of the gate electrodes 130. The horizontal portion 124 may be in contact with the second dummy insulating layer DIL2. The horizontal portion 124 may provide a contact region for connecting the upper wiring to the gate electrode 130 and may be penetrated by the cell contact plug CCP in the third direction.

[0092] The horizontal portion 124 may include a material different from that of the mold insulation layer 120 and may include the same material as that of the extension portion 125a. As the material of the horizontal portion 124, an insulating material having an etching selectivity different from that of the second dummy insulation layer DIL2 and the mold insulation layer 120 may be selected under certain conditions. For example, the horizontal portion 124 may include aluminum oxide (Al2O3), but the present invention is not limited thereto. Since the horizontal portion 124 includes a material that takes etching selectivity into consideration, the etching rate in the horizontal portion 124 may be slower than the etching rate in the second dummy insulation layer DIL2 during the etching process for forming the cell contact plug CCP. Therefore, the depth of the contact area of ​​the cell contact plug CCP can be adjusted. Since the depth of the contact area of ​​the cell contact plug CCP is adjusted, the cell contact plug CCP and the through wiring can be formed in the same process.

[0093] Figure 7A is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0094] Figure 7B is a diagram showing an exemplary embodiment according to the present inventive concept Figure 7A Magnified view of area B".

[0095] Reference Figure 7A and Figure 7B In the semiconductor device 100b, the first separation region MS1 ​​may include a first dummy insulating layer DIL1 and a second dummy insulating layer DIL2, and each of the first dummy insulating layer DIL1 and the second dummy insulating layer DIL2 may have the same Figure 5A and Figure 5C The shapes of the example embodiments shown in FIG.

[0096] In an exemplary embodiment of the present inventive concept, each extension portion 125b may have a recessed portion DS. The extension portion 125b may extend uniformly along the upper and lower surfaces of the gate electrode 130, such that the recessed portion DS may be disposed between gate electrodes 130 disposed upwardly and downwardly. The thickness of the recessed portion DS in the third direction may be smaller than the thickness of each extension portion 125b in the third direction, and the width of the recessed portion DS in the second direction may be smaller than the width of each extension portion 125b in the second direction. The recessed portion DS may extend in the first direction, and the interior space of the recessed portion DS may be filled with the second dummy insulating layer DIL2. Due to the recessed portion DS of the extension portion 125b, the first dummy insulating layer DIL1 and the extension portion 125b may form a zigzag pattern. The first dummy insulating layer DIL1 and the extension portion 125b may be configured to surround one end of the gate electrode 130.

[0097] Figure 7A and Figure 7B An exemplary embodiment is shown in which the shape of each extension portion (eg, 125b) is different from the aforementioned exemplary embodiment, and the shape of each extension portion is not limited to Figure 7A and Figure 7B For example, the cross-sectional surface of each extension portion may have a square shape, a rectangular shape, a trapezoidal shape, a triangular shape, a semicircular shape, etc., and the cross-sectional surface of the recessed portion DS may have a square shape, a rectangular shape, a trapezoidal shape, a triangular shape, a semicircular shape, etc.

[0098] Figure 8A and Figure 8B is a plan view illustrating an arrangement relationship between dummy channels and cell contact plugs of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0099] Each upper first separation region may have a first width W1 in the second direction, and each lower first separation region may have a second width W2 in the second direction. The first width W1 may be greater than the second width W2.

[0100] The cell contact plug CCP may be provided in the first separation region MS1, and a plurality of dummy channels DCH may be provided between the first separation region MS1 ​​and the second separation region MS2. Figure 8A As shown in , a dummy channel DCH can be set in each segment, and as Figure 8BAs shown in , four dummy channels DCH can be set in each segment. In an exemplary embodiment of the present invention, when the cell contact plug CCP is set in the first separation region MS1, the cell contact plug CCP and the dummy channel DCH can be spaced apart from each other, and the first dummy insulating layer DIL1 is placed between the cell contact plug CCP and the dummy channel DCH. Therefore, the dummy channel DCH can be set independently from the cell contact plug CCP. Therefore, the dummy channel DCH can be set relatively more densely. The number and arrangement of the dummy channel DCH are not limited to Figure 8A and Figure 8B The exemplary embodiments shown in FIG. 1 are exemplary embodiments, but may be varied.

[0101] Figure 9 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 10 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 9 The plan view of area F. Figure 11 is a diagram showing an exemplary embodiment according to the present inventive concept Figure 10 sectional view of the semiconductor device taken along line III-III'.

[0102] Reference Figures 9 to 11 The semiconductor device 200 may include a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be disposed on the peripheral circuit region PERI. Alternatively, in an exemplary embodiment of the present inventive concept, the memory cell region CELL may be disposed below the peripheral circuit region PERI. The memory cell region CELL may include a substrate 101, a gate electrode 130 disposed on the substrate 101, and a channel CH penetrating the gate electrode 130. The peripheral circuit region PERI may include a base substrate 201, a circuit element 220 disposed on the base substrate 201, a circuit contact plug 270, and a wiring 280.

[0103] The base substrate 201 may have an upper surface extending in a first direction and a second direction. The base substrate 201 may include an element separation layer, thereby defining an active region. A source / drain region 205 including impurities may be provided in a portion of the active region. The base substrate 201 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor.

[0104] The circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate insulating layer 222 , a spacer layer 224 , and a circuit gate electrode 225 . The source / drain regions 205 may be disposed in the base substrate 201 and located on both sides of the circuit gate electrode 225 .

[0105] The peripheral region insulating layer 290 may be provided on the circuit element 220 on the base substrate 201. The circuit contact plug 270 may penetrate the peripheral region insulating layer 290 and may be connected to the source / drain region 205. An electrical signal may be applied to the circuit element 220 through the circuit contact plug 270. In an area not shown in the figure, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The wiring 280 may be connected to the circuit contact plug 270 and may be provided in multiple layers.

[0106] The semiconductor device 200 can be manufactured by forming a peripheral circuit region PERI and a memory cell region CELL, and the memory cell region CELL is formed by forming a substrate 101 of the memory cell region CELL on an upper portion of the peripheral circuit region PERI. The substrate 101 may have a size substantially the same as that of the base substrate 201, or may have a size smaller than that of the base substrate 201.

[0107] The gate electrode 130 in the pad region PAD may be electrically connected to the circuit element 220 in the peripheral circuit region PERI through the wiring layer 190 and the cell contact plug CCP. The through wiring 155 may connect the wiring layer 190 in the pad region PAD to the wiring 280 in the peripheral circuit region PERI.

[0108] The through wiring 155 may be provided in the central region of the pad region PAD. The through wiring 155 may penetrate the interlayer insulating layer 60, the stacked structure GS, the substrate 101, and the peripheral region insulating layer 290 in the pad region PAD, and the sacrificial layer 180 that is not replaced with tungsten (W) during the gate replacement process may be included in the stacked structure GS.

[0109] Since the depth of the contact region can be adjusted during the etching process for forming the cell contact plug CCP, the cell contact plug CCP and the through wiring 155 can be formed in the same process. Therefore, when the same process is performed, the time for the cell contact plug CCP to penetrate the horizontal portion 124 of the first dummy insulating layer DIL1 can be increased, and accordingly, the time for the through wiring 155 to penetrate the interlayer insulating layer 60, the stacked structure GS, the substrate 101, and the peripheral region insulating layer 290 and connect to the wiring 280 in the peripheral circuit area PERI can be ensured.

[0110] Figures 12 to 24 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0111] Reference Figure 12, sacrificial layers 180 and mold insulation layers 120 may be alternately stacked on the substrate 101. A portion of each of the sacrificial layers 180 and the mold insulation layers 120 may be removed so that the sacrificial layers 180 extend to different lengths in the second direction in the pad area PAD.

[0112] The sacrificial layer 180 may be replaced by the gate electrode 130 through a subsequent process. The sacrificial layer 180 may be formed of a material having an etch selectivity relative to the mold insulating layer 120 and may be capable of being etched. For example, the mold insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial layer 180 may be formed of a material different from the material of the mold insulating layer 120 and selected from silicon, silicon oxide, silicon carbide, or silicon nitride.

[0113] In an exemplary embodiment of the present inventive concept, the thickness of each molded insulating layer 120 and the thickness of each sacrificial layer 180 may be relatively thin in consideration of the relationship with other elements. In an exemplary embodiment of the present inventive concept, the thickness of the molded insulating layers 120 may be different. For example, each of the lowermost molded insulating layers 120 may have a relatively thin thickness, while each of the uppermost molded insulating layers 120 may have a relatively large thickness. The thickness of the molded insulating layers 120 and the thickness of the sacrificial layers 180, as well as the number of films included, are not limited to the exemplary embodiments shown in the figures and may be varied.

[0114] The sacrificial layer 180 may be repeatedly subjected to a photolithography process and an etching process so that the upper sacrificial layer 180 may extend less than the lower sacrificial layer 180 in the pad area PAD. Thus, the sacrificial layer 180 may be formed in a stepped shape. The material for forming the sacrificial layer 180 may be additionally deposited in an area where the sacrificial layer 180 extends further than the upper sacrificial layer 180, and each end portion of the sacrificial layer 180 may have a relatively large thickness. An interlayer insulating layer 60 may be formed to cover the upper portion of the stacked structure of the sacrificial layer 180 and the molding insulating layer 120.

[0115] A first opening OP1 penetrating the sacrificial layer 180 and the mold insulation layer 120 may be formed.

[0116] The first opening OP1 can be formed by forming a mask layer using a photolithography process and performing a first etching process (e.g., anisotropically etching the sacrificial layer 180 and the mold insulation layer 120). The first opening OP1 can be formed in the form of a trench extending in the third direction, and the width of the first opening OP1 taken in the second direction can decrease toward the substrate 101. The first opening OP1 can extend in the first direction. In the first etching process, the substrate 101 can be exposed in the lower portion of the first opening OP1, and the sidewalls of the sacrificial layer 180 and the sidewalls of the mold insulation layer 120 can be exposed on both sidewalls of the first opening OP1.

[0117] Reference Figure 13 , an expanded first opening EOP1 may be formed by performing a second etching process for selectively etching the sidewalls of the interlayer insulating layer 60, the exposed sidewalls of the sacrificial layer 180, and the sidewalls of the molding insulating layer 120. The first opening OP1 may be additionally etched in the second direction by the second etching process to form the expanded first opening EOP1. Portions of the upper and lower surfaces of the sacrificial layer 180 may be exposed through the expanded first opening EOP1.

[0118] Reference Figure 14 , a first dummy insulating layer DIL1 and an extension portion 125 may be formed in the expanded first opening EOP1. The first dummy insulating layer DIL1 and the extension portion 125 may be formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The first dummy insulating layer DIL1 and the extension portion 125 may include a material different from that of the mold insulating layer 120. For example, the first dummy insulating layer DIL1 and the extension portion 125 may include aluminum oxide (Al2O3), but the inventive concept is not limited thereto.

[0119] Extensions 125 may be formed on portions of the upper and lower surfaces of the sacrificial layer 180 exposed by the expanded first opening EOP1 and sidewalls of the mold insulating layer 120. The thickness of each extension 125 taken in the third direction may be substantially the same as the thickness of each mold insulating layer 120 taken in the third direction.

[0120] When the first dummy insulating layer DIL1 is formed in the expanded first opening EOP1, the first dummy insulating layer DIL1 may be formed along both sidewalls of the expanded first opening EOP1. The first dummy insulating layer DIL1 may cover the unetched portion of the upper surface of the interlayer insulating layer 60. A horizontal portion 124 disposed substantially parallel to the substrate 101 may be included in the region where the first dummy insulating layer DIL1 contacts the uppermost sacrificial layer 180. The horizontal portion 124 may cover a portion of the upper surface of each uppermost sacrificial layer 180.

[0121] Reference Figure 15 In the expanded first opening EOP1, the space between the first dummy insulating layers DIL1 may be filled with a second dummy insulating layer DIL2. The second dummy insulating layer DIL2 may cover the upper surface of the interlayer insulating layer 60. The second dummy insulating layer DIL2 may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The second dummy insulating layer DIL2 may include a material different from that of the first dummy insulating layer DIL1. For example, the second dummy insulating layer DIL2 may include an insulating material such as silicon oxide or silicon nitride.

[0122] A first dummy insulating layer DIL1 and a second dummy insulating layer DIL2 may be included in the first separation region MS1 ​​.

[0123] Reference Figure 16 , a planarization process may be performed on upper portions of the first dummy insulating layer DIL1 , the second dummy insulating layer DIL2 , and the interlayer insulating layer 60 using a chemical mechanical polishing (CMP) process.

[0124] Reference Figure 17 , a dummy channel DCH may be formed penetrating the interlayer insulating layer 60, the sacrificial layer 180, and the molding insulating layer 120. The dummy channel DCH may be formed together with the channel CH of the cell array region CAR in the same process and may have the same structure as that of the inner region of the channel CH.

[0125] Reference Figure 18 , a second opening OP2 penetrating the sacrificial layer 180 and the mold insulation layer 120 may be formed.

[0126] The second opening OP2 can be formed by forming a mask layer using a photolithography process and performing an anisotropic etching process on the sacrificial layer 180 and the mold insulation layer 120. The second opening OP2 can have a groove form extending in the third direction, and the width of the second opening OP2 in the second direction can decrease toward the substrate 101. The second opening OP2 can extend in the first direction. In this process, the substrate 101 can be exposed in the lower portion of the second opening OP2, and the sidewalls of the sacrificial layer 180 and the sidewalls of the mold insulation layer 120 can be exposed on both sidewalls of the second opening OP2.

[0127] Reference Figure 19 , the sacrificial layer 180 may be removed through the second opening OP2 .

[0128] The sacrificial layer 180 can be selectively removed relative to the mold insulating layer 120 using a wet etching process. Consequently, multiple side surface openings can be formed between the mold insulating layers 120, and portions of the sidewalls of the dummy channels DCH can be exposed through the side surface openings. During this process, the structural stability of the mold insulating layer 120 may deteriorate after the sacrificial layer 180 is removed. However, the mold insulating layer 120 can be stably supported by the extension portion 125, the first dummy insulating layer DIL1, and the dummy channels DCH, all of which have a fishbone shape and are adjacent to the mold insulating layer 120. Because the extension portion 125, the first dummy insulating layer DIL1, and the dummy channels DCH act as support platforms, collapse of the mold insulating layer 120 can be prevented. Consequently, bridging defects caused by the reduced width of the mold insulating layer 120 and the gate electrode 130 in the third direction can be prevented. This is because the length of each mold insulating layer 120 supported by a single dummy channel DCH in the second direction can be reduced due to the formation of the extension portion 125.

[0129] In this process, portions of the sacrificial layer 180 may not be selectively removed relative to the mold insulation layer 120, but may remain. For example, the uppermost sacrificial layer of the sacrificial layer 180, which is disposed between the second opening OP2 and the first separation region MS1 ​​and is not penetrated by the second opening OP2, may remain.

[0130] Reference Figure 20 The region where the sacrificial layer 180 is removed may be filled with a conductive material to form the gate electrode 130 .

[0131] The gate electrode 130 may include metal, polysilicon, or metal silicide material. The second opening OP2 may provide a transfer path for the material used to form the gate electrode 130.

[0132] In an exemplary embodiment of the present inventive concept, the thickness of each molded insulating layer 120 and the thickness of each gate electrode 130 may be relatively thin in consideration of the relationship with other components. In an exemplary embodiment of the present inventive concept, the thickness of the gate electrodes 130 may be different. For example, the gate electrode 130 in the lowermost portion may have a relatively thin thickness, while the gate electrode 130 in the uppermost portion may have a relatively large thickness. In consideration of the relationship with other components, the thickness of the gate electrodes 130 may be relatively thin.

[0133] Reference Figure 21The second opening OP2 may be filled with an insulating material such as silicon oxide or silicon nitride and may be included in the second separation region MS2 of the semiconductor device 100. Alternatively, an upper surface of the second separation region MS2 may be disposed at a level higher than that of the first separation region MS1 ​​and may be disposed at a level higher than that of the upper surface of the dummy channel DCH.

[0134] Reference Figure 22 and Figure 23 A first cover insulating layer 70 may be formed to cover the upper surface of the interlayer insulating layer 60. A cell contact plug CCP may be formed to penetrate the second dummy insulating layer DIL2, penetrate the horizontal portion 124 of the first dummy insulating layer DIL1, and contact the uppermost gate electrode 130. A lower wiring layer 150 may be formed to contact the cell contact plug CCP and be disposed on the upper surface of the first cover insulating layer 70.

[0135] Reference Figure 24 , a second cover insulating layer 80 may be formed covering the upper surface of the first cover insulating layer 70 and the upper surface of the lower wiring layer 150. An intermediate wiring layer 160 may be formed penetrating the second cover insulating layer 80 and in contact with the lower wiring layer 150. An upper wiring layer 170 (such as a 170) may be formed in contact with the intermediate wiring layer 160 and disposed on the upper surface of the second cover insulating layer 80. Figure 5A ).

[0136] The lower wiring layer 150 , the middle wiring layer 160 , and the upper wiring layer 170 may be included in and referred to as a wiring layer 190 , and may be electrically connected to the cell contact plugs CCP.

[0137] According to the aforementioned exemplary embodiments of the inventive concept, a semiconductor device having improved electrical performance may be provided by controlling the structures of a region where a cell contact plug contacts a gate electrode and a region where a separation region contacts a molding insulating layer.

[0138] While the present invention has been shown and described above with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and changes in form and details may be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a substrate having a cell array region and a pad region; a stacked structure comprising gate electrodes and molded insulating layers alternately stacked on the substrate and having a stepped shape in the pad region; a plurality of first separation regions vertically penetrating the stacked structure, extending in a first direction in the pad region, arranged side by side in a second direction perpendicular to the first direction, and comprising a first dummy insulating layer and a second dummy insulating layer, wherein the first dummy insulating layer covers inner sidewalls of the plurality of first separation regions and includes a horizontal portion covering a portion of an upper surface of an upper gate electrode among the gate electrodes, and the second dummy insulating layer is arranged between the first dummy insulating layers; an extending portion extending from the first dummy insulating layer toward the molded insulating layer in the second direction; and a plurality of second separation regions, dividing the stack structure into a plurality of regions and extending in the first direction, and Each of the plurality of first separation regions is provided with a plurality of cell contact plugs in the first direction, and the plurality of cell contact plugs penetrate the horizontal portion in the first dummy insulating layer and are connected to the gate electrode.

2. The semiconductor device according to claim 1, wherein The extending portion includes a first extending portion and a second extending portion, the first extending portion and the second extending portion are arranged at different levels in a third direction substantially perpendicular to the upper surface of the substrate, and one end of the first extending portion and one end of the second extending portion are arranged in different positions in the second direction.

3. The semiconductor device according to claim 1, wherein The first dummy insulating layer contacts the extending portion through an outer side surface of the first dummy insulating layer.

4. The semiconductor device according to claim 1, wherein Each of the extending portions has a recessed portion having a concave shape in the second direction.

5. The semiconductor device according to claim 1 , further comprising: an interlayer insulating layer covering the stacked structure in the pad area, The plurality of first separation regions include a first upper separation region in contact with the interlayer insulating layer and a first lower separation region in contact with the stack structure, and A first width of each of the first upper separation regions in the second direction is greater than a second width of each of the first lower separation regions in the second direction. The semiconductor device according to claim 1 , wherein: The plurality of second separation regions extend further in the first direction on the substrate than the plurality of first separation regions.

7. The semiconductor device according to claim 6, wherein The plurality of second separation regions are provided in the cell array region and in the pad region, and the plurality of first separation regions are provided in the pad region.

8. The semiconductor device according to claim 1, wherein The extending portion is disposed under the plurality of cell contact plugs.

9. The semiconductor device according to claim 1, wherein The plurality of cell contact plugs include a first cell contact plug and a second cell contact plug penetrating one of the second dummy insulating layers and having different heights from each other in a third direction substantially perpendicular to an upper surface of the substrate.

10. The semiconductor device according to claim 9, wherein A height difference between the first cell contact plug and the second cell contact plug is substantially the same as a sum of a thickness of one of the gate electrodes and a thickness of one of the mold insulating layers.

11. The semiconductor device according to claim 1, wherein In each of the plurality of first separation regions, a gap between the first dummy insulating layers decreases toward an upper surface of the substrate.

12. The semiconductor device according to claim 1, further comprising: At least one sacrificial layer is disposed between the horizontal portion and the extension portion and includes a material different from that of the gate electrode.

13. The semiconductor device according to claim 1, further comprising: The peripheral circuit region is disposed under the substrate and includes circuit elements electrically connected to the gate electrode.

14. The semiconductor device according to claim 13, further comprising: a through wiring electrically connecting the peripheral circuit region to a memory cell region disposed on the peripheral circuit region in a pad region, The through wiring is electrically connected to the plurality of cell contact plugs.

15. A semiconductor device, comprising: a substrate having a cell array region and a pad region; a stacked structure comprising a gate electrode having a stepped shape in the pad region and a molded insulating layer; an interlayer insulating layer covering the stacked structure in the pad area; a plurality of first separation regions penetrating the stacked structure and the interlayer insulating layer in the pad region, wherein the plurality of first separation regions include a first insulating layer and a second insulating layer, the first insulating layer covering one end of the gate electrode and extending in a first direction substantially perpendicular to the upper surface of the substrate, and the second insulating layer being disposed between the first insulating layers; a plurality of second separation regions dividing the stack structure into a plurality of regions on the substrate and extending in a second direction; and at least one dummy channel disposed between the plurality of first separation regions and the plurality of second separation regions, and Wherein, each of the multiple first separation regions is provided with multiple unit contact plugs, and the multiple unit contact plugs penetrate the first insulating layer and are connected to the gate electrode, and the multiple first separation regions extend in the second direction in the pad region and are arranged side by side in a third direction perpendicular to the second direction.

16. The semiconductor device according to claim 15, wherein The at least one dummy channel is spaced apart from the plurality of cell contact plugs.

17. The semiconductor device according to claim 15, wherein The first insulating layer includes a material different from that of the molded insulating layer.

18. The semiconductor device according to claim 15, wherein One or more of the plurality of first separation regions are disposed between the plurality of second separation regions.

19. A semiconductor device, comprising: a substrate having a cell array region and a pad region; a stacked structure comprising gate electrodes and molded insulating layers alternately stacked on the substrate and having a stepped shape in the pad region; an interlayer insulating layer covering the stacked structure in the pad area; a dummy insulating layer, dividing the stacked structure and the interlayer insulating layer into a plurality of regions and comprising a material different from that of the interlayer insulating layer; an extending portion contacting the dummy insulating layer in a first direction in the stacked structure and spaced apart from each other in a second direction substantially perpendicular to an upper surface of the substrate between the gate electrodes; as well as a plurality of cell contact plugs disposed in the dummy insulating layer and connected to the gate electrode, and The extending portion includes a first extending portion and a second extending portion, the first extending portion and the second extending portion are arranged at different levels in the second direction, and one end of the first extending portion and one end of the second extending portion are arranged in different positions in the first direction.

20. The semiconductor device according to claim 19, wherein Each of the extending portions has a recessed portion having a concave shape.

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