Display device and method for manufacturing the same

Abstract

The present application relates to a display device and a method for manufacturing a display device. The display device includes a substrate and pixels. The substrate includes: a display area including pixel areas, each pixel area including a first area and a second area; and a non-display area surrounding at least one side of the display area. Pixels are arranged in the pixel area, and each pixel includes a light-emitting element. Each pixel also includes: a pixel circuit unit, which is arranged in the first area and includes at least one transistor and at least one capacitor; and a display element unit, which is arranged in the second area and includes an emission area to emit light. Each of the pixel circuit unit and the display element unit has a multilayer structure including one or more conductive layers and one or more insulating layers. At least one layer in the pixel circuit unit and at least one layer in the display element unit are arranged in the same layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0074277, filed on June 21, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Various embodiments generally relate to a display device and a method of manufacturing the display device. Background Art

[0004] Light-emitting diodes (LEDs) can have relatively satisfactory durability even under harsh environmental conditions and have excellent performance in terms of lifespan and brightness characteristics. In order to apply LEDs to lighting equipment, display devices, etc., the LEDs are generally connected to electrodes so that a voltage from a power supply can be applied to the LEDs. Various studies have been conducted on the arrangement relationship between the LEDs and the electrodes with respect to the application purposes of the LEDs, methods for reducing the space required for the electrodes, and methods for manufacturing the LEDs.

[0005] The above information disclosed in this section is only for understanding the background of the present inventive concept and therefore it may contain information that does not form the prior art. Summary of the Invention

[0006] Some aspects can provide a display device in which light emitting elements are concentratedly disposed in a target area so that light output efficiency can be improved, and the number of masks used to manufacture the display device is reduced so that a process of manufacturing the display device can be simplified.

[0007] Some aspects can provide a method of manufacturing a display device in which light-emitting elements are concentratedly disposed in a target area so that light output efficiency can be improved, and the number of masks used to manufacture the display device is reduced so that the process of manufacturing the display device can be simplified.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the inventive concept.

[0009] According to some aspects, a display device includes a substrate and pixels. The substrate includes a display area and a non-display area. The display area includes a pixel area, and each pixel area in the pixel area includes a first area and a second area. The non-display area surrounds at least one side of the display area. The pixels are arranged in the pixel area. Each of the pixels includes a light-emitting element. Each of the pixels also includes a pixel circuit unit and a display element unit. The pixel circuit unit is arranged in the first area. The pixel circuit unit includes at least one transistor and at least one capacitor. The display element unit is arranged in the second area. The display element unit includes an emission area configured to emit light. Each of the pixel circuit unit and the display element unit has a multilayer structure including one or more conductive layers and one or more insulating layers. At least one layer in the pixel circuit unit and at least one layer in the display element unit are arranged in the same layer.

[0010] According to some aspects, a method for manufacturing a display device includes forming a pixel including a pixel region. The pixel region includes a first region and a second region. Forming the pixel includes: forming a pixel circuit portion including at least one transistor and at least one capacitor in the first region; and forming a display element portion including a light-emitting element in the second region. Each of the pixel circuit portion and the display element portion has a multilayer structure including one or more conductive layers and one or more insulating layers. At least one layer in the pixel circuit portion and at least one layer in the display element portion are formed using the same process.

[0011] According to various aspects, a pixel circuit portion and a display element portion can be provided on the same surface of a substrate, so that the thickness of the display device can be reduced.

[0012] Furthermore, in each embodiment, components included in the pixel circuit portion and components included in the display element portion can be formed by the same process, so that the process of manufacturing the display device can be simplified.

[0013] The foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings illustrate embodiments of the present inventive concept and, together with the description, serve to explain the principles of the present inventive concept. The accompanying drawings are included to provide a further understanding of the present inventive concept and are incorporated in and constitute a part of this specification.

[0015] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment.

[0016] Figure 1B It shows that according to the embodiment Figure 1A A cross-sectional view of a light-emitting element.

[0017] Figure 2A is a perspective view schematically showing a light emitting element according to an embodiment.

[0018] Figure 2B It shows that according to the embodiment Figure 2A A cross-sectional view of a light-emitting element.

[0019] Figure 3A is a perspective view schematically showing a light emitting element according to an embodiment.

[0020] Figure 3B It shows that according to the embodiment Figure 3A A cross-sectional view of a light-emitting element.

[0021] Figure 4A is a perspective view schematically showing a light emitting element according to an embodiment.

[0022] Figure 4B It shows that according to the embodiment Figure 4A A cross-sectional view of a light-emitting element.

[0023] Figure 5A A display device according to an embodiment is shown, and more particularly, a display device using Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B Schematic plan view of a display device using any one of the light-emitting elements shown in FIG as a light source.

[0024] Figure 5B It shows that according to the embodiment Figure 5A Schematic cross-sectional view of a display device.

[0025] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E is a diagram showing that according to some embodiments Figure 5A Various circuit diagrams illustrating the electrical connection relationships of components included in a pixel in a display device.

[0026] Figure 7 It shows that according to the embodiment Figure 5A An enlarged plan view of a portion of the EA.

[0027] Figure 8 is a schematic diagram showing an embodiment of the Figure 7 A plan view of the first pixel.

[0028] Figure 9 According to the implementation method Figure 8 A sectional view taken along section line II'.

[0029] Figure 10 According to the implementation method Figure 8 A sectional view taken along section line II-II'.

[0030] Figure 11 According to the implementation method Figure 8 A sectional view taken along section line III-III'.

[0031] Figure 12 Shown according to the embodiment Figure 11 A modified version of the stacking pattern and is related to Figure 8 The cross-sectional view corresponding to the section line III-III'.

[0032] Figure 13 The arrangement according to the embodiment is shown Figure 11 The insulating pattern on the light emitting element is Figure 8 The cross-sectional view corresponding to the section line III-III'.

[0033] Figure 14 According to the implementation method Figure 8 A sectional view taken along section line IV-IV'.

[0034] Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 15E 、 Figure 15F and Figure 15G According to some embodiments, at various stages of manufacture Figure 8 Schematic plan view of a first pixel.

[0035] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 16E 、 Figure 16F 、 Figure 16G 、 Figure 16H 、 Figure 16I 、 Figure 16J and Figure 16K According to some embodiments, at various stages of manufacture Figure 9 A cross-sectional view of a first pixel.

[0036] Figure 17 It shows that according to the embodiment Figure 7 A plan view of the first pixel.

[0037] Figure 18 According to the implementation method Figure 17 A sectional view taken along section line V-V'. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various embodiments. As used herein, the terms "embodiment" and "implementation" can be used interchangeably and are non-limiting examples of one or more concepts in the inventive concepts disclosed herein. However, it is apparent that various embodiments can be put into practice without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of various embodiments. In addition, various embodiments can be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the embodiment can be used or implemented in another embodiment.

[0039] Unless otherwise specified, the embodiments shown should be understood as providing features of varying details of some embodiments. Therefore, unless otherwise specified, the various illustrated features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter, individually or collectively referred to as "an element" or "multiple elements") may be combined, separated, interchanged, and / or rearranged without departing from the present invention.

[0040] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the various elements are not necessarily limited to those shown in the drawings. When the embodiments can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0041] When an element such as a layer is referred to as "on" another element, "connected to" or "coupled to" the other element, it can be directly on the other element, directly connected to or directly coupled to the other element, or there can be an intervening element. However, when an element is referred to as "directly on" another element, "directly connected to" or "directly coupled to" another element, there is no intervening element. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." and "directly between...", "adjacent" and "directly adjacent", "on..." and "directly on..." etc. In addition, the term "connection" can refer to physical connection, electrical connection and / or fluid connection. For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0042] Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0043] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "lower," "above," "upper," "above," "above," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another element(s) as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0044] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the features, wholes, steps, operations, elements, components and / or groups thereof set forth, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and are therefore used to allow for the inherent deviations in the values measured, calculated and / or provided that will be recognized by those of ordinary skill in the art.

[0045] Various embodiments are described herein with reference to cross-sectional views, isometric views, perspective views, plan views, and / or exploded views that are schematic diagrams of idealized embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances should be anticipated. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific illustrated shapes of the regions, but rather include deviations in shapes due to, for example, manufacturing. To this end, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not intended to be limiting.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0047] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings with respect to functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented using electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, and the like, which can be formed using semiconductor-based or other manufacturing technologies. Where blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented using dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the inventive concept, each block, unit, and / or module in some embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the inventive concept, the blocks, units and / or modules in some embodiments may be physically combined into more complex blocks, units and / or modules.

[0048] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0049] Figure 1A is a perspective view schematically showing a light emitting element LD according to an embodiment. Figure 1B It shows that according to the embodiment Figure 1A A cross-sectional view of a light-emitting element LD. Figure 2A is a perspective view schematically showing a light emitting element LD according to an embodiment. Figure 2B It shows that according to the embodiment Figure 2A A cross-sectional view of a light-emitting element LD. Figure 3A is a perspective view schematically showing a light emitting element LD according to an embodiment. Figure 3B It shows that according to the embodiment Figure 3A A cross-sectional view of a light-emitting element LD. Figure 4A is a perspective view schematically showing a light emitting element LD according to an embodiment. Figure 4B It shows that according to the embodiment Figure 4A A cross-sectional view of a light-emitting element LD.

[0050] For the purpose of illustration, reference will be made to Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3BThe light emitting element LD manufactured by the etching method will be described and will be referred to later. Figure 4A and Figure 4B The light emitting element LD manufactured by the growth method is described. In the embodiment, the type and / or shape of the light emitting element LD is not limited to Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B The embodiment shown in .

[0051] refer to Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B The light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as an emission stack formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0052] In an embodiment, the light emitting element LD may be formed into a shape extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end in the extending direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be provided on one end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided on the other end of the light emitting element LD.

[0053] The light emitting element LD may have various shapes. For example, the light emitting element LD may have a rod-like shape or a bar-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). In an embodiment, the length L of the light emitting element LD relative to the longitudinal direction may be greater than the diameter D (or the width of the cross section) of the light emitting element LD. The light emitting element LD may include a light emitting diode manufactured to have a small size (e.g., having a length L and / or diameter D corresponding to the micrometer or nanometer scale). In various embodiments, the shape of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device.

[0054] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material forming the first semiconductor layer 11 is not limited to these materials, and the first semiconductor layer 11 may be formed of various other materials.

[0055] The active layer 12 may be provided on the first semiconductor layer 11 and have a single quantum well structure or a multiple quantum well structure. The position of the active layer 12 may be changed in various ways depending on the type of the light emitting element LD. The active layer 12 may emit light having a wavelength in the range of 400 nm to 900 nm and use a double heterostructure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or InAlGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0056] If an electric field of a predetermined voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by coupling of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for pixels of various light emitting devices and display devices.

[0057] The second semiconductor layer 13 may be provided on the active layer 12 and may include a semiconductor layer having a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials.

[0058] In an embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) relative to the longitudinal direction of the light emitting element LD. For example, the first semiconductor layer 11 may have a width (or thickness) greater than the width (or thickness) of the second semiconductor layer 13 relative to the longitudinal direction of the light emitting element LD. Figures 1A to 3BAs shown in , the active layer 12 of the light emitting element LD may be provided at a position closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11 .

[0059] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. Figure 3A and Figure 3B As shown in , the light emitting element LD may further include an additional electrode 16 provided on one end of the first semiconductor layer 11 (eg, a lower end of the first semiconductor layer 11 ).

[0060] Although each of the additional electrodes 15 and 16 may be formed of an ohmic contact electrode, the embodiment is not limited thereto. Furthermore, each of the additional electrodes 15 and 16 may include a metal or a metal oxide. For example, at least one of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides or alloys thereof, and indium tin oxide (ITO) may be used alone or in combination. However, the embodiment is not limited thereto.

[0061] The materials included in the additional electrodes 15 and 16 can be the same as or different from each other. The additional electrodes 15 and 16 can be transparent or translucent. Therefore, light generated by the light-emitting element LD can pass through the additional electrodes 15 and 16 and then be emitted to the outside of the light-emitting element LD. In some embodiments, in the case where the light generated by the light-emitting element LD passes through areas other than the opposite ends of the light-emitting element LD rather than passing through the additional electrodes 15 and 16 and being emitted to the outside of the light-emitting element LD, the additional electrodes 15 and 16 can be made of an opaque metal.

[0062] In an embodiment, the light emitting element LD may further include an insulating layer 14. However, in some embodiments, the insulating layer 14 may be omitted or provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0063] The insulating layer 14 can prevent (or mitigate) short circuits caused by the active layer 12 contacting conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, due to the insulating layer 14, defects occurring on the surface of the light-emitting element LD can be reduced (e.g., minimized), thereby improving the lifespan and efficiency of the light-emitting element LD. When multiple light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent (or mitigate) undesirable short circuits between the light-emitting elements LD. Whether or not the insulating layer 14 is provided is not limited as long as the active layer 12 can be prevented from short-circuiting with external conductive materials.

[0064] like Figure 1A and Figure 1B As shown in , the insulating layer 14 may be provided in a shape surrounding the entire outer peripheral surface of the emission stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15. For illustration purposes, Figure 1A The insulating layer 14 is shown with a portion thereof removed. The first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 included in the light emitting element LD may be surrounded by the insulating layer 14 .

[0065] Although the insulating layer 14 is described as surrounding the entire outer peripheral surface of the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 in the above embodiment, the embodiment is not limited thereto.

[0066] In some embodiments, such as Figure 2A and Figure 2B As shown in , the insulating layer 14 may surround the outer peripheral surfaces of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not surround the outer peripheral surface of the additional electrode 15 provided on the second semiconductor layer 13, or may surround only a portion of the outer peripheral surface of the additional electrode 15 and not surround another portion of the outer peripheral surface of the additional electrode 15. Here, the insulating layer 14 may allow at least the opposite end of the light emitting element LD to be exposed to the outside. For example, the insulating layer 14 may allow not only the additional electrode 15 provided on one end of the second semiconductor layer 13 to be exposed to the outside, but also one end of the first semiconductor layer 11 to be exposed to the outside. In an embodiment, such as Figure 3A and Figure 3B , in the case where the additional electrodes 15 and 16 are provided on respective opposite ends of the light emitting element LD, the insulating layer 14 may allow at least a portion of each of the additional electrodes 15 and 16 to be exposed to the outside. Alternatively, in some embodiments, the insulating layer 14 may not be provided.

[0067] In an embodiment, the insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include at least one insulating material selected from the group consisting of SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. In other words, various materials having insulating properties may be used.

[0068] If the insulating layer 14 is provided on the light-emitting element LD, a short circuit between the active layer 12 and the first electrode and / or the second electrode (not shown) can be prevented. In addition, due to the insulating layer 14, defects occurring on the surface of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. In the case where multiple light-emitting elements LD are provided in close contact with each other, the insulating layer 14 can prevent undesirable short circuits from occurring between the light-emitting elements LD.

[0069] The above-mentioned light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, the light-emitting element LD can be surface-treated so that when a plurality of light-emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission area (for example, the emission area of each pixel or the emission area of each sub-pixel), the light-emitting elements LD can be evenly distributed in the solution instead of unevenly agglomerated.

[0070] A light-emitting device including at least one of the above-described light-emitting elements LD can be used in various devices, including display devices that utilize light sources. For example, when multiple light-emitting elements LD are arranged in the emission region of each pixel of a display panel, the light-emitting element LD can serve as the light source of the pixel. However, the application areas of the light-emitting element LD are not limited to the above examples. For example, the light-emitting element LD can also be used in various devices that utilize light sources, such as lighting equipment.

[0071] Next, we will refer to Figure 4A and Figure 4B The light-emitting element LD manufactured by the growth method is described.

[0072] The following description of the light-emitting element LD manufactured by the growth method will focus on the differences from the above-described embodiment, and components of the light-emitting element LD not separately described in the following description may be consistent with those of the above-described embodiment. For this reason, the same reference numerals will be used to refer to the same components, and similar reference numerals will be used to refer to similar components.

[0073] refer to Figure 4A and Figure 4B According to an embodiment, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light emitting element LD may include an emission pattern 10 having a core-shell structure. The emission pattern 10 may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an additional electrode 15, wherein the first semiconductor layer 11 is provided in a central portion of the light emitting element LD, the active layer 12 surrounds at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounds at least one side of the active layer 12, and the additional electrode 15 surrounds at least one side of the second semiconductor layer 13.

[0074] The light emitting element LD may be formed in a polygonal pyramid shape extending in one direction. For example, the light emitting element LD may have a hexagonal pyramid shape. If the direction in which the light emitting element LD extends is defined as the longitudinal direction, the light emitting element LD may have a first end (or lower end) and a second end (or upper end) in the longitudinal direction. A portion of any one of the first semiconductor layer 11 and the second semiconductor layer 13 on the first end (or lower end) of the light emitting element LD may be exposed. A portion of the other of the first semiconductor layer 11 and the second semiconductor layer 13 on the second end (or upper end) of the light emitting element LD may be exposed. For example, a portion of the first semiconductor layer 11 on the first end (or lower end) of the light emitting element LD may be exposed, and a portion of the second semiconductor layer 13 on the second end (or upper end) of the light emitting element LD may be exposed. In an embodiment, when the light emitting element LD includes an additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 on the second end (or upper end) of the light emitting element LD may be exposed.

[0075] In an embodiment, the first semiconductor layer 11 may be provided in the core (e.g., the central (or middle) portion) of the light emitting element LD. The light emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting element LD and the emission pattern 10 may each also have a hexagonal pyramid shape.

[0076] The active layer 12 may be provided and / or formed in a shape surrounding the outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD. Specifically, the active layer 12 may be provided and / or formed in a shape surrounding the first semiconductor layer 11 except for the lower end of the opposite ends of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD.

[0077] The second semiconductor layer 13 may be provided and / or formed in a shape surrounding the active layer 12 in the longitudinal direction of the light emitting element LD, and may include a semiconductor layer having a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0078] In an embodiment, the light emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode electrically coupled to the second semiconductor layer 13, but the embodiment is not limited thereto.

[0079] As described above, the light-emitting element LD may have a hexagonal pyramid shape with opposite ends protruding outward, and may be implemented as an emission pattern 10 having a core-shell structure including a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an additional electrode 15, wherein the first semiconductor layer 11 is disposed in the central portion of the core-shell structure, the active layer 12 surrounds the first semiconductor layer 11, the second semiconductor layer 13 surrounds the active layer 12, and the additional electrode 15 surrounds the second semiconductor layer 13. The first semiconductor layer 11 may be disposed on a first end (or lower end) of the light-emitting element LD having a hexagonal pyramid shape, and the additional electrode 15 may be disposed on a second end (or upper end) of the light-emitting element LD.

[0080] In an embodiment, the light emitting element LD may further include an insulating layer 14 disposed on an outer peripheral surface of the emission pattern 10 having the core-shell structure. The insulating layer 14 may include a transparent insulating material.

[0081] Figure 5A A display device according to an embodiment is shown, and more particularly, a display device using Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B Schematic plan view of a display device using any one of the light-emitting elements shown in FIG as a light source.

[0082] For illustrative purposes, Figure 5A The structure of the display device is schematically shown, focusing on the display area where the image is displayed. In some embodiments, although not shown, at least one driving circuit (e.g., a scan driver and a data driver) and / or multiple lines may also be provided in the display device.

[0083] refer to Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B and Figure 5A According to some embodiments, a display device may include a substrate SUB, a plurality of pixels PXL, a driver (not shown), and a line portion (not shown), wherein the plurality of pixels PXL are disposed on the substrate SUB, and each of the plurality of pixels PXL includes at least one light emitting element LD, the driver (not shown) is disposed on the substrate SUB and configured to drive the pixels PXL, and the line portion (not shown) is disposed to connect the pixels PXL to the driver.

[0084] According to the driving method, the display device can be divided into a passive matrix type display device and an active matrix type display device. For example, when the display device according to the embodiment is implemented as an active matrix type, each of the pixels PXL may include a driving transistor and a switching transistor, wherein the driving transistor is configured to control the amount of current to be supplied to the light emitting element LD, and the switching transistor is configured to transmit a data signal to the driving transistor.

[0085] Some active-matrix display devices may be capable of selectively turning on each pixel PXL according to resolution, contrast, and operating speed; however, embodiments are not limited thereto. For example, a passive-matrix display device in which the pixels PXL can be turned on in groups may also employ components for driving the light-emitting element LD (e.g., the first electrode and the second electrode).

[0086] The substrate SUB may include a display area DA and a non-display area NDA.

[0087] In an embodiment, the display area DA may be provided in the central portion of the display device, and the non-display area NDA may be provided outside the display area DA in a manner surrounding the display area DA, for example, in the peripheral portion of the display device. The positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0088] The display area DA may be a region in which pixels PXL for displaying an image are disposed, and the non-display area NDA may be a region in which a driver for driving the pixels PXL and some of line portions for coupling the pixels PXL to the driver are disposed.

[0089] The display area DA can have various shapes. For example, the display area DA can be configured as a closed polygonal shape including linear sides. Alternatively, the display area DA can be configured as a circular shape and / or an elliptical shape including curved sides. As another alternative, the display area DA can be configured as various shapes, such as a semicircular shape and a semi-elliptical shape including linear sides and curved sides.

[0090] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment, the non-display area NDA may surround a circumference (or edge) of the display area DA.

[0091] The substrate SUB may include a transparent insulating material to allow light to be transmitted.

[0092] The substrate SUB may be a rigid substrate. For example, the rigid substrate SUB may be at least one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0093] The substrate SUB may be a flexible substrate. Here, the flexible substrate SUB may be a plastic substrate or a film substrate including a polymer organic material. For example, the flexible substrate SUB may include at least one of polystyrene, polyvinyl alcohol, poly(methyl methacrylate), polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0094] However, the material constituting the substrate SUB may vary and includes, for example, fiber reinforced plastic (FRP).

[0095] One area of the substrate SUB is provided as a display area DA in which the pixels PXL are provided, and another area of the substrate SUB is provided as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel areas in which the pixels PXL are formed, and a non-display area NDA provided around the display area DA.

[0096] The pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment, the pixels PXL may be arranged in the display area DA in a stripe arrangement structure or a pentile arrangement structure, but the embodiment is not limited thereto.

[0097] Each pixel PXL may include at least one light-emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light-emitting element LD may have a small size corresponding to the micrometer or nanometer level and may be connected in parallel with adjacent light-emitting elements LD, but the embodiment is not limited thereto. The light-emitting element LD may form the light source of the corresponding pixel PXL.

[0098] Each of the pixels PXL may include at least one light source driven by a predetermined signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first driving power source and a second driving power source). Figures 1A to 4B At least one of the light-emitting elements LD in the described embodiments is, for example, at least one ultra-small light-emitting element LD having a small size corresponding to the nanometer or micrometer level. However, in some embodiments, the type of light-emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0099] In an embodiment, the color, type, and / or number of the pixels PXL are not particularly limited. For example, the color of light emitted from each pixel PXL may be changed in various ways.

[0100] The driver may provide a predetermined signal and a predetermined power source to each of the pixels PXL through the line portion, and thus control the operation of the pixels PXL. Figure 5A In the figure, the line part is omitted.

[0101] The driver may include a scan driver, an emission driver, a data driver, and a timing controller. The scan driver is configured to provide a scan signal to the pixel PXL via a scan line, the emission driver is configured to provide an emission control signal to the pixel PXL via an emission control line, and the data driver is configured to provide a data signal to the pixel PXL via a data line. The timing controller may control the scan driver, the emission driver, and the data driver.

[0102] Figure 5B It shows that according to the embodiment Figure 5A Schematic cross-sectional view of a display device.

[0103] Reference Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B , a display device according to some embodiments may include a substrate SUB, first to fourth insulating layers INS1 to INS4 disposed over the substrate SUB, and first to fourth conductive layers CL1 to CL4 disposed over the substrate SUB.

[0104] The display device may further include an encapsulation layer ENC disposed on the fourth insulating layer INS4 and the fourth conductive layer CL4 .

[0105] The first insulating layer INS1 may be disposed and / or formed on the substrate SUB. In the case where a buffer layer BFL is disposed on the substrate SUB, the first insulating layer INS1 may be disposed and / or formed on the buffer layer BFL.

[0106] The first insulating layer INS1 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the thickness direction (e.g., the third direction DR3). The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic insulating layer may include, for example, at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0107] The first conductive layer CL1 may be disposed and / or formed on the first insulating layer INS1. The first conductive layer CL1 may have a single-layer structure or a multi-layer structure. The first conductive layer CL1 may include a conductive material. For example, the conductive material may include a metal or a transparent conductive oxide. In an embodiment, if the first conductive layer CL1 has a single-layer structure, the first conductive layer CL1 may include a metal layer or a transparent conductive layer. The metal layer may include at least one of molybdenum, silver, titanium, copper, and aluminum, or an alloy of at least one of these. The transparent conductive layer may include a transparent conductive oxide, such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). In addition, the transparent conductive layer may include at least one of poly(3,4-ethylenedioxythiophene) (PEDOT), metal nanowires, and graphene.

[0108] If the first conductive layer CL1 has a multi-layer structure, the first conductive layer CL1 may include a plurality of metal layers. For example, the plurality of metal layers may form a three-layer structure of titanium / aluminum / titanium, but the embodiment is not limited thereto. Alternatively, the first conductive layer CL1 may have a multi-layer structure including a single metal layer and a transparent conductive layer, or a multi-layer structure including a plurality of metal layers and a transparent conductive layer.

[0109] The second insulating layer INS2 may be disposed and / or formed on the first conductive layer CL1 and cover the first conductive layer CL1. The second insulating layer INS2 may have a material that is the same as or different from that of the first insulating layer INS1. For example, the second insulating layer INS2 may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0110] The second conductive layer CL2 may be disposed and / or formed on the second insulating layer INS2. The second conductive layer CL2 may have a single-layer structure or a multi-layer structure. The second conductive layer CL2 may have a material that is the same as or different from that of the first conductive layer CL1. For example, the second conductive layer CL2 may include a conductive material.

[0111] The third insulating layer INS3 may be disposed and / or formed on the second conductive layer CL2 and cover the second conductive layer CL2. The third insulating layer INS3 may have a material that is the same as or different from that of the first insulating layer INS1 and the second insulating layer INS2. For example, the third insulating layer INS3 may include an inorganic insulating layer or an organic insulating layer, the inorganic insulating layer including an inorganic material and the organic insulating layer including an organic material.

[0112] The third conductive layer CL3 may be disposed and / or formed on the third insulating layer INS3. The third conductive layer CL3 may have a single-layer structure or a multi-layer structure. The third conductive layer CL3 may have a material that is the same as or different from that of the first conductive layer CL1 and the second conductive layer CL2. For example, the third conductive layer CL3 may include a conductive material.

[0113] The fourth insulating layer INS4 may be disposed and / or formed on the third conductive layer CL3 and cover the third conductive layer CL3. The fourth insulating layer INS4 may have a material that is the same as or different from that of the first to third insulating layers INS1 to INS3. For example, the fourth insulating layer INS4 may be formed of an organic insulating layer including an organic material.

[0114] The fourth conductive layer CL4 may be disposed and / or formed on the fourth insulating layer INS4. The fourth conductive layer CL4 may have a single-layer structure or a multi-layer structure. The fourth conductive layer CL4 may have a material that is the same as or different from that of the first to third conductive layers CL1 to CL3. For example, the fourth conductive layer CL4 may include a conductive material.

[0115] The encapsulation layer ENC may be disposed and / or formed on the fourth conductive layer CL4 and the fourth insulating layer INS4. The encapsulation layer ENC may be formed of a single layer or multiple layers. The encapsulation layer ENC may include multiple insulating layers that cover the light-emitting element LD included in each pixel PXL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer ENC may have a structure formed by alternatingly stacking inorganic and organic layers.

[0116] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E is a diagram showing that according to some embodiments Figure 5A Various circuit diagrams illustrating the electrical connection relationships of components included in a pixel in a display device.

[0117] For example, Figures 6A to 6EVarious embodiments of electrical connection relationships between components included in a pixel PXL that may be employed in an active display device are shown. However, the types of components included in a pixel PXL to which the embodiments may be applied are not limited thereto.

[0118] exist Figures 6A to 6E In the definition of the term "pixel PXL", not only Figure 5A Each of the pixels PXL shown in FIG includes components, and also includes an area where components are provided. In an embodiment, Figures 6A to 6E Each pixel PXL shown in FIG can be set to Figure 5A The pixels PXL may have substantially the same or similar structures.

[0119] For the purpose of illustration, reference will be made to 6A to 6D The emission unit EMU including a plurality of light emitting elements LD coupled in parallel with each other will be described, and reference will be made later to Figure 6E An emission unit EMU is described which comprises at least one series stage with light emitting elements LD coupled in parallel with one another.

[0120] refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B as well as 6A to 6D Each pixel (PXL, hereinafter referred to as “pixel”) may include an emission unit EMU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further optionally include a pixel circuit 144 configured to drive the emission unit EMU.

[0121] In an embodiment, the emission unit EMU may include a plurality of light-emitting elements LD coupled between a first power line PL1 and a second power line PL2, wherein a first driving power source VDD (e.g., a first driving power source voltage) is applied to the first power line PL1, and a second driving power source VSS (e.g., a second driving power source voltage) is applied to the second power line PL2. For example, the emission unit EMU may include a first electrode EL1 (or "first array electrode"), a second electrode EL2 (or "second array electrode"), and a plurality of light-emitting elements LD, wherein the first electrode EL1 is coupled to the first driving power source VDD via the pixel circuit 144 and the first power line PL1, and the second electrode EL2 is coupled to the second driving power source VSS via the second power line PL2, and the plurality of light-emitting elements LD are coupled in parallel between the first electrode EL1 and the second electrode EL2. In an embodiment, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0122] In an embodiment, each of the light-emitting elements LD included in the emission unit EMU may include a first end coupled to a first driving power source VDD via a first electrode EL1 and a second end coupled to a second driving power source VSS via a second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. Here, during the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a value greater than or equal to the threshold voltage of the light-emitting element LD.

[0123] As described above, the light emitting elements LD coupled in parallel between the first electrode EL1 and the second electrode EL2 supplied with voltages having different potentials can form respective effective light sources. The effective light sources can be gathered to form the emission unit EMU of the pixel PXL.

[0124] The light-emitting element LD of the emission unit EMU can emit light having a brightness corresponding to the drive current supplied to the light-emitting element LD of the emission unit EMU through the pixel circuit 144. For example, during each frame period, the pixel circuit 144 can supply a drive current corresponding to the grayscale level of the corresponding frame data to the emission unit EMU. The drive current supplied to the emission unit EMU can be divided among the light-emitting elements LD connected in parallel with each other. Therefore, each of the light-emitting elements LD can emit light having a brightness corresponding to the current applied to the light-emitting element LD, so that the emission unit EMU can emit light having a brightness corresponding to the drive current.

[0125] although 6A to 6D The embodiment in which the light emitting elements LD are connected in parallel with each other between the first driving power source VDD and the second driving power source VSS is shown, but the embodiment is not limited thereto. In the embodiment, in addition to the light emitting elements LD forming each effective light source, the emission unit EMU may further include at least one ineffective light source. For example, Figure 6D As shown in FIG, at least one reverse light-emitting element LDr may be coupled between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse light-emitting element LDr and the light-emitting element LD forming the effective light source may be coupled in parallel with each other between the first electrode EL1 and the second electrode EL2. Here, the reverse light-emitting element LDr may be coupled between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the light-emitting element LD. Even when a predetermined drive voltage (e.g., a forward drive voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains deactivated. Therefore, substantially no current flows through the reverse light-emitting element LDr.

[0126] The pixel circuit 144 may be coupled to the scan line and data line of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (where i is a natural number) and the j-th column (where j is a natural number) of the display area DA, the pixel circuit 144 of the pixel PXL may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, as Figure 6A and Figure 6B As shown in FIG, the pixel circuit 144 may include a first transistor T1 and a second transistor T2 and a first capacitor C1 and a second capacitor C2. The structure of the pixel circuit 144 is not limited to Figure 6A and Figure 6B The embodiment shown in .

[0127] The first transistor (switching transistor) T1 may include a first terminal coupled to the j-th data line Dj and a second terminal coupled to the first node N1. Here, the first terminal and the second terminal of the first transistor T1 are different from each other, and for example, if the first terminal is a source electrode, the second terminal is a drain electrode. The gate electrode of the first transistor T1 may be coupled to the i-th scan line Si.

[0128] When a scan signal having a voltage (e.g., a low-level voltage) capable of turning on the first transistor T1 is supplied from the i-th scan line Si, the first transistor T1 is turned on to electrically couple the j-th data line Dj to the first node N1. Here, a data signal of a corresponding frame is supplied to the j-th data line Dj, and the data signal is transmitted to the first node N1. The first capacitor C1 can store a voltage corresponding to the potential voltage difference between the first driving power source VDD and the data signal voltage.

[0129] The second transistor (driving transistor) T2 may include a first terminal coupled to a first driving power source VDD and a second terminal electrically coupled to the first electrode EL1 for the light emitting element LD. The gate electrode of the second transistor T2 may be coupled to the first node N1. The second transistor T2 may control the amount of driving current to be supplied to the light emitting element LD in response to the voltage of the first node N1.

[0130] The first capacitor C1 may have a first electrode coupled to the first driving power source VDD and a second electrode coupled to the first node N1. The first capacitor C1 may be charged with a voltage corresponding to a voltage difference between the first driving power source VDD and the data signal supplied to the first node N1, and maintain the charged voltage until a data signal of a subsequent frame is supplied.

[0131] The second capacitor C2 may have a first electrode coupled to the second node N2 and a second electrode coupled to the second power line PL2. The second capacitor C2 may reduce coupling of the light emitting element LD of the emission unit EMU.

[0132] Figure 6A and Figure 6B Each shows a pixel circuit 144, which includes a first transistor T1, a first capacitor C1, a second transistor T2 and a second capacitor C2, wherein the first transistor T1 is configured to transmit a data signal to the pixel PXL, the first capacitor C1 is configured to store the data signal, the second transistor T2 is configured to supply a driving current to the light-emitting element LD in response to the data signal, and the second capacitor C2 is configured to reduce the coupling of the light-emitting element LD.

[0133] However, the embodiment is not limited thereto, and the structure of the pixel circuit 144 may be modified in various ways. For example, the pixel circuit 144 may further include at least one transistor element (such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD) or other circuit elements (such as a boosting capacitor for boosting the voltage of the first node N1).

[0134] In addition, despite Figure 6A 1 and 2. The transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are shown as being formed of P-type transistors, but the embodiment is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0135] refer to Figures 1A to 4B 、 Figure 5A and Figure 6B , the first transistor T1 and the second transistor T2 according to the embodiment can be formed by N-type transistors. In addition to the change in the connection position of some components due to the change in the type of transistor, Figure 6B The configuration and operation of the pixel circuit 144 shown in FIG. Figure 6A The configuration and operation of the pixel circuit 144 are similar. Therefore, detailed description thereof will be omitted.

[0136] In the embodiment, the configuration of the pixel circuit 144 is not limited to Figure 6A and Figure 6B For example, the configuration of the pixel circuit 144 may be similar to Figure 6C and Figure 6D The configuration of the embodiment shown in .

[0137] like Figure 6C and Figure 6DAs shown in , the pixel circuit 144 can be coupled to the scan line and the data line of the pixel PXL. For example, if the pixel PXL is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the pixel PXL can be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0138] In an embodiment, the pixel circuit 144 may also be coupled to at least one scan line. For example, a pixel PXL arranged in the i-th row of the display area DA may also be coupled to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In an embodiment, the pixel circuit 144 may be coupled not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel circuit 144 may also be coupled to the initialization power supply Vint.

[0139] The pixel circuit 144 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2 .

[0140] The first transistor (driving transistor) T1 may include a first electrode (e.g., a source electrode) coupled to a first driving power source VDD via a fifth transistor T5 and a second electrode (e.g., a drain electrode) coupled to a first end of the light-emitting element LD via a sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 may control a driving current flowing between the first driving power source VDD and the second driving power source VSS via the light-emitting element LD in response to a voltage at the first node N1.

[0141] The second transistor (switching transistor) T2 can be coupled between the j-th data line Dj coupled to the pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 can be coupled to the i-th scan line Si coupled to the pixel PXL. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 is turned on to electrically couple the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj can be transmitted to the first transistor T1.

[0142] The third transistor T3 may be coupled between the drain electrode of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 may be coupled to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 may be turned on to electrically couple the drain electrode of the first transistor T1 to the first node N1.

[0143] The fourth transistor T4 may be coupled between the first node N1 and an initialization power line IPL to which an initialization power source Vint is applied. A gate electrode of the fourth transistor T4 may be coupled to a previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 may be turned on, so that the voltage of the initialization power source Vint may be transmitted to the first node N1. Here, the initialization power source Vint may have a voltage less than or equal to the minimum voltage of the data signal.

[0144] The fifth transistor T5 may be coupled between the first driving power source VDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and in other cases, the fifth transistor T5 may be turned on.

[0145] The sixth transistor T6 is coupled between the first transistor T1 and the first terminal of the light emitting element LD. A gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and otherwise the sixth transistor T6 may be turned on.

[0146] The seventh transistor T7 can be coupled between the initialization power line IPL and the first terminal of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be coupled to any one of the scan lines of the subsequent stage, for example, it can be coupled to the (i+1)th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first terminal of the light-emitting element LD.

[0147] The first capacitor C1 may be coupled between the first driving power source VDD and the first node N1. The first capacitor C1 may store a voltage corresponding to a voltage difference between a data signal voltage applied to the first node N1 during each frame period and a threshold voltage of the first transistor T1.

[0148] The second capacitor C2 may be coupled between the second node N2 and the second power line PL2. The second capacitor C2 may reduce coupling of the light emitting element LD of the emission unit EMU.

[0149] Despite Figure 6C and Figure 6D1 to 7. The transistors included in the pixel circuit 144 (eg, the first to seventh transistors T1 to T7) are shown as being formed of P-type transistors, but the embodiment is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0150] The structure of the pixel PXL that can be used in connection with one or more embodiments is not limited to 6A to 6D , and the pixel PXL may have various structures. In an embodiment, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and the opposite ends of the light-emitting element LD included in the emission unit EMU may be directly connected to the scan lines Si-1, Si, and Si+1, the j-th data line Dj, the first power line PL1 to which the first driving power VDD is applied, the second power line PL2 to which the second driving power VSS is applied, and / or a predetermined control line.

[0151] although 6A to 6D An embodiment is shown in which all light emitting elements LD of each emission unit EMU are connected in parallel to each other, but the embodiment is not limited thereto. In an embodiment, the emission unit EMU may include at least one series stage including a plurality of light emitting elements LD connected in parallel to each other. In other words, Figure 6E As shown in , the transmitting unit EMU can have a series / parallel hybrid structure. Figure 6E In the embodiment, the light emitting element LD coupled only between the first driving power source VDD and the second driving power source VSS in the same direction is shown as being included in the emission unit EMU, but the embodiment is not limited thereto. Figure 6E The pixel PXL shown in FIG4 may further include at least one reverse light emitting element LDr. However, in the case where the light emitting elements LD are arranged in an offset arrangement, even when at least one reverse light emitting element LDr is provided in the pixel PXL, the number of reverse light emitting elements LDr may be less than the number of effective light sources (i.e., light emitting elements LD) provided in the pixel PXL in the forward direction. Hereinafter, the method according to FIG4 will be described. Figure 6E The emission unit EMU of the embodiment focuses on the light emitting element LD that forms the effective light source of the emission unit EMU.

[0152] refer to Figures 1A to 4B 、 Figure 5A and Figure 6E, the emission unit EMU of the pixel PXL may include a plurality of series stages connected in sequence to each other between a first driving power source VDD and a second driving power source VSS. Each of the series stages may include one or more light-emitting elements LD connected in a forward direction between two electrodes of an electrode pair constituting the corresponding series stage. For example, the emission unit EMU may include a first series stage to a third series stage connected in sequence between the first driving power source VDD and the second driving power source VSS. Each of the first series stage to the third series stage may include: two electrodes EL1 and CP1a, CP1b and CP2a, or CP2b and EL2, which constitute an electrode pair of the corresponding series stage; and a plurality of light-emitting elements LD, which are connected in parallel to each other in a forward direction (for example, in the same direction) between the two electrodes EL1 and CP1a, CP1b and CP2a, or CP2b and EL2.

[0153] The first series connection stage may include the first electrode EL1 and the first-a connection electrode CP1a of the electrodes EL1 and CP1a, CP1b and CP2a, and CP2b and EL2 that constitute the electrode pair included in the emission unit EMU, and at least one first light-emitting element LD1 coupled between the first electrode EL1 and the first-a connection electrode CP1a. For example, the first series connection stage may include the first electrode EL1, the first-a connection electrode CP1a, and a plurality of first light-emitting elements LD1. The first electrode EL1 is coupled to the first driving power supply VDD via the pixel circuit 144. The first-a connection electrode CP1a and the first electrode EL1 together form an electrode pair of the first series connection stage and are coupled to the second driving power supply VSS. The plurality of first light-emitting elements LD1 are coupled between the first electrode EL1 and the first-a connection electrode CP1a. The first terminal (e.g., the second semiconductor layer 13 or the P-type terminal) of each of the first light-emitting elements LD1 may be electrically coupled to the first electrode EL1 of the first series connection stage, and the second terminal (e.g., the first semiconductor layer 11 or the N-type terminal) of each of the first light-emitting elements LD1 may be electrically coupled to the first-a connection electrode CP1a of the first series connection stage. The first light emitting element LD1 may be coupled in parallel between the first electrode EL1 and the 1a-th connection electrode CP1a of the first series stage. The first light emitting element LD1 may be coupled between the first driving power source VDD and the second driving power source VSS in the same direction (e.g., in the forward direction) through the first electrode EL1 and the 1a-th connection electrode CP1a.

[0154] The second series connection stage may include the 1b-connection electrode CP1b and the 2a-connection electrode CP2a of the electrodes EL1 and CP1a, CP1b and CP2a, and CP2b and EL2 constituting the electrode pair included in the emission unit EMU, and at least one second light-emitting element LD2 coupled between the 1b-connection electrode CP1b and the 2a-connection electrode CP2a. For example, the second series connection stage may include the 1b-connection electrode CP1b, the 2a-connection electrode CP2a, and a plurality of second light-emitting elements LD2, wherein the 1b-connection electrode CP1b is coupled to the first driving power supply VDD via the pixel circuit 144 and the first series connection stage, the 2a-connection electrode CP2a and the 1b-connection electrode CP1b together form an electrode pair of the second series connection stage and are coupled to the second driving power supply VSS, and the plurality of second light-emitting elements LD2 are coupled between the 1b-connection electrode CP1b and the 2a-connection electrode CP2a. The first end (e.g., the first semiconductor layer 11 or the N-type end) of each of the second light-emitting elements LD2 can be electrically coupled to the 1b-connecting electrode CP1b of the second series stage, and the second end (e.g., the second semiconductor layer 13 or the P-type end) of each of the second light-emitting elements LD2 can be electrically coupled to the 2a-connecting electrode CP2a of the second series stage. The second light-emitting elements LD2 can be coupled in parallel with each other between the 1b-connecting electrode CP1b and the 2a-connecting electrode CP2a of the second series stage. The second light-emitting elements LD2 can be coupled in the same direction (e.g., in the forward direction) between the first driving power supply VDD and the second driving power supply VSS via the 1b-connecting electrode CP1b and the 2a-connecting electrode CP2a.

[0155] In an embodiment, the connection electrode 1a of the first series stage and the connection electrode 1b of the second series stage can be integrally provided and connected to each other. In other words, the connection electrode 1a of the first series stage and the connection electrode 1b of the second series stage can form the first connection electrode CP1 for electrically connecting the first series stage to the second series stage. As described above, when the connection electrode 1a of the first series stage and the connection electrode 1b of the second series stage are integrally provided, the connection electrode 1a and the connection electrode 1b can each be different regions of the first connection electrode CP1.

[0156] The third series stage may include the 2b-connection electrode CP2b and the second electrode EL2 of the electrodes EL1 and CP1a, CP1b and CP2a, and CP2b and EL2 constituting the electrode pair included in the emission unit EMU, and at least one third light-emitting element LD3 coupled between the 2b-connection electrode CP2b and the second electrode EL2. For example, the third series stage may include the 2b-connection electrode CP2b, the second electrode EL2, and a plurality of third light-emitting elements LD3, wherein the 2b-connection electrode CP2b is coupled to the first driving power supply VDD via the pixel circuit 144 and the first and second series stages, the second electrode EL2 and the 2b-connection electrode CP2b together form an electrode pair of the third series stage and are coupled to the second driving power supply VSS, and the plurality of third light-emitting elements LD3 are coupled between the 2b-connection electrode CP2b and the second electrode EL2. The first end (e.g., the second semiconductor layer 13 or the P-type end) of each of the third light-emitting elements LD3 can be electrically coupled to the 2b-connecting electrode CP2b of the third series stage, and the second end (e.g., the first semiconductor layer 11 or the N-type end) of each of the third light-emitting elements LD3 can be electrically coupled to the second electrode EL2 of the third series stage. The third light-emitting elements LD3 can be coupled in parallel with each other between the 2b-connecting electrode CP2b of the third series stage and the second electrode EL2. The third light-emitting elements LD3 can be coupled in the same direction (e.g., in the forward direction) between the first driving power supply VDD and the second driving power supply VSS via the 2b-connecting electrode CP2b and the second electrode EL2.

[0157] In an embodiment, the 2a connection electrode CP2a of the second series stage and the 2b connection electrode CP2b of the third series stage can be integrally provided with each other and connected to each other. In other words, the 2a connection electrode CP2a of the second series stage and the 2b connection electrode CP2b of the third series stage can form a second connection electrode CP2 for electrically connecting the second series stage to the third series stage. As described above, when the 2a connection electrode CP2a of the second series stage and the 2b connection electrode CP2b of the third series stage are integrally provided with each other, the 2a connection electrode CP2a and the 2b connection electrode CP2b can be different regions of the second connection electrode CP2.

[0158] As described above, in the case where the emission unit EMU includes the light emitting elements LD coupled to each other in a series / parallel hybrid structure, driving current / voltage conditions can be easily adjusted according to the specifications of a product to which the emission unit EMU is applied.

[0159] For example, in an emission unit EMU including light-emitting elements LD connected in a series / parallel hybrid configuration, the drive current of the emission unit EMU can be reduced compared to the drive current of an emission unit EMU including light-emitting elements LD connected in parallel. Furthermore, in an emission unit EMU including light-emitting elements LD connected in a series / parallel hybrid configuration, the drive voltage applied to opposite ends of the emission unit EMU can be reduced compared to the drive voltage of an emission unit EMU including light-emitting elements LD connected in parallel. If all light-emitting elements LD are connected in series, if at least one of the series-connected light-emitting elements LD is not properly connected in the forward direction, the path through which the drive current can flow in the pixel PXL is blocked, potentially causing a black spot defect. On the other hand, if the light-emitting elements LD are connected in a series / parallel hybrid configuration, even if some light-emitting elements LD in each series stage are not properly connected in the forward direction or some light-emitting elements LD have defects, the drive current is allowed to flow through the other light-emitting elements LD in the corresponding series stage. Therefore, defects in the pixel PXL can be prevented or mitigated.

[0160] In the aforementioned embodiment, the pixel PXL including the emission unit EMU having a three-stage series / parallel hybrid structure has been described for illustrative purposes, but the embodiment is not limited thereto. For example, the pixel PXL according to the embodiment may include the emission unit EMU having a four-stage or more series / parallel hybrid structure.

[0161] Figure 7 It shows that according to the embodiment Figure 5A An enlarged plan view of a portion of the EA. Figure 8 is a schematic diagram showing an embodiment of the Figure 7 A plan view of the first pixel. Figure 9 According to the implementation method Figure 8 A sectional view taken along section line II'. Figure 10 According to the implementation method Figure 8 A sectional view taken along section line II-II'. Figure 11 According to the implementation method Figure 8 A sectional view taken along section line III-III'. Figure 12 Shown according to the embodiment Figure 11 A modified version of the stacking pattern and is related to Figure 8 The cross-sectional view corresponding to the section line III-III'. Figure 13 The arrangement according to the embodiment is shown Figure 11 The insulating pattern on the light emitting element is Figure 8 The cross-sectional view corresponding to the section line III-III'. Figure 14 According to the implementation method Figure 8 A sectional view taken along section line IV-IV'.

[0162] Figure 7 The first pixel PXL1, the second pixel PXL2, the third pixel PXL3 and the fourth pixel PXL4 shown in FIG. Figure 8 The first pixels PXL1 shown in FIG. 1 and FIG. 2 may each be Figures 6A to 6E For example, Figure 7 The first pixel PXL1, the second pixel PXL2, the third pixel PXL3 and the fourth pixel PXL4 shown in FIG. Figure 8 The first pixels PXL1 shown in FIG. 1 and FIG. 2 may each be Figure 6E The pixel PXL is shown in FIG.

[0163] For the purpose of explanation, based on four pixels PXL1, PXL2, PXL3, and PXL4 disposed at intersections of the j-th pixel column, the j+1-th pixel column, the i-th pixel row, and the i+1-th pixel row in the portion EA, Figure 7 Scan lines Si-1, Si, Si+1 and Si+2, emission control lines Ei and Ei+1, data lines Dj and Dj+1, initialization power lines IPL, and first and second power lines PL1 and PL2 connected to four pixels PXL1, PXL2, PXL3 and PXL4 are shown.

[0164] About Figure 7 For the purpose of explanation, among the scan lines Si-1, Si, Si+1, and Si+2 to which scan signals are to be applied, the scan line arranged on the i-1th row will be referred to as the “i-1th scan line Si-1,” the scan line arranged on the i-th row will be referred to as the “i-th scan line Si,” the scan line arranged on the i+1th row will be referred to as the “i+1th scan line Si+1,” and the scan line arranged on the i+2th row will be referred to as the “i+2th scan line Si+2.” Furthermore, among the emission control lines Ei and Ei+1 to which emission control signals are to be applied, the emission control line arranged on the i-th row will be referred to as the “i-th emission control line Ei,” and the emission control line arranged on the i+1th row will be referred to as the “i+1th emission control line Ei+1.” Among the data lines Dj and Dj+1 to which data signals are applied, the data line disposed on the jth column will be referred to as "jth data line Dj", and the data line disposed on the j+1th column will be referred to as "j+1th data line Dj+1".

[0165] although Figures 7 to 14 The structure of the pixel PXL is simply illustrated, for example, it is illustrated that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the embodiment is not limited thereto.

[0166] In addition, in the description of various embodiments, “components are disposed and / or formed on the same layer” may mean that the components are formed by the same process, and “components are disposed and / or formed on different layers” may mean that the components are formed by different processes.

[0167] refer to Figures 1A to 5B 、 Figure 6E as well as Figures 7 to 14 , the display device may include a substrate SUB, a line unit, and at least one pixel PXL.

[0168] The substrate SUB may include a transparent insulating material to allow light transmission. The substrate SUB may be a rigid substrate or a flexible substrate. During the process of manufacturing the display device, the material applied to the substrate SUB may have resistance to high processing temperatures (e.g., thermal resistance). The substrate SUB may include a display area DA and a non-display area NDA, wherein the display area DA includes at least one pixel area PXA in which the pixels PXL are disposed, and the non-display area NDA is disposed around the display area DA.

[0169] In an embodiment, the pixels PXL may be arranged in a matrix and / or stripe shape in the display area DA along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 intersecting the first direction DR1, but the embodiment is not limited thereto. In an embodiment, the pixels PXL may be provided in the display area DA in various arrangements on the substrate SUB.

[0170] The pixel PXL may include a first pixel PXL1, a second pixel PXL2, a third pixel PXL3, and a fourth pixel PXL4. In the following embodiments, the term "pixel PXL" or "pixels PXL" will be used to collectively refer to any one pixel or two or more pixels of the first pixel PXL1, the second pixel PXL2, the third pixel PXL3, and the fourth pixel PXL4.

[0171] The first pixel PXL1 may be a pixel disposed at the intersection of the i-th pixel row and the j-th pixel column. The second pixel PXL2 may be a pixel disposed at the intersection of the i-th pixel row and the j+1-th pixel column. The third pixel PXL3 may be a pixel disposed at the intersection of the i+1-th pixel row and the j-th pixel column. The fourth pixel PXL4 may be a pixel disposed at the intersection of the i+1-th pixel row and the j+1-th pixel column. In an embodiment, each of the first to fourth pixels PXL1 to PXL4 may be a red pixel, a green pixel, or a blue pixel, but the embodiment is not limited thereto.

[0172] In the display area DA of the substrate SUB, the area in which the first pixel PXL1 is provided may be the first pixel area PXA1, the area in which the second pixel PXL2 is provided may be the second pixel area PXA2, the area in which the third pixel PXL3 is provided may be the third pixel area PXA3, and the area in which the fourth pixel PXL4 is provided may be the fourth pixel area PXA4.

[0173] The first pixel PXL1 can be electrically coupled to each of the scan lines Si-1, Si, and Si+1, the j-th data line Dj, the i-th emission control line Ei, the initialization power line IPL, and the first and second power lines PL1 and PL2 disposed in the first pixel region PXA1. The second pixel PXL2 can be electrically coupled to each of the scan lines Si-1, Si, and Si+1, the j+1-th data line Dj+1, the i-th emission control line Ei, the initialization power line IPL, and the first and second power lines PL1 and PL2 disposed in the second pixel region PXA2. The third pixel PXL3 can be electrically coupled to each of the scan lines Si, Si+1, and Si+2, the j-th data line Dj, the i+1-th emission control line Ei+1, the initialization power line IPL, and the first and second power lines PL1 and PL2 disposed in the third pixel region PXA3. The fourth pixel PXL4 can be electrically coupled to each of the scan lines Si, Si+1 and Si+2, the j+1th data line Dj+1, the i+1th emission control line Ei+1, the initialization power line IPL, and the first and second power lines PL1 and PL2 set in the fourth pixel area PXA4.

[0174] Scan lines Si-1, Si, Si+1, and Si+2 may extend in a first direction DR1 on the substrate SUB and may be provided to the first to fourth pixels PXL1 to PXL4. The scan lines Si-1, Si, Si+1, and Si+2 may include an i-1th scan line Si-1, an i-th scan line Si, an i+1th scan line Si+1, and an i+2th scan line Si+2, sequentially arranged in the second direction DR2. The i-1th scan line Si-1, the i-th scan line Si, and the i+1th scan line Si+1 among the scan lines Si-1, Si, Si+1, and Si+2 may be coupled to each of the first pixel PXL1 and the second pixel PXL2 disposed on the i-th pixel row. The i-th scan line Si, the i+1th scan line Si+1, and the i+2th scan line Si+2 among the scan lines Si-1, Si, Si+1, and Si+2 may be coupled to each of the third pixel PXL3 and the fourth pixel PXL4 disposed on the i+1th pixel row.

[0175] The scan signals may be applied to the corresponding scan lines Si-1, Si, Si+1, and Si+2. For example, the i-1th scan signal may be applied to the i-1th scan line Si-1, the i-th scan signal may be applied to the i-th scan line Si, the i+1th scan signal may be applied to the i+1th scan line Si+1, and the i+2th scan signal may be applied to the i+2th scan line Si+2.

[0176] In an embodiment, each of the scan lines Si-1, Si, Si+1, and Si+2 may be a first conductive layer CL1 disposed and / or formed on the first insulating layer INS1. Here, the first insulating layer INS1 may be an inorganic insulating layer including an inorganic material, but the embodiment is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer including an organic material.

[0177] The emission control lines Ei and Ei+1 may extend on the substrate SUB in a first direction DR1 and be provided to corresponding pixels PXL. The emission control lines Ei and Ei+1 may include an i-th emission control line Ei and an i+1-th emission control line Ei+1 sequentially arranged in a second direction DR2. The i-th emission control line Ei may be coupled to pixels PXL disposed on an i-th pixel row, for example, first and second pixels PXL1 and PXL2. The i+1-th emission control line Ei+1 may be coupled to pixels PXL disposed on an i+1-th pixel row, for example, third and fourth pixels PXL3 and PXL4.

[0178] The emission control signal may be applied to each of the emission control lines Ei and Ei+1. For example, the i-th emission control signal may be applied to the i-th emission control line Ei, and the i+1-th emission control signal may be applied to the i+1-th emission control line Ei+1.

[0179] In an embodiment, the emission control lines Ei and Ei+1 may be provided in the same layer as the scan lines Si-1, Si, Si+1, and Si+2, and may include the same material as the scan lines Si-1, Si, Si+1, and Si+2. For example, each of the emission control lines Ei and Ei+1 may be a first conductive layer CL1 provided and / or formed on the first insulating layer INS1.

[0180] The data lines Dj and Dj+1 may extend in the second direction DR2. The data lines Dj and Dj+1 may include a j-th data line Dj and a j+1-th data line Dj+1 sequentially arranged in the first direction DR1. The j-th data line Dj may be coupled to a pixel PXL disposed on (or in) the j-th pixel column, for example, a first pixel PXL1 and a third pixel PXL3. The j+1-th data line Dj+1 may be coupled to a pixel PXL disposed on the j+1-th pixel column, for example, a second pixel PXL2 and a fourth pixel PXL4. Data signals may be applied to the corresponding data lines Dj and Dj+1.

[0181] In an embodiment, each of the data lines Dj and Dj+1 may be a third conductive layer CL3 disposed and / or formed on the third insulating layer INS3. The third insulating layer INS3 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0182] The initialization power line IPL may extend in the second direction DR2 and may be disposed at a position spaced apart from each of the data lines Dj and Dj+1. For example, the initialization power line IPL disposed on the j-th pixel column may extend in a direction parallel to the direction in which the j-th data line Dj extends and may be electrically and / or physically separated from the j-th data line Dj. The initialization power line IPL disposed on the j+1-th pixel column may extend in a direction parallel to the direction in which the j+1-th data line Dj+1 extends and may be electrically and / or physically separated from the j+1-th data line Dj+1.

[0183] In an embodiment, the initialization power line IPL may be provided in the same layer as the data lines Dj and Dj+1 and may include the same material as the data lines Dj and Dj+1. For example, the initialization power line IPL may be a third conductive layer CL3 provided and / or formed on the third insulating layer INS3. However, embodiments are not limited thereto. In some embodiments, the initialization power line IPL may be a second conductive layer CL2 provided and / or formed on the second insulating layer INS2.

[0184] The first power line PL1 may extend in the second direction DR2 and may be disposed at a position spaced apart from each of the data lines Dj and Dj+1. For example, the first power line PL1 disposed on the j-th pixel column may extend in a direction parallel to the direction in which the j-th data line Dj extends and may be electrically and / or physically separated from the j-th data line Dj. The first power line PL1 disposed on the j+1-th pixel column may extend in a direction parallel to the direction in which the j+1-th data line Dj+1 extends and may be electrically and / or physically separated from the j+1-th data line Dj+1. A first driving power source VDD may be applied to the first power line PL1.

[0185] In an embodiment, the first power line PL1 may be disposed in the same layer as the data lines Dj and Dj+1 and the initialization power line IPL. For example, the first power line PL1 may be a third conductive layer CL3 disposed and / or formed on the third insulating layer INS3.

[0186] The second power line PL2 may extend in the second direction DR2 and may be disposed at a position spaced apart from each of the data lines Dj and Dj+1. For example, the second power line PL2 disposed on the j-th pixel column may extend in a direction parallel to the direction in which the j-th data line Dj extends and may be electrically and / or physically separated from the j-th data line Dj. The second power line PL2 disposed on the j+1-th pixel column may extend in a direction parallel to the direction in which the j+1-th data line Dj+1 extends and may be electrically and / or physically separated from the j+1-th data line Dj+1.

[0187] In an embodiment, the second power line PL2 may be provided in the same layer as the data lines Dj and Dj+1, the initialization power line IPL, and the first power line PL1, and may include the same material as the data lines Dj and Dj+1, the initialization power line IPL, and the first power line PL1. For example, the second power line PL2 may be a third conductive layer CL3 provided and / or formed on the third insulating layer INS3. The second driving power source VSS may be applied to the second power line PL2.

[0188] In an embodiment, each of the first to fourth pixel areas PXA1 to PXA4 may include an emission area EMA from which light is emitted and a peripheral area surrounding the emission area EMA. Here, the term “peripheral area” may include a non-emission area from which no light is emitted.

[0189] The display element portion DPL may be disposed in the emission area EMA of each of the first to fourth pixel regions PXA1 to PXA4, and a plurality of light-emitting elements LD may be disposed in the display element portion DPL. The pixel circuit portion PCL may be disposed in the peripheral region of each of the first to fourth pixel regions PXA1 to PXA4, and circuit elements for driving the light-emitting elements LD may be disposed in the pixel circuit portion PCL.

[0190] The first to fourth pixels PXL1 to PXL4 may have substantially the same or similar structures. Hereinafter, for illustrative purposes, the first pixel PXL1 disposed on the i-th pixel row and the j-th pixel column among the first to fourth pixels PXL1 to PXL4 will be representatively described, and detailed descriptions of the second to fourth pixels PXL2 to PXL4 will be omitted.

[0191] The first pixel region PXA1, in which the first pixel PXL1 is disposed, may include a first area FA and a second area SA divided in one direction. The substrate SUB and the pixel circuit portion PCL including the pixel circuit 144 may be located in the first area FA. The substrate SUB and the display element portion DPL including the light-emitting element LD may be located in the second area SA. In an embodiment, the emission area EMA of the first pixel region PXA1 may be located in the second area SA.

[0192] The pixel circuit portion PCL may include a buffer layer BFL disposed on a substrate SUB and a pixel circuit 144 disposed and / or formed on the buffer layer BFL. In an embodiment, the pixel circuit 144 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2.

[0193] The buffer layer BFL can prevent impurities from diffusing into each of the first to seventh transistors T1 to T7. The buffer layer BFL can be configured as a single-layer structure or a multi-layer structure having at least two or more layers. When the buffer layer BFL has a multi-layer structure, the individual layers can be formed of the same material or different materials. Depending on the material of the substrate SUB or process conditions, the buffer layer BFL may be omitted.

[0194] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , a first drain electrode DE1 , and a conductive pattern CNP.

[0195] The first gate electrode GE1 may be electrically coupled to the 3b-th drain electrode DE3b of the 3b-th transistor T3b and the 4b-th drain electrode DE4b of the 4b-th transistor T4b.

[0196] The first end of the conductive pattern CNP can be coupled to the 3b-th drain electrode DE3b and the 4b-th drain electrode DE4b via a first contact hole CH1 passing through the first insulating layer INS1 to the third insulating layer INS3. The second end of the conductive pattern CNP can be electrically coupled to the first gate electrode GE1 via a second contact hole CH2 passing through the second insulating layer INS2 and the third insulating layer INS3. In an embodiment, the conductive pattern CNP may be a third conductive layer CL3 disposed and / or formed on the third insulating layer INS3.

[0197] Each of the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor layer doped with impurities. The first active pattern ACT1 may be formed of an undoped semiconductor layer.

[0198] The first active pattern ACT1 may have a rod shape extending in a predetermined direction and may be bent at least once or multiple times along its longitudinal extension. In a plan view, the first active pattern ACT1 may overlap with the first gate electrode GE1. Since the first active pattern ACT1 is relatively long, the channel region of the first transistor T1 may also be relatively long. Therefore, the driving range of the gate voltage to be applied to the first transistor T1 can be increased. As a result, the grayscale of the light emitted from the light-emitting element LD can be precisely controlled.

[0199] The first source electrode SE1 may be coupled to a first end of the first active pattern ACT1. The first source electrode SE1 may be coupled to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be coupled to a second end of the first active pattern ACT1. The first drain electrode DE1 may be coupled to the 3a-th source electrode SE3a of the 3a-th transistor T3a and the sixth source electrode SE6 of the sixth transistor T6.

[0200] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0201] The second gate electrode GE2 may be integrally provided with the i-th scan line Si, and thus, may be coupled with the i-th scan line Si. In the case where the second gate electrode GE2 and the i-th scan line Si are integrally provided, the second gate electrode GE2 may be provided as a portion of the i-th scan line Si, or may be formed in a shape protruding from the i-th scan line Si.

[0202] Each of the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor layer doped with impurities. The second active pattern ACT2 may be formed of an undoped semiconductor layer.

[0203] The second active pattern ACT2 may overlap the second gate electrode GE2.

[0204] A first end of the second source electrode SE2 may be coupled to the second active pattern ACT2, and a second end of the second source electrode SE2 may be coupled to the j-th data line Dj via a sixth contact hole CH6 that sequentially passes through the first insulating layer INS1 to the third insulating layer INS3. In an embodiment, the second insulating layer INS2 may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The second insulating layer INS2 may be disposed between the first insulating layer INS1 and the third insulating layer INS3 and may include a material that is the same as or different from that of the first insulating layer INS1 and the third insulating layer INS3.

[0205] A first end of the second drain electrode DE2 may be coupled to the second active pattern ACT2 , and a second end of the second drain electrode DE2 may be coupled to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5 .

[0206] The third transistor T3 may have a dual-gate structure to prevent (or mitigate) current leakage. For example, the third transistor T3 may include a 3a-th transistor T3a and a 3b-th transistor T3b.

[0207] The 3ath transistor T3a may include a 3ath gate electrode GE3a, a 3ath active pattern ACT3a, a 3ath source electrode SE3a, and a 3ath drain electrode DE3a. The 3bth transistor T3b may include a 3bth gate electrode GE3b, a 3bth active pattern ACT3b, a 3bth source electrode SE3b, and a 3bth drain electrode DE3b.

[0208] Each of the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b may be integrally provided with the i-th scan line Si, and therefore, may be coupled to the i-th scan line Si. In the case where the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b and the i-th scan line Si are integrally provided, each of the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b may be provided as a portion of the i-th scan line Si, or may be formed (or formed) in a shape protruding from the i-th scan line Si.

[0209] Each of the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b, the 3a-th source electrode SE3a and the 3b-th source electrode SE3b, and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b can be formed from an impurity-doped semiconductor layer or an undoped semiconductor layer. Each of the 3a-th source electrode SE3a and the 3b-th source electrode SE3b, and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b can be formed from an impurity-doped semiconductor layer. Each of the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b can be formed from an undoped semiconductor layer. The 3a-th active pattern ACT3a can overlap with the 3a-th gate electrode GE3a. The 3b-th active pattern ACT3b can overlap with the 3b-th gate electrode GE3b.

[0210] A first end of the 3a-th source electrode SE3a may be coupled to the 3a-th active pattern ACT3a, and a second end of the 3a-th source electrode SE3a may be coupled to the first drain electrode DE1 of the first transistor T1. A first end of the 3a-th drain electrode DE3a may be coupled to the 3a-th active pattern ACT3a, and a second end of the 3a-th drain electrode DE3a may be coupled to the 3b-th source electrode SE3b of the 3b-th transistor T3b.

[0211] A first end of the 3b-th source electrode SE3b may be coupled to the 3b-th active pattern ACT3b, and a second end of the 3b-th source electrode SE3b may be coupled to the 3a-th drain electrode DE3a of the 3a-th transistor T3a. A first end of the 3b-th drain electrode DE3b may be coupled to the 3b-th active pattern ACT3b. A second end of the 3b-th drain electrode DE3b may be coupled to the 4b-th drain electrode DE4b of the 4b-th transistor T4b and the first gate electrode GE1 of the first transistor T1 through the first and second contact holes CH1 and CH2 and the conductive pattern CNP.

[0212] The fourth transistor T4 may have a dual gate structure to prevent (or mitigate) current leakage in the same manner as the third transistor T3. For example, the fourth transistor T4 may include a 4a-th transistor T4a and a 4b-th transistor T4b.

[0213] The 4a-th transistor T4a may include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a. The 4b-th transistor T4b may include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b.

[0214] Each of the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b may be integrally provided with the (i-1)-th scan line Si-1, and therefore, may be coupled to the (i-1)-th scan line Si-1. In the case where the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b and the (i-1)-th scan line Si-1 are integrally provided, each of the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b may be provided as a portion of the (i-1)-th scan line Si-1, or may be formed (or formed) in a shape protruding from the (i-1)-th scan line Si-1.

[0215] Each of the 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b, the 4a-th source electrode SE4a and the 4b-th source electrode SE4b, and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b may be formed from an impurity-doped semiconductor layer or an undoped semiconductor layer. Each of the 4a-th source electrode SE4a and the 4b-th source electrode SE4b, and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b may be formed from an impurity-doped semiconductor layer. Each of the 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b may be formed from an undoped semiconductor layer. The 4a-th active pattern ACT4a may overlap with the 4a-th gate electrode GE4a. The 4b-th active pattern ACT4b may overlap with the 4b-th gate electrode GE4b.

[0216] A first end of the 4a-th source electrode SE4a may be coupled to the 4a-th active pattern ACT4a, and a second end of the 4a-th source electrode SE4a may be coupled to the initialization power line IPL through a fifth contact hole CH5 sequentially passing through the first insulating layer INS1 to the third insulating layer INS3. A first end of the 4a-th drain electrode DE4a may be coupled to the 4a-th active pattern ACT4a, and a second end of the 4a-th drain electrode DE4a may be coupled to the 4b-th source electrode SE4b of the 4b-th transistor T4b.

[0217] A first end of the 4b-th source electrode SE4b may be coupled to the 4b-th active pattern ACT4b, and a second end of the 4b-th source electrode SE4b may be coupled to the 4a-th drain electrode DE4a of the 4a-th transistor T4a. A first end of the 4b-th drain electrode DE4b may be coupled to the 4b-th active pattern ACT4b, and a second end of the 4b-th drain electrode DE4b may be coupled to the 3b-th drain electrode DE3b of the 3b-th transistor T3b. Furthermore, a second end of the 4b-th drain electrode DE4b may be coupled to the first gate electrode GE1 of the first transistor T1 through the first and second contact holes CH1 and CH2 and the conductive pattern CNP.

[0218] The fifth transistor T5 may include a fifth gate electrode GE5 , a fifth active pattern ACT5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0219] The fifth gate electrode GE5 may be integrally provided with the i-th emission control line Ei, and therefore, may be coupled to the i-th emission control line Ei. In the case where the fifth gate electrode GE5 and the i-th emission control line Ei are integrally provided, the fifth gate electrode GE5 may be provided as a portion of the i-th emission control line Ei, or formed (or formed) in a shape protruding from the i-th emission control line Ei.

[0220] Each of the fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the fifth source electrode SE5 and the fifth drain electrode DE5 may be formed of a semiconductor layer doped with impurities. The fifth active pattern ACT5 may be formed of an undoped semiconductor layer.

[0221] The fifth active pattern ACT5 may overlap the fifth gate electrode GE5 .

[0222] A first end of the fifth source electrode SE5 may be coupled to the fifth active pattern ACT5 , and a second end of the fifth source electrode SE5 may be coupled to the first power line PL1 through a fourth contact hole CH4 sequentially passing through the first to third insulating layers INS1 to INS3 .

[0223] A first end of the fifth drain electrode DE5 may be coupled to the fifth active pattern ACT5 , and a second end of the fifth drain electrode DE5 may be coupled to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2 .

[0224] The sixth transistor T6 may include a sixth gate electrode GE6 , a sixth active pattern ACT6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0225] The sixth gate electrode GE6 may be integrally provided with the i-th emission control line Ei, and therefore, may be coupled to the i-th emission control line Ei. In the case where the sixth gate electrode GE6 and the i-th emission control line Ei are integrally provided, the sixth gate electrode GE6 may be provided as a portion of the i-th emission control line Ei, or formed (or formed) in a shape protruding from the i-th emission control line Ei.

[0226] Each of the sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the sixth source electrode SE6 and the sixth drain electrode DE6 may be formed of a semiconductor layer doped with impurities. The sixth active pattern ACT6 may be formed of an undoped semiconductor layer.

[0227] The sixth active pattern ACT6 may overlap the sixth gate electrode GE6 .

[0228] A first end of the sixth source electrode SE6 may be coupled to the sixth active pattern ACT6 , and a second end of the sixth source electrode SE6 may be coupled to the first drain electrode DE1 of the first transistor T1 and the 3a-th source electrode SE3 a of the 3a-th transistor T3 a .

[0229] A first end of the sixth drain electrode DE6 may be coupled to the sixth active pattern ACT6 , and a second end of the sixth drain electrode DE6 may be coupled to the first electrode EL1 through a seventh contact hole CH7 sequentially passing through the first to third insulating layers INS1 to INS3 .

[0230] The first electrode EL1 of the emission unit EMU can be coupled to the sixth drain electrode DE6 of the sixth transistor T6 via the seventh contact hole CH7. The first electrode EL1 can be coupled to the seventh source electrode SE7 of the seventh transistor T7 via the seventh contact hole CH7. In an embodiment, the first electrode EL1 can be disposed in the same layer as the j-th data line Dj and can include the same material as the j-th data line Dj. For example, the first electrode EL1 can be formed of a third conductive layer CL3 disposed and / or formed on the third insulating layer INS3. The first electrode EL1 can be an anode electrode in the emission unit EMU included in the first pixel PXL1.

[0231] The seventh transistor T7 may include a seventh gate electrode GE7 , a seventh active pattern ACT7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 .

[0232] The seventh gate electrode GE7 may be integrally provided with the i+1th scan line Si+1, and therefore, may be coupled with the i+1th scan line Si+1. In the case where the seventh gate electrode GE7 and the i+1th scan line Si+1 are integrally provided, the seventh gate electrode GE7 may be provided as a portion of the i+1th scan line Si+1, or formed (or formed) in a shape protruding from the i+1th scan line Si+1.

[0233] Each of the seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor layer doped with impurities. The seventh active pattern ACT7 may be formed of an undoped semiconductor layer.

[0234] The seventh active pattern ACT7 may overlap the seventh gate electrode GE7 .

[0235] A first end of the seventh source electrode SE7 may be coupled to the seventh active pattern ACT7 , and a second end of the seventh source electrode SE7 may be coupled to the sixth drain electrode DE6 and the first electrode EL1 of the sixth transistor T6 through a seventh contact hole CH7 .

[0236] A first end of the seventh drain electrode DE7 may be coupled to the seventh active pattern ACT7 , and a second end of the seventh drain electrode DE7 may be coupled to the auxiliary connection line AUX through a tenth contact hole CH10 sequentially passing through the first to third insulating layers INS1 to INS3 .

[0237] The auxiliary connection line AUX may be coupled to the seventh drain electrode DE7 of the seventh transistor T7 through the tenth contact hole CH10. The auxiliary connection line AUX may be coupled to the initialization power line IPL disposed in the second pixel area PXA2 of the second pixel PXL2 through the tenth contact hole CH10. The second pixel PXL2 is disposed on (or in) the same pixel row as the first pixel PXL1. The seventh drain electrode DE7 of the seventh transistor T7 may be coupled to the initialization power line IPL through the auxiliary connection line AUX.

[0238] As described above, the seventh drain electrode DE7 of the seventh transistor T7 may be coupled to the 4a-th source electrode SE4a of the 4a-th transistor T4a of the second pixel PXL2 through the auxiliary connection line AUX and the initialization power line IPL of the second pixel PXL2.

[0239] In an embodiment, the auxiliary connection line AUX of the first pixel PXL1 may be integrally provided with the initialization power line IPL of the second pixel PXL2, and thus, may be connected to the initialization power line IPL. In the case where the auxiliary connection line AUX of the first pixel PXL1 and the initialization power line IPL of the second pixel PXL2 are integrally provided, the auxiliary connection line AUX of the first pixel PXL1 may be provided as a part of the initialization power line IPL of the second pixel PXL2. In other words, the auxiliary connection line AUX of each pixel PXL may be integrally provided with the initialization power line IPL in a pixel PXL that is provided on (or in) the same pixel row as the pixel row of the corresponding pixel PXL and that is immediately adjacent to the corresponding pixel PXL.

[0240] If the auxiliary connection line AUX of the first pixel PXL1 is integrally provided with the initialization power line IPL of the second pixel PXL2, the auxiliary connection line AUX may be provided in the same layer as the initialization power line IPL and may include the same material as the initialization power line IPL. For example, the auxiliary connection line AUX of the first pixel PXL1 may be formed of a third conductive layer CL3 provided and / or formed on the third insulating layer INS3.

[0241] The first capacitor C1 may include a first lower electrode LE1 and a first upper electrode UE1.

[0242] The first lower electrode LE1 may be integrally provided with the first gate electrode GE1 of the first transistor T1, and therefore, may be coupled with the first gate electrode GE1. In the case where the first lower electrode LE1 is integrally provided with the first gate electrode GE1, the first lower electrode LE1 may be regarded as a part of the first gate electrode GE1, or the first gate electrode GE1 may be regarded as a part of the first lower electrode LE1.

[0243] In an embodiment, the first lower electrode LE1 may be disposed in the same layer as the scan lines Si-1, Si, and Si+1 and may include the same material as the scan lines Si-1, Si, and Si+1. For example, the first lower electrode LE1 may be formed of a first conductive layer CL1 disposed and / or formed on the first insulating layer INS1.

[0244] The first upper electrode UE1 may overlap with and cover the first lower electrode LE1. The capacitance of the first capacitor C1 may be increased by increasing the area of the overlapping portion between the first upper electrode UE1 and the first lower electrode LE1. The first upper electrode UE1 may be electrically coupled to the first power line PL1 via a third contact hole CH3 passing through the third insulating layer INS3. Thus, the first driving power VDD applied to the first power line PL1 may be transmitted to the first upper electrode UE1. The first upper electrode UE1 may include an opening OPN corresponding to a region having a second contact hole CH2. The second contact hole CH2 is formed to couple the first gate electrode GE1 of the first transistor T1 to the conductive pattern CNP.

[0245] In an implementation, the first upper electrode UE1 may be the second conductive layer CL2 disposed and / or formed on the second insulating layer INS2.

[0246] The second capacitor C2 may include a second lower electrode LE2 and a second upper electrode UE2.

[0247] In a plan view, the second lower electrode LE2 may be located between the i-th emission control line Ei and the i+1-th scan line Si+1 and may be disposed and / or formed in the same layer as the first lower electrode LE1. The second lower electrode LE2 may be coupled to the second power line PL2 via a ninth contact hole CH9 that sequentially passes through the second insulating layer INS2 and the third insulating layer INS3. Thus, the second driving power VSS applied to the second power line PL2 may be transmitted to the second lower electrode LE2.

[0248] In an embodiment, the second lower electrode LE2 may be disposed in the same layer as the scan lines Si-1, Si, and Si+1 and may include the same material as the scan lines Si-1, Si, and Si+1. For example, the second lower electrode LE2 may be formed of the first conductive layer CL1 disposed and / or formed on the first insulating layer INS1.

[0249] The second upper electrode UE2 may overlap with and cover the second lower electrode LE2. The capacitance of the second capacitor C2 may be increased by increasing the area of the overlapping portion between the second upper electrode UE2 and the second lower electrode LE2. The second upper electrode UE2 may be electrically coupled to the first electrode EL1 via an eighth contact hole CH8 passing through the third insulating layer INS3. Thus, a signal (or voltage) applied to the first electrode EL1 may be transmitted to the second upper electrode UE2.

[0250] In an embodiment, the second upper electrode UE2 may be provided in the same layer as the first upper electrode UE1 and may include the same material as the first upper electrode UE1. For example, the second upper electrode UE2 may be formed of a second conductive layer CL2 provided and / or formed on the second insulating layer INS2.

[0251] As described above, the first lower electrode LE1 and the first upper electrode UE1 may form a first capacitor C1 with the second insulating layer INS2 interposed therebetween. The second lower electrode LE2 and the second upper electrode UE2 may form a second capacitor C2 with the second insulating layer INS2 interposed therebetween.

[0252] The pixel circuit portion PCL may further include a fourth insulating layer INS4 for covering the pixel circuit 144 having the above configuration. The fourth insulating layer INS4 may be an organic insulating layer including an organic material or an inorganic insulating layer including an inorganic material. In an embodiment, the fourth insulating layer INS4 may be an organic insulating layer.

[0253] The first to third floating electrodes FLT1 to FLT3 and the fourth arrangement electrode ARL4 may be disposed in the first area FA of the first pixel area PXA1. Each of the first to third floating electrodes FLT1 to FLT3 and the fourth arrangement electrode ARL4 may be formed of a third conductive layer CL3 disposed and / or formed on the third insulating layer INS3. The first floating electrode FLT1 may be disposed on (or in) the same column as the first electrode EL1 disposed in the emission area EMA of the first pixel area PXA1 and may be spaced apart from the first electrode EL1 by a predetermined distance. The second floating electrode FLT2 may be disposed on (or in) the same column as the first connection electrode CP1 disposed in the emission area EMA of the first pixel area PXA1 and may be spaced apart from the first connection electrode CP1 by a predetermined distance. The third floating electrode FLT3 may be disposed on (or in) the same column as the second connection electrode CP2 disposed in the emission area EMA of the first pixel area PXA1 and may be spaced apart from the second connection electrode CP2 by a predetermined distance. The fourth arrangement electrode ARL4 as the second power line PL2 may be integrally provided with the second electrode EL2 disposed in the emission area EMA of the first pixel PXL1 and may be electrically coupled with the second electrode EL2 .

[0254] In an embodiment, each of the first to third floating electrodes FLT1 to FLT3 may be floated, ie, electrically isolated.

[0255] The display element portion DPL may include a stack pattern LAP, first and second electrodes EL1 and EL2, first and second connection electrodes CP1 and CP2, a light emitting element LD, and a contact electrode CNE disposed in the emission area EMA. Furthermore, the display element portion DPL may include a bank portion BNK disposed in a peripheral region disposed around the emission area EMA.

[0256] The stacking pattern LAP can be a supporting member for supporting the first electrode EL1 and the second electrode EL2 and the first connecting electrode CP1 and the second connecting electrode CP2 to change the respective surface profiles of the first electrode EL1 and the second electrode EL2 and the first connecting electrode CP1 and the second connecting electrode CP2 so that the light emitted from the light emitting element LD can advance more reliably in the image display direction of the display device (for example, in the third direction DR3).

[0257] The stacked pattern LAP may be provided as a multi-layer structure including at least one insulating layer and at least one conductive layer disposed and / or formed on the buffer layer BFL. For example, the stacked pattern LAP may be provided as a multi-layer structure in which a first metal pattern MTP1, a first insulating pattern INSP1, a second metal pattern MTP2, and a second insulating pattern INSP2 are stacked in sequence.

[0258] The first metal pattern MTP1 may be formed of a first conductive layer CL1 disposed and / or formed on the first insulating layer INS1. In an embodiment, the first metal pattern MTP1 may be disposed in the same layer as the scan lines Si-1, Si, and Si+1 and the first and second lower electrodes LE1 and LE2, and may include the same material as the scan lines Si-1, Si, and Si+1 and the first and second lower electrodes LE1 and LE2.

[0259] The first insulating pattern INSP1 may be disposed on the first metal pattern MTP1 and may surround the first metal pattern MTP1. For example, the first insulating pattern INSP1 may be an independent insulating pattern surrounding only the first metal pattern MTP1. In an embodiment, the first insulating pattern INSP1 included in the stacked pattern LAP may be a component corresponding to the second insulating layer INS2 of the pixel circuit portion PCL.

[0260] The second metal pattern MTP2 may be formed of a second conductive layer CL2 disposed and / or formed on the first insulating pattern INSP1. In an embodiment, the second metal pattern MTP2 may be disposed in the same layer as the first and second upper electrodes UE1 and UE2 and may include the same material as the first and second upper electrodes UE1 and UE2.

[0261] The second insulating pattern INSP2 may be disposed on the second metal pattern MTP2 and may surround the second metal pattern MTP2. For example, the second insulating pattern INSP2 may be an independent insulating pattern surrounding only the second metal pattern MTP2. In an embodiment, the second insulating pattern INSP2 included in the stacked pattern LAP may be a component corresponding to the third insulating layer INS3 of the pixel circuit portion PCL.

[0262] As described above, the stack pattern LAP including the first metal pattern MTP1, the first insulating pattern INSP1, the second metal pattern MTP2, and the second insulating pattern INSP2 may have a shape that protrudes upward from one surface (e.g., the upper surface) of the first insulating layer INS1. The stack pattern LAP may have a trapezoidal cross-section in which the width of the stack pattern LAP decreases upward from one surface of the first insulating layer INS1. In a cross-sectional view, adjacent stack patterns LAP may be disposed on the same plane above the buffer layer BFL and may have the same height.

[0263] As described, the stacked pattern LAP has been illustrated as having a four-layer structure in which the first metal pattern MTP1, the first insulating pattern INSP1, the second metal pattern MTP2, and the second insulating pattern INSP2 are sequentially stacked, but embodiments are not limited thereto. In embodiments, the stacked pattern LAP may have a multilayer structure including at least two or more metal patterns and at least three or more insulating patterns, or may have a multilayer structure including a semiconductor layer.

[0264] For example, Figure 12 As shown in , the stack pattern LAP may be provided in a multilayer structure in which the first auxiliary pattern MTP_a, the sub-insulating pattern INSP_S, the first metal pattern MTP1, the first insulating pattern INSP1, the second metal pattern MTP2, and the second insulating pattern INSP2 are sequentially stacked.

[0265] The first auxiliary pattern MTP_a may be formed of a semiconductor layer disposed and / or formed on the buffer layer BFL. In an embodiment, the first auxiliary pattern MTP_a may be disposed in the same layer as the semiconductor layer included in the pixel circuit portion PCL and may include the same material as the semiconductor layer. For example, the first auxiliary pattern MTP_a may be disposed in the same layer as the first to seventh active patterns ACT1 to ACT7 and may include the same material as the first to seventh active patterns ACT1 to ACT7. In an embodiment, the first auxiliary pattern MTP_a may be disposed in the same layer as the source electrodes SE1, SE2, SE3a, SE3b, SE4a, SE4b, SE5, SE6, and SE7 and the drain electrodes DE1, DE2, DE3a, DE3b, DE4a, DE4b, DE5, DE6, and DE7, and may include the same material as the source electrodes SE1, SE2, SE3a, SE3b, SE4a, SE4b, SE5, SE6, and SE7 and the drain electrodes DE1, DE2, DE3a, DE3b, DE4a, DE4b, DE5, DE6, and DE7.

[0266] The sub-insulating pattern INSP_S may be disposed on the first auxiliary pattern MTP_a and may surround the first auxiliary pattern MTP_a. For example, the sub-insulating pattern INSP_S may be an independent insulating pattern surrounding only the first auxiliary pattern MTP_a. In an embodiment, the sub-insulating pattern INSP_S included in the stacked pattern LAP may be a component corresponding to the first insulating layer INS1 included in the pixel circuit portion PCL.

[0267] The first metal pattern MTP1 may be formed of a first conductive layer CL1 disposed and / or formed on the sub-insulation pattern INSP_S.

[0268] The first insulating pattern INSP1 may be disposed on the first metal pattern MTP1 and may surround the first metal pattern MTP1.

[0269] The second metal pattern MTP2 may be formed of a second conductive layer CL2 disposed and / or formed on the first insulating pattern INSP1.

[0270] The second insulation pattern INSP2 may be disposed on the second metal pattern MTP2 and may surround the second metal pattern MTP2.

[0271] As described above, the stack pattern LAP including the first auxiliary pattern MTP_a, the sub-insulating pattern INSP_S, the first metal pattern MTP1, the first insulating pattern INSP1, the second metal pattern MTP2, and the second insulating pattern INSP2 may have a shape protruding upward from one surface (eg, upper surface) of the buffer layer BFL.

[0272] The display element portion DPL of the first pixel PXL1 may include a bank portion BNK disposed in an outer peripheral region of the first pixel area PXA1 .

[0273] The bank BNK may be a structure that defines (or separates) the emission areas EMA of the first pixel PXL1 and the pixels PXL adjacent to the first pixel PXL1 (e.g., the second pixel PXL2 and the third pixel PXL3). For example, the bank BNK may be a pixel-defining (or defining) layer. The bank BNK may include at least two or more conductive layers and at least two or more insulating layers to prevent (or reduce) light leakage between the first pixel PXL1 and the pixels PXL adjacent to the first pixel PXL1.

[0274] In an embodiment, the bank BNK may include at least two or more insulating layers and at least two or more conductive layers disposed and / or formed on the first insulating layer INS1. For example, the bank BNK may be provided in a multilayer structure in which a third metal pattern MTP3, a third insulating pattern INSP3, a fourth metal pattern MTP4, a fourth insulating pattern INSP4, and a fifth insulating pattern INSP5 are stacked in sequence. Furthermore, the bank BNK may further include a fifth metal pattern MTP5 disposed and / or formed between the fourth insulating pattern INSP4 and the fifth insulating pattern INSP5.

[0275] Depending on whether the fifth metal pattern MTP5 is included in the stacked multilayer structure, the bank BNK may be divided into a first bank area BA1 and a second bank area BA2. For example, the first bank area BA1 may refer to an area of the bank BNK that does not include the fifth metal pattern MTP5. The second bank area BA2 may refer to an area of the bank BNK that includes the fifth metal pattern MTP5.

[0276] For example, the first bank area BA1 may be a region of the bank BNK having a multi-layer structure in which the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4, and the fifth insulating pattern INSP5 are sequentially stacked. For example, the second bank area BA2 may be a region of the bank BNK having a multi-layer structure in which the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4, the fifth metal pattern MTP5, and the fifth insulating pattern INSP5 are sequentially stacked.

[0277] The third metal pattern MTP3 may be formed of the first conductive layer CL1 disposed and / or formed on the first insulating layer INS1. In an embodiment, the third metal pattern MTP3 may be disposed in the same layer as the scan lines Si-1, Si, and Si+1, the first and second lower electrodes LE1 and LE2, and the first metal pattern MTP1, and may include the same material as the scan lines Si-1, Si, and Si+1, the first and second lower electrodes LE1 and LE2, and the first metal pattern MTP1.

[0278] The third insulating pattern INSP3 may be disposed on the third metal pattern MTP3 and configured to surround the third metal pattern MTP3. For example, the third insulating pattern INSP3 may be an independent insulating pattern that surrounds only the third metal pattern MTP3. In an embodiment, the third insulating pattern INSP3 may be a component corresponding to the second insulating layer INS2 included in the pixel circuit portion PCL. Furthermore, the third insulating pattern INSP3 may be a component corresponding to the first insulating pattern INSP1 included in the stack pattern LAP. In other words, the third insulating pattern INSP3 included in the bank portion BNK may be disposed in the same layer as both the first insulating pattern INSP1 included in the stack pattern LAP and the second insulating layer INS2 included in the pixel circuit portion PCL, and may include the same material as the first insulating pattern INSP1 and the second insulating layer INS2.

[0279] The fourth metal pattern MTP4 may be formed of the second conductive layer CL2 disposed and / or formed on the third insulating pattern INSP3. In an embodiment, the fourth metal pattern MTP4 may be disposed in the same layer as the first and second upper electrodes UE1 and UE2 and the second metal pattern MTP2, and may include the same material as the first and second upper electrodes UE1 and UE2 and the second metal pattern MTP2.

[0280] The fourth insulating pattern INSP4 may be disposed on and surround the fourth metal pattern MTP4. For example, the fourth insulating pattern INSP4 may be an independent insulating pattern surrounding only the fourth metal pattern MTP4. In an embodiment, the fourth insulating pattern INSP4 may be a component corresponding to the third insulating layer INS3 included in the pixel circuit portion PCL. Furthermore, the fourth insulating pattern INSP4 may be a component corresponding to the second insulating pattern INSP2 included in the stack pattern LAP. In other words, the fourth insulating pattern INSP4 included in the bank portion BNK may be disposed in the same layer as both the second insulating pattern INSP2 included in the stack pattern LAP and the third insulating layer INS3 included in the pixel circuit portion PCL, and may include the same material as the second insulating pattern INSP2 and the third insulating layer INS3.

[0281] The fifth metal pattern MTP5 may be formed of a third conductive layer CL3 disposed and / or formed on the fourth insulating pattern INSP4. In an embodiment, the fifth metal pattern MTP5 may include a signal line extending from the first area FA of the first pixel area PXA1 and crossing the second area SA. For example, the fifth metal pattern MTP5 may include an initialization power line IPL, a j-th data line Dj, and a first power line PL1.

[0282] The fifth insulating pattern INSP5 may be disposed on each of the fifth metal pattern MTP5 and the fourth insulating pattern INSP4 and may surround the fifth metal pattern MTP5 and the fourth insulating pattern INSP4. In an embodiment, the fifth insulating pattern INSP5 may be a component corresponding to the fourth insulating layer INS4 included in the pixel circuit portion PCL. The fifth insulating pattern INSP5 may be disposed in the same layer as the fourth insulating layer INS4 included in the pixel circuit portion PCL and may include the same material as the fourth insulating layer INS4.

[0283] As described above, the embankment BNK including the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4 and the fifth insulating pattern INSP5 or including the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4, the fifth metal pattern MTP5 and the fifth insulating pattern INSP5 may have a shape that protrudes upward (for example, in the third direction DR3) to a predetermined height (or thickness) from a surface (for example, the upper surface) of the first insulating layer INS1.

[0284] In an embodiment, the bank BNK may include at least one light-shielding material and / or a reflective material, thereby preventing (or alleviating) light leakage between the first pixel PXL1 and a pixel PXL adjacent to the first pixel PXL1 .

[0285] In an embodiment, at least one layer of the bank BNK disposed in the peripheral area of the first pixel area PXA1 and at least one layer of the stacked pattern LAP disposed in the emission area EMA of the first pixel area PXA1 may have the same material. In addition, the bank BNK and the stacked pattern LAP may include at least one layer formed by the same process.

[0286] The first electrode EL1 and the second electrode EL2 may be disposed at positions spaced apart from each other in the emission area EMA. The first connection electrode CP1 and the second connection electrode CP2 may be disposed between the first electrode EL1 and the second electrode EL2. For example, the first connection electrode CP1 may be disposed between the first electrode EL1 and the second connection electrode CP2. The second connection electrode CP2 may be disposed between the first connection electrode CP1 and the second electrode EL2. In a plan view, the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may be disposed at positions spaced apart from each other.

[0287] In an embodiment, the first electrode EL1 and the first connection electrode CP1 may be spaced apart from each other by a predetermined distance. The first connection electrode CP1 and the second connection electrode CP2 may be spaced apart from each other by a predetermined distance. The second connection electrode CP2 and the second electrode EL2 may be spaced apart from each other by a predetermined distance. In the emission area EMA of the first pixel PXL1, the distance between the first electrode EL1 and the first connection electrode CP1, the distance between the first connection electrode CP1 and the second connection electrode CP2, and the distance between the second connection electrode CP2 and the second electrode EL2 may be the same. Therefore, the light-emitting element LD may be more uniformly arranged in the emission area EMA of the first pixel PXL1. However, the embodiment is not limited thereto. In an embodiment, the distance between the first electrode EL1 and the first connection electrode CP1, the distance between the first connection electrode CP1 and the second connection electrode CP2, and the distance between the second connection electrode CP2 and the second electrode EL2 may be different from each other or different from at least one of the others.

[0288] The first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may be disposed and / or formed on the stack pattern LAP, and therefore, each may have a surface profile corresponding to the shape of the stack pattern LAP. For example, the first electrode EL1, the second electrode EL2, and the first connection electrode CP1 and the second connection electrode CP2 may each include a protruding portion corresponding to the stack pattern LAP and a planar portion corresponding to the first insulating layer INS1. The first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may be formed of a material having a predetermined reflectivity to allow light emitted from each of the light-emitting elements LD to move in an image display direction of the display device.

[0289] Each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may be formed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal, which has the advantage of reflecting light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal may include, for example, at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and an alloy of at least two of these materials. In an embodiment, each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may include a transparent conductive material. The transparent conductive material may include a conductive oxide such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), or a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT). In the case where each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 includes a transparent conductive material, a separate conductive layer made of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device may be included in each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2. However, the material used for each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 is not limited to the above materials.

[0290] In addition, although each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 can be arranged and / or formed as a single-layer structure, the embodiment is not limited thereto. In the embodiment, each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 can be arranged and / or formed as a multilayer structure in which layers made of at least two or more materials selected from metals, alloys, conductive oxides, and conductive polymers are stacked. Each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 can be formed of a multilayer having at least two or more layers to minimize (or at least reduce) distortion that may occur due to signal delay when a signal (or voltage) is transmitted to the opposite ends of each of the light-emitting elements LD. For example, each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 can have a multilayer structure in which layers are stacked in the order of ITO / Ag / ITO.

[0291] In an embodiment, each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may be formed of the third conductive layer CL3. Each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may be disposed in the same layer as the j-th data line Dj, the initialization power line IPL, and the first power line PL1, and may include the same material as that of the j-th data line Dj, the initialization power line IPL, and the first power line PL1.

[0292] As described above, since each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 has a surface profile corresponding to the shape of the stack pattern LAP provided thereunder, light emitted from each of the light-emitting elements LD can be reflected by the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2, and therefore, light emitted from each of the light-emitting elements LD can more reliably advance in the image display direction of the display device. The output efficiency of light emitted from each of the light-emitting elements LD can be further improved.

[0293] In an embodiment, each of the stack pattern LAP, the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may function as a reflective member for guiding light emitted from the light emitting element LD in a desired direction, thereby improving the optical efficiency of the display device. In other words, each of the stack pattern LAP, the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 may function as a reflective member for causing light emitted from the light emitting element LD to advance in an image display direction of the display device, thereby improving the light output efficiency of the display device.

[0294] In the emission area EMA of the first pixel PXL1, a plurality of light-emitting elements LD are arranged and / or disposed between the first electrode EL1 and the first connection electrode CP1, between the first connection electrode CP1 and the second connection electrode CP2, and between the second connection electrode CP2 and the second electrode EL2. In the emission area EMA, the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, the second electrode EL2, and the light-emitting elements LD may form an emission unit EMU of the first pixel PXL1.

[0295] The first electrode EL1 included in the emission unit EMU of the first pixel PXL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0296] The first electrode EL1 can be electrically coupled to the pixel circuit unit PCL via the seventh contact hole CH7. For example, the first electrode EL1 can be coupled to the sixth drain electrode DE6 of the sixth transistor T6 of the pixel circuit unit PCL via the seventh contact hole CH7. Thus, a signal (or voltage) applied to the sixth transistor T6 can be transmitted to the first electrode EL1. Furthermore, the first electrode EL1 can be electrically coupled to the second upper electrode UE2 via the eighth contact hole CH8. Thus, a signal (or voltage) transmitted to the first electrode EL1 can be transmitted to the second upper electrode UE2.

[0297] In an embodiment, the second electrode EL2 may be integrally provided with the second power line PL2 that intersects the first area FA and the second area SA of the first pixel area PXA1, and thus may be coupled to the second power line PL2. If the second electrode EL2 and the second power line PL2 are integrally provided, the second electrode EL2 may be considered part of the second power line PL2, or the second power line PL2 may be considered part of the second electrode EL2. As described above, since the second electrode EL2 is integrally provided with the second power line PL2, the second driving power VSS applied to the second power line PL2 may be transmitted to the second electrode EL2.

[0298] In the above, each of the light-emitting elements LD can be formed by a light-emitting element that is made of a material having an inorganic crystal structure and has an ultra-small size ranging from the nanometer level to the micrometer level, for example. For example, each of the light-emitting elements LD can be an ultra-small light-emitting element manufactured by an etching method or a growth method. The type, size, shape, etc. of the light-emitting element LD can be changed in various ways. Although at least two to several dozen light-emitting elements LD can be arranged and / or set in the emission area EMA of the first pixel PXL1, the number of light-emitting elements LD is not limited thereto. In an embodiment, the number of light-emitting elements LD in the emission area EMA of the first pixel PXL1 can be changed in various ways.

[0299] The light-emitting element LD can be arranged in a dispersed form in a solution and then supplied to the emission area EMA of the first pixel PXL1. In an embodiment, the light-emitting element LD can be supplied to the emission area EMA by an inkjet printing method, a slit coating method, or various other methods. For example, the light-emitting element LD can be mixed with a volatile solvent and then supplied to the emission area EMA by an inkjet printing method or a slit coating method. Here, if corresponding alignment signals (or alignment voltages) are respectively applied to the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2 set in the emission area EMA, an electric field can be formed between the first electrode EL1 and the first connection electrode CP1, between the first connection electrode CP1 and the second connection electrode CP2, and between the second connection electrode CP2 and the second electrode EL2. Therefore, the light-emitting element LD can be aligned between the first electrode EL1 and the first connection electrode CP1, between the first connection electrode CP1 and the second connection electrode CP2, and between the second connection electrode CP2 and the second electrode EL2. After the light-emitting element LD has been aligned, the solvent can be removed by volatilization or other methods. Therefore, the light emitting element LD may be aligned and / or disposed in the emission area EMA of the first pixel PXL1 .

[0300] The light emitting element LD may include a first light emitting element LD1 disposed between the first electrode EL1 and the first connection electrode CP1, a second light emitting element LD2 disposed between the first connection electrode CP1 and the second connection electrode CP2, and a third light emitting element LD3 disposed between the second connection electrode CP2 and the second electrode EL2.

[0301] Before the light-emitting element LD is arranged in the emission area EMA of the first pixel PXL1, the first electrode EL1 may be integrally provided with the first floating electrode FLT1 and, therefore, may be coupled to the first floating electrode FLT1. In the case where the first electrode EL1 and the first floating electrode FLT1 are integrally provided, the first electrode EL1 may be considered as part of the first floating electrode FLT1, or the first floating electrode FLT1 may be considered as part of the first electrode EL1. Before the light-emitting element LD is arranged, the first electrode EL1 and the first floating electrode FLT1, which are integrally provided and coupled to each other, may serve as arrangement electrodes.

[0302] After the light-emitting element LD is arranged, the first electrode EL1 and the first floating electrode FLT1, which are arranged integrally, can be electrically and / or physically separated from each other. Thus, the first floating electrode FLT1, which is arranged in the first area FA of the first pixel area PXA1 of the first pixel PXL1, can be spaced apart from the first electrode EL1, which is arranged in the emission area EMA of the first pixel area PXA1. After the light-emitting element LD is arranged, the first electrode EL1 can serve as a drive electrode for driving the light-emitting element LD. For example, after the light-emitting element LD is arranged, the first electrode EL1 can serve as the anode electrode of the emission unit EMU of the first pixel PXL1. Furthermore, after the light-emitting element LD is arranged, the first floating electrode FLT1 can be floating, i.e., electrically isolated.

[0303] Before arranging the light-emitting element LD in the emission area EMA of the first pixel PXL1, the first connection electrode CP1 may be integrally provided with the second floating electrode FLT2 and, therefore, may be coupled to the second floating electrode FLT2. In the case where the first connection electrode CP1 and the second floating electrode FLT2 are integrally provided, the first connection electrode CP1 may be considered as part of the second floating electrode FLT2, or the second floating electrode FLT2 may be considered as part of the first connection electrode CP1. Before arranging the light-emitting element LD, the first connection electrode CP1 and the second floating electrode FLT2, which are integrally provided and coupled to each other, may serve as arrangement electrodes.

[0304] After the light-emitting element LD is arranged, the first connection electrode CP1 and the second floating electrode FLT2, which are integrally arranged, can be electrically and / or physically separated from each other. Thus, the second floating electrode FLT2, which is arranged in the first area FA of the first pixel area PXA1 of the first pixel PXL1, can be spaced apart from the first connection electrode CP1, which is arranged in the emission area EMA of the first pixel area PXA1. After the light-emitting element LD is arranged, the first connection electrode CP1 can form a path between the first electrode EL1 and the second electrode EL2 for the drive current to flow from the first electrode EL1 to the second electrode EL2. Furthermore, after the light-emitting element LD is arranged, the second floating electrode FLT2 can be floating, that is, electrically isolated.

[0305] Before the light emitting element LD is arranged in the emission area EMA of the first pixel PXL1, the second connection electrode CP2 may be integrally provided with the third floating electrode FLT3 and, therefore, may be coupled to the third floating electrode FLT3. In the case where the second connection electrode CP2 and the third floating electrode FLT3 are integrally provided, the second connection electrode CP2 may be considered as part of the third floating electrode FLT3, or the third floating electrode FLT3 may be considered as part of the second connection electrode CP2. Before the light emitting element LD is arranged, the second connection electrode CP2 and the third floating electrode FLT3, which are integrally provided and coupled to each other, may serve as arrangement electrodes.

[0306] After the light-emitting element LD is arranged, the second connection electrode CP2 and the third floating electrode FLT3, which are integrally arranged, can be electrically and / or physically separated from each other. Thus, the third floating electrode FLT3, which is arranged in the first area FA of the first pixel area PXA1 of the first pixel PXL1, can be spaced apart from the second connection electrode CP2, which is arranged in the emission area EMA of the first pixel area PXA1. After the light-emitting element LD is arranged, the second connection electrode CP2 can serve as a path for the drive current to flow from the first electrode EL1 to the second electrode EL2. Furthermore, after the light-emitting element LD is arranged, the third floating electrode FLT3 can be floating, that is, electrically isolated.

[0307] Whether before or after arranging the light-emitting element LD in the emission area EMA of the first pixel PXL1, the second electrode EL2 can be integrally provided with the fourth arrangement electrode ARL4 and, therefore, can be coupled to the fourth arrangement electrode ARL4. The fourth arrangement electrode ARL4 can be a second power supply line PL2 to which the second drive power source VSS is applied. After the light-emitting element LD has been arranged, the second electrode EL2 and the fourth arrangement electrode ARL4 can function as drive electrodes for driving the light-emitting element LD. For example, after the light-emitting element LD has been arranged, the second electrode EL2 and the fourth arrangement electrode ARL4 can function as cathode electrodes of the emission unit EMU of the first pixel PXL1.

[0308] In the emission area EMA of the first pixel PXL1, the first electrode EL1 and the first connection electrode CP1, together with the first light-emitting element LD1 connected in parallel between the first electrode EL1 and the first connection electrode CP1, may be a series stage (hereinafter referred to as the "first series stage"). In the emission area EMA of the first pixel PXL1, the first connection electrode CP1 and the second connection electrode CP2, together with the second light-emitting element LD2 connected in parallel between the first connection electrode CP1 and the second connection electrode CP2, may be another series stage (hereinafter referred to as the "second series stage"). In the emission area EMA of the first pixel PXL1, the second connection electrode CP2 and the second electrode EL2, together with the third light-emitting element LD3 connected in parallel between the second connection electrode CP2 and the second electrode EL2, may be another series stage (hereinafter referred to as the "third series stage").

[0309] In an embodiment, the first to third series connection stages may be disposed in the emission area EMA of the first pixel PXL1 . The first to third series connection stages may form an emission unit EMU of the first pixel PXL1 .

[0310] Each of the light-emitting elements LD may include a first end electrically coupled to one of two electrodes spaced a predetermined distance apart from each other, and a second end electrically coupled to the other electrode. The first end of each of the light-emitting elements LD may be directly coupled to one of the two electrodes disposed adjacent to each other with a predetermined distance therebetween, or may be coupled to one electrode via a contact electrode CNE. Furthermore, the second end of each of the light-emitting elements LD may be directly coupled to the other of the two adjacent electrodes, or may be coupled to the other electrode via another contact electrode CNE.

[0311] The light emitting element LD may be disposed in the emission area EMA of the first pixel PXL1 and / or arranged on the fifth insulating pattern INSP5. In an embodiment, the fifth insulating pattern INSP5 may be a component corresponding to the fourth insulating layer INS4 included in the pixel circuit portion PCL. In addition, the fifth insulating pattern INSP5 disposed in the emission area EMA may have the same configuration as the fifth insulating pattern INSP5 included in the bank portion BNK.

[0312] The fifth insulating pattern INSP5 may be formed and / or disposed below the light-emitting element LD, wherein the light-emitting element LD is arranged and / or disposed between two electrodes spaced a predetermined distance apart from each other in the emission area EMA. The fifth insulating pattern INSP5 may fill the space between the light-emitting element LD and the first insulating layer INS1, thereby stably supporting the light-emitting element LD and preventing the light-emitting element LD from being removed from the first insulating layer INS1. For example, the fifth insulating pattern INSP5 may be formed and / or disposed below the light-emitting element LD disposed between the first electrode EL1 and the first connection electrode CP1. Furthermore, the fifth insulating pattern INSP5 may be formed and / or disposed below the light-emitting element LD disposed between the first connection electrode CP1 and the second connection electrode CP2. Furthermore, the fifth insulating pattern INSP5 may be formed and / or disposed below the light-emitting element LD disposed between the second connection electrode CP2 and the second electrode EL2.

[0313] In the emission area EMA of the first pixel PXL1, the fifth insulating pattern INSP5 may expose a region of one of the two electrodes spaced apart from each other by a predetermined distance, and cover the remaining region except the exposed region to protect the remaining region. In addition, the fifth insulating pattern INSP5 may expose a region of the other of the two electrodes spaced apart from each other by a predetermined distance, and cover the remaining region except the exposed region to protect the remaining region.

[0314] The fifth insulating pattern INSP5 may be an organic insulating layer including an organic material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0315] In an embodiment, such as Figure 13 As shown in , an auxiliary insulating pattern INSP_a may be provided and / or formed on each of the light-emitting elements LD. The auxiliary insulating pattern INSP_a may be provided and / or formed on each of the light-emitting elements LD to cover the light-emitting element LD so that opposite ends of the light-emitting element LD are exposed to the outside. The auxiliary insulating pattern INSP_a may be provided as an independent insulating pattern in the emission area EMA, but the embodiment is not limited thereto. After the light-emitting elements LD have been arranged in the emission area EMA, the auxiliary insulating pattern INSP_a is formed on each light-emitting element LD, thereby preventing the light-emitting element LD from being removed from the arrangement position.

[0316] The contact electrode CNE may be disposed on each of the first electrode EL1 , the first connection electrode CP1 , the second connection electrode CP2 , and the second electrode EL2 .

[0317] The contact electrode CNE can be formed of various transparent conductive materials. For example, the contact electrode CNE can include at least one of various conductive materials such as ITO, IZO, and ITZO, and can be substantially transparent or translucent to meet a predetermined transmittance. However, the material of the contact electrode CNE is not limited to the materials of the aforementioned embodiments. In some embodiments, the contact electrode CNE can be formed of various opaque conductive materials.

[0318] A contact electrode CNE (hereinafter referred to as a "first contact electrode") formed on the first electrode EL1 may electrically and / or physically couple the first electrode EL1 to one of the opposite ends of each of the first light-emitting elements LD1. The first contact electrode CNE may overlap both one of the opposite ends of each of the first light-emitting elements LD1 and the first electrode EL1. Furthermore, the first contact electrode CNE may overlap with the stack pattern LAP disposed below the first electrode EL1 and, therefore, may cover the stack pattern LAP.

[0319] A contact electrode CNE (hereinafter referred to as a "second contact electrode") formed on the first connection electrode CP1 can electrically and / or physically couple one side of the first connection electrode CP1 to the remaining one of the opposite ends of each of the first light-emitting elements LD1. The second contact electrode CNE can electrically and / or physically couple the other side of the first connection electrode CP1 to one of the opposite ends of each of the second light-emitting elements LD2. The second contact electrode CNE can overlap with the remaining one of the opposite ends of the corresponding first light-emitting element LD1, one of the opposite ends of each of the second light-emitting elements LD2, and the first connection electrode CP1. In addition, the second contact electrode CNE can overlap with the stack pattern LAP disposed below the first connection electrode CP1 and, therefore, can cover the stack pattern LAP.

[0320] A contact electrode CNE (hereinafter referred to as a "third contact electrode") formed on the second connection electrode CP2 can electrically and / or physically couple one side of the second connection electrode CP2 to the remaining one of the opposite ends of each of the second light-emitting elements LD2. The third contact electrode CNE can electrically and / or physically couple the other side of the second connection electrode CP2 to one of the opposite ends of each of the third light-emitting elements LD3. The third contact electrode CNE can overlap with the remaining one of the opposite ends of each of the second light-emitting elements LD2, one of the opposite ends of each of the third light-emitting elements LD3, and the second connection electrode CP2. In addition, the third contact electrode CNE can overlap with the stack pattern LAP disposed below the second connection electrode CP2 and, therefore, can cover the stack pattern LAP.

[0321] A contact electrode CNE on the second electrode EL2 (hereinafter referred to as a "fourth contact electrode") may electrically and / or physically couple the second electrode EL2 to the remaining one of the opposite ends of each of the third light-emitting elements LD3. The fourth contact electrode CNE may overlap both the remaining one of the opposite ends of each of the third light-emitting elements LD3 and the second electrode EL2. Furthermore, the fourth contact electrode CNE may overlap the stack pattern LAP disposed below the second electrode EL2 and, therefore, may cover the stack pattern LAP.

[0322] The first, second, third, and fourth contact electrodes CNE may extend in the second direction DR2 and may be disposed in the emission area EMA of the first pixel PXL1. Each of the first, second, third, and fourth contact electrodes CNE may be spaced apart from an adjacent contact electrode CNE and, therefore, may be electrically and / or physically separated from the adjacent contact electrode CNE. The first, second, third, and fourth contact electrodes CNE may be disposed and / or formed in the same layer and include the same material. In an embodiment, each of the first, second, third, and fourth contact electrodes CNE may be formed from the fourth conductive layer CL4.

[0323] Each of the first, second, third, and fourth contact electrodes CNE may have a rod shape extending in the second direction DR2, but the embodiment is not limited thereto, and for example, each of the first, second, third, and fourth contact electrodes CNE may be changed to various shapes as long as it can reliably electrically and / or physically couple an electrode disposed thereunder with one of the opposite ends of each of the light emitting elements LD.

[0324] The encapsulation layer ENC may be disposed and / or formed on the first, second, third, and fourth contact electrodes CNE. The encapsulation layer ENC may be a protective member for covering the pixel circuit portion PCL and the display element portion DPL. The encapsulation layer ENC may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC may have a structure formed by alternating stacking of at least one or more inorganic layers and at least one or more organic layers.

[0325] In an embodiment, the first electrode EL1 of the paired electrodes of the first series stage of the emission unit EMU constituting the first pixel PXL1 (e.g., the first electrode EL1 and the first connection electrode CP1) can be electrically coupled to the first transistor T1 of the pixel circuit 144 through the seventh contact hole CH7 and the sixth transistor T6 of the pixel circuit 144.

[0326] When a drive current flows from the first power line PL1 to the second power line PL2 via the first transistor T1 included in the pixel circuit 144 of the first pixel PXL1 via the pixel circuit 144, the drive current can be supplied to the emission unit EMU of the first pixel PXL1 via the sixth transistor T6 and the seventh contact hole CH7. For example, the drive current can be supplied to the first electrode EL1 via the seventh contact hole CH7. The drive current can flow via the first light-emitting element LD1 to the first connection electrode CP1. As a result, each of the first light-emitting elements LD1 can emit light at a brightness corresponding to the distributed current. The drive current flowing through the first connection electrode CP1 can flow via the second light-emitting element LD2 to the second connection electrode CP2. As a result, each of the second light-emitting elements LD2 can emit light at a brightness corresponding to the distributed current. The drive current flowing through the second connection electrode CP2 can flow via the third light-emitting element LD3 to the second electrode EL2. As a result, each of the third light-emitting elements LD3 can emit light at a brightness corresponding to the distributed current.

[0327] As described above, each of the pixel circuit portion PCL and the display element portion DPL of the first pixel PXL1 can be provided in a multilayer structure including at least one or more conductive layers and at least one or more insulating layers provided and / or formed on one surface of the substrate SUB. At least one layer in the pixel circuit portion PCL and at least one layer in the display element portion PDL can be provided in the same layer and can have the same material.

[0328] In an embodiment, since the pixel circuit portion PCL and the display element portion DPL of each of the pixels PXL are arranged on the same surface of the substrate SUB, the display device can have a slim structure with a reduced thickness compared to the structure of a conventional display device in which the display element portion DPL is arranged on the pixel circuit portion PCL.

[0329] According to the aforementioned embodiment, the components included in the pixel circuit portion PCL and the components included in the display element portion DPL are formed using the same process. Therefore, the number of masks can be reduced compared to the number of masks used in a conventional display device in which the pixel circuit portion PCL and the display element portion DPL are formed using separate processes. Therefore, the process for manufacturing the display device can be simplified. When the display device manufacturing process is simplified, the production cost of the display device can also be reduced.

[0330] Furthermore, according to the aforementioned embodiment, the light-emitting elements LD are centrally arranged and disposed in a desired area, for example, in the second area SA of the display element portion DPL of the first pixel area PXA1 in which the first pixel PXL1 is disposed. Therefore, the arrangement distribution of the light-emitting elements LD in the first pixel PXL1 and the arrangement distribution of the light-emitting elements LD in the adjacent pixels PXL can be uniform. With the uniform arrangement distribution of the light-emitting elements LD in each pixel PXL, the display device can have a uniform light emission distribution throughout the entire display area DA.

[0331] Furthermore, according to the aforementioned embodiment, since the light emitting elements LD are centrally provided and arranged in a desired area, it is possible to prevent or mitigate the problem of contact failure between each of the light emitting elements LD and the electrodes to be electrically coupled to the light emitting elements LD. Here, the electrodes to be electrically coupled to the light emitting elements LD may include the first and second electrodes EL1 and EL2, the first and second connection electrodes CP1 and CP2, and the contact electrode CNE.

[0332] Figures 15A to 15G According to some embodiments, at various stages of manufacture Figure 8 Schematic plan view of a first pixel. Figures 16A to 16K According to some embodiments, at various stages of manufacture Figure 9 A cross-sectional view of a first pixel.

[0333] In the following, reference will be made to Figures 15A to 15G as well as Figures 16A to 16K Describing the manufacturing process according to the embodiment Figure 8 and Figure 9 The method of the first pixel PXL1 is shown in FIG.

[0334] refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15A and Figure 16A , providing a substrate SUB.

[0335] A buffer layer BFL is formed on the substrate SUB. In some embodiments, the buffer layer BFL may be omitted.

[0336] A semiconductor layer SML is formed on the buffer layer BFL. The semiconductor layer SML may be an undoped semiconductor layer. In an embodiment, the semiconductor layer SML may be provided only in the first area FA included in the first pixel area PXA1 of the first pixel PXL1, but the embodiment is not limited thereto. In some embodiments, the semiconductor layer SML may also be provided in the second area SA included in the first pixel area PXA1.

[0337] The semiconductor layer SML may be formed of silicon (Si), such as amorphous silicon (a-Si), or may be formed of polycrystalline silicon (p-Si). In the case where the semiconductor layer SML is formed of amorphous silicon (a-Si), a crystallization process using laser light may be further performed.

[0338] In an embodiment, the semiconductor layer SML may be made of a binary compound (AB x ), ternary compound (AB x C y ), quaternary compound (AB x C y D z ) etc., wherein the semiconductor oxide contains at least one of indium, zinc, tin, gallium, titanium, aluminum, hafnium, zirconium, magnesium, etc. These components may be used alone or in combination with each other.

[0339] refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15B 、 Figure 16A and Figure 16B , a first insulating layer INS1 is formed on the entire surface of the substrate SUB including the semiconductor layer SML.

[0340] Thereafter, a first conductive layer CL1 of the pixel circuit portion PCL and a first conductive layer CL1 of the display element portion DPL are formed on the first insulating layer INS1. The first conductive layer CL1 of the pixel circuit portion PCL and the first conductive layer CL1 of the display element portion DPL are provided in the same layer, include the same material, and are formed by the same process.

[0341] In an embodiment, the first conductive layer CL1 of the pixel circuit portion PCL may include an i-1th scan line Si-1, an i-th scan line Si, an i+1th scan line Si+1, an i-th emission control line Ei, and first and second lower electrodes LE1 and LE2. The first conductive layer CL1 of the display element portion DPL may include a first metal pattern MTP1 and a third metal pattern MTP3.

[0342] Subsequently, the semiconductor layer SML is doped with impurities using the first conductive layer CL1 of the pixel circuit portion PCL as a mask. Thus, the impurity-doped region of the semiconductor layer SML can serve as the source electrodes SE1, SE2, SE3a, SE3b, SE4a, SE4b, SE5, SE6, and SE7, and the drain electrodes DE1, DE2, DE3a, DE3b, DE4a, DE4b, DE5, DE6, and DE7, of the first to seventh transistors T1 to T7, respectively.

[0343] Meanwhile, other regions of the semiconductor layer SML overlapping with the first conductive layer CL1 of the pixel circuit portion PCL and thus not doped with impurities may become respective active patterns ACT1, ACT2, ACT3a, ACT3b, ACT4a, ACT4b, ACT5, ACT6, and ACT7 of the first to seventh transistors T1 to T7.

[0344] In an embodiment, the region of the first lower electrode LE1 overlapping with the first active pattern ACT1 may become the first gate electrode GE1. The region of the i-th scan line Si overlapping with the second active pattern ACT2 may become the second gate electrode GE2. The region of the i-th scan line Si overlapping with the 3a-th active pattern ACT3a may become the 3a-th gate electrode GE3a. The region of the i-th scan line Si overlapping with the 3b-th active pattern ACT3b may become the 3b-th gate electrode GE3b. Furthermore, the region of the i-1-th scan line Si-1 overlapping with the 4a-th active pattern ACT4a may become the 4a-th gate electrode GE4a. The region of the i-1-th scan line Si-1 overlapping with the 4b-th active pattern ACT4b may become the 4b-th gate electrode GE4b. The region of the i-th emission control line Ei overlapping with the fifth active pattern ACT5 may become the fifth gate electrode GE5. The region of the i-th emission control line Ei overlapping with the sixth active pattern ACT6 may become the sixth gate electrode GE6. A region of the (i+1)th scan line Si+1 overlapping the seventh active pattern ACT7 may become the seventh gate electrode GE7.

[0345] refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 as well as 16A to 16C A second insulating layer INS2 is formed on the first conductive layer CL1 of the pixel circuit portion PCL, and a first insulating pattern INSP1 and a third insulating pattern INSP3 are formed on the first conductive layer CL1 of the display element portion DPL.

[0346] The second insulating layer INS2 of the pixel circuit portion PCL and the first and third insulating patterns INSP1 and INSP3 of the display element portion DPL may be disposed in the same layer, include the same material, and be formed through the same process.

[0347] The first insulating pattern INSP1 of the display element portion DPL may be disposed on the first metal pattern MTP1 and thus may cover the first metal pattern MTP1. The third insulating pattern INSP3 of the display element portion DPL may be disposed on the third metal pattern MTP3 and thus may cover the third metal pattern MTP3.

[0348] refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15C as well as 16A to 16D , a second conductive layer CL2 is formed on the second insulating layer INS2 of the pixel circuit portion PCL, and is formed on each of the first and third insulating patterns INSP1 and INSP3 of the display element portion DPL.

[0349] The second conductive layer CL2 of the pixel circuit portion PCL and the second conductive layer CL2 of the display element portion DPL may be provided in the same layer, include the same material, and be formed through the same process.

[0350] In an embodiment, the second conductive layer CL2 of the pixel circuit portion PCL may include a first upper electrode UE1 and a second upper electrode UE2. The second conductive layer CL2 of the display element portion DPL may include a second metal pattern MTP2 and a fourth metal pattern MTP4.

[0351] The first upper electrode UE1 may include an opening OPN. The first upper electrode UE1 may overlap with the first lower electrode LE1, with the second insulating layer INS2 interposed therebetween, and the first upper electrode UE1 and the first lower electrode LE1 may form a first capacitor C1 together. The second upper electrode UE2 may overlap with the second lower electrode LE2, with the second insulating layer INS2 interposed therebetween, and the second upper electrode UE2 and the second lower electrode LE2 may form a second capacitor C2 together.

[0352] The second metal pattern MTP2 may be disposed on the first metal pattern MTP1 with the first insulating pattern INSP1 interposed therebetween, and thus the second metal pattern MTP2 may overlap the first metal pattern MTP1. The fourth metal pattern MTP4 may be disposed on the third metal pattern MTP3 with the third insulating pattern INSP3 interposed therebetween, and thus the fourth metal pattern MTP4 may overlap the third metal pattern MTP3.

[0353] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 as well as 16A to 16E A third insulating layer INS3 is formed on the second conductive layer CL2 of the pixel circuit portion PCL, and a second insulating pattern INSP2 and a fourth insulating pattern INSP4 are formed on the second conductive layer CL2 of the display element portion DPL.

[0354] The third insulating layer INS3 of the pixel circuit portion PCL and the second and fourth insulating patterns INSP2 and INSP4 of the display element portion DPL may be disposed in the same layer, include the same material, and be formed through the same process.

[0355] The third insulating layer INS3 of the pixel circuit portion PCL may cover the second conductive layer CL2 disposed under the third insulating layer INS3 .

[0356] The second insulating pattern INSP2 of the display element portion DPL may be disposed on and thus cover the second metal pattern MTP2. In addition, the fourth insulating pattern INSP4 of the display element portion DPL may be disposed on and thus cover the fourth metal pattern MTP4.

[0357] In an embodiment, the display element part DPL may include a stack pattern LAP having a multi-layer structure in which a first metal pattern MTP1 , a first insulating pattern INSP1 , a second metal pattern MTP2 , and a second insulating pattern INSP2 are sequentially stacked on a surface of the first insulating layer INS1 .

[0358] Thereafter, first to tenth contact holes CH1 to CH10 are formed in the first pixel area PXA1 of the first pixel PXL1 .

[0359] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15D as well as 16A to 16F A third conductive layer CL3 is formed on the third insulating layer INS3 of the pixel circuit portion PCL, and is formed on each of the second and fourth insulating patterns INSP2 and INSP4 of the display element portion DPL.

[0360] The third conductive layer CL3 of the pixel circuit portion PCL and the third conductive layer CL3 of the display element portion DPL may be provided in the same layer, include the same material, and be formed through the same process.

[0361] In an embodiment, the third conductive layer CL3 of the pixel circuit portion PCL may include an initialization power line IPL, a j-th data line Dj, an auxiliary connection line AUX, a first power line PL1, and a conductive pattern CNP. The third conductive layer CL3 of the display element portion DPL may include first to fourth arrangement electrodes ARL1 to ARL4 and a fifth metal pattern MTP5.

[0362] In an embodiment, the first to fourth arrangement electrodes ARL1 to ARL4 included in the third conductive layer CL3 of the display element portion DPL may be provided in both the first area FA and the second area SA of the first pixel region PXA1. Therefore, the first to fourth arrangement electrodes ARL1 to ARL4 of the display element portion DPL may overlap with some components, for example, the first and third transistors T1 and T3, the first and second capacitors C1 and C2, the scan lines Si-1, Si, and Si+1, and the i-th emission control line Ei included in the pixel circuit portion PCL.

[0363] The fifth metal pattern MTP5 included in the third conductive layer CL3 of the display element portion DPL may be a portion of the initialization power line IPL of the pixel circuit portion PCL, a portion of the j-th data line Dj, or a portion of the first power line PL1. The fourth arrangement electrode ARL4 included in the third conductive layer CL3 of the display element portion DPL may be a second power line PL2 to which the second driving power VSS is applied.

[0364] Each of the first to fourth arrangement electrodes ARL1 to ARL4 included in the third conductive layer CL3 of the display element portion DPL may be formed on a corresponding stack pattern LAP.

[0365] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 as well as Figures 16A to 16G, a fourth insulating layer INS4 is formed in the pixel circuit portion PCL, and a fifth insulating pattern INSP5 is formed in the display element portion DPL.

[0366] The fourth insulating layer INS4 of the pixel circuit portion PCL and the fifth insulating pattern INSP5 of the display element portion DPL may be disposed in the same layer, include the same material, and be formed through the same process.

[0367] The fifth insulating pattern INSP5 of the display element portion DPL may be formed in a space formed between two adjacent arrangement electrodes among the first to fourth arrangement electrodes ARL1 to ARL4. Furthermore, the fifth insulating pattern INSP5 of the display element portion DPL may be formed on the fourth insulating pattern INSP4 and the fifth metal pattern MTP5 to cover them.

[0368] In an embodiment, the display element portion DPL may include a dam portion BNK having the following multi-layer structure, in which the third metal pattern MTP3, the third insulation pattern INSP3, the fourth metal pattern MTP4, the fourth insulation pattern INSP4 and the fifth insulation pattern INSP5 are stacked in sequence, or the display element portion DPL may include a dam portion BNK having the following multi-layer structure, in which the third metal pattern MTP3, the third insulation pattern INSP3, the fourth metal pattern MTP4, the fourth insulation pattern INSP4, the fifth metal pattern MTP5 and the fifth insulation pattern INSP5 are stacked in sequence.

[0369] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15E as well as 16A to 16H , arrangement signals (or arrangement voltages) are applied to the first to fourth arrangement electrodes ARL1 to ARL4, respectively, thereby forming an electric field between two adjacent arrangement electrodes. For example, when AC power or DC power having a predetermined voltage and period is repeatedly applied to each of the first to fourth arrangement electrodes ARL1 to ARL4, an electric field corresponding to the difference between the respective potentials of the two adjacent arrangement electrodes can be formed between two adjacent arrangement electrodes among the first to fourth arrangement electrodes ARL1 to ARL4.

[0370] When an electric field is formed between the first and second arrangement electrodes ARL1 and ARL2, between the second and third arrangement electrodes ARL3, and between the third and fourth arrangement electrodes ARL3 and ARL4, a mixed solution including light-emitting elements LD can be supplied onto the fifth insulating pattern INSP5 using an inkjet printing method or the like. For example, an inkjet nozzle can be provided above the fifth insulating pattern INSP5, and a solvent containing a plurality of light-emitting elements LD can be supplied onto the fifth insulating pattern INSP5 using the inkjet nozzle. Here, the solvent can be any one of acetone, water, alcohol, and toluene, but the embodiment is not limited thereto. For example, the solvent can be in the form of ink or paste. The method of supplying the light-emitting elements LD is not limited to the method of the aforementioned embodiment. The method of supplying the light-emitting elements LD can be modified in various ways.

[0371] After the supply of the light emitting element LD is completed, the solvent may be removed.

[0372] If the light-emitting elements LD are supplied, self-alignment of the light-emitting elements LD can be induced by electric fields formed between the first arrangement electrode ARL1 and the second arrangement electrode ARL2, between the second arrangement electrode ARL2 and the third arrangement electrode ARL3, and between the third arrangement electrode ARL3 and the fourth arrangement electrode ARL4. Therefore, the light-emitting elements LD can be aligned (or arranged) between the first arrangement electrode ARL1 and the second arrangement electrode ARL2, between the second arrangement electrode ARL2 and the third arrangement electrode ARL3, and between the third arrangement electrode ARL3 and the fourth arrangement electrode ARL4. The light-emitting elements LD can be aligned (or arranged) on the fifth insulating pattern INSP5.

[0373] In an embodiment, the light emitting element LD may be coupled in the same direction between two adjacent arrangement electrodes disposed adjacent to each other in the first direction DR1. In some embodiments, depending on the waveforms of the arrangement signals (or arrangement voltages) respectively applied to the two adjacent arrangement electrodes, the light emitting element LD may include at least one reverse light emitting element (refer to FIG. 1 ) oriented in a direction opposite to the direction of the light emitting element LD arranged in the forward direction (the same direction). Figure 6D LDr).

[0374] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15F as well as 16A to 16IThe first to third arrangement electrodes ARL1 to ARL3 are separated between the first pixel PXL1 and the adjacent pixel PXL by an etching method or the like using a mask, so that the first pixel PXL1 can be driven independently (or separately) from the adjacent pixel PXL. The fourth arrangement electrode ARL4 is not separated by the process of separating the first to third arrangement electrodes ARL1 to ARL3, and the fourth arrangement electrode ARL4 may be commonly coupled to the first pixel PXL1 and the adjacent pixel PXL disposed adjacent to the first pixel PXL in the second direction DR2.

[0375] In an embodiment, when the first to third arrangement electrodes ARL1 to ARL3 are separated between the first pixel PXL1 and a pixel PXL adjacent to the first pixel PXL1, for example, between the second area SA of the first pixel PXL1 and a first area (not shown) of the adjacent pixel PXL, a portion of each of the first to third arrangement electrodes ARL1 to ARL3 corresponding to the first area FA may be removed.

[0376] When a portion of the first arrangement electrode ARL1 is removed from the first area FA of the first pixel PXL1, the first floating electrode FLT1 can be disposed in the first area FA of the first pixel PXL1, and the first electrode EL1 can be disposed in the second area SA of the first pixel PXL1. The first floating electrode FLT1 and the first electrode EL1 can be disposed on (or in) the same column and spaced apart from each other. In other words, the first floating electrode FLT1 and the first electrode EL1 are electrically and physically separated from each other.

[0377] In an embodiment, after the light emitting element LD is arranged in the first pixel PXL1, a portion of the first arrangement electrode ARL1 is removed so that the first floating electrode FLT1 may be formed in the first area FA of the first pixel PXL1 and the first electrode EL1 may be formed in the second area SA of the first pixel PXL1.

[0378] When a portion of the second arrangement electrode ARL2 is removed from the first area FA of the first pixel PXL1, a second floating electrode FLT2 may be provided in the first area FA of the first pixel PXL1, and a first connection electrode CP1 may be provided in the second area SA of the first pixel PXL1. The second floating electrode FLT2 and the first connection electrode CP1 may be provided on (or in) the same column and spaced apart from each other. In other words, the second floating electrode FLT2 and the first connection electrode CP1 are electrically and physically separated from each other.

[0379] In an embodiment, after the light emitting element LD is arranged in the first pixel PXL1, a portion of the second arrangement electrode ARL2 is removed so that the second floating electrode FLT2 can be formed in the first area FA of the first pixel PXL1 and the first connection electrode CP1 can be formed in the second area SA of the first pixel PXL1.

[0380] When a portion of the third arrangement electrode ARL3 is removed from the first area FA of the first pixel PXL1, a third floating electrode FLT3 may be provided in the first area FA of the first pixel PXL1, and a second connection electrode CP2 may be provided in the second area SA of the first pixel PXL1. The third floating electrode FLT3 and the second connection electrode CP2 may be provided on (or in) the same column and spaced apart from each other. In other words, the third floating electrode FLT3 and the second connection electrode CP2 are electrically and physically separated from each other.

[0381] In an embodiment, after the light emitting element LD is arranged in the first pixel PXL1, a portion of the third arrangement electrode ARL3 is removed so that the third floating electrode FLT3 can be formed in the first area FA of the first pixel PXL1 and the second connection electrode CP2 can be formed in the second area SA of the first pixel PXL1.

[0382] In an embodiment, after the light emitting element LD has been arranged, the fourth arrangement electrode ARL4 disposed in the first area FA and the second area SA of the first pixel PXL1 may be used as the second electrode EL2 .

[0383] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 、 Figure 15G as well as Figures 16A to 16J A fourth conductive layer CL4 is formed on the first and second electrodes EL1 and EL2 of the display element portion DPL and the first and second connection electrodes CP1 and CP2.

[0384] In an embodiment, the fourth conductive layer CL4 may include a contact electrode CNE. The contact electrode CNE may be disposed and / or formed on each of the first electrode EL1, the first connection electrode CP1, the second connection electrode CP2, and the second electrode EL2.

[0385] The contact electrode CNE provided on the first electrode EL1 may be electrically and / or physically coupled to the first electrode EL1 in a manner that the contact electrode CNE is directly formed on the first electrode EL1. The contact electrode CNE provided on the first connection electrode CP1 may be electrically and / or physically coupled to the first connection electrode CP1 in a manner that the contact electrode CNE is directly formed on the first connection electrode CP1. The contact electrode CNE provided on the second connection electrode CP2 may be electrically and / or physically coupled to the second connection electrode CP2 in a manner that the contact electrode CNE is directly formed on the second connection electrode CP2. The contact electrode CNE provided on the second electrode EL2 may be electrically and / or physically coupled to the second electrode EL2 in a manner that the contact electrode CNE is directly formed on the second electrode EL2.

[0386] The contact electrode CNE disposed on the first electrode EL1 , the contact electrode CNE disposed on the first connection electrode CP1 , the contact electrode CNE disposed on the second connection electrode CP2 , and the contact electrode CNE disposed on the second electrode EL2 may be formed of the same conductive material and may be disposed and / or formed in the same layer.

[0387] Next, refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figures 8 to 14 as well as Figures 16A to 16K , an encapsulation layer ENC is formed on the fourth insulating layer INS4 of the pixel circuit portion PCL and the contact electrode CNE of the display element portion DPL.

[0388] The encapsulation layer ENC may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. Although the encapsulation layer ENC may have a single-layer structure as shown in the figure, the embodiment is not limited thereto. For example, the encapsulation layer ENC may have a multi-layer structure.

[0389] Figure 17 It shows that according to the embodiment Figure 7 A plan view of the first pixel. Figure 18 According to the implementation method Figure 17 A sectional view taken along section line V-V'.

[0390] In addition to the fact that the stack pattern LAP further includes the first auxiliary pattern MTP_a disposed under the first metal pattern MTP1 and the bank BNK further includes the second auxiliary pattern MTP6 disposed under the third metal pattern MTP3, Figure 17 and Figure 18 The configuration of the first pixel PXL1 shown in FIG can be Figure 8 The configurations of the first pixels PXL1 are substantially the same or similar.

[0391] Therefore, to avoid redundant explanations, Figure 17 and Figure 18 The description of the first pixel PXL1 will focus on the differences from the description of the previous embodiment. Components not separately described in the following description are consistent with the components described above. The same reference numerals will be used to refer to the same components, and similar reference numerals will be used to refer to similar components.

[0392] refer to Figures 1A to 4B 、 Figure 5A 、 Figure 5B 、 Figure 6E 、 Figure 7 、 Figure 17 and Figure 18 The first pixel PXL1 may be a pixel disposed at the intersection of the i-th pixel row and the j-th pixel column. In the display area DA of the substrate SUB, the region in which the first pixel PXL1 is disposed may be a first pixel area PXA1. The first pixel area PXA1 may include an emission area EMA from which light is emitted, and a peripheral area surrounding the periphery of the emission area EMA and not emitting light.

[0393] The first pixel PXL1 may be electrically coupled to each of the scan lines Si-1, Si, and Si+1, the jth data line Dj, the ith emission control line Ei, the initialization power line IPL, and the first and second power lines PL1 and PL2 provided in the first pixel area PXA1.

[0394] The first pixel region PXA1, in which the first pixel PXL1 is disposed, may include a first area FA and a second area SA divided in one direction. A substrate SUB and a pixel circuit portion PCL disposed thereon and including a pixel circuit 144 may be disposed in the first area FA. The substrate SUB and a display element portion DPL including a light-emitting element LD may be disposed in the second area SA. The emission area EMA of the first pixel region PXA1 may be included in the second area SA.

[0395] The pixel circuit portion PCL may include a buffer layer BFL disposed on a substrate SUB and a pixel circuit 144 disposed and / or formed on the buffer layer BFL. In an embodiment, the pixel circuit 144 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2.

[0396] The display element portion DPL may include a stack pattern LAP, first and second electrodes EL1 and EL2, first and second connection electrodes CP1 and CP2, a light emitting element LD, and a contact electrode CNE disposed in the emission area EMA. Furthermore, the display element portion DPL may include a bank BNK disposed in a peripheral region disposed around the emission area EMA.

[0397] The stacking pattern LAP can be a supporting member for supporting the first electrode EL1 and the second electrode EL2 and the first connecting electrode CP1 and the second connecting electrode CP2 to change the respective surface profiles of the first electrode EL1 and the second electrode EL2 and the first connecting electrode CP1 and the second connecting electrode CP2 so that the light emitted from the light emitting element LD can advance more reliably in the image display direction of the display device.

[0398] The stack pattern LAP may be provided as a multi-layer structure including at least one insulating layer and at least one conductive layer provided and / or formed on the buffer layer BFL. Figure 18 As shown in , the stacked pattern LAP may be provided in a multilayer structure in which a first auxiliary pattern MTP_a, a sub-insulating pattern INSP_S, a first metal pattern MTP1, a first insulating pattern INSP1, a second metal pattern MTP2, and a second insulating pattern INSP2 are sequentially stacked on a surface (e.g., an upper surface) of the buffer layer BFL. However, embodiments are not limited thereto. In embodiments, the stacked pattern LAP may not include the first auxiliary pattern MTP_a and the sub-insulating pattern INSP_S.

[0399] The stack pattern LAP including the first auxiliary pattern MTP_a, the sub-insulating pattern INSP_S, the first metal pattern MTP1, the first insulating pattern INSP1, the second metal pattern MTP2, and the second insulating pattern INSP2 may have a shape protruding upward from a surface (eg, upper surface) of the buffer layer BFL.

[0400] The bank BNK may be a structure that defines (or separates) the emission area EMA of the first pixel PXL1 and the pixels PXL adjacent to the first pixel PXL1. For example, the bank BNK may be a pixel defining (or defining) layer.

[0401] The embankment BNK may be disposed in a peripheral region surrounding the periphery of the emission area EMA and include at least two or more conductive layers and at least two or more insulating layers, and thus, may prevent (or reduce) light leakage between the first pixel PXL1 and the pixel PXL adjacent to the first pixel PXL1.

[0402] In an embodiment, the bank BNK may include at least two or more insulating layers and at least two or more conductive layers disposed and / or formed on the buffer layer BFL. For example, the bank BNK may be provided in a multilayer structure in which the second auxiliary pattern MTP6, the additional insulating pattern INSP_AD, the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4, and the fifth insulating pattern INSP5 are stacked in sequence. In addition, the bank BNK may further include a fifth metal pattern MTP5 disposed and / or formed between the fourth insulating pattern INSP4 and the fifth insulating pattern INSP5.

[0403] Depending on whether the fifth metal pattern MTP5 is included in the stacked multilayer structure, the bank BNK may be divided into a first bank area BA1 and a second bank area BA2. For example, the first bank area BA1 may refer to an area of the bank BNK that does not include the fifth metal pattern MTP5. The second bank area BA2 may refer to an area of the bank BNK that includes the fifth metal pattern MTP5.

[0404] For example, the first bank area BA1 may be a region of the bank BNK having a multi-layer structure in which the second auxiliary pattern MTP6, the additional insulating pattern INSP_AD, the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4, and the fifth insulating pattern INSP5 are sequentially stacked. For example, the second bank area BA2 may be a region of the bank BNK having a multi-layer structure in which the second auxiliary pattern MTP6, the additional insulating pattern INSP_AD, the third metal pattern MTP3, the third insulating pattern INSP3, the fourth metal pattern MTP4, the fourth insulating pattern INSP4, the fifth metal pattern MTP5, and the fifth insulating pattern INSP5 are sequentially stacked.

[0405] The second auxiliary pattern MTP6 may be formed of a semiconductor layer disposed and / or formed on the buffer layer BFL. In an embodiment, the second auxiliary pattern MTP6 may be disposed in the same layer as both the semiconductor layer included in the pixel circuit portion PCL and the first auxiliary pattern MTP_a included in the stacked pattern LAP, and may include the same material as that of the semiconductor layer and the first auxiliary pattern MTP_a.

[0406] The additional insulating pattern INSP_AD may be provided and formed on the second auxiliary pattern MTP6 and surround the second auxiliary pattern MTP6. For example, the additional insulating pattern INSP_AD may be an independent insulating pattern surrounding only the second auxiliary pattern MTP6. In an embodiment, the additional insulating pattern INSP_AD may have the same configuration as that of the sub-insulating pattern INSP_S included in the stack pattern LAP. The additional insulating pattern INSP_AD included in the bank portion BNK and the sub-insulating pattern INSP_S included in the stack pattern LAP may each be a first insulating layer (reference layer) included in the pixel circuit portion PCL. Figure 9 The additional insulating pattern INSP_AD included in the bank portion BNK and the sub-insulating pattern INSP_S included in the stack pattern LAP may be provided in the same layer as the first insulating layer INS1 included in the pixel circuit portion PCL, include the same material as that of the first insulating layer INS1, and may be formed by the same process as that of the first insulating layer INS1.

[0407] The third metal pattern MTP3 may be formed of the first conductive layer CL1 disposed and / or formed on the sub-insulating pattern INSP_S. In an embodiment, the third metal pattern MTP3 may be disposed in the same layer as the first metal pattern MTP1 included in the stacked pattern LAP and may include the same material as the first metal pattern MTP1.

[0408] The third insulating pattern INSP3 may be disposed on the third metal pattern MTP3 and configured to surround the third metal pattern MTP3. For example, the third insulating pattern INSP3 may be an independent insulating pattern surrounding only the third metal pattern MTP3. In an embodiment, the third insulating pattern INSP3 may be disposed in the same layer as the first insulating pattern INSP1 included in the stack pattern LAP and may include the same material as the first insulating pattern INSP1. The third insulating pattern INSP3 included in the bank portion BNK and the first insulating pattern INSP1 included in the stack pattern LAP may each be a second insulating layer (refer to FIG. 1 ) included in the pixel circuit portion PCL. Figure 9 In an embodiment, the third insulating pattern INSP3 included in the bank portion BNK and the first insulating pattern INSP1 included in the stack pattern LAP may be provided in the same layer as the second insulating layer INS2 included in the pixel circuit portion PCL, include the same material as that of the second insulating layer INS2, and may be formed by the same process as that of the second insulating layer INS2.

[0409] The fourth metal pattern MTP4 may be formed of the second conductive layer CL2 disposed and / or formed on the third insulating pattern INSP3. In an embodiment, the fourth metal pattern MTP4 may be disposed in the same layer as the second metal pattern MTP2 included in the stacked pattern LAP and may include the same material as that of the second metal pattern MTP2.

[0410] The fourth insulating pattern INSP4 may be disposed on the fourth metal pattern MTP4 and configured to surround the fourth metal pattern MTP4. For example, the fourth insulating pattern INSP4 may be an independent insulating pattern surrounding only the fourth metal pattern MTP4. In an embodiment, the fourth insulating pattern INSP4 may be disposed in the same layer as the second insulating pattern INSP2 included in the stack pattern LAP and may include the same material as that of the second insulating pattern INSP2. The fourth insulating pattern INSP4 included in the bank portion BNK and the second insulating pattern INSP2 included in the stack pattern LAP may each be a third insulating layer (referenced to FIG. 1 ) included in the pixel circuit portion PCL. Figure 9 In an embodiment, the fourth insulating pattern INSP4 included in the bank portion BNK and the second insulating pattern INSP2 included in the stack pattern LAP may be provided in the same layer as the third insulating layer INS3 included in the pixel circuit portion PCL, include the same material as that of the third insulating layer INS3, and may be formed by the same process as that of the third insulating layer INS3.

[0411] The fifth metal pattern MTP5 may be formed of a third conductive layer CL3 disposed and / or formed on the fourth insulating pattern INSP4. In an embodiment, the fifth metal pattern MTP5 may include a signal line extending from the first area FA of the first pixel region PXA1 and intersecting the second area SA. For example, the fifth metal pattern MTP5 may include an initialization power line IPL, a j-th data line Dj, and a first power line PL1.

[0412] The fifth insulating pattern INSP5 may be disposed on each of the fifth metal pattern MTP5 and the fourth insulating pattern INSP4 and may surround the fifth metal pattern MTP5 and the fourth insulating pattern INSP4. In an embodiment, the fifth insulating pattern INSP5 may be a component corresponding to the fourth insulating layer INS4 included in the pixel circuit portion PCL. In an embodiment, the fifth insulating pattern INSP5 included in the bank portion BNK and the fourth insulating layer INS4 included in the pixel circuit portion PCL may be disposed in the same layer, include the same material, and may be formed by the same process.

[0413] The bank BNK having the above-described configuration may have a shape protruding by a predetermined height (or thickness) from a surface (eg, upper surface) of the buffer layer BFL in an upward direction (eg, the third direction DR3 ).

[0414] In an embodiment, since the pixel circuit portion PCL and the display element portion DPL are provided on the same surface of the substrate SUB, the display device can have a slim structure with a reduced thickness compared to a conventional display device in which the display element portion DPL is provided on the pixel circuit portion PCL.

[0415] According to the aforementioned embodiment, the components included in the pixel circuit portion PCL and the components included in the display element portion DPL are formed using the same process. Therefore, the number of masks can be reduced compared to the number of masks used in a conventional display device in which the pixel circuit portion PCL and the display element portion DPL are formed using separate processes. Therefore, the process for manufacturing the display device can be simplified. When the display device manufacturing process is simplified, the production cost of the display device can also be reduced.

[0416] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, comprising: A substrate comprising: A display area including pixel areas, each of the pixel areas including a first area and a second area; and a non-display area surrounding at least one side of the display area; and pixels, arranged in the pixel area, each of the pixels including a light emitting element, Each of the pixels further comprises: a pixel circuit portion disposed in the first region, the pixel circuit portion including at least one transistor and at least one capacitor; and a display element portion provided in the second region, the display element portion including an emission region configured to emit light, a first electrode provided in the emission region, a second electrode provided in the emission region and spaced apart from the first electrode, and the light-emitting element provided between the first electrode and the second electrode, wherein each of the light emitting elements includes a first end connected to the first electrode and a second end connected to the second electrode and provided in the same layer as the first end, wherein each of the pixel circuit portion and the display element portion has a multilayer structure including one or more conductive layers and one or more insulating layers, and Here, at least one layer in the pixel circuit portion and at least one layer in the display element portion are provided in the same layer.

2. A display device comprising: A substrate comprising: A display area including pixel areas, each of the pixel areas including a first area and a second area; and a non-display area surrounding at least one side of the display area; and pixels, arranged in the pixel area, each of the pixels including a light emitting element, Each of the pixels further comprises: a pixel circuit portion disposed in the first region, the pixel circuit portion including at least one transistor and at least one capacitor; and a display element portion provided in the second region, the display element portion including an emission region configured to emit light, Each of the pixel circuit section and the display element section has a multilayer structure including one or more conductive layers and one or more insulating layers, At least one layer in the pixel circuit portion and at least one layer in the display element portion are provided in the same layer, The one or more insulating layers included in each of the pixel circuit portion and the display element portion include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially stacked on the substrate, and The one or more conductive layers included in each of the pixel circuit portion and the display element portion include: a first conductive layer, disposed on the first insulating layer; a second conductive layer disposed on the second insulating layer; and The third conductive layer is arranged on the third insulating layer.

3. The display device according to claim 2, wherein The at least one transistor comprises: an active pattern, disposed on the substrate; a gate electrode disposed on the active pattern, wherein the first insulating layer is interposed between the gate electrode and the active pattern; a first terminal coupled to a first end of the active pattern; and The second terminal is coupled to a second end of the active pattern, the second end being opposite to the first end.

4. The display device according to claim 3, wherein: The first conductive layer of the pixel circuit portion includes a scan line configured to transmit a scan signal to at least one of the pixels, a lower electrode of the at least one capacitor, and the gate electrode; The second conductive layer of the pixel circuit portion includes an upper electrode overlapping the lower electrode of the at least one capacitor; as well as The third conductive layer of the pixel circuit portion includes a data line configured to transmit a data signal to at least one of the pixels.

5. The display device according to claim 4, wherein The display element portion includes: a first electrode disposed in the emission region; a second electrode disposed in the emission region and spaced apart from the first electrode; The light emitting element is disposed between the first electrode and the second electrode; stacking patterns, respectively disposed between the substrate and the first electrode and between the substrate and the second electrode; and A contact electrode is provided on each of the first electrode and the second electrode. The display device according to claim 5 , wherein: The first electrode and the second electrode are included in the third conductive layer of the display element portion and are provided in the same layer as the data line.

7. The display device according to claim 6, wherein Each of the stacking patterns comprises: a first metal pattern, disposed on the first insulating layer; the second insulating layer is disposed on and covers the first metal pattern; a second metal pattern disposed on the second insulating layer and overlapping the first metal pattern; and The third insulating layer is disposed on and covers the second metal pattern.

8. The display device according to claim 7, wherein: Each of the stack patterns includes a structure in which the first metal pattern, the second insulating layer, the second metal pattern, and the third insulating layer are stacked in sequence; The first metal pattern is included in the first conductive layer of the display element portion; and The second metal pattern is included in the second conductive layer of the display element portion.

9. The display device according to claim 8, wherein: The first metal pattern is provided in the same layer as the lower electrode, the scan line, and the gate electrode of the at least one capacitor; as well as The second metal pattern is disposed in a same layer as the upper electrode of the at least one capacitor.

10. The display device according to claim 6, wherein: Each of the stacking patterns comprises: a first auxiliary pattern, disposed on the substrate; the first insulating layer is disposed on and covers the first auxiliary pattern; a first metal pattern, disposed on the first insulating layer; the second insulating layer is disposed on and covers the first metal pattern; a second metal pattern disposed on the second insulating layer; and the third insulating layer is disposed on and covers the second metal pattern; and The first auxiliary pattern is disposed in the same layer as the active pattern.

11. The display device according to claim 10, wherein Each of the stack patterns includes a structure in which the first auxiliary pattern, the first insulating layer, the first metal pattern, the second insulating layer, the second metal pattern, and the third insulating layer are sequentially stacked.

12. The display device according to claim 6, wherein: In the pixel circuit portion, the fourth insulating layer is provided on and covers the data line; and In the display element portion, the fourth insulating layer covers one side of each of the first electrode and the second electrode.

13. The display device according to claim 12, wherein Each of the light emitting elements is provided on the fourth insulating layer between the first electrode and the second electrode.

14. The display device according to claim 13, wherein: The display element portion further includes a fourth conductive layer provided on the third conductive layer; and The fourth conductive layer includes the contact electrode.

15. The display device according to claim 10, wherein: The display element portion further includes a bank portion provided around the emission region; and The bank includes a multi-layer structure having two or more conductive layers and two or more insulating layers.

16. The display device according to claim 15, wherein: The bank includes a first bank region and a second bank region having different stacking structures; The first bank area includes: a third metal pattern, disposed on the first insulating layer; the second insulating layer is disposed on and covers the third metal pattern; a fourth metal pattern, disposed on the second insulating layer; the third insulating layer is disposed on and covers the fourth metal pattern; and The fourth insulating layer is disposed on the third insulating layer; and The second bank area includes: the third metal pattern; the second insulating layer; the fourth metal pattern; the third insulating layer; The third conductive layer is disposed on the third insulating layer; and The fourth insulating layer is arranged on the third conductive layer.

17. The display device according to claim 16, wherein: The third metal pattern is disposed in the same layer as the first metal pattern; and The fourth metal pattern is disposed in the same layer as the second metal pattern.

18. The display device according to claim 15, wherein: The bank includes a first bank region and a second bank region having different stacking structures; The first bank area includes: a second auxiliary pattern, disposed on the substrate; the first insulating layer is disposed on and covers the second auxiliary pattern; a third metal pattern, disposed on the first insulating layer; the second insulating layer is disposed on and covers the third metal pattern; a fourth metal pattern, disposed on the second insulating layer; the third insulating layer is disposed on and covers the fourth metal pattern; and The fourth insulating layer is disposed on the third insulating layer; and The second bank area includes: the second auxiliary pattern; the first insulating layer; the third metal pattern; the second insulating layer; the fourth metal pattern; the third insulating layer; The third conductive layer is disposed on the third insulating layer; and The fourth insulating layer is arranged on the third conductive layer.

19. The display device according to claim 18, wherein: The second auxiliary pattern is provided in the same layer as the active pattern, The third metal pattern is disposed in the same layer as the first metal pattern; and The fourth metal pattern is disposed in the same layer as the second metal pattern.

20. A method of manufacturing a display device, the method comprising: forming a pixel including a pixel region including a first region and a second region, Wherein, forming the pixel comprises: forming a pixel circuit portion including at least one transistor and at least one capacitor in the first region; and A display element portion including a light emitting element is formed in the second region, wherein the display element portion includes an emission region configured to emit light, a first electrode provided in the emission region, a second electrode provided in the emission region and spaced apart from the first electrode, and the light emitting element provided between the first electrode and the second electrode, wherein each of the light emitting elements includes a first end connected to the first electrode and a second end connected to the second electrode and provided in the same layer as the first end, wherein each of the pixel circuit portion and the display element portion has a multilayer structure including one or more conductive layers and one or more insulating layers, and Here, at least one layer in the pixel circuit portion and at least one layer in the display element portion are formed by the same process.

Images