Display panel

Abstract

A display panel is disclosed. The display panel includes a substrate including a first region, a second region, and a third region; a stack structure corresponding to a plurality of display elements in the second region, the stack structure including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode; and a plurality of recesses in the third region, wherein the stack structure includes at least one organic material layer that is broken by the plurality of recesses, at least one recess of the plurality of recesses is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0073101, filed on June 19, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] One or more embodiments relate to a display panel including a first area inside a display area. BACKGROUND

[0003] Recently, the use of display devices has become more diversified. In addition, as display devices have become thinner and lighter, their range of use has gradually expanded.

[0004] As the area occupied by the display area of a display device increases, functions that can be combined or related to the display device are being added. As a way to add various functions while expanding the area, research is being conducted on display devices in which various components can be arranged in the display area.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, therefore, it can not necessarily be construed as existing technology that is already known to those skilled in the art. SUMMARY

[0006] One or more example embodiments include a display panel including a first area in which various components can be arranged inside a display area, and a display device including the same. However, it should be understood that the embodiments described herein should be considered in a descriptive sense only and not as a limitation on the disclosure.

[0007] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following disclosure or can be learned by practice of the disclosed subject matter.

[0008] According to one or more embodiments, a display panel includes a substrate including a first area, a second area, and a third area positioned between the first area and the second area, a stack structure corresponding to a plurality of display elements positioned in the second area, the stack structure including a pixel electrode, a counter electrode, and an intermediate layer positioned between the pixel electrode and the counter electrode, and a plurality of recesses positioned in the third area, wherein the stack structure includes at least one organic material layer, the at least one organic material layer is disconnected by the plurality of recesses, at least one recess of the plurality of recesses is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers.

[0009] According to some example embodiments, the first upper layer can include an inorganic material layer.

[0010] According to some example embodiments, the first upper layer can include an electrically conductive oxide layer, a metal layer, or an inorganic insulating layer.

[0011] According to some example embodiments, the first lower layer can include a first sub-lower layer including an organic insulating material, and a second sub-lower layer below the first sub-lower layer.

[0012] According to some example embodiments, the display panel can further include a transistor between the substrate and the plurality of display elements, a first organic insulating layer and a second organic insulating layer between the transistor and the pixel electrode, and a pixel definition layer on the pixel electrode.

[0013] According to some example embodiments, the first sub-lower layer can include the same material as that of the second organic insulating layer, and the second sub-lower layer can include the same material as that of the first organic insulating layer.

[0014] According to some example embodiments, the display panel can further include a second multi-layer including a second lower layer and a second upper layer, a first recess of the plurality of recesses can be defined in the second multi-layer, wherein the second lower layer can include a third sub-lower layer including the same material as that of the pixel definition layer and a fourth sub-lower layer including the same material as that of the second organic insulating layer.

[0015] According to some example embodiments, the first recess can overlap a plurality of data lines passing through the third area.

[0016] According to some example embodiments, the display panel can further include at least one inorganic insulating layer between the substrate and the first organic insulating layer, wherein the first sub-lower layer can include the same material as that of the first organic insulating layer, and the second sub-lower layer can include the same material as that of the at least one inorganic insulating layer.

[0017] According to some example embodiments, the first upper layer can include a pair of tips protruding toward a center of the at least one recess.

[0018] According to some example embodiments, the first upper layer can include a first sub-upper layer including a metal or an electrically conductive oxide, and a second sub-upper layer on the first sub-upper layer.

[0019] According to some example embodiments, a side surface of the first sub-upper layer facing a center of the at least one recess can be covered by the second sub-upper layer.

[0020] According to some example embodiments, the display panel can further include a first opening positioned in the first area and passing through the display panel.

[0021] According to some example embodiments, the display panel may further include a thin film encapsulation layer covering the stack structure and including an inorganic encapsulation layer and an organic encapsulation layer, wherein the inorganic encapsulation layer may continuously cover an inner surface of each of the plurality of grooves.

[0022] According to some example embodiments, a thickness of a first portion of the inorganic encapsulation layer positioned on the top surface of the first upper layer may be greater than a thickness of a second portion of the inorganic encapsulation layer positioned on the bottom surface of the first upper layer.

[0023] According to one or more embodiments, a display panel includes: a substrate including a first area, a display area, and an intermediate area located between the first area and the display area; a transistor arranged in the display area; a display element including a pixel electrode, an intermediate layer, and a counter electrode, the pixel electrode being electrically connected to the transistor, the intermediate layer being located on the pixel electrode, and the counter electrode being located on the intermediate layer; a first organic insulating layer being located between the transistor and the pixel electrode; a second organic insulating layer being located above the first organic insulating layer; and a plurality of grooves positioned in the intermediate area and disconnecting at least one organic material layer of the intermediate layer, each of the plurality of grooves having an undercut structure, wherein at least one of the plurality of grooves is defined in a first multilayer, the first multilayer including a first lower layer and a first upper layer, the first lower layer including a first sub-lower layer and a second sub-lower layer below the first sub-lower layer, and the first upper layer being located on the first lower layer.

[0024] According to some example embodiments, the first upper layer may include a pair of tips extending toward at least one of the plurality of grooves.

[0025] According to some example embodiments, the first sub-lower layer may include the same material as that of the second organic insulating layer, and the second sub-lower layer may include the same material as that of the first organic insulating layer.

[0026] According to some example embodiments, the first upper layer may include at least one of a conductive oxide, a metal, and an inorganic insulating material.

[0027] According to some example embodiments, a first groove adjacent to the display area among the plurality of grooves may be defined in a second multi-layer including a second lower layer and a second upper layer.

[0028] According to some example embodiments, the display panel may further include a pixel defining layer on the pixel electrode, wherein the second lower layer may include a fourth sub-lower layer and a fifth sub-lower layer, the fourth sub-lower layer includes the same material as that of the pixel defining layer, and the fifth sub-lower layer includes the same material as that of the second organic insulating layer.

[0029] According to some example embodiments, the second upper layer can include at least one of a conductive oxide, a metal, and an inorganic insulating material.

[0030] According to some example embodiments, the first recess can be superposed with the plurality of data lines passing through the middle area.

[0031] According to some example embodiments, the plurality of data lines can be alternately arranged on and under the second organic insulating layer.

[0032] According to some example embodiments, the first sub lower layer can include the same material as that of the first organic insulating layer, and the second sub lower layer can include at least one inorganic insulating layer.

[0033] According to some example embodiments, the first upper layer can include an inorganic insulating material.

[0034] According to some example embodiments, the display panel can further include a passivation layer disposed between the transistor and the pixel electrode, the passivation layer including an inorganic insulating material, wherein the first upper layer can include the same material as that of the passivation layer.

[0035] According to some example embodiments, the first upper layer can include a first sub upper layer, and a second sub upper layer on the first sub upper layer.

[0036] According to some example embodiments, the first sub upper layer can include a conductive oxide or a metal, and the second sub upper layer can include an inorganic insulating material.

[0037] According to some example embodiments, a side surface of the first sub upper layer facing a center of at least one of the plurality of recesses can be covered by the second sub upper layer.

[0038] The above and other aspects and features of certain embodiments disclosed herein will become more apparent from the following description, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other aspects and features of certain embodiments disclosed herein will become more apparent from the following description, the accompanying drawings, and the claims.

[0040] Figure 1 is a perspective view of a display device according to some example embodiments;

[0041] Figure 2 is a cross-sectional view of a display device according to some example embodiments;

[0042] Figure 3 is a cross-sectional view of a display device according to some example embodiments;

[0043] Figures 4A-4Dis a cross-sectional view of a display panel according to some example embodiments;

[0044] Figure 5 is a plan view of a display panel according to some example embodiments;

[0045] Figure 6 is an equivalent circuit representation of one of the pixels in a display panel according to some example embodiments;

[0046] Figure 7 is a plan view of a portion of a display panel according to some example embodiments;

[0047] Figure 8 is a cross-sectional view of an organic light emitting diode of one of the pixels in a display panel according to some example embodiments;

[0048] Figures 9A-9F is a cross-sectional view of one of the recesses in a display panel according to some example embodiments;

[0049] Figure 10 is a plan view of a portion of a display panel according to some example embodiments;

[0050] Figure 11 is a cross-sectional view of a display panel according to some example embodiments;

[0051] Figures 12A-12C is a cross-sectional view of a process of manufacturing a display panel according to some example embodiments;

[0052] Figure 13 is a cross-sectional view of one of the recessed areas;

[0053] Figure 14 is a cross-sectional view of a display panel according to some example embodiments;

[0054] Figure 15 is a cross-sectional view of a first area and an intermediate area in a display panel according to an embodiment;

[0055] Figure 16 is a cross-sectional view of a first area and an intermediate area in a display panel according to some example embodiments;

[0056] Figure 17 is a cross-sectional view of a display panel according to some example embodiments;

[0057] Figure 18 is a cross-sectional view of a display panel according to some example embodiments;

[0058] Figure 19 is a cross-sectional view of a display panel according to some example embodiments; and

[0059] Figure 20is a cross-sectional view of a display panel according to some example embodiments. DETAILED DESCRIPTION

[0060] Reference will now be made in detail to various aspects of some example embodiments, one or more aspects of which are illustrated in the drawings, wherein like reference numbers refer to like elements throughout. In this regard, the present example embodiments can take on a variety of different forms and should not be limited by what is described here. Accordingly, the example embodiments are described here with the understanding that the present description is an exemplification of the present teachings and is not intended to provide the only example embodiments. As such, the following description is not meant to limit the many aspects of this description to the example embodiments presented. For example, to the extent that the figures illustrate corners of the structures, these are intended to be illustrative of aspects of the example embodiments and there is no intention for the example embodiments to be limited to rectangularly shaped structures as illustrated in the figures. As such, the example embodiments can have different shapes and should not be limited by the shapes illustrated in the figures. Thus, the following description is presented for the purpose of illustrating some example embodiments and should not be construed as limiting the scope of the present teachings in any way.

[0061] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components can be present.

[0062] The size of the elements in the figures can be exaggerated for the purpose of explanation. In other words, the embodiments are not limited to the sizes of the components and the thicknesses of the layers as illustrated in the figures.

[0063] When a certain embodiment can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse sequence to the described sequence.

[0064] In this specification, "A and / or B" means A or B, or A and B.

[0065] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, the layer, region, or component can be "directly connected" to the other layer, region, or component, and / or can be "indirectly connected" to the other layer, region, or component, with other layers, regions, or components in between them. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, the layer, region, or component can be "directly electrically connected" to the other layer, region, or component, and / or can be "indirectly electrically connected" to the other layer, region, or component, with other layers, regions, or components in between them.

[0066] Figure 1 is a perspective view of a display device 1 according to some example embodiments.

[0067] Referring to Figure 1 , the display device 1 includes a first area OA and a display area DA, which is a second area at least partially surrounding the first area OA. The display device 1 can provide an image (e.g., a set or predetermined image) by using light emitted from a plurality of pixels arranged (e.g., positioned or placed) in the display area DA. The first area OA can be completely surrounded by the display area DA. The first area OA can be an area in which components described below with reference to Figure 2 are arranged or positioned.

[0068] The middle area MA as a third area can be arranged (e.g., positioned) between the first area OA and the display area DA as a second area. The display area DA can be surrounded by a peripheral area PA as a fourth area. According to some example embodiments, the middle area MA and the peripheral area PA can be non-display areas in which no pixels are placed. The middle area MA can be completely surrounded by the display area DA, and the display area DA can be completely surrounded by the peripheral area PA.

[0069] Hereinafter, although an organic light emitting display device is described as an example of the display device 1 according to some example embodiments, the display device is not limited thereto. According to some example embodiments, the display device 1 can be a display device such as an inorganic light emitting display and a quantum dot light emitting display.

[0070] Although it is shown in Figure 1 that one first area OA is provided and has a circular shape, embodiments are not limited thereto. The number of first areas OA can be two or more. Each of the first areas OA can have various shapes such as a circular shape, an elliptical shape, a polygonal shape, a star shape, and a diamond shape.

[0071] Figure 2 and Figure 3 are cross-sectional views of the display device 1 according to some example embodiments taken along line II-II' of Figure 1 .

[0072] Referring to Figure 2 , the display device 1 can include a display panel 10, an input sensing layer 40, and an optical functional layer 50 placed on the display panel 10. The display panel 10, the input sensing layer 40, and the optical functional layer 50 can be covered by a window 60. The display device 1 can be various electronic devices such as a mobile phone, a notebook computer, and a smart watch.

[0073] The display panel 10 can display an image. The display panel 10 includes pixels positioned in a display area DA. Each pixel can include a display element and a pixel circuit connected to the display element. The display element can be an organic light emitting diode or a quantum dot organic light emitting diode.

[0074] The input sensing layer 40 acquires coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 can include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 can be positioned on the display panel 10. The input sensing layer 40 can sense an external input by using a mutual capacitance method and / or a self-capacitance method.

[0075] In some embodiments, the input sensing layer 40 can be positioned directly on the display panel 10, or separately formed and then bonded to the display panel 10 by using an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 can be continuously formed after a process of forming the display panel 10. In this case, the input sensing layer 40 can be a part of the display panel 10, and an adhesive layer can not be placed between the input sensing layer 40 and the display panel 10. Although the input sensing layer 40 is shown as being positioned between the display panel 10 and the optical functional layer 50 in Figure 2 In some other embodiments, the input sensing layer 40 can be positioned on the optical functional layer 50.

[0076] The optical functional layer 50 can include an anti-reflection layer. The anti-reflection layer can reduce a reflectance of light (e.g., external light) incident / impinging on the display panel 10 from the outside through the window 60. The anti-reflection layer can include a retarder and a polarizer. The retarder can include a film type retarder or a liquid crystal type retarder. The retarder can include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer can include a film type polarizer or a liquid crystal type polarizer. The film type polarizer can include a stretchable synthetic resin film, and the liquid crystal type polarizer can include liquid crystals placed in a set or predetermined arrangement. Each of the retarder and the polarizer can further include a protective film. The retarder and the polarizer themselves or the protective film can be defined as a base layer of the anti-reflection layer.

[0077] In some other embodiments, the anti-reflection layer can include a black matrix and a color filter. The color filter can be placed by considering colors of light respectively emitted from the pixels of the display panel 10. In some other embodiments, the anti-reflection layer can include a destructive interference structure. The destructive interference structure can include a first reflection layer and a second reflection layer respectively placed on different layers. First reflected light and second reflected light respectively reflected by the first reflection layer and the second reflection layer can generate destructive interference, and thus can reduce a reflectance of external light.

[0078] The optical function layer 50 may further include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens or a convex lens shape and / or may include multiple layers having different refractive indices. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or may include only one of these layers.

[0079] In an embodiment, the optical function layer 50 may be formed continuously after the process of forming the display panel 10 and / or the input sensing layer 40. In this case, an adhesive layer may not be placed between the optical function layer 50 and the display panel 10 and / or the input sensing layer 40.

[0080] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may include an opening. Figure 2 , the display panel 10, the input sensing layer 40, and the optical function layer 50 include a first opening 10H, a second opening 40H, and a third opening 50H, respectively, and the first opening 10H, the second opening 40H, and the third opening 50H overlap each other. The first opening 10H, the second opening 40H, and the third opening 50H may correspond to the first area OA. In some other embodiments, at least one of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. For example, one or two of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. Optionally, as Figure 3 As shown in , the display panel 10 , the input sensing layer 40 , and the optical function layer 50 may not include openings.

[0081] As described above, the first area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) in which the component 20 is located, and the component 20 may add various functions to the display device 1. Figure 2 As shown in FIG, the assembly 20 may be positioned within the first to third openings 10H, 40H, and 50H. Figure 3 As shown in , the assembly 20 may be positioned below the display panel 10 .

[0082] The component 20 may include an electronic component. For example, the component 20 may include an electronic component that uses light or sound. For example, the electronic component may be a sensor such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize a fingerprint, a small lamp that outputs light, or a speaker that outputs sound. The electronic component that uses light may use light in various wavelength bands such as visible light, infrared light, and ultraviolet light. In an embodiment, the first area OA may be a transmissive area through which light and / or sound output from the component 20 to the outside or propagated from the outside toward the electronic component can pass.

[0083] In a case where the display device 1 is used as a smart watch or as an instrument panel for a car, the component 20 can be a member such as a clock hand or a hand indicating set or scheduled information (e.g., a speed of a vehicle, etc.). In a case where the display device 1 includes a clock hand or an instrument panel for a car, the component 20 can pass through the window 60 and can be exposed to the outside. In such a case, the window 60 can include an opening corresponding to the first area OA.

[0084] As described above, the component 20 can include an element related to a function of the display panel 10, or can include an element such as an ornament that increases the aesthetic of the display panel 10. Although not shown in Figure 2 and Figure 3 , a layer including an optically transparent adhesive can be positioned between the window 60 and the optical functional layer 50.

[0085] Figures 4A-4D is a cross-sectional view of the display panel 10 according to an embodiment.

[0086] Referring to Figure 4A , the display panel 10 includes a display layer 200 positioned on a substrate 100. The substrate 100 can include a glass material or a polymer resin. The substrate 100 can include multiple layers. For example, as shown in a magnified view of Figure 4A , the substrate 100 can include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104.

[0087] The first base layer 101 and the second base layer 103 can each include a polymer resin. For example, the first base layer 101 and the second base layer 103 can include a polymer resin including polyether sulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). The polymer resin can be transparent.

[0088] The first barrier layer 102 and the second barrier layer 104 are barrier layers that reduce or prevent penetration of external foreign matter, and can include a single layer or multiple layers of an inorganic material including, for example, silicon nitride (SiN x ) and silicon oxide (SiO x ).

[0089] The display layer 200 can include a plurality of pixels. The display layer 200 can include a display element layer 200A including a display element for each pixel and a pixel circuit layer 200B including a pixel circuit and an insulating layer for each pixel. The display element layer 200A can include a pixel electrode, a counter electrode, and a stacked structure therebetween. Each display element can be an organic light emitting diode (OLED). Each pixel circuit (e.g., 200B) can include a thin film transistor and a storage capacitor.

[0090] The display element of the display layer 200 can be covered by an encapsulation member such as a thin film encapsulation layer 300. The thin film encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In a case where the display panel 10 includes the substrate 100 and the thin film encapsulation layer 300, the substrate 100 includes a polymer resin, and the thin film encapsulation layer 300 includes an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display panel 10 can be improved.

[0091] The display panel 10 can include a first opening 10H passing through the display panel 10. The first opening 10H can be positioned in the first area OA. In this case, the first area OA can be an opening area. In a case where the first area OA is an opening area, the display panel 10 can include a display element layer 200A positioned in the first area OA. Figure 4A The substrate 100 and the thin film encapsulation layer 300 are shown to each include a via 100H and 300H, respectively, which each correspond to the first opening 10H of the display panel 10. The display layer 200 can include a via 200H which corresponds to the first area OA.

[0092] In some other embodiments, as shown in Figure 4B The substrate 100 can not include a via 100H which corresponds to the first area OA, as shown in Figure 4C The display layer 200 can not include a via 200H which corresponds to the first area OA, as shown in

[0093] Although the display element layer 200A is shown to be positioned in the first area OA in Figures 4A-4C some other embodiments, as shown in Figure 4D The auxiliary display element layer 200C can be positioned in the first area OA. The auxiliary display element layer 200C can include a display element having a structure different from that of the display element of the display element layer 200A and / or operating in a manner different from that of the display element of the display element layer 200A.

[0094] In an embodiment, each pixel in the display element layer 200A can include an active organic light emitting diode, and the auxiliary display element layer 200C can include pixels each including a passive organic light emitting diode. In a case where the auxiliary display element layer 200C includes a passive organic light emitting diode as a display element, there is no element constituting a pixel circuit below the passive organic light emitting diode. For example, a portion of the pixel circuit layer 200B below the auxiliary display element layer 200C does not include a transistor and a storage capacitor.

[0095] In some other embodiments, although the auxiliary display element layer 200C can include display elements of the same type as the display elements of the display element layer 200A (e.g., active organic light emitting diodes), the structure of the pixel circuit thereunder can be different. For example, the pixel circuit below the auxiliary display element layer 200C (e.g., a pixel circuit including a light-blocking layer between the substrate and the transistor) can have a structure different from that of the pixel circuit below the display element layer 200A. The display elements of the auxiliary display element layer 200C can be operated in accordance with control signals different from the control signals of the display elements of the display element layer 200A, optionally. A component (e.g., an infrared sensor) not required to have relatively high transmittance can be positioned in the first region OA in which the auxiliary display element layer 200C is positioned. In this case, the first region OA can be a component region and an auxiliary display region.

[0096] Figure 5 is a plan view of a display panel 10 according to an embodiment, Figure 6 is an equivalent circuit representation of one of the pixels P in the display panel 10 according to an embodiment.

[0097] Referring to Figure 5 The display panel 10 can include a first region OA, a display region DA as a second region, an intermediate region MA as a third region, and a peripheral region PA as a fourth region. Figure 5 A substrate 100 of the display panel 10 is illustrated. For example, the substrate 100 can include the first region OA, the display region DA, the intermediate region MA, and the peripheral region PA.

[0098] The display panel 10 includes a plurality of pixels P placed in the display region DA. As Figure 6 illustrated in FIG. 1A, each pixel P can include a pixel circuit PC and an organic light emitting diode OLED as a display element, the display element being connected to the pixel circuit PC. The pixel circuit PC can include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P can emit, for example, red light, green light, blue light, or white light from the organic light emitting diode OLED.

[0099] The second thin-film transistor T2 can include a switching thin-film transistor, can be connected to a scan line SL and a data line DL, and can transmit a data voltage input to the data line DL to the first thin-film transistor T1 based on a switching voltage input to the scan line SL. The storage capacitor Cst can be connected to the second thin-film transistor T2 and a driving voltage line PL, and can store a voltage corresponding to a difference between a voltage transmitted from the second thin-film transistor T2 and a first power voltage ELVDD supplied through the driving voltage line PL.

[0100] The first thin-film transistor T1 is a driving thin-film transistor, can be connected to a driving voltage line PL and a storage capacitor Cst, and can control a driving current flowing through the organic light emitting diode OLED from the driving voltage line PL in response to a voltage value (or a charge) stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light having a set or predetermined brightness according to the driving current. A counter electrode (for example, a cathode) of the organic light emitting diode OLED can receive a second power voltage ELVSS.

[0101] Although the pixel circuit PC is shown to include two thin-film transistors and one storage capacitor in Figure 6 , the present disclosure is not limited thereto. The number of thin-film transistors and the number of storage capacitors can be variously modified according to the design of the pixel circuit PC. For example, the pixel circuit PC can include four or more thin-film transistors in addition to two thin-film transistors.

[0102] Referring again to Figure 5 , the middle area MA can surround the first area OA in a plan view. The middle area MA is an area in which a display element such as the organic light emitting diode OLED emitting light is not placed. A signal line can pass through the middle area MA, the signal line providing a signal to the pixels P positioned around the first area OA. The scan driver 1100 providing a scan signal to each of the pixels P, the data driver 1200 providing a data signal to each of the pixels P, and a main power line (not shown) providing a first power voltage ELVDD and a second power voltage ELVSS can be placed in the peripheral area PA. Although the data driver 1200 is shown to be adjacent to one side of the substrate 100 in Figure 5 , in some other embodiments, the data driver 1200 can be positioned on a flexible printed circuit board (FPCB) electrically connected to pads (also referred to as "bonding pads") positioned on one side of the display panel 10.

[0103] Figure 7 is a plan view of a portion of the display panel 10 according to an embodiment, Figure 8is a cross-sectional view of an organic light emitting diode OLED of one of the pixels P in the display panel 10 according to an embodiment. For ease of description, in Figure 8 In the display panel 10 according to an embodiment, the thin film encapsulation layer 300 as the encapsulation member is omitted.

[0104] Referring to Figure 7 , the pixels P are placed around the first area OA in the display area DA. The first area OA can be defined between (e.g., among) the pixels P. For example, the pixels P can be placed vertically around the first area OA in a plan view, and the pixels P can be placed horizontally around the first area OA in a plan view.

[0105] As shown in Figure 8 , each of the pixels P can include an organic light emitting diode OLED. The organic light emitting diode OLED can include a pixel electrode 221, a counter electrode 223 facing the pixel electrode 221, and an intermediate layer 222 between the pixel electrode 221 and the counter electrode 223.

[0106] The pixel electrode 221 is positioned on the planarization layer PNL. The pixel electrode 221 can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some other embodiments, the pixel electrode 221 can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. In some other embodiments, the pixel electrode 221 can further include a layer including ITO, IZO, ZnO, or In2O3 on / beneath the reflective layer.

[0107] A pixel definition layer PDL can be positioned on the pixel electrode 221. The pixel definition layer PDL can include an opening that can expose a top surface of the pixel electrode 221 and cover edges of the pixel electrode 221. The pixel definition layer PDL can include an organic insulating material. Optionally, the pixel definition layer PDL can include an organic insulating material and an inorganic insulating material.

[0108] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 can include a first functional layer 222a under the emission layer 222b and / or a second functional layer 222c on the emission layer 222b. The emission layer 222b can include a polymer material or a low molecular weight organic material that emits light of a set or predetermined color.

[0109] The first functional layer 222a can include a single layer or multiple layers. For example, in a case where the first functional layer 222a includes a polymer material, the first functional layer 222a can be a hole transport layer (HTL) having a single layer structure. The first functional layer 222a can include poly-(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). In a case where the first functional layer 222a includes a low molecular weight organic material, the first functional layer 222a can include a hole injection layer (HIL) and a hole transport layer (HTL).

[0110] In some embodiments, the second functional layer 222c can be optional. For example, in a case where the first functional layer 222a and the emission layer 222b include a polymer material, the second functional layer 222c can be formed. The second functional layer 222c can include a single layer or multiple layers. The second functional layer 222c can include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0111] The emission layer 222b of the intermediate layer 222 can be placed for each pixel P. For example, the emission layer 222b can be patterned to correspond to the pixel electrode 221. Unlike the emission layer 222b, each of the first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 can be formed in one body to correspond to a plurality of pixels P.

[0112] The counter electrode 223 can include a conductive material having a low work function. For example, the counter electrode 223 can include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Optionally, the counter electrode 223 can further include a layer including ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the above-described material. The counter electrode 223 can be positioned not only in the display area DA but also in the intermediate area MA. The first functional layer 222a, the second functional layer 222c, and the counter electrode 223 can be formed by thermal deposition.

[0113] The cap layer 230 can be positioned on the counter electrode 223. For example, the cap layer 230 can include LiF and can be formed by thermal deposition. In an embodiment, the cap layer 230 can be omitted.

[0114] A layer including an organic material provided into the layers of the display panel 10 can provide a path through which moisture can travel. The first functional layer 222a and / or the second functional layer 222c included in the stack structure of the organic light emitting diode OLED include an organic material, and thus the first functional layer 222a and / or the second functional layer 222c can provide a path through which moisture can travel. However, because the first functional layer 222a and / or the second functional layer 222c are disposed in the intermediate area MA through the groove G (as described above with reference to FIG. 2), the first functional layer 222a and / or the second functional layer 222c can not provide a path through which moisture can travel.Figure 7 The one or more grooves G can be positioned in the middle area MA as shown in FIG. 1B, so the above moisture transmission problem and damage to the organic light emitting diode OLED can be prevented or reduced.

[0115] As shown in FIG. 1B, the one or more grooves G can be positioned in the middle area MA. As shown in FIG. 1C, the grooves G can have a ring shape around the first area OA in a plan view, and can be separated from each other. Figure 7 Figure 7 As shown in FIG. 1C, the grooves G can have a ring shape around the first area OA in a plan view, and can be separated from each other.

[0116] The grooves G can be positioned in a multi-layer including a plurality of layers, and the grooves G recessed in a depth direction of the multi-layer can have an undercut structure. The structure of the multi-layer and the grooves G will be described below with reference to FIGS. 2A to 2C. Figures 9A-9F

[0117] Figures 9A-9F is a cross-sectional view of one of the grooves G in the display panel 10 according to an embodiment. For ease of description, the thin film encapsulation layer 300 as an encapsulation member is omitted. Figures 9A-9F

[0118] Referring to FIG. 3A, the multi-layer ML includes an upper layer UL and a lower layer LL. The lower layer LL and / or the upper layer UL include a plurality of sub-layers. Figures 9A-9F Referring to FIG. 3B, the multi-layer ML includes a lower layer LL and an upper layer UL. The lower layer LL can include a first sub-lower layer LL1 and a second sub-lower layer LL2 under the first sub-lower layer LL1. The upper layer UL can include a single layer.

[0119] Figure 9A Figure 9B Referring to FIG. 3B, the multi-layer ML includes a lower layer LL and an upper layer UL. The lower layer LL can include a first sub-lower layer LL1 and a second sub-lower layer LL2 under the first sub-lower layer LL1. The upper layer UL can include a single layer.

[0120] The lower layer LL and the upper layer UL can include different materials. For example, the first sub-lower layer LL1 and the second sub-lower layer LL2 can include an organic material, for example, an organic insulating material. The upper layer UL can include an inorganic material.

[0121] The organic insulating material of the lower layer LL can include an organic insulating material including a general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof.

[0122] The inorganic material of the upper layer UL can include a material different from the organic material including a carbon element, the material including a conductive oxide such as IZO, ITO, ZnO, In2O3, IGO, and / or AZO. Alternatively, the inorganic material of the upper layer UL can include a metal such as Mo, Al, Cu, and / or Ti. Alternatively, the inorganic material of the upper layer UL can include an insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride.​​​​​

[0123] The recess G can be positioned in a depth direction of the multi-layer ML. The recess G can include a top hole UL-h through the upper layer UL and a bottom hole or a bottom recess positioned in the lower layer LL. In embodiments, as shown in Figure 9A , the recess G can include a top hole UL-h of the upper layer UL, a first bottom hole LL1-h of the first sub-lower layer LL1, and a second recess LL2-r of the second sub-lower layer LL2. Alternatively, as shown in Figure 9B , the recess G can include a top hole UL-h of the upper layer UL, a first bottom hole LL1-h of the first sub-lower layer LL1, and a second bottom hole LL2-h of the second sub-lower layer LL2. The depth d of the recess G can be less than the thickness t of the lower layer LL, and a bottom surface of the recess G can be positioned between a top surface and a bottom surface of the second sub-lower layer LL2 (see Figure 9A ). Alternatively, the depth d of the recess G can be equal to the thickness t of the lower layer LL, and a bottom surface of the recess G can be positioned on the same surface as a bottom surface of the second sub-lower layer LL2 (see Figure 9B ).

[0124] The recess G can have an undercut structure. Referring to Figure 9A and Figure 9B , a first width W1 of the top hole UL-h can be less than a width of the lower layer LL (e.g., a second width W2 of the first bottom hole LL1-h of the first sub-lower layer LL1). An end portion of the upper layer UL protruding toward the recess G (e.g., a center of the recess G) can constitute a pair of tips PT. A protruding length d1 of each tip PT can be less than the depth d of the recess G. The protruding length d1 of the tip PT can be less than 2 µm. For example, the protruding length d1 of the tip PT can be about 1 µm to about 1.5 µm. The depth d of the recess G can be 2 µm or more, 2.5 µm or more, 3 µm or more, or 3.5 µm or more.

[0125] The organic material layers included in the stack structure of the organic light emitting diode OLED (see Figure 8 ) described with reference to Figure 7 and Figure 8 may be disconnected or separated by the recess G. For example, as shown in Figure 9A and Figure 9B , the first functional layer 222a and the second functional layer 222c can be disconnected or separated around the recess G. Likewise, the counter electrode 223 and the cap layer 230 can be disconnected or separated around the recess G. Although the following Figure 9A , Figure 9B and Figures 9C-19 are discussed below, the following discussion can apply to the stack structure of the organic light emitting diode OLED (see Figure 8 ) described with reference to Figure 7 and Figure 8 .The first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 are shown as being broken or separated around the groove G in FIG. 12, but embodiments are not limited thereto. As described above, the second functional layer 222c and / or the cap layer 230 can be omitted. In this case, the second functional layer 222c and / or the cap layer 230 are not present around the groove G.

[0126] As described with reference to Figure 9A and Figure 9B , the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 can be broken or separated by the groove G, and the multi-layer ML in which the groove G is positioned can have not only the structure shown in Figure 9A and Figure 9B , but also various structures described with reference to Figures 9C-9F .

[0127] With reference to Figure 9C , the groove G is positioned in the multi-layer ML. The lower layer LL' of the multi-layer ML can include a first sub-lower layer LL1, a second sub-lower layer LL2 below the first sub-lower layer LL1, and a third sub-lower layer LL3 below the second sub-lower layer LL2.

[0128] Two or three of the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3 can include different materials. For example, the first sub-lower layer LL1 can include an organic insulating material, and the second sub-lower layer LL2 and the third sub-lower layer LL3 can include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride.

[0129] Although the lower layer LL' is shown as including two layers of inorganic insulating material (e.g., the second sub-lower layer LL2 and the third sub-lower layer LL3) in Figure 9C , embodiments are not limited thereto. In some other embodiments, the lower layer LL' includes the first sub-lower layer LL1 and one or three or more sub-layers placed below the first sub-lower layer LL1 and including an inorganic insulating material.

[0130] As described with reference to Figure 9A , the upper layer UL can include a single layer or multiple layers and include an inorganic material. The upper layer UL can include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Alternatively, the upper layer UL can include a conductive oxide such as IZO, or can include a metal such as Mo, Ti, and Cu.

[0131] The groove G can have an undercut shape. The protruding length d1 of the pair of tips PT protruding toward the center of the groove G, the depth d of the groove G, and the characteristics in which the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 are broken around the groove G are the same as those described with reference to Figure 9A andFigure 9B The same as described above. Although the bottom surface of the groove G is positioned between the top surface and the bottom surface of the third sub-lower layer LL3 in Figure 9C , in some other embodiments, the bottom surface of the groove G can be positioned on the same surface as the bottom surface of the third sub-lower layer LL3.

[0132] Referring to Figure 9D , the groove G is positioned in the multi-layer ML, and as described with reference to Figure 9C , the lower layers LL' of the multi-layer ML can include the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3. In some other embodiments, Figure 9D , the lower layers LL' can have the structure of the lower layers LL described with reference to Figure 9A and Figure 9B .

[0133] The upper layers UL' of the multi-layer ML can include the first sub-upper layer UL1 and the second sub-upper layer UL2 on the first sub-upper layer UL1. The upper layers UL' can include an inorganic material, and the first sub-upper layer UL1 and the second sub-upper layer UL2 can have different materials. For example, the first sub-upper layer UL1 can include a conductive oxide such as IZO, or can include a metal such as Al, Mo, and Ti. The second sub-upper layer UL2 can include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride.

[0134] The side surface UL1-S of the first sub-upper layer UL1 facing the groove G can be covered by the second sub-upper layer UL2. The side surface UL1-S of the first sub-upper layer UL1 can be next to the side surface UL2-S of the second sub-upper layer UL2. In an embodiment, in the case where the first sub-upper layer UL1 includes three layers of titanium, aluminum, and titanium, the aluminum is damaged much more than the titanium during a process of manufacturing the display panel, and thus an unevenness can be formed in the side surface UL1-S of the first sub-upper layer UL1. In contrast, according to the embodiment, because the side surface UL1-S of the first sub-upper layer UL1 is covered by the second sub-upper layer UL2, the side surface UL1-S of the first sub-upper layer UL1 can be protected from damage or prevented from being damaged.

[0135] The first sub-upper layer UL1 and the second sub-upper layer UL2 can further extend to the center of the groove G than the side surface of the lower layers LL, thereby defining a pair of tips PT. The protruding length d1 of each tip PT and the depth d of the groove G are the same as those described above.

[0136] Although the bottom surface of the groove G is positioned between the top surface and the bottom surface of the third sub-lower layer LL3 in Figure 9D , embodiments are not limited thereto. In some other embodiments, similar to Figure 9BAs described, the bottom surface of the groove G may be positioned on the same surface as the bottom surface of the third sub-lower layer LL3 .

[0137] Reference Figure 9E , the upper layer UL' of multi-layer ML and the reference Figure 9D The upper layer UL' described is the same as Figure 9E Multi-layer ML with Figure 9D The multi-layer ML is different in that the lower layer LL″ is a single layer. The lower layer LL″ may include an organic insulating material. The depth d of the groove G may be equal to or less than the thickness of the lower layer LL″.

[0138] Despite Figure 9E FIG3 shows that the bottom surface of the groove G is between the top surface and the bottom surface of the lower layer LL", but in some other embodiments, the bottom surface of the groove G may be positioned on the same surface as the bottom surface of the lower layer LL".

[0139] Reference Figure 9F , the lower layer LL of the multi-layer ML may include the above Figure 9A and Figure 9B In some other embodiments, the lower layer LL may include the first lower layer LL1 and the second lower layer LL2 as shown in FIG. Figures 9C-9E The structures of the lower layers LL' and LL" are described to be identical.

[0140] The upper layer UL″ of the multi-layer ML may include a plurality of layers. For example, the upper layer UL″ may include a first sub-upper layer UL1, a second sub-upper layer UL2 on the first sub-upper layer UL1, and a third sub-upper layer UL3 on the second sub-upper layer UL2. Two or more of the first sub-upper layer UL1, the second sub-upper layer UL2, and the third sub-upper layer UL3 may include different materials.

[0141] For example, the first upper sub-layer UL1 and the third upper sub-layer UL3 may include a conductive oxide such as IZO or a metal, and the second upper sub-layer UL2 may include an insulating material such as silicon nitride. Alternatively, the first upper sub-layer UL1 and the third upper sub-layer UL3 may include an insulating material such as silicon nitride, and the second upper sub-layer UL2 may include a conductive oxide such as IZO or a metal.

[0142] Despite Figure 9F , it is shown that the upper layer UL″ includes three sublayers, but the embodiment is not limited thereto. The upper layer UL″ may include two sublayers including a first upper sublayer UL1 and a second upper sublayer UL2. Alternatively, the upper layer UL″ may include four or more sublayers.

[0143] The first, second, and third sub-uper-layers UL1, UL2, and UL3 extend further toward the center of the groove G than the sides of the lower layer LL, thereby defining a pair of tips PT. The protruding length d1 of each tip PT and the depth d of the groove G are the same as those described above.

[0144] Although the bottom surface of the groove G is shown as being positioned between the top and bottom surfaces of the second sub-lower layer LL2 in Figure 9F , embodiments are not limited thereto. In some other embodiments, the bottom surface of the groove G can be positioned on the same surface as the bottom surface of the second sub-lower layer LL2, as described with reference to Figure 9B

[0145] Figure 10 is a plan view of a portion of a display panel 10 according to an embodiment.

[0146] Referring to Figure 10 , the intermediate area MA is positioned between the first area OA and the display area DA, and a plurality of grooves G are positioned in the intermediate area MA. Although Figure 10 three grooves G are shown, the number of grooves G can be four or more.

[0147] A line can run around the edge of the first area OA in the intermediate area MA. A signal line connected to pixels P that are separated from each other around the first area OA can extend along the edge of the first area OA in the intermediate area MA.

[0148] In the plan view of Figure 10 , at least one data line DL passing through the display area DA can extend in the y-direction to provide a data signal to pixels P positioned vertically around the first area OA, and extend along the edge of the first area OA in the intermediate area MA. Similarly, at least one of the scan lines SL passing through the display area DA can extend in the x-direction to provide a scan signal to pixels P positioned horizontally around the first area OA, and extend along the edge of the first area OA in the intermediate area MA.

[0149] ​The detour (or bypass) portion SL-D of the scan line SL can be positioned on the same layer as a layer on which the extension portion SL-L that crosses (e.g., intersects) the display area DA is positioned, and can be formed integrally. The detour portion DL-D1 of at least one of the data lines DL (hereinafter, referred to as a first data line DL1) can be positioned on a layer different from a layer on which the extension portion DL-L1 that crosses the display area DA is positioned, and the detour portion DL-D1 of the first data line DL1 can be connected to the extension portion DL-L1 through a contact hole CNT. The detour portion DL-D2 of at least one of the data lines DL (hereinafter, referred to as a second data line DL2) can be positioned on the same layer as a layer on which the extension portion DL-L2 is positioned, and can be formed integrally.

[0150] Figure 11 is a cross-sectional view of a display panel 10-1 according to an embodiment, Figures 12A-12C is a cross-sectional view of a process of manufacturing a display panel 10-1 according to some example embodiments and shows an intermediate area MA, Figure 13 is a cross-sectional view of one of the groove areas G (G1). Figure 11 may correspond to a cross-section taken along a line X-X' of Figure 10 .

[0151] Referring to Figure 11 , the intermediate area MA is located between the first area OA and the display area DA, and a pixel circuit PC and an organic light emitting diode OLED corresponding to each pixel P (see Figure 10 ) are positioned in the display area DA.

[0152] First, referring to the display area DA of Figure 11 , the substrate 100 can include a glass material or a polymer resin. In an embodiment, as shown in the enlarged view of Figure 4A , the substrate 100 can include a plurality of sub-layers.

[0153] A buffer layer 201 can be located on the substrate 100. The buffer layer 201 can reduce or prevent impurities from penetrating into a semiconductor layer Act of a thin film transistor TFT. The buffer layer 201 can include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride, and can also include a single layer or a plurality of layers including the above inorganic insulating material.

[0154] A pixel circuit PC can be located on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT can include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. A data line DL of the pixel circuit PC can be electrically connected to a switching thin film transistor (not shown) included in the pixel circuit PC. Although the present embodiment illustrates a top gate type thin film transistor TFT in which the gate electrode GE is placed on the semiconductor layer Act with the gate insulating layer 203 therebetween, in embodiments, the thin film transistor TFT can be a bottom gate type thin film transistor TFT.

[0155] The semiconductor layer Act can include polysilicon. Alternatively, the semiconductor layer Act can include amorphous silicon, oxide semiconductor, or organic semiconductor. The gate electrode GE can include a low-resistance metal material. The gate electrode GE can include a conductive material including Mo, Al, Cu, and Ti, and can include a single layer or multiple layers including the above materials.

[0156] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE can include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 can include a single layer or multiple layers including the above materials.

[0157] The source electrode SE and the drain electrode DE can be positioned on the same layer as the layer on which the data line DL is placed, and can include the same material as the material of the data line DL. The source electrode SE, the drain electrode DE, and the data line DL can include a material having relatively high (e.g., excellent) conductivity. The source electrode SE and the drain electrode DE can include a conductive material including Mo, Al, Cu, and Ti, and can include a single layer or multiple layers including the above materials. In embodiments, the source electrode SE, the drain electrode DE, and the data line DL can each include multiple layers of Ti / Al / Ti.

[0158] The storage capacitor Cst can include a bottom electrode CE1 and a top electrode CE2, the bottom electrode CE1 being superposed with the top electrode CE2, and a first interlayer insulating layer 205 being located between the bottom electrode CE1 and the top electrode CE2. The storage capacitor Cst can be superposed with the thin film transistor TFT. In this regard, the gate electrode GE of the thin film transistor TFT is shown in Figure 11 In some other embodiments, the storage capacitor Cst can not be superposed with the thin film transistor TFT. The storage capacitor Cst can be covered by a second interlayer insulating layer 207. The top electrode CE2 of the storage capacitor Cst can include a conductive material including Mo, Al, Cu, and Ti, and can include a single layer or multiple layers including the above materials.

[0159] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 can include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 can include a single layer or multiple layers including the above materials.

[0160] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst can be covered by the first organic insulating layer 209. The first organic insulating layer 209 can include an approximately planar top surface.

[0161] The pixel circuit PC can be electrically connected to the pixel electrode 221. For example, as shown in FIG. 2B, a contact metal layer CM can be placed between the thin film transistor TFT and the pixel electrode 221. The contact metal layer CM can be connected to the thin film transistor TFT through a contact hole in the first organic insulating layer 209, and the pixel electrode 221 can be connected to the contact metal layer CM through a contact hole in the second organic insulating layer 211 on the contact metal layer CM. The contact metal layer CM can include a conductive material including Mo, Al, Cu, and Ti, and can include a single layer or multiple layers including the above materials. In an embodiment, the contact metal layer CM can include three layers of Ti / Al / Ti. Figure 11 The first organic insulating layer 209 and the second organic insulating layer 211 can include an organic insulating material including a general-purpose polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof. In an embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 can include polyimide.

[0162] The pixel electrode 221 can be located on the second organic insulating layer 211. The second organic insulating layer 211 can be a planarization layer PNL described above with reference to FIG. 2A. An edge of the pixel electrode 221 can be covered by a pixel definition layer 215. The pixel definition layer 215 can include an opening that overlaps a central portion of the pixel electrode 221. A spacer 217 can be positioned on the pixel definition layer 215. The spacer 217 can include a material different from that of the pixel definition layer 215, or can include the same material as that of the pixel definition layer 215. In an embodiment, the pixel definition layer 215 and the spacer 217 can include the same material and can be formed simultaneously during a mask process using a half-tone mask. In an embodiment, the pixel definition layer 215 and the spacer 217 can include polyimide.

[0163] Figure 8 The pixel electrode 221 can be located on the second organic insulating layer 211. The second organic insulating layer 211 can be a planarization layer PNL described above with reference to FIG. 2A. An edge of the pixel electrode 221 can be covered by a pixel definition layer 215. The pixel definition layer 215 can include an opening that overlaps a central portion of the pixel electrode 221. A spacer 217 can be positioned on the pixel definition layer 215. The spacer 217 can include a material different from that of the pixel definition layer 215, or can include the same material as that of the pixel definition layer 215. In an embodiment, the pixel definition layer 215 and the spacer 217 can include the same material and can be formed simultaneously during a mask process using a half-tone mask. In an embodiment, the pixel definition layer 215 and the spacer 217 can include polyimide.

[0164] ​The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 can further include a first functional layer 222a below the emission layer 222b and / or a second functional layer 222c above the emission layer 222b. The emission layer 222b can include a polymer material or a low molecular weight organic material that emits light having a set or predetermined color. The counter electrode 223 can be positioned on the intermediate layer 222, and the cover layer 230 can be positioned on the counter electrode 223. The cover layer 230 can be omitted.

[0165] The materials, structures, and characteristics of the pixel electrode 221, the intermediate layer 222, and the counter electrode 223 are the same as those described with reference to Figure 8

[0166] The organic light emitting diode OLED is covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 can include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 11 As shown in the middle, the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. In some other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be modified.

[0167] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include one or more inorganic materials selected from among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon nitride, silicon oxide, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include a single layer or multiple layers of the above-mentioned materials. The organic encapsulation layer 320 can include a polymer-based material. The polymer-based material can include an acrylic resin, an epoxy resin, a polyimide, and a polyethylene. In an embodiment, the organic encapsulation layer 320 can include an acrylate.

[0168] The thickness of the first inorganic encapsulation layer 310 can be different from the thickness of the second inorganic encapsulation layer 330. The thickness of the first inorganic encapsulation layer 310 can be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 can be greater than the thickness of the first inorganic encapsulation layer 310, or the thickness of the first inorganic encapsulation layer 310 can be the same as the thickness of the second inorganic encapsulation layer 330.

[0169] Referring to Figure 11 The middle area MA can include a first sub-middle area SMA1 relatively far from the first area OA and a second sub-middle area SMA2 relatively close to the first area OA.

[0170] ​The wires (eg, signal wires) may be positioned in the first sub-middle area SMA1. Figure 10 The detour portion DL-D1 of the first data line DL1 and the detour portion DL-D2 of the second data line DL2 may be positioned at Figure 11 The first sub-middle area SMA1 may be a line area and a detour area in which the data line DL detours. Figure 10 The data lines DL positioned in the middle area MA may include first data lines DL1 and second data lines DL2 alternately placed above and below the first organic insulating layer 209, with the first organic insulating layer 209 located between the first data lines DL1 and the second data lines DL2. Figure 11 2 shows that the detour portion DL-D1 of the first data line DL1 and the detour portion DL-D2 of the second data line DL2 are adjacent to each other and are respectively placed above and below the first organic insulating layer 209. In this case, the gap (or spacing Δd) between the first data line DL1 and the second data line DL2 adjacent to each other (for example, between the detour portion DL-D1 of the first data line DL1 and the detour portion DL-D2 of the second data line DL2) can be reduced.

[0171] The groove G is positioned in the second sub-middle area SMA2. The groove G is positioned in the multilayer ML. In an embodiment, as Figure 11 and Figure 12A As shown in FIG, the multilayer ML may include a first organic insulating layer 209, a second organic insulating layer 211, and an inorganic layer 213. The first organic insulating layer 209 and the second organic insulating layer 211 may correspond to the reference layers 1 and 2, respectively. Figure 9A and Figure 9B The described second lower sub layer LL2 and the first lower sub layer LL1 of the multi-layer ML, and the inorganic layer 213 may correspond to an upper layer UL.

[0172] The inorganic layer 213 may include a material different from that of the pixel electrode 221. The inorganic layer 213 may include a conductive oxide such as IZO, ITO, ZnO, In2O3, IGO, and / or AZO, may include a metal such as Mo, Cu, and / or Ti, or may include an insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride.

[0173] Reference Figure 12AIn this case, a bottom surface of the recess G can be positioned between a top surface and a bottom surface of the first organic insulating layer 209. In some other embodiments, the first organic insulating layer 209 can include a hole passing through the first organic insulating layer 209 instead of the recess 209r. In this case, a bottom surface of the recess G can be placed on the same surface as a bottom surface of the first organic insulating layer 209 or a top surface of the second interlayer insulating layer 207.

[0174] The inorganic layer 213 can include a pair of tips PT extending toward the recess G. As described above, a protruding length d1 of the tips PT can be less than about 2 µm. A depth d of the recess G can be 2 µm or more, 2.5 µm or more, 3 µm or more, or 3.5 µm or more.

[0175] The partition wall PW can be positioned in the middle area MA. The partition wall PW can be positioned between the recesses G adjacent to each other. The partition wall PW can be formed while sequentially stacking (e.g., arranging) the portion 211P of the layers constituting the second organic insulating layer 211, the portion 215P of the layers constituting the pixel definition layer 215, and the portion 217P of the layers constituting the spacer 217. A height from a top surface of the substrate 100 to a top surface of the partition wall PW can be less than a height from the top surface of the substrate 100 to a top surface of the spacer 217.

[0176] The middle area MA can include an inorganic contact region ICR. The inorganic contact region ICR can be positioned between the recesses G adjacent to each other. The inorganic contact region ICR is a region in which layers including an inorganic material directly contact each other. In the inorganic contact region ICR, the inorganic layer 213 can directly contact the second interlayer insulating layer 207. Figure 11 The inorganic layer 213 is shown to directly contact the second interlayer insulating layer 207 in the middle area MA. The inorganic layer 213 can contact the second interlayer insulating layer 207 through the opening 209OP positioned in the first organic insulating layer 209 and the opening 211OP in the second organic insulating layer 211.

[0177] The first recess G1, the second recess G2, and the third recess G3 can be formed before performing a process of forming the middle layer 222. The first recess G1, the second recess G2, and the third recess G3 can be formed by the recess G as described above with reference to FIGS. 1A to 1C. Figure 11 and Figure 12A and Figure 12B The first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 can be disconnected or separated by the recess G as described above with reference to FIGS. 1A to 1C.

[0178] Reference is made to Figure 12CThe first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 can be sequentially formed. The first inorganic encapsulation layer 310 can be formed by chemical vapor deposition or the like. Unlike the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230, the first inorganic encapsulation layer 310 has a relatively large (e.g., excellent) step coverage. Accordingly, as shown in Figure 11 、 Figure 12C and Figure 13 , the first inorganic encapsulation layer 310 can continuously cover the inner surface of the first groove G1. For example, the first inorganic encapsulation layer 310 can continuously extend to cover the top surface, the side surface, and the bottom surface of the inorganic layer 213, the side surface of the second organic insulating layer 211, and the side surface of the first organic insulating layer 209.

[0179] As shown in Figure 13 , a first thickness t1 of a first portion of the first inorganic encapsulation layer 310 on the top surface of the inorganic layer 213 can be greater than a second thickness t2 of a second portion of the first inorganic encapsulation layer 310 under the bottom surface of the inorganic layer 213. Further, the first thickness t1 can be greater than a third thickness t3 of a third portion of the first inorganic encapsulation layer 310 on the side surface of the second organic insulating layer 211.

[0180] The first inorganic encapsulation layer 310 can include a single layer or a plurality of sub-layers. For example, the first inorganic encapsulation layer 310 can include two layers of silicon oxynitride having different film materials. In such a case, the cap layer 230 can be omitted. Alternatively, the first inorganic encapsulation layer 310 can include silicon oxynitride and silicon oxide, silicon oxynitride and silicon nitride, or silicon nitride and silicon oxide.

[0181] As shown in Figure 11 and Figure 12C , the organic encapsulation layer 320 can cover a portion of the middle area MA and the display area DA. An end portion of the organic encapsulation layer 320 adjacent to the first area OA can be adjacent to one side surface of the partition wall PW.

[0182] The second inorganic encapsulation layer 330 is positioned on the organic encapsulation layer 320 and can directly contact the first inorganic encapsulation layer 310 in the middle area MA. For example, the first inorganic encapsulation layer 310 can directly contact the second inorganic encapsulation layer 330 in the area between the first area OA and the partition wall PW.

[0183] Similar to the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330 can have a relatively large (e.g., excellent) step coverage. Accordingly, the second inorganic encapsulation layer 330 can continuously cover the inner side surface of the groove G positioned between the first area OA and the partition wall PW. Similar to Figure 13In the first inorganic encapsulating layer 310 described in , the thickness of the fourth portion of the second inorganic encapsulating layer 330 on the top surface of the inorganic layer 213 may be greater than the thickness of the fifth portion of the second inorganic encapsulating layer 330 below the bottom surface of the inorganic layer 213 .

[0184] In the plan view, Figure 11 The structure shown in FIG may be a structure surrounding the first area OA. Figure 10 As shown in FIG, in a diagram along a direction perpendicular to the top surface of the substrate 100, Figure 11 The groove G may have an annular shape surrounding the first area OA. Similarly, in a drawing in a direction perpendicular to the top surface of the substrate 100, the partition wall PW may have an annular shape surrounding the first area OA.

[0185] Figure 14 It is along Figure 10 A cross-sectional view of the display panel 10 - 2 according to the embodiment taken along line XX′. Figure 14 The display panel 10-2 may have a Figure 11 The structure of the display panel 10 - 1 described in the following is similar to that of the display panel 10 - 1 .

[0186] Reference Figure 14 , the multilayer ML of the display panel 10-2 may include a first organic insulating layer 209, a second organic insulating layer 211, and an inorganic layer 213'. The inorganic layer 213' may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. The first organic insulating layer 209 and the second organic insulating layer 211 may correspond to the reference Figure 9A and Figure 9B The described second lower sub layer LL2 and the first lower sub layer LL1 of the multi-layer ML, the inorganic layer 213 ′ may correspond to the upper layer UL.

[0187] The inorganic layer 213' is positioned in the middle area MA and can be formed during the same process as the process of forming the passivation layer 212 including the inorganic insulating material. The inorganic layer 213' includes a pair of tips PT extending toward the groove G, and the protruding length of the tips PT and the structural characteristics of the groove G (such as the depth of the groove G) are the same as those described above.

[0188] The middle area MA may include a plurality of inorganic contact regions ICR. In this regard, Figure 14 The inorganic contact region ICR adjacent to the partition wall PW and the inorganic contact region ICR located between the grooves G adjacent to each other are shown. Figure 14 The multiple inorganic contact regions ICR described are applicable to reference Figure 11 Described embodiments, reference Figures 15-19 The embodiments described and those derived therefrom.

[0189] Although the passivation layer 212 positioned in the display area DA is positioned on the second organic insulating layer 211 in Figure 14 , in some other embodiments, the passivation layer 212 can be positioned under the second organic insulating layer 211.

[0190] Figure 15 is a cross-sectional view of the first area OA and the middle area MA in the display panel 10-3 according to an embodiment, taken along the line X-X' of Figure 10 . Figure 15 The display panel 10-3 shown in Figure 15 shows that the first recess G1 overlaps with the detour portions DL-D1 and DL-D2 of the data lines extending along the edges of the first area OA.

[0191] The recess G positioned between the first area OA and the first recess G1 can be defined in a plurality of layers different from the plurality of layers of the first recess G1. The recess G other than the first recess G1 can be located in a plurality of layers (hereinafter, referred to as a first plurality of layers ML1) including the first organic insulating layer 209, the second organic insulating layer 211, and the inorganic layer 213. The detailed structure thereof is the same as the detailed structure of the plurality of layers ML described with reference to Figures 11-13 .

[0192] The first recess G1 can be located in a plurality of layers (hereinafter, referred to as a second plurality of layers ML2) including the second organic insulating layer 211, the pixel-defining layer 215, and the inorganic layer 216. The second organic insulating layer 211 and the pixel-defining layer 215 can correspond to the second sub-lower layer LL2 and the first sub-lower layer LL1 described with reference to Figure 9A and Figure 9B .

[0193] The pixel-defining layer 215 can include an organic insulating material, and the inorganic layer 216 can include a conductive oxide such as IZO or include an inorganic insulating material such as silicon nitride. Alternatively, the inorganic layer 216 can include a metal such as Mo and Ti. The inorganic layer 216 of the second plurality of layers ML2 can include the same or different material as that of the inorganic layer 213 of the first plurality of layers ML1.

[0194] The first recess G1 can include a hole 216h of the inorganic layer 216, a hole 215h of the pixel-defining layer 215, and a recess 211r of the second organic insulating layer 211. The inorganic layer 216 can include a pair of tips PT extending toward the center of the first recess G1. The protruding length of the tips PT and the depth of the first recess G1 are the same as those described with reference toFigure 9A are the same as those described above.

[0195] Figure 16 is a cross-sectional view of the first area OA and the middle area MA in the display panel 10-4 according to the embodiment taken along the line X-X' of Figure 10 Because the display panel 10-4 of Figure 16 differs from the display panel 10-3 shown in Figure 15 in the structure of the first recess G1, only the difference is mainly described.

[0196] The first recess G1 is positioned in the second multi-layer ML2', and the upper layer of the second multi-layer ML2' can include a plurality of inorganic layers. In this regard, the second multi-layer ML2' is shown in Figure 16 to include a second organic insulating layer 211, a pixel-defining layer 215, a first inorganic layer 216a, and a second inorganic layer 216b. As described with reference to Figure 9F , the second organic insulating layer 211 and the pixel-defining layer 215 can correspond to the second sub-lower layer LL2 and the first sub-lower layer LL1, respectively, and the first inorganic layer 216a and the second inorganic layer 216b can correspond to the upper layer. Although the upper layer is shown in Figure 16 to include two layers including the first inorganic layer 216a and the second inorganic layer 216b, the upper layer can include three or more inorganic layers as described with reference to Figure 9F .

[0197] The first recess G1 can include a hole 216bh of the second inorganic layer 216b, a hole 216ah of the first inorganic layer 216a, a hole 215h of the pixel-defining layer 215, and a recess 211r of the second organic insulating layer 211. As described with reference to Figure 15 , the first recess G1 can overlap with the looped portion DL-D1 of the first data line DL1 and the looped portion DL-D2 of the second data line DL2, respectively.

[0198] The first inorganic layer 216a can include a material different from that of the second inorganic layer 216b. For example, the first inorganic layer 216a can include a conductive oxide such as IZO, and the second inorganic layer 216b can include an insulating material such as silicon nitride. The first inorganic layer 216a and the second inorganic layer 216b can include a tip PT protruding toward the center of the first recess G1, and the conditions of the protruding length of the tip PT and the depth of the first recess G1 are the same as those described above.

[0199] Although the first inorganic layer 216a and the second inorganic layer 216b are shown in Figure 16The inorganic layer 213 shown as the upper layer of the first multi-layer ML1 includes a single layer, but in some other embodiments, the inorganic layer 213 can include two or more layers. The upper layer of the second multi-layer ML2' and the upper layer of the first multi-layer ML1 can have different stack structures or include different materials. In an embodiment, the upper layer of the second multi-layer ML2' can include two sub-layers including a first inorganic layer 216a and a second inorganic layer 216b, but the inorganic layer 213 as the upper layer of the first multi-layer ML1 can include one or three or more sub-layers.

[0200] Referring to Figure 15 and Figure 16 The above-described properties (e.g., the property in which the first recess G1 adjacent to the display area DA is positioned on a different layer from the layer on which the other recesses G are placed, the property in which the first recess G1 is superposed with the wiring) and the structure of the second multi-layer ML2 and ML2' are applicable to the embodiments described with reference to Figures 8-14 , the embodiments described with reference to Figures 17-19 , and embodiments derived therefrom.

[0201] Figure 17 is a cross-sectional view of a display panel 10-5 according to an embodiment. Figure 17 may correspond to a cross-section taken along a line X-X' of Figure 10 .

[0202] Referring to Figure 17 , the display panel 10-5 includes a recess G in a multi-layer ML. The multi-layer ML can include a first organic insulating layer 209, a second interlayer insulating layer 207, a first interlayer insulating layer 205, and an inorganic layer 210. The first organic insulating layer 209, the second interlayer insulating layer 207, and the first interlayer insulating layer 205 can correspond to the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3 of the multi-layer ML described with reference to Figure 9C , respectively, and the inorganic layer 210 can correspond to the upper layer UL.

[0203] The inorganic layer 210 can include a material different from that of the data line DL and a contact metal layer CM connecting the thin film transistor TFT to the pixel electrode 221. The inorganic layer 210 can include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. Optionally, the inorganic layer 210 can include a conductive oxide such as IZO. Optionally, the inorganic layer 210 can include a metal such as Mo and Ti.

[0204] The inorganic layer 210 can include a pair of tips PT extending toward the center of the recess G, and the properties of the protruding length of the tips PT and the depth of the recess G are the same as those described above.

[0205] Although in the above-described embodiments, the first recess G1 is positioned on a different layer from the layer on which the other recesses G are placed, the first recess G1 can be positioned on the same layer as the layer on which the other recesses G are placed.Figure 17 2 shows that the lower layer of the multilayer ML includes three sublayers, but the embodiment is not limited thereto. In some other embodiments, the lower layer of the multilayer ML may include two sublayers including the first organic insulating layer 209 and the second interlayer insulating layer 207. Figure 17 In addition to the sub-layers, the lower layer of the multilayer ML may further include a gate insulating layer 203 .

[0206] The partition wall PW positioned in the middle area MA may be formed while sequentially stacking a portion 209P of a layer including the first organic insulating layer 209 , a portion 215P of a layer including the pixel defining layer 215 , and a portion 217P of a layer including the spacer 217 . Figure 17 The structure of the partition wall PW shown in FIG is applicable to the reference Figures 11-16 The following describes the embodiment of Figure 19 The described embodiments and / or embodiments derived therefrom.

[0207] Figure 18 is a cross-sectional view of a display panel 10 - 6 according to an embodiment. Figure 18 can correspond to along Figure 10 The cross section is taken along the line X-X'. Figure 18 The display panel 10-6 is different from the display panel 10-6 in the structure of the upper layer of the multi-layer ML. Figure 17 , so the following mainly describes the differences.

[0208] Reference Figure 18 , the multilayer ML may include a first organic insulating layer 209, a second interlayer insulating layer 207, a first interlayer insulating layer 205, a first inorganic layer 210a, and a second inorganic layer 210b. The first organic insulating layer 209, the second interlayer insulating layer 207, and the first interlayer insulating layer 205 may correspond to a first sub-lower layer, a second sub-lower layer, and a third sub-lower layer, respectively. The first inorganic layer 210a and the second inorganic layer 210b may correspond to a first sub-upper layer and a second sub-upper layer, respectively. Although Figure 18 The lower layer of the multi-layer ML is shown to include three sub-layers, but in some other embodiments, the lower layer may include Figure 9E In this case, the multi-layer ML may include a first organic insulating layer 209 as a lower layer and first and second inorganic layers 210a and 210b as upper layers.

[0209] The first inorganic layer 210a may include the same material as the contact metal layer CM. For example, the first inorganic layer 210a may have a structure of Ti / Al / Ti stacked sequentially. The second inorganic layer 210b may include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride.

[0210] A side surface of the first inorganic layer 210a facing a center of the recess G can be covered by a second inorganic layer 210b. The first inorganic layer 210a having a three-layer structure of Ti / Al / Ti can be formed during the same mask process as a process of forming the contact metal layer CM. The second inorganic layer 210b can prevent or reduce damage to the first inorganic layer 210a. For example, in a case where the first inorganic layer 210a includes a multilayer including aluminum (which can be damaged during a process) and titanium (which can not be damaged during a process), the side surface of the first inorganic layer 210a can not include unevenness by reducing or preventing damage to the aluminum.

[0211] The upper layer including the first inorganic layer 210a and the second inorganic layer 210b can include a pair of tips PT. Characteristics of a protruding length of the tips PT and a depth of the recess G are the same as those described above.

[0212] Although the lower layer of the multilayer ML is shown to include three sub-layers in Figure 18 , embodiments are not limited thereto. In some other embodiments, the lower layer of the multilayer ML can include two sub-layers including the first organic insulating layer 209 and the second interlayer insulating layer 207. Optionally, in addition to the sub-layers of Figure 18 , the lower layer of the multilayer ML can include the gate insulating layer 203.

[0213] Figure 19 is a cross-sectional view of a display panel 10-7 according to an embodiment, Figure 20 is a cross-sectional view of a display panel 10-8 according to an embodiment. Figure 19 and Figure 20 may correspond to a cross-section taken along a line X-X' of Figure 10 .

[0214] Figure 19 The display panel 10-7 of Figure 20 and the display panel 10-8 of Figure 11 may include a planarization organic material layer 420 positioned on the thin film encapsulation layer 300 in the middle area MA. In an embodiment, a structure of the display panel 10-7 in a range from the substrate 100 to the thin film encapsulation layer 300 is the same as a structure described above with reference to Figure 20 . In some other embodiments, as shown in Figure 20A portion of the organic encapsulation layer 320 is shown to be positioned between the partition walls PW and PW' adjacent to each other, but in some other embodiments, the end portion of the organic encapsulation layer 320 can be positioned on a side of the partition wall PW adjacent to the display area DA according to a flow control condition. As Figure 19 and Figure 20 The planarization organic material layer 420 can be positioned in the intermediate area MA as shown in FIGS. 10A and 10B. The planarization organic material layer 420 can be positioned only in the intermediate area MA, for example, between the first area OA and the display area DA. The planarization organic material layer 420 can include an organic insulating layer. The planarization organic material layer 420 can include a polymer-based material. For example, the planarization organic material layer 420 can include a silicon-based resin, an acrylic-based resin, an epoxy-based resin, a polyimide, and a polyethylene. In an embodiment, the planarization organic material layer 420 can include a material different from a material of the organic encapsulation layer 320.

[0215] The planarization organic material layer 420 can cover at least one groove G positioned in the intermediate area MA. The planarization organic material layer 420 can increase the flatness of the display panel 10-7 and 10-8 around the first area OA by covering an area of the intermediate area MA that is not covered by the organic encapsulation layer 320. Accordingly, separation or peeling of the input sensing layer 40 (see Figure 2 or Figure 3 ) and / or the optical functional layer 50 (see Figure 2 or Figure 3 ) on the display panel 10-7 can be reduced or prevented. A portion of the planarization organic material layer 420 can be overlapped with the organic encapsulation layer 320. One edge (e.g., the first edge 420e adjacent to the display area DA) of the planarization organic material layer 420 can be positioned on the second inorganic encapsulation layer 330.

[0216] The planarization organic material layer 420 can be positioned in the intermediate area MA during an exposure and development process. In case that an external foreign substance (e.g., moisture) travels in a side direction (or a direction parallel to the top surface of the substrate 100, x direction) of the display panel 10-7 and 10-8 during some processes (e.g., a cleaning process) among processes of forming the planarization organic material layer 420, the organic light emitting diode OLED in the display area DA can be damaged. However, because the insulating layers (e.g., the first insulating layer 410 and the second insulating layer 430) are respectively arranged or placed under and above the planarization organic material layer 420, a problem related to moisture penetration and / or lifting of layers positioned around the planarization organic material layer 420 during and after the processes of forming the planarization organic material layer 420 can be reduced or prevented.

[0217] The first insulating layer 410 and the second insulating layer 430 can directly contact a bottom surface and a top surface of the planarized organic material layer 420, respectively. The first insulating layer 410 and the second insulating layer 430 can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The first insulating layer 410 and the second insulating layer 430 can each include a single layer or multiple layers including the above-described materials.

[0218] The planarized organic material layer 420 can form a step difference with the layer thereunder. A portion of the planarized organic material layer 420 including the first edge 420e can form a step difference with the top surface of the first insulating layer 410. To reduce or prevent a problem of the planarized organic material layer 420 being separated or lifted from the layer thereunder due to the above-described step difference during and / or after a process of manufacturing the display panels 10-7 and 10-8, the cover layer 440 can be positioned on the first edge 420e.

[0219] The cover layer 440 can include a metal. The first insulating layer 410, the second insulating layer 430, and the third insulating layer 450 described below each extend not only to the middle area MA but also to the display area DA. In contrast, the cover layer 440 can cover the first edge 420e of the planarized organic material layer 420 with a set or predetermined width. The cover layer 440 on the planarized organic material layer 420 can extend beyond the first edge 420e toward the display area DA but not to the display area DA.

[0220] The third insulating layer 450 can be positioned on the cover layer 440. The third insulating layer 450 can include an organic insulating material. For example, the organic insulating material of the third insulating layer 450 can include a photoresist (e.g., a negative or positive photoresist) or a polymer-based organic material, and can extend toward the display area DA to cover the display area DA.

[0221] Figure 19 and Figure 20 the structures shown in Figures 13-18 described embodiments and embodiments derived therefrom.

[0222] Although it is shown that each of the display panels described with reference to Figures 11-20 includes the first opening 10H corresponding to the first area OA, and the base 100 further includes the via hole corresponding to the first area OA, embodiments are not limited thereto. In some other embodiments, the display panel can not include the hole through the base 100, as described with reference to Figure 4B .

[0223] The display panel according to the embodiments can reduce or prevent damage of the display element by an external impurity such as moisture around the first area.

[0224] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element,”“a first component,”“a first region,”“a first layer,” or“a first portion” discussed herein could be termed a“second element,”“a second component,”“a second region,”“a second layer,” or“a second portion” without departing from the scope of the present disclosure.

[0225] For ease of description, spatially relative terms, such as“below,”“beneath,”“lower,”“under,”“above,”“upper,” and the like, can be used herein for describing an element’s or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations depicted in the figures. For example, if a device is turned over, elements described as“below” or“beneath” or“under” other elements or features would then be oriented“above” the other elements or features. Thus, the example term“below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and that the spatially relative descriptions used herein should be interpreted accordingly. It will also be understood that, when a layer is referred to as being“between” two layers, it can be the only layer between the two layers or there can be one or more intervening layers between the two layers.

[0226] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the terms“substantially,”“approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0227] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding the list of two or more members, modify the members of the list of two or more members to induce the selection of one or more of the members from the list of two or more members. Also, the use of "can," "could," "might," and / or "may," for example, will be understood to allow for a desired feature or combination of features to be present or possible, but not necessary. Further, the use of terms such as "example" and / or "exemplary," for example, is intended to illustrate the present disclosure one or more embodiments of the present disclosure. Likewise, the use of terms such as "implies" and / or "implies," for example, is intended to indicate a desired feature or combination of features. As used herein, the terms "using" and variations thereof can be considered synonymous with the term "utilizing" and variations thereof.

[0228] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" another element or layer, "coupled to" another element or layer, or "adjacent to" another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers present.

[0229] Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, e.g., 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

[0230] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.

Claims

1. A display panel, comprising: a substrate comprising a first region, a second region, and a third region located between the first region and the second region; a stacked structure corresponding to the plurality of display elements in the second region, the stacked structure comprising a pixel electrode, a counter electrode, and an intermediate layer located between the pixel electrode and the counter electrode; a transistor located between the substrate and the plurality of display elements; a first organic insulating layer and a second organic insulating layer, each of the first organic insulating layer and the second organic insulating layer being positioned between the transistor and the pixel electrode; a pixel defining layer, located on the pixel electrode; as well as A plurality of grooves are located in the third region, wherein: At least one of the plurality of grooves is defined in a first multilayer including a first lower layer and a first upper layer and including the first groove, wherein the first lower layer includes: a first sub-lower layer located in the same layer as the first organic insulating layer and including the same material; and a second sub-lower layer below the first sub-lower layer and including an inorganic insulating material; The display panel further includes: a thin film encapsulation layer covering the stacked structure and including a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer; the intermediate layer of the stacked structure includes at least one functional layer including an organic material layer, the at least one functional layer including a plurality of portions separated from each other by the plurality of grooves in the third region; The first upper layer includes a pair of tips protruding toward a center of the first groove; and A first portion of the plurality of portions is disposed on a bottom surface of the first groove, a second portion of the plurality of portions is disposed on one of the pair of tips, and the first portion and the second portion are covered by the first inorganic encapsulation layer.

2. The display panel according to claim 1, wherein The first upper layer includes an inorganic material layer.

3. The display panel according to claim 2, wherein: The first upper layer includes a conductive oxide layer, a metal layer or an inorganic insulating layer.

4. The display panel according to claim 1, further comprising: a second multilayer comprising a second lower layer and a second upper layer, wherein a second groove of the plurality of grooves is defined in the second multilayer, The second lower layer includes a third sub-lower layer and a fourth sub-lower layer, the third sub-lower layer includes the same material as the pixel defining layer, and the fourth sub-lower layer includes the same material as the second organic insulating layer.

5. The display panel according to claim 4, wherein: The second groove overlaps a plurality of data lines passing through the third region.

6. The display panel according to claim 1, further comprising: at least one inorganic insulating layer located between the substrate and the first organic insulating layer, The second lower sub-layer includes the same material as that of the at least one inorganic insulating layer.

7. The display panel according to claim 1, wherein: The first upper layer comprises: a first upper sub-layer comprising metal or conductive oxide; and The second upper sub-layer is located on the first upper sub-layer.

8. The display panel according to claim 7, wherein: A side surface of the first sub-upper layer facing the center of the at least one groove is covered by the second sub-upper layer.

9. The display panel according to claim 1, further comprising: A first opening is located in the first region and passes through the display panel.

10. The display panel according to claim 1, wherein The inorganic encapsulation layer continuously covers an inner surface of each of the plurality of grooves.

11. The display panel according to claim 10, wherein: A thickness of a first portion of the inorganic encapsulating layer on the top surface of the first upper layer is greater than a thickness of a second portion of the inorganic encapsulating layer on the bottom surface of the first upper layer.

12. An electronic device, comprising: The display panel according to any one of claims 1 to 11; as well as A component located below the substrate of the display panel and corresponding to the first area of ​​the substrate, Wherein, the component includes a sensor or a camera.

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