Semiconductor device and semiconductor package including semiconductor device

Abstract

Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. In addition, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2019-0075216, filed on June 24, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor package including the semiconductor device. BACKGROUND

[0003] A semiconductor package including a semiconductor chip makes it possible to easily use the semiconductor chip as a part of an electronic product. Generally, the semiconductor package includes a printed circuit board (PCB) and a semiconductor chip mounted on the PCB and electrically connected to the PCB using a wire or a bump. As the electronic industry develops, many studies are being conducted to improve the reliability and durability of the semiconductor package. SUMMARY

[0004] Some embodiments of the inventive concept provide a semiconductor device having improved reliability. In addition, some embodiments of the inventive concept provide a semiconductor package having improved reliability.

[0005] According to some embodiments of the inventive concept, a semiconductor device can include a first insulating layer. The semiconductor device can include a conductive element in the first insulating layer. The semiconductor device can include a first barrier pattern in contact with a surface of the conductive element and a surface of the first insulating layer. The semiconductor device can include a second barrier pattern on the first barrier pattern. In addition, the semiconductor device can include a first metal pattern on the second barrier pattern. A width of the first barrier pattern can be smaller than a width of the first metal pattern, and a width of the second barrier pattern can be smaller than a width of the first barrier pattern.

[0006] According to some embodiments of the inventive concept, a semiconductor device can include an insulating layer. The semiconductor device can include a conductive element in the insulating layer. The semiconductor device can include a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. In addition, the semiconductor device can include a metal pattern on the first barrier pattern. A thickness of the first barrier pattern can be in a range of 10 angstroms to , and the first barrier pattern can include a metal nitride.

[0007] According to some embodiments of the inventive concepts, a semiconductor package can include a board and a first semiconductor package mounted on the board. The first semiconductor package can include a redistribution layer, a semiconductor chip on the redistribution layer, and a terminal structure between the redistribution layer and the board. The redistribution layer can include an insulating layer and a conductive element in the insulating layer. The terminal structure can include a first barrier pattern and a second barrier pattern sequentially stacked on a surface of the conductive element and a surface of the insulating layer. The terminal structure can include a metal pattern on the second barrier pattern and a connection terminal between the metal pattern and the board. A width of the second barrier pattern can be smaller than a width of the first barrier pattern and a width of the metal pattern. The second barrier pattern can include titanium. BRIEF DESCRIPTION OF DRAWINGS

[0008] Example embodiments will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0009] Figure 1 FIG. 1 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to some embodiments of the inventive concepts.

[0010] Figure 2A FIG. 2 is an enlarged cross-sectional view illustrating a portion A of FIG. 1. Figure 1

[0011] Figure 2B FIG. 3 is a plan view illustrating an under bump metal (UBM) layer of FIG. 1. Figure 2A

[0012] Figure 2C FIG. 4 is an enlarged cross-sectional view illustrating a portion A of FIG. 1. Figure 1

[0013] Figure 2D FIG. 5 is an enlarged cross-sectional view illustrating a portion A of FIG. 1. Figure 1

[0014] Figure 3 FIG. 6 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to some embodiments of the inventive concepts.

[0015] Figure 4A FIG. 7 is an enlarged cross-sectional view illustrating a portion B of FIG. 6. Figure 3

[0016] Figure 4B FIG. 8 is an enlarged cross-sectional view illustrating a portion C of FIG. 6. Figure 3

[0017] Figure 5 FIG. 9 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to some embodiments of the inventive concepts.

[0018] Figure 6 ​​​​​​is a cross-sectional view showing a chip stack including a semiconductor device according to some embodiments of inventive concepts.

[0019] Figures 7A to 7D is a cross-sectional view showing a method of manufacturing a semiconductor package including a semiconductor device according to some embodiments of inventive concepts.

[0020] It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures and / or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, intended to define or limit the precise architecture or values of the nature or values of the examples embodiments and that such examples embodiments can be practiced with variations that are not precisely as shown or described. For example, the relative thicknesses and positions of molecular, layered, regional and / or structural elements can be reduced or exaggerated for clarity. The use of similar or same reference numerals in various drawings is intended to indicate like or similar elements or features. DETAILED DESCRIPTION

[0021] Figure 1 is a cross-sectional view showing a semiconductor package including a semiconductor device according to some embodiments of inventive concepts. Figure 2A is a cross-sectional view showing Figure 1 is an enlarged cross-sectional view of portion A of Figure 2B is a cross-sectional view showing Figure 2A is a plan view showing an under-bump metallurgy (UBM) layer of ， Figure 2C is a cross-sectional view showing Figure 1 is an enlarged cross-sectional view of portion A of Figure 2D is a cross-sectional view showing Figure 1 is an enlarged cross-sectional view of portion A of Figure 2A , Figure 2C and Figure 2D are different examples of portion A of Figure 1

[0022] Referring to Figure 1 ​​The first semiconductor package 1000 can include a first semiconductor chip 100, a first redistribution layer 200, a first terminal structure 300, and a molding layer 400. The first semiconductor chip 100 can include a first surface 100a and a second surface 100b opposite (or "opposed") to each other. The first surface 100a can be an active surface of the first semiconductor chip 100, and the second surface 100b can be a non-active surface of the first semiconductor chip 100. A first chip pad 102 can be disposed on the first surface 100a of the first semiconductor chip 100. The first chip pad 102 can be in contact with the first surface 100a of the first semiconductor chip 100. The first chip pad 102 can include a metallic material such as aluminum. A first protection layer 104 can be disposed on the first surface 100a of the first semiconductor chip 100. The first protection layer 104 can cover side surfaces of the first chip pad 102 and expose other specific surfaces (e.g., surfaces parallel to the first surface 100a but not in contact with the first surface 100a) of the first chip pad 102. The first protection layer 104 can include a single layer or multiple layers.

[0023] A first redistribution layer 200 can be disposed on the first surface 100a of the first semiconductor chip 100. A first protective layer 104 can be disposed between the first surface 100a of the first semiconductor chip 100 and the first redistribution layer 200. The first redistribution layer 200 can include a first insulating layer 202a, a second insulating layer 202b, a third insulating layer 202c, a plurality of redistribution members 204, and a plurality of vias 206. The first insulating layer 202a, the second insulating layer 202b, and the third insulating layer 202c can be sequentially stacked on the first protective layer 104. The number of insulating layers is not limited to the illustrated example and can be four or more. The first insulating layer 202a, the second insulating layer 202b, and the third insulating layer 202c can be formed of or include a polymer layer or an oxide layer (e.g., a silicon oxide layer). The polymer layer can be a photosensitive polymer, for example, a photosensitive polyimide (PSPI), a polybenzoxazole (PBO), a phenol polymer, or a benzocyclobutene polymer (BCB). The redistribution members 204 can be disposed in the first insulating layer 202a and the second insulating layer 202b. Each of the redistribution members 204 can be disposed to correspond to a respective one of the first chip pads 102, and each of the redistribution members 204 corresponding to each other and each of the first chip pads 102 can be electrically and physically connected to each other. Each of the redistribution members 204 can include a first portion 204a and a second portion 204b. The first portion 204a can be disposed to penetrate at least the first insulating layer 202a and the second insulating layer 202b, and the first portion 204a can be in contact with the first chip pads 102. The second portion 204b can be disposed on a specific surface 2 of the first portion 204a and the second insulating layer 202b. The second portion 204b can be in contact with the specific surface 2 of the second insulating layer 202b. In some embodiments, the second portion 204b can have a linear shape. The redistribution members 204 can include a plurality of conductive layers. The redistribution members 204 can be formed of or include at least one of a metal material or a metal nitride. The metal material can include, for example, at least one of titanium (Ti), copper (Cu), nickel (Ni), or gold (Au). The metal nitride can include, for example, titanium nitride (TiN). The plurality of vias 206 can be disposed in the third insulating layer 202c and on the redistribution members 204. Each of the vias 206 can be disposed to correspond to a respective one of the redistribution members 204. The vias 206 can be in contact with the redistribution members 204, and the vias 206 can be electrically connected to the redistribution members 204. The vias 206 can be exposed on a specific surface 4 of the third insulating layer 202c (and / or can have a respective surface that is coplanar with the specific surface 4 of the third insulating layer 202c). In some embodiments, the vias 206 can be conductive, and thus can be referred to as conductive elements.Other examples of the conductive element in the insulating layer according to the inventive concept include a redistribution member or a pad.

[0024] The first terminal structure 300 can be disposed on the specific surface 4 of the third insulating layer 202c. Each of the first terminal structures 300 can be disposed to correspond to a respective one of the vias 206. The first terminal structure 300 can be in contact with and electrically connected to the via 206. Referring to FIG. 2, the first terminal structure 300 can be disposed on the specific surface 4 of the third insulating layer 202c. The first terminal structure 300 can be disposed to correspond to the via 206. The first terminal structure 300 can be in contact with and electrically connected to the via 206. Figure 2A Figure 2B Each of the first terminal structures 300 can include a UBM layer 310 and a connection terminal 320. The UBM layer 310 can include a first barrier pattern 302, a second barrier pattern 304, a metal pattern 306, and a metal film 308, which are sequentially stacked on the specific surface 4 of the third insulating layer 202c.

[0025] The first barrier pattern 302 can cover the specific surface 4 of the third insulating layer 202c and a specific surface of the via 206 that is exposed by (and / or coplanar with) the third insulating layer 202c. The first barrier pattern 302 can be in contact with the specific surface 4 of the third insulating layer 202c and the specific surface of the via 206. The first barrier pattern 302 can be formed to have a thin thickness. For example, the thickness of the first barrier pattern 302 can be in the range of about 10 angstroms (A) to about 100 A. The first barrier pattern 302 can be formed of or include at least one of metal nitrides. For example, the first barrier pattern 302 can be formed of or include titanium nitride (TiN). The second barrier pattern 304 can be disposed on the first barrier pattern 302. The second barrier pattern 304 can be in contact with a specific surface of the first barrier pattern 302. The second barrier pattern 304 can function as a diffusion barrier layer. The second barrier pattern 304 can be formed of or include a metal material. A metal element included in the second barrier pattern 304 can be the same as a metal element included in the first barrier pattern 302. For example, the second barrier pattern 304 can include titanium (Ti). The metal pattern 306 can be disposed on the second barrier pattern 304. The metal pattern 306 can be in contact with a specific surface of the second barrier pattern 304. The metal pattern 306 can include a first metal pattern 306a and a second metal pattern 306b, which are sequentially stacked on the specific surface of the second barrier pattern 304. The second metal pattern 306b can be thicker than the first metal pattern 306a. The first metal pattern 306a and the second metal pattern 306b can be formed of or include the same metal material. The first metal pattern 306a and the second metal pattern 306b can be formed of or include, for example, copper (Cu). ​​

[0026] Referring to Figure 2A and Figure 2B In some embodiments, the width W1 of the first barrier pattern 302, the width W2 of the second barrier pattern 304, and the width W3 of the metal pattern 306 can be different from each other. The width W3 of the metal pattern 306 can be greater than the width W1 of the first barrier pattern 302 (i.e., W3 > W1). The width W1 of the first barrier pattern 302 can be greater than the width W2 of the second barrier pattern 304 (i.e., W1 > W2). In other words, the metal pattern 306 can have the greatest width W3, and the second barrier pattern 304 can have the smallest width W2. The side surfaces of the first barrier pattern 302, the side surfaces of the second barrier pattern 304, and the side surfaces of the metal pattern 306 can be misaligned with each other (i.e., can be misaligned vertically (in a vertical direction) with each other). The width of the first metal pattern 306a can be equal to the width of the second metal pattern 306b, and the side surfaces of the first metal pattern 306a can be aligned with the side surfaces of the second metal pattern 306b. The side surfaces of the first barrier pattern 302, the side surfaces of the second barrier pattern 304, and the side surfaces of the metal pattern 306 can be perpendicular to the certain surface 4 of the third insulating layer 202c, and can each be substantially flat. In some embodiments, referring to Figure 2C , the side surfaces of the first barrier pattern 302, the side surfaces of the second barrier pattern 304, and the side surfaces of the metal pattern 306 can be perpendicular to the certain surface 4 of the third insulating layer 202c, and can be unflat. For example, as shown in Figure 2C , the side surfaces of the first barrier pattern 302 and the side surfaces of the second barrier pattern 304, and the side surfaces of the metal pattern 306 can each be unflat or rough.

[0027] Referring back to Figure 2A , the metal film 308 can be disposed on the metal pattern 306. The metal film 308 can be in contact with the certain surface of the metal pattern 306. Although Figure 2A shows that the width of the metal film 308 is greater than the width W3 of the metal pattern 306, the width of the metal film 308 is not limited thereto. For example, the width of the metal film 308 can be greater than, less than, or equal to the width W3 of the metal pattern 306. The metal film 308 can be formed of or include a metal material. For example, the metal film 308 can include nickel (Ni).

[0028] The connection terminal 320 can be disposed on the metal film 308. The connection terminal 320 can be in contact with a certain surface of the metal film 308. The connection terminal 320 can not cover the side surface of the metal pattern 306 or the side surface of the first barrier pattern 302 and the side surface of the second barrier pattern 304. In other words, the connection terminal 320 can be disposed to expose the side surface of the metal pattern 306 and the side surface of the first barrier pattern 302 and the side surface of the second barrier pattern 304. The connection terminal 320 can be spaced apart from the certain surface 4 of the third insulating layer 202c, the side surface of the metal pattern 306, the side surface of the first barrier pattern 302, and the side surface of the second barrier pattern 304. The connection terminal 320 can include a solder ball, a bump, or a pillar. The connection terminal 320 can be formed of or include at least one of a metal material (e.g., tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and bismuth (Bi)).

[0029] Referring to Figure 2D , in some embodiments, unlike as shown in Figure 2A and Figure 2C , the metal film 308 can be omitted. In other words, the UBM layer 310 can not include the metal film 308. Accordingly, the connection terminal 320 can be in contact with a certain surface of the metal pattern 306.

[0030] Referring back to Figure 1 , the molding layer 400 can be disposed on the certain surface 6 of the first insulating layer 202a. The molding layer 400 can cover the certain surface 6 of the first insulating layer 202a of the first redistribution layer 200, the side surface of the first protective layer 104, and the side surface and the top surface of the first semiconductor chip 100. The molding layer 400 can include an epoxy molding compound.

[0031] The first semiconductor package 1000 can be disposed on a board 2000. For example, the first terminal structure 300 can be disposed on a first surface of the board 2000. The board 2000 can be, for example, a printed circuit board (PCB). The external terminal 500 can be disposed on a second surface of the board 2000 opposite the first surface. Each of the external terminals 500 can be electrically connected to a corresponding one of the first terminal structures 300. The external terminal 500 can include a solder ball, a bump, or a pillar. The external terminal 500 can be formed of or include at least one of a metal material (e.g., tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and bismuth (Bi)).

[0032] Figure 3 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to some embodiments of the inventive concept. Figure 4A is a cross-sectional view illustrating Figure 3 part B of FIG. 1. Figure 4B is a cross-sectional view illustrating Figure 3 part C of FIG. 1.

[0033] Referring to Figure 3 , the semiconductor package 4000 can include a first semiconductor package 1000 and a second semiconductor package 3000. The first semiconductor package 1000 can be disposed on the second semiconductor package 3000. Since the first semiconductor package 1000 has been described with reference to Figure 1 , a repetitive description of the first semiconductor package 1000 will be omitted.

[0034] The second semiconductor package 3000 can include a second semiconductor chip 700, a second redistribution layer 800, a second chip pad 806, a third chip pad 808, and a second terminal structure 840. The second semiconductor chip 700 can include a first surface 700a and a second surface 700b opposite to each other. The first surface 700a can correspond to an active surface of the second semiconductor chip 700, and the second surface 700b can correspond to an inactive surface of the second semiconductor chip 700. The second chip pad 806 can be disposed on the first surface 700a of the second semiconductor chip 700. The second chip pad 806 can be in contact with the first surface 700a of the second semiconductor chip 700. The second chip pad 806 can be formed of or include a metal material such as aluminum (Al). The third chip pad 808 can be disposed on the second surface 700b of the second semiconductor chip 700. The third chip pad 808 can be in contact with the second surface 700b of the second semiconductor chip 700. The third chip pad 808 can be formed of or include a metal material such as aluminum (Al). A second protective layer 830 can be disposed on the second surface 700b of the second semiconductor chip 700. The second protective layer 830 can cover the second surface 700b of the second semiconductor chip 700 and a side surface of the third chip pad 808. The second protective layer 830 can expose a certain surface (e.g., a surface parallel to the second surface 700b but not in contact with the second surface 700b) of the third chip pad 808. A through-hole 809 can be disposed to penetrate the second semiconductor chip 700. The through-hole 809 can be disposed between the second chip pad 806 and the third chip pad 808 and can electrically connect the second chip pad 806 to the third chip pad 808. The through-hole 809 can be formed of or include at least one of a semiconductor material (e.g., silicon) or a conductive material (e.g., a metal material).

[0035] The second redistribution layer 800 may be disposed on the first surface 700a of the second semiconductor chip 700. The second redistribution layer 800 may include fourth to eighth insulating layers 802a, 802b, 802c, 802d, and 802e, vias 804, redistribution members 810, and pads 820. The fourth to eighth insulating layers 802a, 802b, 802c, 802d, and 802e may be sequentially stacked on the first surface 700a of the second semiconductor chip 700. The fourth to eighth insulating layers 802a, 802b, 802c, 802d, and 802e may be formed of or include at least one of a polymer layer or an oxide layer (e.g., a silicon oxide layer). The polymer layer may be a photosensitive polymer, such as photosensitive polyimide (PSPI), polybenzoxazole (PBO), a phenol polymer, or a benzocyclobutene polymer (BCB). The fourth insulating layer 802a may cover the first surface 700a of the second semiconductor chip 700 and the side surfaces of the second die pad 806. A fifth insulating layer 802b may be disposed on the fourth insulating layer 802a. The fifth insulating layer 802b may cover a specific surface of the second die pad 806 and a specific surface of the fourth insulating layer 802a. A via 804 may be disposed in the fifth insulating layer 802b. The via 804 may be disposed to penetrate the fifth insulating layer 802b and may contact the second die pad 806. The via 804 may be formed of or include at least one conductive material. In some embodiments, the via 804 may be conductive and, therefore, may be referred to as a conductive element. A sixth insulating layer 802c may be disposed on the fifth insulating layer 802b. The sixth insulating layer 802c may cover a specific surface of the fifth insulating layer 802b.

[0036] The redistribution member 810 may be disposed in the sixth insulating layer 802c. The redistribution member 810 may be disposed to penetrate the sixth insulating layer 802c. Each of the redistribution members 810 may be disposed to correspond to a corresponding one of the vias 804. The redistribution member 810 may contact a specific surface 12 of the fifth insulating layer 802b and a specific surface of the via 804, the specific surface of the via 804 being exposed by the fifth insulating layer 802b. In some embodiments, the redistribution member 810 may be conductive and thus may be referred to as a conductive element. Figure 4A Each of the redistribution parts 810 may include a first barrier pattern 812, a second barrier pattern 814, and a metal pattern 816 sequentially stacked on a specific surface 12 of the fifth insulating layer 802b. The first barrier pattern 812 may be in contact with a specific surface of each of the vias 804 and the specific surface 12 of the fifth insulating layer 802b. The first barrier pattern 812 may be formed to have a thin thickness. For example, the thickness of the first barrier pattern 812 may be about 1000 nm. to about The first barrier pattern 812 can be formed of or include at least one of metal nitride. For example, the first barrier pattern 812 can include titanium nitride (TiN). The second barrier pattern 814 can be disposed on the first barrier pattern 812. The second barrier pattern 814 can be in contact with a certain surface of the first barrier pattern 812. The second barrier pattern 814 can function as a diffusion barrier layer. The second barrier pattern 814 can be formed of or include at least one of a metal material. A metal element included in the second barrier pattern 814 can be the same as a metal element included in the first barrier pattern 812. For example, the second barrier pattern 814 can be formed of or include titanium (Ti). The metal pattern 816 can be disposed on the second barrier pattern 814. The metal pattern 816 can be in contact with a certain surface of the second barrier pattern 814. The metal pattern 816 can include a first metal pattern 816a and a second metal pattern 816b sequentially stacked on the certain surface of the second barrier pattern 814. The second metal pattern 816b can be thicker than the first metal pattern 816a. The first metal pattern 816a and the second metal pattern 816b can be formed of or include the same metal material. The first metal pattern 816a and the second metal pattern 816b can be formed of or include, for example, copper (Cu).

[0037] In some embodiments, the width W1_a of the first barrier pattern 812, the width W2_a of the second barrier pattern 814, and the width W3_a of the metal pattern 816 can be different from each other. The width W3_a of the metal pattern 816 can be greater than the width W1_a of the first barrier pattern 812 (i.e., W3_a > W1_a). The width W1_a of the first barrier pattern 812 can be greater than the width W2_a of the second barrier pattern 814 (i.e., W1_a > W2_a). In other words, the metal pattern 816 can have the greatest width W3_a, and the second barrier pattern 814 can have the smallest width W2_a. The side surfaces of the first barrier pattern 812, the side surfaces of the second barrier pattern 814, and the side surfaces of the metal pattern 816 can be misaligned with each other. The width of the first metal pattern 816a can be equal to the width of the second metal pattern 816b, and the side surfaces of the first metal pattern 816a can be aligned with the side surfaces of the second metal pattern 816b. The side surfaces of the first barrier pattern 812, the side surfaces of the second barrier pattern 814, and the side surfaces of the metal pattern 816 can be perpendicular to the certain surface 12 of the fifth insulating layer 802b and can be substantially flat. However, in some embodiments, the side surfaces of the first barrier pattern 812, the side surfaces of the second barrier pattern 814, and the side surfaces of the metal pattern 816 can be perpendicular to the certain surface 12 of the fifth insulating layer 802b and can not be flat (i.e., can be unflat).

[0038] In some embodiments, the redistribution 204 of the first redistribution layer 200 can have the same stack structure as the stack structure of the redistribution 810 of the second redistribution layer 800 and can include a plurality of layers that are substantially the same as the layers that make up the redistribution 810 of the second redistribution layer 800. For example, the redistribution 204 can include a first barrier pattern, a second barrier pattern, and a metal pattern. The first barrier pattern of the redistribution 204 corresponding to the first barrier pattern 812 (see, e.g., Figure 4A ) of the redistribution 810 can be in contact with a certain surface 2 of the second insulating layer 202b. The metal pattern of the redistribution 204 corresponding to the metal pattern 816 (see, e.g., Figure 4A ) of the redistribution 810 can be in contact with the via 206.

[0039] Referring back to Figure 3 , the seventh insulating layer 802d can be disposed on the certain surface of the sixth insulating layer 802c and the certain surface of the redistribution 810. The seventh insulating layer 802d can cover the certain surface of the sixth insulating layer 802c and the certain surface of the redistribution 810. The pads 820 can be disposed in the seventh insulating layer 802d. The pads 820 can be disposed to penetrate the seventh insulating layer 802d and be in contact with the certain surface of the redistribution 810. Each of the pads 820 can be disposed to correspond to a respective one of the redistribution 810. Referring to Figure 4B , each of the pads 820 can include a first portion P1 and a second portion P2. The first portion P1 can be disposed to penetrate the seventh insulating layer 802d and the second portion P2 can be disposed on the certain surface 14 of the seventh insulating layer 802d. The second portion P2 can extend from the first portion P1 to cover the certain surface 14 of the seventh insulating layer 802d. The first portion P1 of each of the pads 820 can be in contact with a respective one of the redistribution 810. The second portion P2 of the pads 820 can be in contact with the certain surface 14 of the seventh insulating layer 802d. In some embodiments, the pads 820 can be electrically conductive and thus can be referred to as electrically conductive elements.

[0040] Each of the pads 820 can include a first barrier pattern 822, a second barrier pattern 824, a metal pattern 826, a first metal film 828, and a second metal film 829. The first barrier pattern 822 can cover a certain surface of the redistribution member 810, a side surface of the through-hole 20 of the seventh insulating layer 802d, and a certain surface 14 of the seventh insulating layer 802d. The first barrier pattern 822 can be in contact with the certain surface of the redistribution member 810, the side surface of the through-hole 20 of the seventh insulating layer 802d, and the certain surface 14 of the seventh insulating layer 802d. For example, the first barrier pattern 822 can be in contact with a certain surface of the metal pattern 816 of the redistribution member 810, which is exposed by the sixth insulating layer 802c. The first barrier pattern 822 can be formed to have a thin thickness. For example, the thickness of the first barrier pattern 822 can be in the range of about 0.1 μm to about 1 μm. to about The first barrier pattern 822 can be formed of or include at least one of metal nitride. For example, the first barrier pattern 822 can be formed of or include titanium nitride (TiN). The second barrier pattern 824 can be disposed on the first barrier pattern 822. The second barrier pattern 824 can be in contact with the bottom and side surfaces of the first barrier pattern 822 located in the penetration hole 20 and the top surface of the first barrier pattern 822 located on the specific surface 14 of the seventh insulating layer 802d. The second barrier pattern 824 can function as a diffusion barrier layer. The second barrier pattern 824 can be formed of or include at least one of a metal material. The metal element included in the second barrier pattern 824 can be the same as the metal element included in the first barrier pattern 822. For example, the second barrier pattern 824 can be formed of or include titanium (Ti). The metal pattern 826 can be disposed on the second barrier pattern 824. The metal pattern 826 can be in contact with the bottom and side surfaces of the second barrier pattern 824 located in the penetration hole 20 and the top surface of the second barrier pattern 824 located on the specific surface 14 of the seventh insulating layer 802d. The metal pattern 826 can be disposed to completely fill the penetration hole 20. The metal pattern 826 can include a first metal pattern 826a and a second metal pattern 826b sequentially stacked on the bottom, side, and top surfaces of the second barrier pattern 824. The second metal pattern 826b can be thicker than the first metal pattern 826a. The first metal pattern 826a and the second metal pattern 826b can include the same metal material. For example, the first metal pattern 826a and the second metal pattern 826b can include copper (Cu). The first metal film 828 can be disposed on the metal pattern 826. The first metal film 828 can be in contact with the specific surface of the metal pattern 826. The first metal film 828 can be formed of or include a metal material. For example, the first metal film 828 can include nickel (Ni). The second metal film 829 can be disposed on the first metal film 828. The second metal film 829 can be in contact with the specific surface of the first metal film 828. The second metal film 829 can be configured to increase the adhesion strength between the pad 820 and a terminal to be disposed on the pad 820. The second metal film 829 can be formed of or include at least one of a metal material (e.g., Au).

[0041] In some embodiments, the width W1_b of the first barrier pattern 822, the width W2_b of the second barrier pattern 824, and the width W3_b of the metal pattern 826 can be different from each other. The width W3_b of the metal pattern 826 can be greater than the width W1_b of the first barrier pattern 822 (i.e., W3_b > W1_b). The width W1_b of the first barrier pattern 822 can be greater than the width W2_b of the second barrier pattern 824 (i.e., W1_b > W2_b). In other words, the metal pattern 826 can have the greatest width W3_b, and the second barrier pattern 824 can have the smallest width W2_b. Although it is shown in Figure 4B that the width of the first metal film 828 is greater than the width W3_b of the metal pattern 826, the width of the first metal film 828 is not limited thereto. For example, the width of the first metal film 828 can be greater than, less than, or equal to the width W3_b of the metal pattern 826.

[0042] The side surfaces of the first barrier pattern 822, the second barrier pattern 824, and the metal pattern 826 disposed on the particular surface 14 of the seventh insulating layer 802d can be misaligned with each other. The width of the first metal pattern 826a can be equal to the width of the second metal pattern 826b, and the side surfaces of the first metal pattern 826a and the second metal pattern 826b disposed on the particular surface 14 of the seventh insulating layer 802d can be aligned with each other. The side surfaces of the first barrier pattern 822, the second barrier pattern 824, and the metal pattern 826 can be perpendicular to the particular surface 14 of the seventh insulating layer 802d, and can be substantially flat. However, in some embodiments, the side surfaces of the first barrier pattern 822, the second barrier pattern 824, and the metal pattern 826 can be perpendicular to the particular surface 14 of the seventh insulating layer 802d, and can not be flat (i.e., can be unflat).

[0043] Referring back to Figure 3 , an eighth insulating layer 802e can be disposed on the seventh insulating layer 802d. The eighth insulating layer 802e can cover the particular surface 14 of the seventh insulating layer 802d and the side surface of the second portion P2 (see, e.g., Figure 4B ) of the pad 820. The eighth insulating layer 802e can be disposed to expose the particular (e.g., top) surface of the second portion P2 (see, e.g., Figure 4B ) of the pad 820. The particular surface of the second portion P2 (see, e.g., Figure 4B ) of the pad 820 can correspond to (e.g., can be) the second metal film 829 (see, e.g., Figure 4Ba particular (e.g., top) surface of the second semiconductor package 3000. The first semiconductor package 1000 can be disposed on the second semiconductor package 3000. In detail, the first terminal structure 300 of the first semiconductor package 1000 can be disposed on the pad 820. The connection terminal 320 of the first terminal structure 300 can be disposed on the pad 820. The connection terminal 320 can be in contact with the second metal film 829 (e.g., see Figure 4B ) of the pad 820.

[0044] The second terminal structure 840 can be disposed on the third chip pad 808. In some embodiments, the second terminal structure 840 can have the same stack structure as that of the first terminal structure 300 of the first semiconductor package 1000 and can include a plurality of layers which are substantially the same as those constituting the first terminal structure 300 of the first semiconductor package 1000. For example, the second terminal structure 840 can include a first barrier pattern, a second barrier pattern, a metal pattern, a metal film, and a connection terminal. In some embodiments, the connection terminal of the second terminal structure 840 corresponding to the connection terminal 320 of the first terminal structure 300 can be in contact with a particular (e.g., top) surface of the board 2000, the first barrier pattern of the second terminal structure 840 corresponding to the first barrier pattern 302 of the first terminal structure 300 (e.g., see Figure 2A ) can be in contact with a particular (e.g., bottom) surface of the third chip pad 808 and a particular (e.g., side) surface of the second protective layer 830. In some embodiments, the second terminal structure 840 can be composed of only terminals such as solder balls, bumps, or pillars. The second terminal structure 840 can be electrically connected to the external terminal 500.

[0045] Figure 5 is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to some embodiments of the inventive concept.

[0046] Referring to Figure 5 , the first semiconductor package 1000 can be disposed on the redistribution substrate 900. The redistribution substrate 900 can include first to fifth insulating layers 902a, 902b, 902c, 902d, and 902e, a first pad 904 and a second pad 908, a redistribution 905, and a via 906. The second to fifth insulating layers 902b, 902c, 902d, and 902e can be sequentially stacked on the first insulating layer 902a. The first pad 904 can be disposed to penetrate the fourth insulating layer 902d and can be in contact with a side surface of the fifth insulating layer 902e. The first pad 904 of the redistribution substrate 900 can have the same stack structure as that of the first terminal structure 300 of the first semiconductor package 1000 and can include a plurality of layers which are substantially the same as those constituting the first terminal structure 300 of the first semiconductor package 1000. For example, the first pad 904 of the redistribution substrate 900 can include a first barrier pattern, a second barrier pattern, a metal pattern, a metal film, and a connection terminal. Figure 3 and Figure 4BThe stack structure of the pad 820 of the second redistribution layer 800 shown in FIG. 1 is the same as that of the pad 820 and may include a plurality of layers that are substantially the same as the layers constituting the pad 820 of the second redistribution layer 800. For example, the first pad 904 may include a first barrier pattern, a second barrier pattern, a metal pattern, a first metal film, and a second metal film. In some embodiments, the connection terminal 320 of the first semiconductor package 1000 may be in contact with the second metal film of the first pad 904, which corresponds to the second metal film 829 of the pad 820 (e.g., see FIG. 1 ). Figure 4B ). In addition, the first barrier pattern 822 of the pad 820 (eg, see Figure 4B ) The first barrier pattern of the corresponding first pad 904 may be in contact with the side surface of the fifth insulating layer 902e.

[0047] The redistribution member 905 of the redistribution substrate 900 may be disposed in the third insulating layer 902c. The redistribution member 905 may have a Figure 3 and Figure 4A The stack structure of the redistribution member 810 of the second redistribution layer 800 described above may be the same as that of the stack structure and may include a plurality of layers that are substantially the same as the layers constituting the redistribution member 810 of the second redistribution layer 800. For example, the redistribution member 905 may include a first barrier pattern, a second barrier pattern, and a metal pattern. In some embodiments, the first barrier pattern 812 of the redistribution member 810 (e.g., see Figure 4A ) The first barrier pattern of the redistribution member 905 corresponding to the first barrier pattern may contact a specific surface (eg, top surface) of the second insulating layer 902b and the via 906, and contact the metal pattern 816 (eg, see Figure 4AA metal pattern of the corresponding redistribution member 905 can be in contact with the first pad 904. A via 906 can be disposed to penetrate the second insulating layer 902b. A second pad 908 can be disposed in the first insulating layer 902a. The second pad 908 can be in contact with the via 906. The second pad 908 can be formed of or include at least one of metal materials (e.g., aluminum). In some embodiments, the second pad 908 can have the same stack structure as the stack structure of the first pad 904 and can include a plurality of layers which are substantially the same as the layers constituting the first pad 904. For example, the second pad 908 can include a first barrier pattern, a second barrier pattern, a metal pattern, a first metal film, and a second metal film. An external terminal 910 can be disposed on the second pad 908. The external terminal 910 can have the same stack structure as the stack structure of the first terminal structure 300 of the first semiconductor package 1000 and can include a plurality of layers which are substantially the same as the layers constituting the first terminal structure 300 of the first semiconductor package 1000. In some embodiments, the external terminal 910 can be constituted only of terminals such as solder balls, bumps, or pillars.

[0048] Figure 6 FIG. 1 is a cross-sectional view illustrating a chip stack including semiconductor devices according to some embodiments of the inventive concepts.

[0049] The chip stack 5000 can include a first chip 920, a second chip 922, a third chip 924, a fourth chip 926, and a chip molding layer 928. The second chip 922 can be stacked on the first chip 920, the third chip 924 can be stacked on the second chip 922, and the fourth chip 926 can be stacked on the third chip 924. In other words, the second chip 922, the third chip 924, and the fourth chip 926 can be sequentially stacked on the first chip 920. As an example, the first chip 920 can be a semiconductor logic chip, and the second chip 922, the third chip 924, and the fourth chip 926 can be semiconductor memory chips. A width of the first chip 920 can be greater than widths of the second chip 922, the third chip 924, and the fourth chip 926.

[0050] Through-vias 930 may be provided in the first chip 920, the second chip 922, and the third chip 924. The through-vias 930 may be provided to penetrate the first chip 920, the second chip 922, and the third chip 924. The through-vias 930 may not be provided in the fourth chip 926. The through-vias 930 may be formed of or include at least one of a metal material (e.g., copper, tungsten, aluminum) or a semiconductor material (e.g., silicon). A redistribution layer 940 may be provided on the top and bottom surfaces of the first chip 920, the second chip 922, and the third chip 924. The redistribution layer 940 may include an insulating layer 942 and a pad 944. The insulating layer 942 may cover the top and bottom surfaces of the first chip 920, the second chip 922, and the third chip 924. The pad 944 may be provided to penetrate the insulating layer 942 and extend onto a specific surface of the insulating layer 942. In some embodiments, the redistribution layer 940 may also include vias and redistribution members. The pad 944 may have Figure 4B The stacked structure of the pad 820 shown in FIG may be the same as that of the pad 820 and may include a plurality of layers that are substantially the same as the layers constituting the pad 820. For example, each of the pads 944 may include a first barrier pattern, a second barrier pattern, a metal pattern, a first metal film, and a second metal film. The first barrier pattern of the pad 944 may be in contact with a specific surface of the insulating layer 942.

[0051] The pads 944 provided on the top and bottom surfaces of the first chip 920 may be provided on the through vias 930 penetrating the first chip 920. The pads 944 provided on the top and bottom surfaces of the second chip 922 may be provided on the top and bottom surfaces of the through vias 930 penetrating the second chip 922. The pads 944 provided on the top and bottom surfaces of the third chip 924 may be provided on the top and bottom surfaces of the through vias 930 penetrating the third chip 924. In addition, the pads 950 provided on the bottom surface of the fourth chip 926 may be provided to correspond to the pads 944 provided on the top surface of the third chip 924 (for example, may be on the pads 944 provided on the top surface of the third chip 924). The pads 950 provided on the bottom surface of the fourth chip 926 may have the same Figure 4B The stacked structure of the pad 820 shown in FIG5 is the same stacked structure and may include a plurality of layers substantially the same as the layers constituting the pad 820. For example, each of the pads 950 may include a first barrier pattern, a second barrier pattern, a metal pattern, a first metal film, and a second metal film.

[0052] The first terminal 960 can be disposed on a pad 944 disposed on a bottom surface of the first chip 920. The second terminal 962 can be disposed between the first chip 920 and the second chip 922, between the second chip 922 and the third chip 924, and between the third chip 924 and the fourth chip 926. For example, the second terminal 962 can be disposed between a pad 944 on a top surface of the first chip 920 and a pad 944 on a bottom surface of the second chip 922. The second terminal 962 can be disposed between a pad 944 on a top surface of the second chip 922 and a pad 944 on a bottom surface of the third chip 924. In addition, the second terminal 962 can be disposed between a pad 944 on a top surface of the third chip 924 and a pad 950 on a bottom surface of the fourth chip 926. The first terminal 960 and the second terminal 962 can be formed of or include at least one of a metal material, for example, tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and bismuth (Bi).

[0053] The chip molding layer 928 can be disposed on a top surface of the first chip 920. The chip molding layer 928 can be disposed on the top surface of the first chip 920 to cover side surfaces of the second chip 922, the third chip 924, and the fourth chip 926. The chip molding layer 928 can fill spaces between the first chip 920 and the second chip 922, between the second chip 922 and the third chip 924, and between the third chip 924 and the fourth chip 926. The chip molding layer 928 can be formed of or include an epoxy molding compound (EMC).

[0054] Figures 7A to 7D FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor package including a semiconductor device according to some embodiments of the inventive concept.

[0055] Referring to Figure 7A A first chip pad 102 can be formed on a first surface 100a of the first semiconductor chip 100. The formation of the first chip pad 102 can include forming a conductive layer on the first surface 100a of the first semiconductor chip 100 and then patterning the conductive layer. A first protective layer 104 can be formed on the first surface 100a of the first semiconductor chip 100. The first protective layer 104 can cover side surfaces of the first chip pad 102 and expose a certain surface of the first chip pad 102. A molding layer 400 can be formed to cover side surfaces of the first semiconductor chip 100, side surfaces of the first protective layer 104, and a second surface 100b of the first semiconductor chip 100.

[0056] The first insulating layer 202a and the second insulating layer 202b can be sequentially formed on the first chip pad 102, the first protective layer 104, and the molding layer 400. The first insulating layer 202a can be formed to conformally cover certain surfaces of the first protective layer 104, certain surfaces of the first chip pad 102 exposed by the first protective layer 104, and certain surfaces of the molding layer 400. The second insulating layer 202b can be formed on the first insulating layer 202a. The redistribution 204 can be formed in the first insulating layer 202a and the second insulating layer 202b and on certain surfaces 2 of the second insulating layer 202b. The formation of the redistribution 204 can include forming first penetration holes H1 to penetrate the first insulating layer 202a and the second insulating layer 202b, forming a layer to fill the first penetration holes H1 and cover the certain surfaces 2 of the second insulating layer 202b, and patterning the layer. In some embodiments, the first penetration holes H1 can be formed to expose certain surfaces of the first chip pad 102. The redistribution 204 can include a single layer or multiple layers. The redistribution 204 can be formed of or include at least one of a metal layer or a metal nitride layer. A third insulating layer 202c can be formed on the certain surfaces 2 of the second insulating layer 202b. The third insulating layer 202c can be formed to cover certain surfaces and side surfaces of the redistribution 204 formed on the certain surfaces 2 of the second insulating layer 202b. A via 206 can be disposed in the third insulating layer 202c. The formation of the via 206 can include forming second penetration holes H2 in the third insulating layer 202c and filling the second penetration holes H2 with a metal material.

[0057] The first barrier layer 52, the second barrier layer 54, and the seed layer 56 can be sequentially formed on certain surfaces 4 of the third insulating layer 202c. The first barrier layer 52 can be in contact with the certain surfaces 4 of the third insulating layer 202c and certain surfaces of the via 206. The first barrier layer 52 can be formed using a deposition process (e.g., PVD, CVD, or ALD). The first barrier layer 52 can be formed of or include at least one of a metal nitride. For example, the first barrier layer 52 can be formed of or include a titanium nitride layer (TiN). The first barrier layer 52 can be formed to a thickness selected to reduce the impact on resistance and prevent the second barrier layer 54 from being over-etched in a subsequent etching process. The first barrier layer 52 can be formed to have a thickness of about about 10 nm to about 50 nm. The second barrier layer 54 can be formed on the first barrier layer 52. The second barrier layer 54 can be formed using a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD)). The second barrier layer 54 can be formed of or include at least one of a metal material. For example, the second barrier layer 54 can be formed of or include titanium (Ti). A seed layer 56 can be formed on the second barrier layer 54. The seed layer 56 can be formed using a deposition process (e.g., PVD, CVD, or ALD). The seed layer 56 can be a layer to be used in a subsequent plating process. The seed layer 56 can be used to improve a deposition rate of a metal in the subsequent plating process. The seed layer 56 can be formed of or include at least one of a metal material. For example, the seed layer 56 can be formed of or include copper (Cu).

[0058] Referring to Figure 7B The first plating layer 58 and the second plating layer 60 can be sequentially formed on the seed layer 56. The first plating layer 58 and the second plating layer 60 can be formed using a plating process. In some embodiments, the first plating layer 58 can be formed of or include copper (Cu), and the second plating layer 60 can be formed of or include nickel (Ni). The first plating layer 58 and the second plating layer 60 can be formed in an in-situ manner.

[0059] A terminal pattern 62 can be formed on the second plating layer 60. As an example, the terminal pattern 62 can be formed by forming a metal layer on the second plating layer 60 and patterning the metal layer. In some embodiments, the formation of the terminal pattern 62 can include forming a sacrificial layer having a hole on the second plating layer 60, filling the hole with a metal material, and then removing the sacrificial layer. The terminal pattern 62 can be formed of or include at least one of a metal material (e.g., tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and bismuth (Bi)).

[0060] Referring to Figure 7CThe second plating layer 60, the first plating layer 58, and the seed layer 56 can be sequentially patterned using the terminal pattern 62 as an etching mask. Accordingly, the first metal pattern 306a, the second metal pattern 306b, and the metal film 308 can be sequentially formed on the second barrier layer 54. The terminal pattern 62 can be disposed on the metal film 308. The patterning process can be performed using a wet etching process. The wet etching process can be performed using a copper etching solution. Although the metal film 308 is illustrated as having a width greater than widths of the first metal pattern 306a and the second metal pattern 306b, the inventive concept is not limited to this example. For example, according to process conditions for an etching or patterning process, the metal film 308 can be formed to have a width less than or equal to widths of the first metal pattern 306a and the second metal pattern 306b. Since the copper etching solution has an etching selectivity with respect to the terminal pattern 62, the terminal pattern 62 can not be removed during the etching process.

[0061] Referring to Figure 7D The second barrier layer 54 and the first barrier layer 52 can be sequentially patterned using the terminal pattern 62, the metal film 308, and the first metal pattern 306a and the second metal pattern 306b as etching masks. Accordingly, the first barrier pattern 302 and the second barrier pattern 304 can be sequentially formed on the specific surface 4 of the third insulating layer 202c. The second barrier pattern 304 can be formed between the first barrier pattern 302 and the first metal pattern 306a. The patterning process can be performed using a wet etching process. The wet etching process can be performed using a titanium etching solution. If the wet etching process is performed using the titanium etching solution, an etching rate of the first barrier layer 52 can be lower than an etching rate of the second barrier layer 54. Accordingly, an etching amount of the second barrier pattern 304 can be greater than an etching amount of the first barrier pattern 302, and thus, the second barrier pattern 304 can be formed to have a width smaller than a width of the first barrier pattern 302. The first barrier pattern 302 can be formed to have a width smaller than widths of the first metal pattern 306a and the second metal pattern 306b.

[0062] According to some embodiments of the inventive concept, the first barrier pattern 302 formed of a metal nitride can be formed between the second barrier pattern 304 and the third insulating layer 202c, and this can enable protection / prevention of a reduction in adhesion strength between the second barrier pattern 304 and the third insulating layer 202c by a metal oxide, which can be formed between the third insulating layer 202c and the second barrier pattern 304 when the second barrier pattern 304 formed of a metal material is directly formed on the third insulating layer 202c.

[0063] Referring back to Figure 1The connection terminal 320 can be formed by performing a reflow process on the terminal pattern 62. The reflow process can be performed using a low-temperature process. The connection terminal 320 can be mounted on a first (e.g., top) surface of the board 2000. The connection terminal 320 can be electrically connected to the external terminal 500 formed on a second (e.g., bottom) surface of the board 2000 facing the first surface.

[0064] According to some embodiments of the inventive concepts, a metal nitride barrier layer can be formed between the insulating layer and the metal barrier layer of the redistribution, pad, or UBM layer. The metal nitride barrier layer can inhibit / prevent formation of a metal oxide layer between the metal barrier layer and the insulating layer. Thus, reliability of the semiconductor device can be improved.

[0065] While example embodiments of the inventive concepts have been particularly shown and described, ordinary skilled in the art will understand that changes can be made in form and details without departing from the scope of the claims.

Claims

1. A semiconductor device, comprising: a first insulating layer; a conductive element in the first insulating layer; a first barrier pattern in contact with a surface of the conductive element and a surface of the first insulating layer; a second blocking pattern on the first blocking pattern; as well as a first metal pattern, on the second barrier pattern, The width of the first barrier pattern is smaller than that of the first metal pattern. The width of the second barrier pattern is smaller than that of the first barrier pattern. wherein the second barrier pattern contacts a surface of the first barrier pattern, and The first barrier pattern includes a metal nitride, and the second barrier pattern includes a metal material.

2. The semiconductor device according to claim 1, wherein The first barrier pattern has a thickness in a range of 10Å to 100Å.

3. The semiconductor device according to claim 1 , further comprising: a metal film on the first metal pattern; as well as Connecting terminals, on and in contact with the metal film, wherein the first metal pattern comprises copper, and Wherein, the metal film includes nickel.

4. The semiconductor device according to claim 1, wherein The first insulating layer includes a polymer layer or an oxide layer.

5. The semiconductor device according to claim 1 , further comprising a connection terminal on the first metal pattern, in, The connection terminal does not cover side surfaces of the first barrier pattern and side surfaces of the second barrier pattern.

6. The semiconductor device according to claim 1, further comprising: a first metal film on the first metal pattern; a second metal film on the first metal film; as well as a connecting terminal on and in contact with the second metal film, Wherein, the first metal pattern comprises copper, wherein the first metal film comprises nickel, and Wherein, the second metal film includes gold.

7. The semiconductor device according to claim 1, wherein Conductive elements include: a third blocking pattern; a second metal pattern between the third barrier pattern and the first barrier pattern; and a fourth barrier pattern between the third barrier pattern and the second metal pattern, wherein the first barrier pattern contacts the second metal pattern, and The third barrier pattern includes metal nitride, and the fourth barrier pattern includes a metal material.

8. The semiconductor device according to claim 1, wherein Side surfaces of the first barrier pattern, the second barrier pattern, and the first metal pattern are flat surfaces, respectively.

9. The semiconductor device according to claim 1, wherein A side surface of the first barrier pattern, a side surface of the second barrier pattern, and a side surface of the first metal pattern are respectively uneven surfaces. 10 . The semiconductor device of claim 1 , further comprising a second insulating layer on the first insulating layer to cover side surfaces of the first barrier pattern, side surfaces of the second barrier pattern, and side surfaces of the first metal pattern.

11. The semiconductor device according to claim 1, wherein The conductive elements are vias, redistribution pieces, or pads.

12. The semiconductor device according to claim 1, wherein The first barrier pattern, the second barrier pattern, and the first metal pattern provide a redistribution, a pad, or an under bump metallurgy.

13. A semiconductor device, comprising: Insulation layer; Conductive elements, in an insulating layer; a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer; as well as The metal pattern, on the first barrier pattern, wherein the thickness of the first barrier pattern is in the range of 10Å to 100Å, Wherein, the first barrier pattern comprises metal nitride, The semiconductor device further includes a second barrier pattern between the metal pattern and the first barrier pattern, the second barrier pattern being in contact with a surface of the first barrier pattern and having a width smaller than that of the first barrier pattern, and Wherein, the second barrier pattern comprises metal material.

14. The semiconductor device according to claim 13, wherein A side surface of the first barrier pattern is not vertically aligned with a side surface of the metal pattern.

15. The semiconductor device according to claim 13, wherein A width of the metal pattern is greater than a width of the first barrier pattern.

16. A semiconductor package, comprising: plate; as well as a first semiconductor package mounted on a board, the first semiconductor package comprising a redistribution layer, a semiconductor chip on the redistribution layer, and a terminal structure between the redistribution layer and the board; The redistribution layer includes an insulating layer and conductive elements in the insulating layer. Among them, the terminal structure includes: a first barrier pattern and a second barrier pattern sequentially stacked on a surface of the conductive element and a surface of the insulating layer; a metal pattern on the second barrier pattern; and Connecting terminals, between metal pattern and board, The width of the second barrier pattern is smaller than the width of the first barrier pattern and the width of the metal pattern. wherein the second barrier pattern comprises titanium, wherein the second barrier pattern contacts a surface of the first barrier pattern, and Wherein, the first barrier pattern comprises metal nitride.

17. The semiconductor package according to claim 16, wherein The first barrier pattern includes titanium nitride.

18. The semiconductor package according to claim 16, wherein The thickness of the first barrier pattern is in the range of 10Å to 100Å.

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