Display Devices

Abstract

The present invention relates to a display device, comprising: a substrate; a first gate and a second gate, arranged on the substrate; a gate insulating layer, arranged on the first gate; a first active layer, arranged on the gate insulating layer and corresponding to the first gate, and comprising a polysilicon layer; a first insulating layer, arranged on the first active layer; a second active layer, arranged on the first insulating layer and corresponding to the second gate, and comprising a metal oxide layer; a first source, a first drain, a second source and a second drain, wherein the first source and the first drain are arranged on the first insulating layer and electrically connected to the first active layer through a plurality of through holes, and the second source and the second drain are arranged on the second active layer and electrically connected to the second active layer; and a conductive layer, covering the second source and the second drain.

Description

Technical Field

[0001] The main purpose of the present invention is to provide a display device, in particular a display device including both a low-temperature polysilicon thin-film transistor unit and a metal oxide thin-film transistor unit. Background Art

[0002] As display technology continues to advance, all display panels are developing towards a trend of small size, thin thickness, and light weight. Therefore, the mainstream display devices on the market have evolved from the previous cathode ray tubes to thin displays, such as liquid crystal display panels, organic light emitting diode display panels, or inorganic light emitting diode display panels. Among them, thin displays can be applied in many fields, including mobile phones, laptops, video cameras, cameras, music players, mobile navigation devices, televisions, etc., which are used in daily life. Most of them use these display panels.

[0003] Although liquid crystal display devices or organic light emitting diode display devices are common display devices on the market, especially liquid crystal display devices, the technology is quite mature. However, with the continuous development of display devices and the increasing demand of consumers for display quality, all manufacturers are striving to develop display devices with higher display quality. Among them, in addition to the thin film transistor structure on the display area, the thin film transistor component structure used in the gate drive circuit area in the non-display area is also a factor affecting the overall efficiency of the display device.

[0004] If both the display area and the gate drive circuit area use thin film transistor components, if the two are different thin film transistor components, the processes of the two will affect each other, and will also cause the overall process of the display device to be complicated (for example, more chemical vapor deposition processes are required). In view of this, it is still necessary to improve the thin film transistor component structure of the display area and the gate drive circuit area to simplify the process and structure of the two while having good thin film transistor component characteristics. Summary of the invention

[0005] The main purpose of the present invention is to provide a display device, which includes a low-temperature polysilicon thin film transistor unit and a metal oxide thin film transistor unit.

[0006] In one embodiment of the present invention, a display device may include: a substrate; a first gate and a second gate, disposed on the substrate; a gate insulating layer, disposed on the first gate; a first active layer, disposed on the gate insulating layer and corresponding to the first gate, wherein the first active layer includes a polysilicon layer; a first insulating layer, disposed on the first active layer; a second active layer, disposed on the first insulating layer and corresponding to the second gate, wherein the second active layer includes a metal oxide layer; a first source, a first drain, a second source and a second drain, wherein the first source and the first drain are disposed on the first insulating layer and electrically connected to the first active layer through a plurality of through holes, and the second source and the second drain are disposed on the second active layer and electrically connected to the second active layer; and a conductive layer, wherein the conductive layer covers the second source and the second drain.

[0007] As can be seen from the foregoing, the display device of the present invention includes a first thin film transistor unit whose first active layer is a polysilicon layer and a second thin film transistor unit whose second active layer is a metal oxide layer. In particular, by adjusting the relationship between the first and second active layers and the gate insulating layer and the first insulating layer, the component structure on the substrate can be simplified, and the process of forming the first and second thin film transistor units can be simplified; at the same time, the first and second thin film transistor units obtained can still maintain good thin film transistor unit characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a top view of a display device according to Embodiment 1 of the present invention;

[0009] Figure 1B is a cross-sectional schematic diagram of a display device according to Embodiment 1 of the present invention;

[0010] Figures 2A to 2G is a cross-sectional schematic diagram of a manufacturing process of components on a substrate of a display device according to Embodiment 1 of the present invention;

[0011] FIG. 3A to FIG. 3E is a cross-sectional schematic diagram of a manufacturing process of components on a substrate of a display device according to Embodiment 2 of the present invention;

[0012] Figure 4 is a cross-sectional schematic diagram of a display device according to Embodiment 2 of the present invention;

[0013] FIG. 5A to FIG. 5H is a cross-sectional schematic diagram of a manufacturing process of components on a substrate of a display device according to Embodiment 3 of the present invention;

[0014] Fig. 6A is a cross-sectional schematic diagram of a display device according to Embodiment 4 of the present invention;

[0015] Figure 6Bis a partial layer-by-layer top view of a second thin film transistor unit of a display device according to Embodiment 4 of the present invention;

[0016] FIG. 7A to FIG. 7G is a cross-sectional schematic diagram of a manufacturing process of components on a substrate of a display device according to Embodiment 5 of the present invention;

[0017] Fig. 8A is a cross-sectional schematic diagram of a display device according to Embodiment 6 of the present invention;

[0018] Figure 8B is a partial layer-by-layer top view of a second thin film transistor unit of a display device according to Embodiment 6 of the present invention;

[0019] Fig. 9 is a cross-sectional schematic diagram of a display device according to Embodiment 7 of the present invention;

[0020] Fig.10 is a cross-sectional schematic diagram of a display device according to Embodiment 8 of the present invention;

[0021] Fig.11 is a cross-sectional schematic diagram of a display device according to Embodiment 9 of the present invention;

[0022]

Explanation of symbols

[0023] 1 first substrate 11 substrate

[0024] 121 first gate 122, 122' second gate

[0025] 123 first conductive layer 124 second conductive layer

[0026] 125 scanning line 125a through hole

[0027] 13 Gate insulating layer 131 Bottom gate insulating layer

[0028] 132 top gate insulating layer 14 amorphous silicon layer

[0029] 14' Polysilicon layer 141 Source region

[0030] 142 drain region 143 channel region

[0031] 145 amorphous silicon layer 146 doped amorphous silicon layer

[0032] 15 first insulating layer 151 first bottom insulating layer

[0033] 152 first top insulating layer 16 second active layer

[0034] 171 First source 171a, 172a Through hole

[0035] 172 first drain 173 second source

[0036] 174 second drain electrode 175 fourth conductive layer

[0037] 18 second insulating layer 19 pixel electrode

[0038] 19a Contact hole 2 Second substrate

[0039] 21,21',22 Mask 3 Display dielectric layer

[0040] AA Display area B Peripheral area

[0041] H1, H2 Distance TFT1 First thin film transistor unit

[0042] TFT2 Second thin film transistor unit SL Scan line DETAILED DESCRIPTION

[0043] The following is an explanation of the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways for different viewpoints and applications without departing from the spirit of the present invention.

[0044] Furthermore, the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify the components of the claims, do not themselves imply or represent any previous ordinal numbers of the claimed components, nor do they represent the order of one claimed component and another claimed component, or the order in the manufacturing method. The use of these ordinals is only used to clearly distinguish a claimed component with a certain name from another claimed component with the same name.

[0045] Example 1

[0046] Figure 1A and Figure 1B They are respectively a top view and a cross-sectional schematic diagram of the display device of the present embodiment. The display device of the present embodiment comprises: a first substrate 1; a second substrate 2, arranged opposite to the first substrate 1; and a display medium layer 3, arranged between the first substrate 1 and the second substrate 2. The display device may include: a display area AA; and a peripheral area B, arranged around the display area AA. Here, the so-called peripheral area B is the area where the wiring is distributed, such as: the gate drive circuit area; and the so-called display area AA is the area where the pixel units are distributed.

[0047] Figures 2A to 2GFIG. 1 is a cross-sectional schematic diagram of the manufacturing process of components on a substrate of a display device of this embodiment, for example, the manufacturing process of components on a first substrate 1. First, as Figure 2A As shown, a substrate 11 is provided, and a first gate 121 and a second gate 122 are formed on the substrate 11. Here, the substrate 11 is made of a base material such as glass, plastic, or a flexible material; and the first gate 121 and the second gate 122 can be made of a metal material such as Cu or Al. Then, a gate insulating layer 13 is formed on the substrate 11, the first gate 121, and the second gate 122. In this embodiment, the gate insulating layer 13 includes a bottom gate insulating layer 131 and a top gate insulating layer 132, and the bottom gate insulating layer 131 is disposed between the substrate 11 and the top gate insulating layer 132, and the material of the bottom gate insulating layer 131 is silicon nitride, and the material of the top gate insulating layer 132 is silicon oxide. Next, an amorphous silicon layer 14 is formed on the gate insulating layer 13.

[0048] like Figure 2B As shown in FIG. 1 , the amorphous silicon layer 14 can be converted into a polysilicon layer 14′ by a laser sintering process and a channel doping process. Figure 2C As shown, the polysilicon layer 14' is patterned using a mask 21 made of photoresist, and the formed polysilicon layer 14' corresponds to the first gate 121. Then, as shown in FIG. Figure 2D As shown, a mask 21' is used to perform n+ or p+ doping process, which can make Figure 2C The polysilicon layer 14 ′ is transformed into a doped source region 141 , a drain region 142 and a channel region 143 ; wherein the channel region 143 is located between the source region 141 and the drain region 142 .

[0049] After removing the mask 21, Figure 2E As shown, in the first active layer (polysilicon layer 14 ′ (refer to Figure 2C ), including the source region 141, the drain region 142 and the channel region 143) and a first insulating layer 15 is formed on the gate insulating layer 13. In the present embodiment, the first insulating layer 15 includes a first bottom insulating layer 151 and a first top insulating layer 152, and the first bottom insulating layer 151 is disposed between the gate insulating layer 13 and the first top insulating layer 152; wherein the material of the first bottom insulating layer 151 is silicon nitride, and the material of the first top insulating layer 152 is silicon oxide. Then, a patterned second active layer 16 is formed on the first insulating layer 15 and in the region corresponding to the second gate 122; wherein the second active layer 16 is an oxide metal layer, such as an IGZO layer.

[0050] like Figure 2F As shown, the first active layer (polysilicon layer 14 '(refer to Figure 2C), including a source region 141, a drain region 142 and a channel region 143), a first source 171, a first drain 172, a second source 173 and a second drain 174 are formed on the first insulating layer 15 and the second active layer 16, and the materials of the first source 171, the first drain 172, the second source 173 and the second drain 174 can be, for example, Cu or Al. The first source 171 and the first drain 172 are disposed on the first insulating layer 15 and are connected to the polysilicon layer 14′ (refer to Figure 2C ) are electrically connected to the source region 141 and the drain region 142, and the second source 173 and the second drain 174 are disposed on the second active layer 16 and electrically connected to the second active layer 16.

[0051] Then, if Figure 2G As shown, a second insulating layer 18 is formed on the first source 171, the first drain 172, the second source 173 and the second drain 174, and then a pixel electrode 19 is formed on the second insulating layer 18, and the pixel electrode 19 is electrically connected to the second drain 174 through a contact hole 19a. Here, the second insulating layer 18 can have a single-layer structure composed of silicon oxide, or a double-layer structure with a lower layer of silicon oxide and an upper layer of silicon nitride, or a multi-layer structure with an organic material layer stacked on top of the double-layer structure. In addition, the material of the pixel electrode 19 can use transparent conductive oxides such as ITO and IZO.

[0052] After the above process, the components on the substrate 11 are completed. Figure 2G As shown, the display device of this embodiment includes: a substrate 11; a first gate 121 and a second gate 122, which are disposed on the substrate 11; a gate insulating layer 13, which is disposed on the substrate 11, the first gate 121 and the second gate 122; a first active layer (polysilicon layer 14' (refer to Figure 2C), including a source region 141, a drain region 142 and a channel region 143), which is disposed on the gate insulating layer 13 and corresponds to the first gate 121; a first insulating layer 15, which is disposed on the first active layer and the gate insulating layer 13; a second active layer 16, which is disposed on the first insulating layer 15 and corresponds to the second gate 122, wherein the second active layer 16 is a metal oxide layer (in this embodiment, an IGZO layer); and a first source 171, a first drain 172, a second source 173 and a second drain 174, wherein the first source 171 and the first drain 172 are disposed on the first insulating layer 15 and are connected to the second gate 122 by a through hole. The holes 171a, 172a are electrically connected to the source region 141 and the drain region 142 of the first active layer, and the second source 173 and the second drain 174 are arranged on the second active layer 16 and are electrically connected to the second active layer 16; wherein, the first gate 121, the gate insulating layer 13, the first active layer 14′, the first insulating layer 15, the first source 171 and the first drain 172 constitute a first thin film transistor unit TFT1, and the second gate 122, the gate insulating layer 13, the first insulating layer 15, the second active layer 16, the second source 173 and the second drain 174 constitute a second thin film transistor unit TFT2.

[0053] In this embodiment, the display device includes a first thin film transistor unit TFT1 whose first active layer is a polysilicon layer and a second thin film transistor unit TFT2 whose second active layer 16 is a metal oxide layer. In particular, in this embodiment, by adjusting the relationship between the first active layer and the second active layer 16 and the gate insulating layer 13 and the first insulating layer 15, the process steps can be reduced, and the processes of forming a low-temperature polysilicon thin film transistor unit (i.e., the first thin film transistor unit TFT1) and an oxide metal (e.g., IGZO) thin film transistor unit (i.e., the second thin film transistor unit TFT2) can be avoided to affect each other. At the same time, in the obtained display device, the component structure on the substrate 11 can be further simplified.

[0054] Furthermore, there is a thicker insulating layer between the second gate electrode 122 of the metal oxide thin film transistor unit TFT2 and the second active layer 16, that is, the first gate electrode of the first thin film transistor unit TFT1 and the first active layer (polysilicon layer 14', see Figure 2C ) is smaller than the distance H2 between the second gate electrode 122 of the second thin film transistor unit TFT2 and the second active layer 16.

[0055] In addition, since the first thin film transistor unit TFT1 and the second thin film transistor unit TFT2 are both thin film transistor units with a bottom gate structure, it is not necessary to additionally set a light shielding layer on the substrate 11, thereby reducing process steps and simplifying the device structure.

[0056] In particular, in the display device of this embodiment, if Figure 2G As shown, the gate insulating layer 13 includes a bottom gate insulating layer 131 and a top gate insulating layer 132. The bottom gate insulating layer 131 is disposed between the substrate 11 and the top gate insulating layer 132, and the material of the bottom gate insulating layer 131 is silicon nitride, while the material of the top gate insulating layer 132 is silicon oxide. In addition, the first insulating layer 15 includes a first bottom insulating layer 151 and a first top insulating layer 152. The first bottom insulating layer 151 is disposed between the gate insulating layer 13 and the first top insulating layer 152, and the material of the first bottom insulating layer 151 is silicon nitride, while the material of the first top insulating layer 152 is silicon oxide. Therefore, in the display device of this embodiment, the first active layer (polysilicon layer 14′ (refer to Figure 2C ), including a source region 141, a drain region 142 and a channel region 143), which is covered by a first bottom insulating layer 151 formed by silicon nitride, so that the component characteristics of the low-temperature polysilicon thin film transistor unit can be maintained; and the second active layer 16 formed by a metal oxide (such as IGZO) layer is arranged on the first top insulating layer 152 formed by silicon oxide, so that the component characteristics of the metal oxide thin film transistor unit can be maintained.

[0057] In addition, if Figure 1A , Figure 1B and Figure 2G As shown, in the display device of this embodiment, the first thin film transistor unit TFT1 is arranged in the peripheral area B to serve as a line switch; and the second thin film transistor unit TFT2 is arranged in the display area AA to serve as a pixel electrode 19 switch.

[0058] Example 2

[0059] In Example 1, Figure 2G As shown, the first gate 121 and the second gate 122 are made of the same material, which can be Cu or Al. The structure of the display device of this embodiment is similar to that of Embodiment 1, except that the structures and materials of the first gate 121 and the second gate 122 are different.

[0060] Figures 3A to 3E FIG. 1 is a cross-sectional schematic diagram of the manufacturing process of the first gate electrode and the second gate electrode on the substrate of the display device of this embodiment. Figure 3A As shown, a substrate 11 is provided, on which a first conductive layer 123 and a second conductive layer 124 are sequentially formed. Then, a first mask 21 made of photoresist is formed in a region where the first thin film transistor unit TFT1 is to be formed, and a second mask 22 made of photoresist is formed in a region where the second thin film transistor unit TFT2 is to be formed, using, for example, a half tone mask. Figure 3BAs shown, the first conductive layer 123 and the second conductive layer 124 are etched; and then the masks 21 and 22 are ashed. Figure 3C and removing the second conductive layer 124 in the region where the first thin film transistor unit TFT1 is to be formed by etching, as shown in FIG. Figure 3D Finally, the mask 22 is removed, and the first gate 121 and the second gate 122 of this embodiment are completed.

[0061] After forming the first gate electrode 121 and the second gate electrode 122, the process of the thin film transistor unit is similar to that of the first embodiment (eg Figures 2A to 2G As shown in the figure), it will not be described here again.

[0062] After the above-mentioned processes, the display device of this embodiment can be obtained. Figure 4 As shown, the display device of this embodiment is different from that of Embodiment 1 in that, in this embodiment, the first gate 121 is formed by a first conductive layer 123, and the second gate 122 is formed by the first conductive layer 123 and a second conductive layer 124 being sequentially stacked on the substrate 11, and the second conductive layer 124 completely covers the first conductive layer 123. In this embodiment, the material of the first conductive layer 123 is preferably selected from high heat-resistant metal materials such as Ti, Cr, Mo, or transparent conductive oxides such as ITO, IZO, etc.; this can prevent the subsequent laser process for forming polysilicon from damaging the first gate 121; and the second conductive layer 124 can be selected from metal materials such as Cu or Al, in addition to high heat-resistant metal materials such as Ti, Cr, Mo, or transparent conductive oxides.

[0063] Therefore, in this embodiment, since the first gate 121 is made of only the first conductive layer 123, the thickness of the first gate 121 can be reduced, so that the thickness of the first gate 121 is less than the thickness of the second gate 122. At the same time, since the first conductive layer 123 is made of a highly heat-resistant metal material or a transparent conductive oxide, the first gate 121 can be prevented from being damaged by subsequent laser processes.

[0064] Example 3

[0065] The structure of the display device of this embodiment is different from that of Embodiment 1 in that the components above the substrate 11 are different. FIG. 5A to FIG. 5H FIG. 1 is a cross-sectional diagram of the manufacturing process of the components on the substrate of the display device of this embodiment. Figure 5A As shown, a substrate 11 is provided, and a first gate 121 is formed on the substrate 11. Here, the substrate 11 is made of a base material such as glass, plastic, or a flexible material; and the first gate 121 can be made of a high heat-resistant metal material such as Ti, Cr, or Mo, or a transparent conductive oxide.

[0066] like Figure 5BAs shown, a gate insulating layer 13 is formed on the substrate 11 and the first gate 121. In this embodiment, the gate insulating layer 13 includes a bottom gate insulating layer 131 and a top gate insulating layer 132. The bottom gate insulating layer 131 is disposed between the substrate 11 and the top gate insulating layer 132, and the material of the bottom gate insulating layer 131 is silicon nitride, while the material of the top gate insulating layer 132 is silicon oxide. Then, an amorphous silicon layer 14 is formed on the gate insulating layer 13.

[0067] like Figure 5C As shown in FIG. 1 , the amorphous silicon layer 14 can be converted into a polysilicon layer 14′ by a laser sintering process and a channel doping process. Figure 5D As shown, the polysilicon layer 14' is patterned using a mask 21 made of photoresist so that the polysilicon layer 14' is arranged corresponding to the first gate 121, and then the mask 21 (which can be the same as the mask used when patterning the polysilicon layer 14', or a mask 21 formed separately) is used to perform an n+ or p+ doping process, so that the polysilicon layer 14' includes a source region 141, a drain region 142 and a channel region 143, as shown in FIG. Figure 5D shown.

[0068] After removing the mask 21, Figure 5E As shown, a second gate 122 is formed on the gate insulating layer 13, which can be made of metal materials such as Cu or Al. Then, a second gate 122 is formed on the polysilicon layer 14' (including the source region 141, the drain region 142 and the channel region 143) (refer to Figure 5C ) and the second gate 122 to form a first insulating layer 15. In this embodiment, the first insulating layer 15 includes a first bottom insulating layer 151 and a first top insulating layer 152, and the first bottom insulating layer 151 is disposed between the gate insulating layer 13 and the first top insulating layer 152; wherein the material of the first bottom insulating layer 151 is silicon nitride, and the material of the first top insulating layer 152 is silicon oxide. Then, a second active layer 16 is formed on the first insulating layer 15 and in a region corresponding to the second gate 122; wherein the second active layer 16 is an oxide metal layer, such as an IGZO layer.

[0069] like Figure 5G and Figure 5H As shown, the subsequent processes of forming the first source 171 , the first drain 172 , the second source 173 , the second drain 174 , a second insulating layer 18 and a pixel electrode 19 are similar to those in Embodiment 1, and thus will not be described again.

[0070] After the above process, the components on the substrate 11 are completed. Figure 5HAs shown, the display device of this embodiment includes: a substrate 11; a first gate 121, which is arranged on the substrate 11; a gate insulating layer 13, which is arranged on the substrate 11 and the first gate 121; a first active layer (polysilicon layer, including a source region 141, a drain region 142 and a channel region 143), which is arranged on the gate insulating layer 13 and corresponds to the first gate 121, wherein the first active layer is a polysilicon layer; a second gate 122, which is arranged on the gate insulating layer 13; a first insulating layer 15, which is arranged on the first active layer and the second gate 122; a second active layer 16, which is arranged on the first insulating layer 15 and corresponds to the second gate 122, wherein The second active layer 16 is a metal oxide layer (in this embodiment, an IGZO layer); and a first source 171, a first drain 172, a second source 173 and a second drain 174, wherein the first source 171 and the first drain 172 are disposed on the first insulating layer 15 and are electrically connected to the source region 141 and the drain region 142 of the first active layer through the through holes 171a, 172a, and the second source 173 and the second drain 174 are disposed on the second active layer 16 and are electrically connected to the second active layer 16; wherein the first gate 121, the gate insulating layer 13, the first active layer (polysilicon layer 14′, refer to Figure 5C ), the first insulating layer 15, the first source 171 and the first drain 172 constitute a first thin film transistor unit TFT1, and the second gate 122, the first insulating layer 15, the second active layer 16, the second source 173 and the second drain 174 constitute a second thin film transistor unit TFT2.

[0071] Similar to the display device of the first embodiment, in this embodiment, the display device includes a first thin film transistor unit TFT1 whose first active layer is a polysilicon layer and a second thin film transistor unit TFT2 whose second active layer 16 is a metal oxide layer. The biggest difference between the display device structures of this embodiment and the first embodiment is that in this embodiment, the second gate 122 is formed on the gate insulating layer 13, such as Figure 5H As shown; in Embodiment 1, the second gate 122 is formed below the gate insulating layer 13, as shown Figure 2G In addition, another difference between the display device structures of this embodiment and embodiment 1 is that in this embodiment, the first gate 121 is made of a highly heat-resistant metal material such as Ti, Cr, Mo, or a transparent conductive oxide, which can prevent the first gate 121 from being damaged by the laser process and reduce the thickness of the first gate 121.

[0072] Example 4

[0073] Fig. 6A is a cross-sectional schematic diagram of the display device of this embodiment; and Figure 6BIt is a partial top view of the second thin film transistor unit, which shows the relationship between the second gate electrode 122', the scan line 125, the second active layer 16, the second source electrode 173 and the second drain electrode 174. The structure of the display device of this embodiment is similar to that of the embodiment 3, except for the following differences.

[0074] In the third embodiment, the second gate 122 can be made of metal materials such as Cu or Al. Figure 5H As shown. However, in this embodiment, the material of the second gate 122' is polysilicon. More specifically, when forming the first active layer (polysilicon layer, including the source region 141, the drain region 142 and the channel region 143), polysilicon is also formed on the region where the second thin film transistor unit TFT2 is to be formed; and the polysilicon formed on the region of the second thin film transistor unit TFT2 is also heavily doped with n+ to form the second gate 122' of this embodiment.

[0075] In addition, in this embodiment, while forming the first source 171 , the first drain 172 , the second source 173 and the second drain 174 , a scan line 125 is also formed on the first insulating layer 15 , and the scan line 125 is electrically connected to the second gate 122 ′ through a through hole 125 a .

[0076] Example 5

[0077] The structure of the display device of this embodiment is similar to that of Embodiment 1, except that the structure and material of the second gate electrode 122 are different.

[0078] Figures 7A to 7G FIG. 1 is a cross-sectional diagram of the manufacturing process of the components on the substrate of the display device of this embodiment. Fig. 7A As shown, a substrate 11 is provided, on which a first conductive layer 123 and a second conductive layer 124 are sequentially formed. Then, a first mask 21 made of photoresist is formed in a region where the first thin film transistor unit TFT1 is to be formed using a half-tone mask, and a first mask 22 is formed in a region where the second thin film transistor unit TFT2 and the scanning line SL are to be formed. Next, as Figure 7B As shown, the first conductive layer 123 and the second conductive layer 124 are etched; the masks 21 and 22 are then ashed, and the second conductive layer 124 in the area where the first thin film transistor unit TFT1 and the second thin film transistor unit TFT2 are to be formed is removed by etching. Figure 7C Finally, the mask 22 is removed, and the first gate 121 and the second gate (the first conductive layer 123 and the second conductive layer 124 located in the region of the second thin film transistor unit TFT2) of this embodiment are completed. Fig.7D shown.

[0079] In this embodiment, the first gate 121 is formed by the first conductive layer 123, and the second gate is formed by stacking the first conductive layer 123 and the second conductive layer 124 in sequence on the substrate 11, and the second conductive layer 124 partially covers the first conductive layer 123. The second gate in the second thin film transistor unit TFT2 region is composed of the first conductive layer 123, and the second gate in the scan line SL region is composed of the first conductive layer 123 and the second conductive layer 124. The material of the first conductive layer 123 includes Ti, Cr, Mo or a transparent conductive oxide, and the material of the second conductive layer 124 includes Cu, Al, Ti, Cr, Mo or a transparent conductive oxide.

[0080] After forming the first gate 121 and the second gate, a first active layer (polysilicon layer, including a source region 141, a drain region 142 and a channel region 143), a first insulating layer 15 and a second active layer 16 are sequentially formed using a process similar to that of Embodiment 1. Fig.7D and Fig. 7E The second conductive layer 124 partially covers the first conductive layer 123 , and the region of the first conductive layer 123 not covered by the second conductive layer 124 corresponds to the second active layer 16 .

[0081] Then, if Figure 7F As shown, a first source 171, a first drain 172, a second source 173 and a second drain 174 are formed using a process similar to that of Embodiment 1, except that the materials and structures are different. In this embodiment, the first source 171 and the first drain 172, the second source 173 and the second drain 174 are formed by a third conductive layer such as Ti, Cr, Mo or a transparent conductive oxide; and a fourth conductive layer 175 such as Cu or Al partially covers at least one of the second source 173 and the second drain 174. In this embodiment, the fourth conductive layer 175 is formed on the second source 173 to serve as a data line.

[0082] Finally, if Figure 7G As shown, a second insulating layer 18 and a pixel electrode 19 are formed by using a process similar to that of Embodiment 1, thereby completing the production of various components on the substrate 11 of this embodiment.

[0083] Example 6

[0084] Fig. 8A is a cross-sectional schematic diagram of the display device of this embodiment; and Figure 8B It is a partial top view of the second thin film transistor unit, which shows the relationship between the second conductive layer 124 of the second gate, the second active layer 16, the second source 173, the second drain 174 and the fourth conductive layer 175. The process and structure of this embodiment are similar to those of the fifth embodiment, except for the following differences.

[0085] First, in the region of the second thin film transistor unit TFT2, the second conductive layer 124 completely covers the first conductive layer 123; and this portion can be made of the same material as in the second embodiment. FIG. 3A to FIG. 3E In addition, in the region of the second thin film transistor unit TFT2, a fourth conductive layer 175 such as Cu or Al not only partially covers the second source 173 as in the fifth embodiment, but also partially covers the second drain 174.

[0086] Example 7

[0087] Fig. 9 1 is a cross-sectional view of the display device of this embodiment. The process and structure of this embodiment are similar to those of Embodiment 6, except that the fourth conductive layer 175 is only formed on the second source electrode 173 , but not on the second drain electrode 174 .

[0088] Example 8

[0089] Fig.10 2 is a cross-sectional schematic diagram of the display device of this embodiment. The process and structure of this embodiment are similar to those of Embodiment 1, except for the following differences.

[0090] In the display device of this embodiment, on the first thin film transistor unit TFT1, the first active layer may further include an amorphous silicon layer 145 and a doped amorphous silicon layer 146, wherein the amorphous silicon layer 145 and the doped amorphous silicon layer 146 are sequentially disposed on the source region 141 and the drain region 142 of the polycrystalline silicon layer. In this way, the leakage current of the low temperature polycrystalline silicon thin film transistor unit can be reduced.

[0091] Example 9

[0092] Fig.11 1 is a cross-sectional view of the display device of this embodiment. This embodiment is similar to the process and structure of Embodiment 9, except that the amorphous silicon layer 145 is further disposed on the channel region 143 of the polysilicon layer.

[0093] The amorphous silicon layer 145 and the doped amorphous silicon layer 146 of the aforementioned embodiments 8 and 9 may be disposed on the display device of the embodiment 1 as well as the display devices of the embodiments 1 to 7.

[0094] In the present invention, the display device manufactured in the above-mentioned embodiment can be used in combination with a touch panel to serve as a touch display device. At the same time, the display device or touch display device manufactured in the above-mentioned embodiment of the present invention can be applied to any electronic device that needs a display screen known in the art, such as a display, a mobile phone, a notebook computer, a video camera, a camera, a music player, a mobile navigation device, a television, and other electronic devices that need to display images.

[0095] The above embodiments are merely examples for the convenience of description. The scope of rights claimed by the present invention should be based on the claims, but not limited to the above embodiments.

Claims

1. A display device, characterized in that: include: a substrate; A first gate and a second gate are disposed on the substrate; A gate insulating layer, disposed on the first gate; a first active layer, disposed on the gate insulating layer and corresponding to the first gate, wherein the first active layer comprises a polysilicon layer; a first insulating layer, disposed on the first active layer; a second active layer, disposed on the first insulating layer and corresponding to the second gate, wherein the second active layer comprises a metal oxide layer; a first source, a first drain, a second source and a second drain, wherein the first source and the first drain are disposed on the first insulating layer and electrically connected to the first active layer through a plurality of through holes, and the second source and the second drain are disposed on the second active layer and electrically connected to the second active layer; and a conductive layer, wherein the conductive layer covers the second source and the second drain; The display device includes a display area and a peripheral area, the peripheral area is arranged around the display area, the first active layer is arranged in the peripheral area, and the second active layer is arranged in the display area; the conductive layer includes Al or Cu.

2. The display device according to claim 1, characterized in that The first insulating layer includes a first top insulating layer, and the material of the first top insulating layer is silicon oxide.

3. The display device according to claim 1, characterized in that The distance between the first gate and the first active layer is smaller than the distance between the second gate and the second active layer.

4. The display device according to claim 1, characterized in that The first source, the first drain, the second source and the second drain include Ti, Cr, Mo or transparent conductive oxide.

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