A flow-type dynamic display light control circuit

Abstract

The present invention discloses a flow-type dynamic display light control circuit, comprising: a control signal generating unit for generating a clock signal group; a driving control unit, comprising a plurality of driving control subunits with the same structure and cascaded, each driving control subunit corresponding to a first-level LED light group lighting. The present invention optimizes the circuit structure, utilizes an externally input clock signal and a control signal having a timing relationship with the clock signal, or a pull-down control signal generated inside the circuit, controls the driving control subunits of each level to work sequentially, thereby controlling the corresponding LED light groups to light up sequentially, and realizing a streamer effect, without the need to use a multi-channel D flip-flop, effectively saving costs, optimizing the product's cost performance, and having promotion value.

Description

Technical Field

[0001] The invention relates to the field of control technology, and in particular to a low-power, low-cost flow-type dynamic display light control circuit. Background Art

[0002] With the development of the national economy, cars are appearing in more and more families. With the rapid development of the automobile industry, people's requirements for cars are getting higher and higher. In the automobile lighting system, automobile display lights can be divided into two types, indicator lights and decorative lights. Indicator lights can indicate the driving status of the car, such as turn signals; decorative lights play a role in improving the appearance of the vehicle and can be installed in many parts of the car, such as door handles.

[0003] With the development of LED lighting technology, LEDs have also begun to be widely used in automotive lighting systems. People have begun to pursue more dazzling display effects, and flowing dynamic display lights have gradually been used in indicator lights and decorative lights. At present, there are sequential flow turn signal functions similar to the effect of a marquee on the headlights and taillights of cars. In order to unify the display effect of the flow turn signal on the headlights and taillights, the turn signal on the exterior rearview mirror also needs to be made into a flow turn signal.

[0004] Please refer to Figure 1 , a schematic diagram of the architecture of an existing flow-type dynamic display light control circuit. The control circuit includes: a clock generation oscillation unit 11, a data shift unit 12, a drive unit 13 and an LED light source group 14. The clock generation oscillation unit 11 uses a 555 periodic pulse generation chip to generate a clock signal and a data signal. The data shift unit 12 uses an 8-bit integrated D flip-flop chip (such as 74HC273 or 74HC595) to generate a drive control signal according to the period of the clock signal. The drive unit 13 uses a triode to drive the corresponding LED lights in the LED light source group 14 to dynamically light up according to the drive control signal. That is, each D flip-flop is controlled in turn according to the period of the clock signal, and each D flip-flop controls a triode to drive an LED light, thereby achieving a flow display effect in which the LED lights are lit one by one.

[0005] At present, the power supply voltage standard of most automobile bodies is generally 9V-16V. The conduction voltage drop of an LED is generally 1.9V-2.7V. Taking the middle value of 2.3V, the conduction voltage drop of 4 LEDs will be 2.3*4=9.2V, which is greater than the lower limit of the body power supply voltage of 9V. Therefore, in a body system powered by 9V-16V, at most 3 LEDs can be connected in series, that is, the output of a D flip-flop can only drive 3 LEDs at most. For a flow-type dynamic display lamp with a relatively large number of LED lights, such as 9-24 LED lights, multiple 8-way D flip-flop chips are required, which requires a high cost. In addition, the 8-way D flip-flop chip itself occupies a certain space, and its eight output ports need to be individually wired to the transistors corresponding to each LED light. When the circuit board space is relatively small, it is impossible to provide the required space for the chip and the eight output port leads, which brings difficulties to the circuit layout design.

[0006] Therefore, how to use a relatively simple circuit structure to achieve the control of streamer turn signals, optimize the control effect and reduce the control cost has become a technical problem that needs to be urgently solved in the development of streamer turn signals. Summary of the invention

[0007] The purpose of the present invention is to provide a flow-type dynamic display light control circuit to address the technical problems existing in the prior art, which can use a relatively simple circuit structure to achieve dynamic control of the dynamic display light, optimize the control effect and reduce the control cost.

[0008] To achieve the above-mentioned purpose, the present invention provides a flow-type dynamic display light control circuit, comprising: a control signal generating unit, used to generate a clock signal group, wherein the clock signal group includes a clock signal and a control signal having a timing relationship with the clock signal; a driving control unit, comprising a plurality of driving control subunits having the same structure and being cascaded, wherein each driving control subunit corresponds to controlling the lighting of a first-level LED light group; wherein the first-level driving control subunit is used to drive the corresponding LED sub-light group in the first-level LED light group to dynamically light up according to a first power supply voltage and the clock signal group, and to maintain the lighting result of the last group of LED sub-light groups in the first-level LED light group according to a second power supply voltage and the lighting result of the last group of LED sub-light groups in the first-level LED light group. The nth-level driving control subunit is used to control the lighting status of all LED sub-lamp groups in the first-level LED lamp group, and provide a pull-down control signal to the next-level driving control subunit so that the corresponding LED sub-lamp group in the corresponding next-level LED lamp group supports dynamic lighting; the nth-level driving control subunit is used to drive the corresponding LED sub-lamp group in the corresponding nth-level LED lamp group to dynamically light up according to the first power supply voltage, the clock signal group and the pull-down control signal provided by the previous-level driving control subunit, and maintain the lighting status of all LED sub-lamp groups in the nth-level LED lamp group according to the second power supply voltage and the lighting result of the last group of LED sub-lamp groups in the nth-level LED lamp group, and provide a pull-down control signal to the next-level driving control subunit.

[0009] The advantages of the present invention are: by optimizing the circuit structure, the present invention does not need to use a multi-way D flip-flop, and can realize the dynamic lighting function of the dynamic display light by using simple components and circuit architecture, which effectively saves costs, optimizes the cost performance of the product, and has promotion value. The dynamic display light can replace the traditional static display light and be used for indication or decoration. For example, the dynamic display light can replace the static indicator light of the existing car to indicate the driving status of the car and achieve the streamer steering effect; the dynamic display light can also replace the static decorative light of the existing car and be installed on the door handle of the car and other parts to achieve the streamer decoration effect and improve the aesthetics of the car. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 , a schematic diagram of the architecture of the existing flow-type dynamic display light control circuit;

[0011] Figure 2 , a schematic diagram of the structure of the flow-type dynamic display light control circuit of the present invention;

[0012] Figure 3 , a circuit diagram of an embodiment of a control signal generating unit of the present invention;

[0013] Figure 4 , a circuit diagram of a first embodiment of a flow-type dynamic display light control circuit of the present invention;

[0014] Figure 5 , a circuit diagram of a second embodiment of a flow-type dynamic display light control circuit of the present invention;

[0015] Figure 6 , a circuit diagram of a third embodiment of a flow-type dynamic display light control circuit of the present invention;

[0016] Figure 7 , a circuit diagram of a fourth embodiment of a flow-type dynamic display light control circuit of the present invention;

[0017] Figure 8 , a circuit diagram of a fifth embodiment of a flow-type dynamic display light control circuit of the present invention;

[0018] Fig. 9 , a schematic diagram of an embodiment of an LED lamp assembly of the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. In addition, the present invention repeats reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0020] Please refer to Figure 2 , a schematic diagram of the structure of the flow-type dynamic display light control circuit of the present invention. The circuit comprises: a control signal generating unit 21 and a driving control unit 22.

[0021] The control signal generating unit 21 is used to generate a clock signal group, and the clock signal group includes a clock signal and a control signal having a timing relationship with the clock signal. Since the control signal has a strict timing relationship with the clock signal, these control signals can be derived from the clock signal, and the control signal and the clock signal together form a clock signal group. The clock signal group can be formed by using a 555 chip plus a resistor and capacitor component, or by using a voltage comparator plus a resistor and capacitor component. Specifically, the clock signal can be generated first, and then other control signals can be derived.

[0022] The driving control unit 22 includes multiple stages of driving control subunits (221, 222, ..., 22n) with the same structure and connected in cascade, and each stage of driving control subunits controls the lighting of a corresponding stage of LED light groups (231, 232, ..., 23n).

[0023] Specifically, the first-level driving control subunit 221 is used to drive the corresponding LED sub-lamp group in the corresponding first-level LED lamp group 231 to dynamically light up according to the first power supply voltage V1 and the clock signal group; and to maintain the lighting state of all LED sub-lamp groups in the first-level LED lamp group 231 according to the second power supply voltage V2 and the lighting result of the last group of LED sub-lamp groups in the first-level LED lamp group 231, and provide a pull-down control signal to the next-level driving control subunit 222 so that the corresponding LED sub-lamp group in the corresponding next-level LED lamp group 232 supports dynamic lighting. Wherein, the first power supply voltage V1 is greater than the second power supply voltage V2, for example, the first power supply voltage V1 is 12V, and the second power supply voltage V2 is 5V.

[0024] Specifically, the second-level driving control subunit 222 is used to drive the corresponding LED sub-lamp groups in the corresponding second-level LED light group 232 to dynamically light up according to the first power supply voltage V1, the clock signal group and the pull-down control signal provided by the previous-level driving control subunit 221; and to maintain the lighting status of all LED sub-lamp groups in the second-level LED light group according to the second power supply voltage V2 and the lighting result of the last group of LED sub-lamp groups in the second-level LED light group 232, and provide a pull-down control signal to the next-level driving control subunit.

[0025] Specifically, the n-th level driving control subunit 22n (n is greater than 1) is used to drive the corresponding LED sub-lamp group in the corresponding n-th level LED lamp group 23n to dynamically light up according to the first power supply voltage V1, the clock signal group and the pull-down control signal provided by the previous level driving control subunit; and to maintain the lighting state of all LED sub-lamp groups in the n-th level LED lamp group according to the second power supply voltage V2 and the lighting result of the last group of LED sub-lamp groups in the n-th level LED lamp group 23n, and provide a pull-down control signal to the next level driving control subunit. It should be noted that for the last level driving control subunit, after the last group of LED sub-lamp groups in the last level LED lamp group is lit, it maintains the lighting state of all LED sub-lamp groups in the last level LED lamp group; since there is no next level driving control subunit, there is no need to provide a pull-down control signal to the next level driving control subunit.

[0026] The flow-type dynamic display light control circuit proposed by the present invention adopts a multi-stage drive control subunit with the same structure and cascaded by optimizing the circuit structure. Each stage of the drive control subunit controls the lighting of a corresponding LED light group. The external clock signal and the control signal with a timing relationship with the clock signal, or the pull-down control signal generated inside the circuit, are used to control the sequential operation of the drive control subunits at each stage, thereby controlling the corresponding LED light groups to light up in sequence and realizing the streamer effect. The present invention does not need to adopt a multi-channel D trigger, and can realize the dynamic lighting function of the dynamic display light by adopting a simple component and circuit architecture, which effectively saves costs, optimizes the cost performance of the product, and has promotion value. The dynamic display light can replace the traditional static display light and be applied to indication or decoration. For example, the dynamic display light can replace the static indicator light of the existing car to indicate the driving status of the car and realize the streamer steering effect; the dynamic display light can also replace the static decorative light of the existing car and be installed on the door handle and other parts of the car to realize the streamer decoration effect and improve the beauty of the car.

[0027] Please refer to Figure 3 , a circuit diagram of an embodiment of a control signal generating unit of the present invention. In this embodiment, the control signal generating unit 21 includes: a first voltage comparator CMP1 and a control transistor Q0. The positive input terminal of the first voltage comparator CMP1 is used to receive a reference voltage Vref, the negative input terminal thereof is connected to the charging capacitor C1, and the output terminal thereof outputs the clock signal CLK. The control terminal of the control transistor Q0 is coupled to the output terminal of the first voltage comparator CMP1, the first terminal thereof is used to receive the reference voltage Vref, and output a second control signal CE2 having a timing opposite to that of the clock signal CLK, and the second terminal thereof is grounded. It should be noted that, for a control circuit using a D flip-flop, the second control signal CE2 may also be an enable signal for controlling the D flip-flop. By reversing the control transistor Q0, the timing of the second control signal CE2 is opposite to that of the clock signal CLK. Among them, the clock signal CLK may be a signal having the same high and low level pulse widths, or a signal having asymmetric high and low levels.

[0028] In a further embodiment, the control signal generating unit 21 further includes: a first resistor R1 and a first diode D1 connected in series, and a second resistor R2 and a second diode D2 connected in series. The first resistor R1 and the first diode D1 connected in series are electrically connected between the negative input terminal and the output terminal of the first voltage comparator CMP1; the second resistor R2 and the second diode D2 connected in series are electrically connected between the negative input terminal and the output terminal of the first voltage comparator CMP1. Among them, the connection directions of the first diode D1 and the second diode D2 are opposite, and by configuring the resistance values ​​of the first resistor R1 and the second resistor R2, the first voltage comparator CMP1 outputs asymmetric clock signals of high and low levels. Specifically, the charging capacitor C1 is charged through the second resistor R2 and the second diode D2, and discharged through the first diode D1 and the first resistor R1; by configuring the resistance value of the second resistor R2 to be twice the resistance value of the first resistor R1, the clock signal CK can meet the high-level pulse width twice its low-level pulse width.

[0029] In a further embodiment, the control signal generating unit 21 further includes: a second voltage comparator CMP2. The positive input terminal of the first voltage comparator CMP1 is coupled to the output terminal of the reference voltage Vref through the third resistor R3, and its output terminal is electrically connected to its positive input terminal through the fourth resistor R4; the positive input terminal of the second voltage comparator CMP2 is connected to the charging capacitor C1, and its negative input terminal is electrically connected to the positive input terminal of the first voltage comparator CMP1 through the fifth resistor R5, and is grounded through the sixth resistor R6, and its output terminal outputs the first control signal CE1. By configuring the resistance values ​​of the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6, the pulse width of the first control signal CE1 is smaller than the pulse width of the clock signal CLK. Specifically, the high-level pulse width of the clock signal CLK can be twice the low-level pulse width of the first control signal CE1.

[0030] The following Figure 3The working principle of the embodiment shown is further explained. After power-on (switch S1 is closed), since the charging capacitor C1 has not been charged, the voltage at the positive input terminal of the first voltage comparator CMP1 is higher than the voltage at its negative input terminal, and the first voltage comparator CMP1 outputs a high level; similarly, the negative input terminal of the second voltage comparator CMP2 is higher than its positive input terminal, and the second voltage comparator CMP2 outputs a low level. Subsequently, the charging capacitor C1 is charged through the second resistor R2 and the second diode D2. When the voltage on the charging capacitor C1 (that is, the voltage at the positive input terminal of the second voltage comparator CMP2) is higher than the negative input terminal level of the second voltage comparator CMP2, the second voltage comparator CMP2 flips and outputs a high level. However, at this time, the voltage on the charging capacitor C1 is not higher than the voltage at the positive input terminal of the first voltage comparator CMP1. The charging capacitor C1 continues to charge until the voltage is higher than the voltage at the positive input terminal of the first voltage comparator CMP1. The first voltage comparator CMP1 flips and outputs a low level. The voltage at the positive input terminal of the first voltage comparator CMP1 becomes the voltage drop U1 on the fourth resistor R4 after the reference voltage Vref passes through the third resistor R3 and the fourth resistor R4. At this time, the charging capacitor C1 is discharged through the first diode D1 and the first resistor R1, and the voltage at the negative input terminal of the second voltage comparator CMP2 is zero, and the output of the second voltage comparator CMP2 remains high. When the discharge level of the charging capacitor C1 is lower than the voltage at the positive input terminal of the first voltage comparator CMP1, the first voltage comparator CMP1 flips and outputs a high level. At this time, the voltage at the negative input terminal of the second voltage comparator CMP2 suddenly changes to the voltage drop U2 on the sixth resistor R6 after the reference voltage Vref passes through the third resistor R3 and the fourth resistor R4 connected in parallel, and the fifth resistor R5 and the sixth resistor R6 connected in series; the voltage at the negative input terminal of the second voltage comparator CMP2 is higher than its positive input terminal (i.e., the voltage on the charging capacitor C1 after discharge), and the second voltage comparator CMP2 flips and outputs a low level. At this point, a cycle is completed, and the high level output by the first voltage comparator CMP1 begins to charge the charging capacitor C1 through the second resistor R2 and the second diode D2, and the next cycle begins.

[0031] The control signal generating unit 21 uses two diodes D1 and D2 with different directions to control the current direction of charging and discharging the charging capacitor C1. The charging and discharging time is determined by the capacitance of the charging capacitor C1 and the resistance of the second resistor R2 and the first resistor R1. Since the clock signal CLK output by the first voltage comparator CMP1 is high when charging the charging capacitor C1, and the clock signal CLK output by the first voltage comparator CMP1 is low when discharging the charging capacitor C1; in order to meet the requirement that the high level time of the clock signal CLK is twice the low level time, the resistance value of the second resistor R2 is twice the resistance value of the first resistor R1. The charging and discharging time also depends on the voltage at the positive input terminal of the first voltage comparator CMP1, because the negative input terminal is connected to the charging capacitor C1. When the voltage on the charging capacitor C1 is charged or discharged to a voltage higher or lower than the voltage at the positive input terminal of the first voltage comparator CMP1, the output of the first voltage comparator CMP1 will flip. When the first voltage comparator CMP1 outputs zero, the voltage at its positive input terminal is the voltage drop U1 on the fourth resistor R4 after the reference voltage Vref passes through the third resistor R3 and the fourth resistor R4, that is, U1=Vref*R4 / (R4+R3). When the first voltage comparator CMP1 outputs a high level, the voltage at its positive input terminal is approximately equal to the voltage drop U1' on the fifth resistor R5 and the sixth resistor R6 connected in series after the reference voltage Vref passes through the third resistor R3 and the fourth resistor R4 connected in parallel, and the fifth resistor R5 and the sixth resistor R6 connected in series, that is, U1'=Vref*(R5+R6) / (R4 / / R3+R5+R6). When the first voltage comparator CMP1 outputs a high level, the voltage at the negative input terminal of the second voltage comparator CMP2 is U2=Vref*R6 / (R4 / / R3+R5+R6); the voltage at the negative input terminal of the second voltage comparator CMP2 is lower than the voltage at the positive input terminal of the first voltage comparator CMP1, so the output of the second voltage comparator CMP2 will be reversed before the output of the first voltage comparator CMP1, generating a first control signal CE1 with a narrower pulse than the clock signal CLK output by the first voltage comparator CMP1. By reasonably setting and adjusting the resistance values ​​of the resistors R3, R4, R5 and R6, a clock signal CLK with a required pulse width and a first control signal CE1 with a pulse width of half the pulse width of the clock signal CLK can be generated. The second control signal CE2 can be obtained by reversing the clock signal CLK. This embodiment uses a voltage comparator with external components such as resistors and capacitors to generate a clock signal group, which effectively saves circuit costs.

[0032] Please refer to Figure 4, a circuit diagram of the first embodiment of the flow-type dynamic display light control circuit of the present invention. In this embodiment, the driving control subunit includes a first pull-up transistor (such as the first pull-up transistor Q10 of the first-level driving control subunit 221 and the first pull-up transistor Q20 of the second-level driving control subunit 222), a first switch tube (such as the first switch tube M10 of the first-level driving control subunit 221 and the first switch tube M20 of the second-level driving control subunit 222) and a pull-down transistor (such as the pull-down transistor Q19 of the first-level driving control subunit 221 and the pull-down transistor Q29 of the second-level driving control subunit 222). Each level of LED light group includes a first LED sub-light group (such as the first LED sub-light group LED1 of the first level LED light group shown in the figure, the first LED sub-light group LED4 of the second level LED light group), a second LED sub-light group (such as the second LED sub-light group LED2 of the first level LED light group shown in the figure, the second LED sub-light group LED5 of the second level LED light group) and a third LED sub-light group (such as the third LED sub-light group LED3 of the first level LED light group shown in the figure, the third LED sub-light group LED6 of the second level LED light group) connected in sequence.

[0033] The control end of the first pull-up transistor (Q10, Q20) is coupled to the output end of the first power supply voltage V1, the first end thereof is electrically connected to the first LED sub-lamp group (LED1, LED4) in the current LED lamp group, and the second end thereof is coupled to the output end of the first power supply voltage V1. The control end of the first switch tube (M10, M20) is coupled to the output end of the clock signal CLK, and is electrically connected to the first LED sub-lamp group (LED1, LED4) in the current LED lamp group through a feedback resistor (R4, R18), the first end thereof is coupled to the output end of the first power supply voltage V1, and the second end thereof is grounded (for the first-stage drive control subunit) or used to receive a pull-down control signal provided by the previous-stage drive control subunit (for the drive control subunits after the first stage). The control end of the pull-down transistor (Q19, Q29) is coupled to the input end (LED3, LED6) of the last LED sub-lamp group in the current LED lamp group, the first end is coupled to the output end of the second power supply voltage V2, and is electrically connected to the second end of the first switch tube of the next-level driving control subunit to provide a pull-down control signal (for the last level of driving control subunit, the control end of the corresponding pull-down transistor is only coupled to the output end of the second power supply voltage V2), and the second end is grounded. The first pull-up transistor (Q10, Q20) and the pull-down transistor (Q19, Q29) have different directions of current in each electrode when they are working. Specifically, the first pull-up transistor (Q10, Q20) is turned on and maintained on in response to the first power supply voltage V1; the first switch tube (M10, M20) is turned on and maintained on in response to the clock signal (for the first-level drive control subunit), or is turned on and maintained on in response to the pull-down control signal provided by the previous-level drive control subunit and the clock signal (for the drive control subunit after the first level); the pull-down transistor (Q19, Q29) is turned on and maintained on in response to the lighting of the last LED sub-light group (LED3, LED6) in the current LED light group. The first power supply voltage V1 is greater than the second power supply voltage V2, for example, the first power supply voltage V1 is 12V, and the second power supply voltage V2 is 5V.

[0034] In the present embodiment, the first end of the first pull-up transistor (Q10, Q20) is electrically connected to the positive electrode of the first LED sub-lamp group (LED1, LED4), the negative electrode of the third LED sub-lamp group (LED3, LED6) is grounded, and the drive control subunit further includes a first transistor (such as the first transistor Q11 of the first-level drive control subunit 221 and the first transistor Q21 of the second-level drive control subunit 222), and a second transistor (such as the second transistor Q12 of the first-level drive control subunit 221 and the second transistor Q22 of the second-level drive control subunit 222).

[0035] The control end of the first transistor (Q11, Q21) is coupled to the output end of the second power supply voltage V2 and the first end of the pull-down transistor (Q19, Q29), the first end of which is electrically connected to the cathode of the first LED sub-lamp group (LED1, LED4), and the second end of which is used to receive the first control signal CE1. The high-level pulse width of the clock signal CLK is twice the low-level pulse width, the first control signal CE1 is derived from the clock signal CLK, and the low-level holding time is half of the high-level duration of the clock signal CLK.

[0036] The control end of the second transistor (Q12, Q22) is coupled to the output end of the second power supply voltage V2 and the first end of the pull-down transistor (Q19, Q29), the first end of which is electrically connected to the cathode of the second LED sub-lamp group (LED2, LED5), and the second end of which is used to receive a second control signal CE2. The second control signal CE2 is derived from the clock signal CLK and has a timing opposite to that of the clock signal CLK.

[0037] In this embodiment, the control end of the pull-down transistor (Q19, Q29) is coupled to the positive electrode of the third LED sub-lamp group (LED3, LED6) and is also coupled to the ground. In this embodiment, each level of LED light groups works in sequence, and the first LED sub-lamp group (, LED4), the second LED sub-lamp group (LED2, LED5) and the third LED sub-lamp group (LED3, LED6) in each level of LED light groups are lit in sequence.

[0038] Specifically, in this embodiment, the first pull-up transistor (Q10, Q20), the pull-down transistor (Q19, Q29), the first transistor (Q11, Q21), and the second transistor (Q12, Q22) all use triodes. Among them, the base of the triode serves as the control end of the corresponding transistor, the collector of the triode serves as the first end of the corresponding transistor, and the emitter of the triode serves as the second end of the corresponding transistor. In this embodiment, the first switch tube (M10, M20) uses an NMOS tube, the gate of the NMOS tube serves as the control end of the first switch tube, the drain of the NMOS tube serves as the first end of the first switch tube, and the source of the NMOS tube serves as the second end of the first switch tube. Among them, the current directions of each electrode of the first pull-up transistor (Q10, Q20) and the pull-down transistor (Q19, Q29) are different when they are working; the current directions of each electrode of the first transistor, the second transistor, and the pull-down transistor are the same when they are working. For example, the first pull-up transistor (Q10, Q20) uses a PNP transistor; the pull-down transistor (Q19, Q29), the first transistor (Q11, Q21), and the second transistor (Q12, Q22) all use an NPN transistor. It should be noted that one or more of the first pull-up transistor (Q10, Q20), the pull-down transistor (Q19, Q29), the first transistor (Q11, Q21), and the second transistor (Q12, Q22) may also use a corresponding MOS transistor; the first switch transistor (M10, M20) may also use a corresponding transistor.

[0039] The following Figure 4The working principle of the embodiment shown is further explained. The circuit is divided into two identical parts (as shown in the figure, the first stage and the second stage). The operation of the second stage depends on whether M20 is turned on, and whether M20 is turned on depends on whether Q19 in the first stage is turned on. That is, the first stage works first, and the second stage works second. The first stage and the second stage work sequentially, and the three LED sub-light groups in each stage are also lit sequentially. Specifically, in the T1-T2 stage, CLK is at a high level, CE1 and CE2 are at a low level, Q10, M10, Q11 and Q12 in the first stage are turned on, and LED1 is lit; in the T2-T3 stage, CE1 becomes a high level, Q11 is turned off, but CE2 is still at a low level, so Q12 remains on, and LED1 and LED2 are lit; in the T3-T4 stage, CLK becomes a low level, and CE2 becomes a high level, but due to the feedback resistor R4, M10 remains on, Q10 also remains on, Q12 is turned off, and LED1, LED2, and LED3 are turned on. After LED3 is lit, a voltage drop is generated, which acts on R7 and R25, causing Q19 to be turned on as well, thereby enabling M20 in the second stage to meet the conditions for conduction; since CLK is at a low level at this time, M20 cannot be turned on yet. After CLK becomes high again and starts the next cycle, M20 is turned on, and the second stage begins the process of lighting up LED4, LED5, and LED6 in the same order as the first stage. The conduction of Q19 also prevents Q11 and Q12 from being turned on again, so that LED2 and LED3 will not go out again after being lit, thereby ensuring that the LED lighting process is a one-way sequential lighting process. The figure shows that six LED sub-light groups are lit in sequence. If more LED sub-light groups need to be added, the same cascade circuit can be added after the second stage. This embodiment can achieve the pipeline effect of sequential lighting of all LED sub-light groups under the control of three pulse signals CLK, CE1 and CE2, without the need for multiple D flip-flops, simplifying the circuit design and saving circuit costs.

[0040] This embodiment controls the conduction of a transistor or a MOS tube by changing the voltage between the base (B) and the emitter (E) of a transistor or the gate (G) and the source (S) of a MOS tube by using an externally input clock control signal (clock signal and its derived control signal) or by using the voltage level conversion inside the circuit. After the first level, this embodiment designs the emitter (E) of the transistor or the source (S) of the MOS tube, which is usually fixed to the reference ground of the circuit, to be floating, and the corresponding level will change with the externally input clock control signal or the voltage change of the internal circuit; when the emitter (E) of the transistor or the source (S) of the MOS tube is set to a high level, the transistor will not be turned on even if the base (B) of the transistor or the gate (G) of the MOS tube is at a high level. Based on this improvement, the voltage of the emitter (E) or source (S) of the transistor can be controlled by the clock control signal in the same level circuit, thereby controlling the conduction of the transistor; and the base (B) or gate (G) of the transistor with variable voltage of the emitter (E) or source (S) will be locked to a low level by the last transistor after all the transistors of the same level driving control sub-unit are turned on, thereby locking the state of the transistor in the level to no longer be turned on, thereby ensuring that all LED sub-light groups in the same level remain in the lit state after being lit. The sequential lighting between the levels is also achieved by controlling the voltage of the emitter of the corresponding transistor or the source of the MOS tube. When the last transistor of the previous level is not turned on, the emitter of the transistor of the next level or the drain of the MOS tube is at a high level, and the change of the clock signal cannot turn on the transistor or MOS tube of the next level. When the last transistor of the current level is turned on, the emitter or source of the first transistor or MOS tube of the next level will be pulled down, so that the first transistor or MOS tube of the next level has the conditions for conduction. At this time, a clock signal is added to make the transistors of the next stage turn on sequentially, so that the LED sub-light groups in the circuit light up sequentially to produce a flowing water effect.

[0041] Please refer to Figure 5 , a circuit diagram of the second embodiment of the flow-type dynamic display light control circuit of the present invention, showing the entire circuit of the first stage and part of the circuit of the second stage, wherein the first stage and the second stage have the same structure, and the undescribed details of the second stage can refer to those shown in the first stage. Figure 4 The difference of the embodiment shown is that, in this embodiment, each level of LED lamp group includes a first LED sub-lamp group LED1, a second LED sub-lamp group LED2, a third LED sub-lamp group LED3 connected in sequence, and a fourth LED sub-lamp group LED4, a fifth LED sub-lamp group LED5, and a sixth LED sub-lamp group LED6 connected in sequence; the drive control subunit includes Figure 4In addition to the same first pull-up transistor (Q10, Q20), first switch tube (M10, M20) and pull-down transistor (only Q19 is shown in the figure), it also includes a first transistor (only Q11 is shown in the figure), a second pull-up transistor (only Q18 is shown in the figure), a second NMOS tube (only M12 is shown in the figure) and a second transistor (only Q12 is shown in the figure).

[0042] In this embodiment, the control end of the first transistor Q11 is coupled to the output end of the second power supply voltage V2 and the first end of the pull-down transistor Q19, the first end of which is electrically connected to the cathode of the second LED sub-lamp group LED2, and the second end of which is used to receive the first control signal CE1. The high-level pulse width of the clock signal CLK is twice the low-level pulse width, the first control signal CE1 is derived from the clock signal CLK, and the low-level holding time is half of the high-level duration of the clock signal CLK.

[0043] The control end of the second pull-up transistor Q18 is coupled to the output end of the first power supply voltage V1, the first end thereof is electrically connected to the anode of the fourth LED sub-light group LED4, and the second end thereof is coupled to the output end of the first power supply voltage V1 (similar to the wiring method of the first pull-up transistor Q11).

[0044] The gate of the second NMOS transistor M12 is coupled to the cathode of the second LED sub-lamp group LED2 and to the ground, the drain of the second NMOS transistor M12 is coupled to the output end of the first power supply voltage V1 , and the source of the second NMOS transistor M12 is grounded.

[0045] The control end of the second transistor Q12 is coupled to the output end of the second power supply voltage V2 and the first end of the pull-down transistor Q19, the first end of which is electrically connected to the cathode of the fourth LED sub-lamp group LED4, and the second end of which is used to receive a second control signal CE2. The second control signal CE2 is derived from the clock signal CLK and has a timing opposite to that of the clock signal CLK.

[0046] In this embodiment, the control end of the pull-down transistor Q19 is coupled to the positive electrode of the fifth LED sub-lamp group LED5 and is also coupled to the ground. In this embodiment, each level of LED lamp groups works in sequence, and the first LED sub-lamp group LED1 and the second LED sub-lamp group LED2 in each level of LED lamp group are lit at the same time, the third LED sub-lamp group LED3 and the fourth LED sub-lamp group LED4 are lit at the same time, and the fifth LED sub-lamp group LED5 and the sixth LED sub-lamp group LED6 are lit at the same time, and the three LED sub-lamp groups are lit in sequence. That is, in this embodiment, in the same level of LED lamp groups, two LED sub-lamp groups are lit as one group at the same time.

[0047] Specifically, in this embodiment, the first pull-up transistor Q10, the pull-down transistor Q19, the first transistor Q11, the second pull-up transistor Q18, and the second transistor Q12 are all triodes. Among them, the base of the triode is used as the control end of the corresponding transistor, the collector of the triode is used as the first end of the corresponding transistor, and the emitter of the triode is used as the second end of the corresponding transistor. In this embodiment, the first switch tube (M10, M20) is an NMOS tube, the gate of the NMOS tube is used as the control end of the first switch tube, the drain of the NMOS tube is used as the first end of the first switch tube, and the source of the NMOS tube is used as the second end of the first switch tube. Among them, the first pull-up transistor Q10 and the second pull-up transistor Q18 are PNP-type triodes; the pull-down transistor Q19, the first transistor Q11, and the second transistor Q12 are all NPN-type triodes.

[0048] The following Figure 5 The working principle of the embodiment shown is further explained. The circuit is divided into two identical parts (as shown in the figure, the first stage and the second stage). The operation of the second stage depends on whether M20 is turned on, and whether M20 is turned on depends on whether Q19 in the first stage is turned on. That is, the first stage works first, and the second stage works second, and the first and second stages work sequentially, and the six LED sub-light groups in each stage are lit in groups of two, and the groups are lit sequentially. Specifically, in the T1-T2 stage, CLK is high, CE1 and CE2 are low, Q10, M10, and Q11 in the first stage are turned on, and LED1 and LED2 are lit; in the T2-T3 stage, CE1 becomes high, Q11 is turned off, and LED3 is lit. After LED3 is lit, M12 is turned on. Since CE2 is still low, Q12 is turned on, and LED4 is also lit; in the T3-T4 stage, CLK becomes low, and CE2 becomes high, but due to the feedback resistor R4, M10 remains turned on, Q10 also remains turned on, Q12 is turned off, and LED5 and LED6 are lit. Since LED5 and LED6 generate a voltage drop after lighting, Q19 is also turned on, so that M20 in the second stage has the conditions for turning on; since CLK is low at this time, M20 cannot turn on. After CLK becomes high again to start the next cycle, M20 turns on, and the second stage begins the same sequential lighting process as the first stage. The conduction of Q19 also prevents Q11 and Q12 from being turned on again, so that LED3~LED6 will not go out again after being lit, thereby ensuring that the lighting process of the LED is a unidirectional sequential lighting process.

[0049] Please refer to Figure 6 , a circuit diagram of a third embodiment of a flow-type dynamic display light control circuit of the present invention. Figure 4 The difference of the embodiment shown is that, in this embodiment, the drive control subunit only includes Figure 4The same first pull-up transistors (Q10, Q20), first switch tubes (M10, M20) and pull-down transistors (Q19, Q29) are shown. This embodiment is for the case where three LED sub-light groups are lit up at the same time as a group, that is, LED1, LED2, LED3 are a group, LED4, LED5, LED6 are a group, and the groups are lit up sequentially. In this case, the clock control signal and the drive control circuit of each LED light group will become much simpler.

[0050] In this embodiment, the control end of the first switch tube M10 of the current stage driving control subunit is coupled to the output end of the clock signal CLK1; the control end of the first switch tube M20 of the next stage driving control subunit is coupled to the first control signal CLK2. The high and low level pulse widths of the clock signal CLK1 are the same, and the first control signal CLK2 is derived from the clock signal CLK1 and has the opposite timing to the clock signal CLK1.

[0051] In this embodiment, the control end of the pull-down transistor Q19 of the current-stage driving control subunit is coupled to the anode of the third LED sub-lamp group LED3 or the anode of the second LED sub-lamp group LED2, and is also coupled to the ground. In this embodiment, the first LED sub-lamp group LED1, the second LED sub-lamp group LED2, and the third LED sub-lamp group LED2 are lit at the same time. That is, in this embodiment, in the LED light groups of the same level, three LED sub-lamp groups are lit as a group at the same time.

[0052] Specifically, in this embodiment, the first pull-up transistor (Q10, Q20) and the pull-down transistor (Q19, Q29) are both triodes. The base of the triode is used as the control end of the corresponding transistor, the collector of the triode is used as the first end of the corresponding transistor, and the emitter of the triode is used as the second end of the corresponding transistor. In this embodiment, the first switch tube (M10, M20) is an NMOS tube, the gate of the NMOS tube is used as the control end of the first switch tube, the drain of the NMOS tube is used as the first end of the first switch tube, and the source of the NMOS tube is used as the second end of the first switch tube. The first pull-up transistor (Q10, Q20) is a PNP type triode; the pull-down transistor (Q19, Q29) is an NPN type triode.

[0053] The following Figure 6The working principle of the embodiment shown is further explained. The circuit is divided into two identical parts (as shown in the figure, the first stage and the second stage). The operation of the second stage depends on whether M20 is turned on, and whether M20 is turned on depends on whether Q19 in the first stage is turned on. That is, the first stage works first, and the second stage works second. The first stage and the second stage work sequentially, and the three LED sub-light groups in each stage are lit at the same time. Specifically, when CLK1 is at a high level, Q10 and M10 in the first stage are turned on, and the feedback of the feedback resistor R4 keeps M10 locked in the turned-on state, and LED1, LED2, and LED3 are lit; at the same time, due to the voltage drop generated after LED2 and LED3 are lit, Q19 is also turned on, and the source of M20 in the second stage is pulled to a low level, so that M20 in the second stage has the conditions for conduction; because CLK2 is at a low level at this time, M20 cannot be turned on, but because the source of M20 is pulled down by Q19, it is ready to be turned on when CLK2 is high. At the same time, Q29 in the second stage will not be turned on either. Therefore, although the gate of M30 in the third stage of the subsequent cascade is connected to CLK1, since Q29 in the second stage is not turned on, M30 in the third stage will not be turned on either. Similarly, if there are other cascaded stages after the third stage, they will not be turned on either. Next, CLK1 becomes a low level, and CLK2 becomes a high level; since M10 in the first stage can remain turned on by obtaining feedback voltage from the feedback resistor R4, LED1~LED3 can be kept lit; and the second stage will repeat the lighting process of the first stage and prepare for the conduction of the third stage after CLK1 becomes a high level again. In this way, under the control of CLK1 and CLK2, each cascaded drive control sub-circuit is turned on sequentially.

[0054] Since the LED sub-light groups in each stage are connected in series, and there is a forward conduction voltage drop when the LED lights are turned on, if only one current-limiting resistor is used at the second end of the first pull-up transistor of each stage of the driving control sub-unit, the current flowing through each LED sub-light group when turned on will be different, which will make the brightness of each LED sub-light group different. Preferably, a constant current control transistor can be configured at the pull-up transistor of each stage to form a constant current source module, so that the current of each LED sub-light group turned on in sequence in each stage is equal; it is also possible to configure current-limiting resistors of different resistance values ​​at the output end of each LED sub-light group, so that the current of each LED sub-light group when it is turned on in sequence is approximately equal.

[0055] Please refer to Figure 7, a circuit diagram of the fourth embodiment of the flow-type dynamic display light control circuit of the present invention. In this embodiment, a constant current control transistor Q17 is added to each of the drive control subunits (such as the drive control subunit 221 shown in the figure); the control end of the constant current control transistor Q17 is electrically connected to the second end of the first pull-up transistor Q10, the first end is electrically connected to the control end of the first pull-up transistor Q10, and the second end is electrically connected to the output end of the first power supply voltage V1; wherein, when the first pull-up transistor Q10 and the constant current control transistor Q17 are working, the current directions of the electrodes are the same.

[0056] Specifically, the constant current control transistor Q17 also uses a triode, the base of the triode serves as the control end of the corresponding transistor, the collector of the triode serves as the first end of the corresponding transistor, and the emitter of the triode serves as the second end of the corresponding transistor. For example, the first pull-up transistor Q10 and the constant current control transistor Q17 both use NPN-type triodes; the base of the constant current control transistor Q17 is electrically connected to the emitter of the first pull-up transistor Q10, the collector thereof is electrically connected to the base of the first pull-up transistor Q10, and the emitter thereof is electrically connected to the output end of the first power supply voltage V1.

[0057] By adding the constant current control transistor Q17, a constant current source module can be formed with the corresponding first pull-up transistor Q10, so that when the LED sub-lamp groups controlled by the driving control sub-unit in the circuit are lit in sequence, the current flowing through each LED sub-lamp group is equal (I1=I2=I3); that is, the brightness of all LED sub-lamp groups after being lit in sequence is consistent.

[0058] Please refer to the figure Figure 8 , the circuit diagram of the fifth embodiment of the flow-type dynamic display light control circuit of the present invention. In this embodiment, in each of the driving control subunits (such as the driving control subunit 221 shown in the figure), current limiting resistors R101, R102, and R103 with different resistance values ​​are configured at the output end of each LED sub-lamp group to achieve constant current. Specifically, the first end of the first transistor Q11 is electrically connected to the cathode of the first LED sub-lamp group LED1 through the corresponding first current limiting resistor R101; the first end of the second transistor Q12 is electrically connected to the cathode of the second LED sub-lamp group LED2 through the corresponding second current limiting resistor R102; the cathode of the third LED sub-lamp group LED3 is electrically connected to the ground through the corresponding third current limiting resistor R103. Among them, by configuring the resistance values ​​of the first current limiting resistor R101, the second current limiting resistor R102, and the third current limiting resistor R103, when the first LED sub-lamp group LED1, the second LED sub-lamp group LED2, and the third LED sub-lamp group LED3 are lit in sequence, the current flowing through each LED sub-lamp group is equal (I1=I2=I3); that is, the brightness of all LED sub-lamp groups after being lit in sequence is consistent.

[0059] Please refer to Fig. 9 , a schematic diagram of an embodiment of an LED lamp group of the present invention. In this embodiment, each level of LED lamp group includes a plurality of LED sub-lamp groups connected in series, and each LED sub-lamp group includes a plurality of LED lamps connected in parallel. That is, each LED sub-lamp group in the circuit can be regarded as an LED sub-lamp group composed of one or several LED lamps connected in parallel, and each LED sub-lamp group is connected in series with each other, and the number of LED sub-lamp groups connected in series is determined by the working voltage range provided by the vehicle body and the forward conduction voltage drop of the LED. If the working voltage range provided by the vehicle body is 9V-16V, and the forward conduction voltage drop of the LED sub-lamp group (a single LED lamp or multiple LED lamps connected in parallel) is 2.3V, then three LED sub-lamp groups can be connected in series. The transistor in the figure is used as a transistor for lighting up each LED sub-lamp group in sequence. In the figure of the above circuit example of the present invention, only one LED lamp is schematically drawn for one LED sub-lamp group, but each LED sub-lamp group can be regarded as composed of one or several LED lamps connected in parallel, and each LED sub-lamp group will be lit at the same time. This design can keep the cost of the control circuit unchanged while increasing the number of LED lamps that can be lit, saving circuit costs.

[0060] The above is only a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as within the protection scope of the present invention.

Claims

1. A flow-type dynamic display light control circuit, characterized in that: include: A control signal generating unit, configured to generate a clock signal group, wherein the clock signal group includes a clock signal and a control signal having a timing relationship with the clock signal; The driving control unit includes a plurality of cascaded driving control subunits having the same structure, and each driving control subunit correspondingly controls the lighting of a first-level LED light group; Among them, the first-level driving control subunit is used to drive the corresponding LED sub-lamp group in the corresponding first-level LED lamp group to dynamically light up according to the first power supply voltage and the clock signal group, and maintain the lighting status of all LED sub-lamp groups in the first-level LED lamp group according to the second power supply voltage and the lighting result of the last group of LED sub-lamp groups in the first-level LED lamp group, and provide a pull-down control signal to the next-level driving control subunit so that the corresponding LED sub-lamp group in the corresponding next-level LED lamp group supports dynamic lighting; the n-th-level driving control subunit is used to drive the corresponding LED sub-lamp group in the corresponding n-th-level LED lamp group to dynamically light up according to the first power supply voltage, the clock signal group and the pull-down control signal provided by the previous-level driving control subunit, and maintain the lighting status of all LED sub-lamp groups in the n-level LED lamp group according to the second power supply voltage and the lighting result of the last group of LED sub-lamp groups in the n-level LED lamp group, and provide a pull-down control signal to the next-level driving control subunit, The driving control subunit includes a first pull-up transistor, a first switch tube and a pull-down transistor; The control end of the first pull-up transistor is coupled to the output end of the first power supply voltage, the first end of the first pull-up transistor is electrically connected to the first LED sub-lamp group in the current LED lamp group, and the second end of the first pull-up transistor is coupled to the output end of the first power supply voltage; The control end of the first switch tube is coupled to the output end of the clock signal and is electrically connected to the first LED sub-lamp group in the current LED lamp group through a feedback resistor, the first end of the first switch tube is coupled to the output end of the first power supply voltage, and the second end of the first switch tube is grounded or used to receive the pull-down control signal provided by the previous stage drive control sub-unit; The control end of the pull-down transistor is coupled to the input end of the last LED sub-lamp group in the current LED lamp group, the first end of the pull-down transistor is coupled to the output end of the second power supply voltage, and is electrically connected to the second end of the first switch tube of the next-stage driving control sub-unit to provide a pull-down control signal, and the second end of the pull-down transistor is grounded; Among them, the current directions of each electrode of the first pull-up transistor and the pull-down transistor are different when they are working; the first pull-up transistor is turned on and maintained on in response to the first power supply voltage; the first switch tube is turned on and maintained on in response to the clock signal, or is turned on and maintained on in response to the pull-down control signal provided by the previous stage drive control sub-unit and the clock signal; the pull-down transistor is turned on and maintained on in response to the lighting of the last group of LED sub-lights in the current LED light group.

2. The circuit according to claim 1, characterized in that The control signal generating unit comprises: A first voltage comparator, whose positive input terminal is used to receive a reference voltage, whose negative input terminal is connected to a charging capacitor, and whose output terminal outputs the clock signal; A control transistor has a control end coupled to the output end of the first voltage comparator, a first end for receiving the first power supply voltage and outputting a second control signal with a timing opposite to that of the clock signal, and a second end for grounding.

3. The circuit according to claim 2, characterized in that The control signal generating unit further includes: A first resistor and a first diode connected in series, electrically connected between a negative input terminal and an output terminal of the first voltage comparator; A second resistor and a second diode connected in series are electrically connected between the negative input terminal and the output terminal of the first voltage comparator, wherein the connection directions of the first diode and the second diode are opposite, and by configuring the resistance values ​​of the first resistor and the second resistor, the first voltage comparator outputs a high-level and a low-level asymmetric clock signal; The positive input terminal of the first voltage comparator is coupled to the output terminal of the reference voltage through a third resistor, and its output terminal is electrically connected to its positive input terminal through a fourth resistor; A second voltage comparator, whose positive input terminal is connected to the charging capacitor, whose negative input terminal is electrically connected to the positive input terminal of the first voltage comparator through a fifth resistor and is grounded through a sixth resistor, and whose output terminal outputs a first control signal, and by configuring the resistance values ​​of the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor, the pulse width of the first control signal is smaller than the pulse width of the clock signal.

4. The circuit according to claim 3, characterized in that The high-level pulse width of the clock signal is twice the low-level pulse width thereof, and the high-level pulse width of the clock signal is twice the low-level pulse width of the first control signal.

5. The circuit according to claim 1, characterized in that The first pull-up transistor and the pull-down transistor are both triodes, wherein the base of the triode serves as the control end of the corresponding transistor, the collector of the triode serves as the first end of the corresponding transistor, and the emitter of the triode serves as the second end of the corresponding transistor; the first switch tube is an NMOS tube, wherein the gate of the NMOS tube serves as the control end of the first switch tube, the drain of the NMOS tube serves as the first end of the first switch tube, and the source of the NMOS tube serves as the second end of the first switch tube.

6. The circuit according to claim 1, characterized in that The drive control subunit further includes a constant current control transistor; the control end of the constant current control transistor is electrically connected to the second end of the first pull-up transistor, the first end is electrically connected to the control end of the first pull-up transistor, and the second end is electrically connected to the output end of the first power supply voltage; wherein, when the first pull-up transistor and the constant current control transistor are working, the current directions of the electrodes are the same.

7. The circuit according to claim 1, characterized in that Each level of LED lamp group includes a first LED sub-lamp group, a second LED sub-lamp group and a third LED sub-lamp group connected in sequence, the first end of the first pull-up transistor is electrically connected to the positive electrode of the first LED sub-lamp group, the negative electrode of the third LED sub-lamp group is coupled to the ground, and the drive control sub-unit also includes a first transistor and a second transistor; The control end of the first transistor is coupled to the output end of the second power supply voltage and the first end of the pull-down transistor, the first end of the first transistor is coupled to the cathode of the first LED sub-lamp group, and the second end of the first transistor is used to receive a first control signal, wherein the high-level pulse width of the clock signal is twice the low-level pulse width thereof, the first control signal is derived from the clock signal, and the low-level holding time thereof is half the high-level duration of the clock signal; The control end of the second transistor is coupled to the output end of the second power supply voltage and the first end of the pull-down transistor, the first end of the second transistor is coupled to the cathode of the second LED sub-lamp group, and the second end of the second transistor is used to receive a second control signal, wherein the second control signal is derived from the clock signal and has a timing opposite to that of the clock signal; The control end of the pull-down transistor is coupled to the positive electrode of the third LED sub-lamp group and is also coupled to the ground end; Among them, when the first transistor, the second transistor and the pull-down transistor are working, the directions of the currents of the electrodes are the same; the first LED sub-lamp group, the second LED sub-lamp group and the third LED sub-lamp group are lit in sequence.

8. The circuit according to claim 7, characterized in that The first end of the first transistor is electrically connected to the cathode of the first LED sub-lamp group through a first current limiting resistor, the first end of the second transistor is electrically connected to the cathode of the second LED sub-lamp group through a second current limiting resistor; the cathode of the third LED sub-lamp group is electrically connected to the ground through a third current limiting resistor; Among them, by configuring the resistance values ​​of the first current limiting resistor, the second current limiting resistor, and the third current limiting resistor, the brightness of the first LED sub-lamp group, the second LED sub-lamp group, and the third LED sub-lamp group after being lit in sequence is basically the same.

9. The circuit according to claim 1, characterized in that Each level of LED lamp group includes a first LED sub-lamp group, a second LED sub-lamp group, a third LED sub-lamp group connected in sequence, and a fourth LED sub-lamp group, a fifth LED sub-lamp group, and a sixth LED sub-lamp group connected in sequence, the first end of the first pull-up transistor is electrically connected to the positive electrode of the first LED sub-lamp group, the negative electrodes of the third LED sub-lamp group and the sixth LED sub-lamp group are grounded, and the drive control subunit also includes a first transistor, a second pull-up transistor, a second NMOS tube and a second transistor; The control end of the first transistor is coupled to the output end of the second power supply voltage and the first end of the pull-down transistor, the first end of the first transistor is electrically connected to the cathode of the second LED sub-lamp group, and the second end of the first transistor is used to receive a first control signal, wherein the high-level pulse width of the clock signal is twice the low-level pulse width thereof, the first control signal is derived from the clock signal, and the low-level holding time thereof is half the high-level duration of the clock signal; The control end of the second pull-up transistor is coupled to the output end of the first power supply voltage, the first end thereof is electrically connected to the positive electrode of the fourth LED sub-lamp group, and the second end thereof is coupled to the output end of the first power supply voltage; The gate of the second NMOS tube is coupled to the cathode of the second LED sub-lamp group and to the ground, the drain of the second NMOS tube is coupled to the output end of the first power supply voltage, and the source of the second NMOS tube is grounded; The control end of the second transistor is coupled to the output end of the second power supply voltage and the first end of the pull-down transistor, the first end of the second transistor is electrically connected to the cathode of the fourth LED sub-lamp group, and the second end of the second transistor is used to receive a second control signal, wherein the second control signal is derived from the clock signal and has a timing opposite to that of the clock signal; The control end of the pull-down transistor is coupled to the positive electrode of the fifth LED sub-lamp group and is also coupled to the ground end; Among them, the current directions of each electrode of the first transistor, the second transistor and the pull-down transistor are the same when they are working; the first LED sub-lamp group and the second LED sub-lamp group are lit at the same time, the third LED sub-lamp group and the fourth LED sub-lamp group are lit at the same time, the fifth LED sub-lamp group and the sixth LED sub-lamp group are lit at the same time, and the three LED sub-lamp groups are lit in sequence.

10. The circuit according to claim 1, characterized in that Each level of LED lamp group includes a first LED sub-lamp group, a second LED sub-lamp group, and a third LED sub-lamp group connected in sequence, the first end of the first pull-up transistor is electrically connected to the positive electrode of the first LED sub-lamp group, and the negative electrode of the third LED sub-lamp group is grounded; The control end of the first switch tube of the current stage driving control subunit is coupled to the output end of the clock signal, and the control end of the first switch tube of the next stage driving control subunit is coupled to the first control signal, wherein the high and low level pulse widths of the clock signal are the same, and the first control signal is derived from the clock signal and has a timing opposite to that of the clock signal; The control end of the pull-down transistor of the current stage driving control subunit is coupled to the anode of the third LED sub-lamp group or the anode of the second LED sub-lamp group and is coupled to the ground end at the same time; Wherein, the first LED sub-lamp group, the second LED sub-lamp group, and the third LED sub-lamp group are lit at the same time.

11. The circuit according to claim 1, characterized in that The flowing dynamic display light comprises a multi-stage LED light group, each stage of the LED light group comprises a plurality of LED sub-light groups connected in series, and each LED sub-light group comprises one LED lamp or a plurality of LED lamps connected in parallel.

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