Multi-channel address register, probe card, addressable test chip, system and method

Abstract

The present invention provides a multi-way address register, including counter logic, shifter logic, multiplexer, selective addressing module and clock edge trigger; the multiplexer is provided with at least two; the clock edge trigger is provided with multiple, including: a first clock edge trigger is used to receive an address signal, a second clock edge trigger is used to receive an addressing mode selection signal, and a third clock edge trigger is used to receive auxiliary data. The present invention also provides an addressable test chip and a probe card, which have the multi-way address register of the present invention and can support more addressing modes, which is beneficial to saving costs and improving addressing efficiency; the present invention also provides a test system, which adopts the probe card or addressable test chip of the present invention, and takes into account test accuracy, good stability, high efficiency and low cost in test applications. A test method of the present invention is based on the test system of the present invention, which optimizes the test work efficiency and is conducive to promotion.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design and manufacturing, and specifically relates to a multi-channel address register, a probe card, a high-density addressable test chip supporting selective addressing, and a test method and a test system thereof. Background Art

[0002] As the design scale of integrated circuits continues to expand, the density of electronic devices on a single chip is increasing, and the characteristic size of electronic devices is getting smaller and smaller. At the same time, the integrated circuit process contains many complex process steps, and each step has a specific process manufacturing deviation, which leads to a decrease in the yield of integrated circuit chips. In the context of manufacturability design, in order to improve the yield of integrated circuit products and shorten the yield maturity cycle, the industry generally adopts a testing method based on specially designed test chips, and obtains the necessary data for process and design yield improvement through testing of test chips.

[0003] Short-range test chips and addressable test chips are two types of test chips often used in the manufacturing process of integrated circuit chips. Short-range test chips are widely used because of their short production cycle, flexible testing, and high testing accuracy. However, in traditional short-range test chips, each terminal of each device under test needs to be connected to the terminal pad separately, so each device under test needs to be connected to two or more pads. These devices under test and the pads may be placed on the same layer, or the connection terminals of the devices under test may be connected to the pads on the pad layer through a layer of contact holes, resulting in particularly low area utilization. The addressable test chip configures an addressable circuit for the device under test, and uses a decoder and a switch selection circuit to achieve the purpose of multiple test structures sharing pads.

[0004] The address signal in the addressable circuit is converted from the walking signal provided by the external electrical device through a decoder. At present, the method of generating the addressing signal directly uses the source measurement unit in the test instrument to provide the addressing signal, generates different addressing signals by controlling the signal state of the source measurement unit, and transmits the signal to the addressable circuit of the device under test through the probe card. This method requires manual or computer control of the signal generated by the source measurement unit. Before the test, the algorithm needs to be edited manually or by computer, and the power supply of the source measurement unit is adjusted to achieve the purpose of selecting the test device. In this method, the algorithm editing process is cumbersome, and instruction running debugging is required during the switching process of the device under test, which takes up a lot of test time, wastes manpower and time costs, and has low test efficiency.

[0005] The patent "An addressable test chip test system (201721911051.5)" discloses the use of a function generator and a multi-purpose address register to generate an address signal, replacing the original source measurement unit to generate the address signal. This multi-purpose address register has two functions: a counter and a shift register, and can support two addressing modes: (1) continuous addressing. In this method, the address increases by 1 each time, which can generate a continuous address signal and is the core of achieving continuous and fast measurement; (2) fixed-point addressing. In this method, the required address is transmitted to the chip through a specific communication protocol. This method can change the address in the chip arbitrarily, but only one address can be changed at a time. If you want to fix the address to any 100 addresses, you need to perform fixed-point addressing 100 times, and the efficiency will begin to decline.

[0006] On the other hand, ordinary addressable circuits can measure fewer devices, and measurements must be performed one by one by scanning. They cannot meet the requirements for fast measurement of high-density devices under advanced processes, and cannot quickly locate the location and type of defects in devices ranging from millions to hundreds of millions. Summary of the invention

[0007] The present invention is made to solve some or all of the above-mentioned problems, and its purpose is to provide a multi-way address register, probe card, high-density addressable test chip and its test method and test system that can expand the support of selective addressing mode on the basis of retaining the existing continuous addressing mode and fixed-point addressing mode.

[0008] The present invention provides a multi-way address register, comprising a counter logic, a shifter logic, a multiplexer, a selective addressing module and a clock edge trigger; the counter logic comprises at least a first counter logic; the multiplexer is provided with at least two, which are set as a first multiplexer and a second multiplexer; the clock edge trigger is provided with a plurality of, including: a plurality of first clock edge triggers, a plurality of second clock edge triggers and a plurality of third clock edge triggers; the first clock edge trigger is used to receive an address signal, the second clock edge trigger is used to receive an address mode selection signal, and the third clock edge trigger is used to receive auxiliary data; the selective addressing module can realize: judging whether the received current address belongs to an address area to be addressed, if the current address belongs to the address area to be addressed, then the received current address signal is increased by 1 and output as the next address signal; if the current address does not belong to the address area to be addressed, then the address area where the current address is located is skipped, and the starting address of the next address area to be addressed is output as the next address signal; the input ports of the multi-way address register comprise: a reset signal port RST, A clock signal port CLK, a shift register enable port SE and a shift register input port SI; wherein: the input end D of the clock edge trigger is connected to the output end of the first multiplexer, the input end R of the clock edge trigger is connected to the reset signal port RST, and the input end CK of the clock edge trigger is connected to the clock signal port CLK; the output end Q of the first clock edge trigger and the output end Q of the second clock edge trigger are respectively connected to the output port of the multiplexed address register; the input end of the shifter logic is connected to the shift register input port SI and the output end Q of the clock edge trigger; the input end of the first counter logic is connected to the output end Q of the first clock edge trigger; the input end of the selection addressing module is connected to the output end Q of the first clock edge trigger and the output end Q of the third clock edge trigger; the input end of the second multiplexer is connected to the output end of the first counter logic, the output end of the selection addressing module and the output end Q of the second clock edge trigger; the input end of the first multiplexer is connected to the shift register enable port SE, the output end of the shifter logic and the output end of the second multiplexer.

[0009] In a preferred implementation, the output port of the multi-way address register includes an address signal port addr and a data type port GB; the address signal port addr is connected to the output terminal Q of the first clock edge trigger; the data type port GB is connected to the output terminal Q of the second clock edge trigger. The address signal port addr is used to output an address signal, and the data type port GB is used to output the data type of the address signal output by the address signal port addr.

[0010] In a preferred embodiment, the output port of the multi-channel address register further includes an auxiliary debugging port AUX, and the auxiliary debugging port AUX is connected to the output terminal Q of the first clock edge trigger for address verification.

[0011] In an advantageous implementation, the multiplexed address register supports at least two continuous addressing modes: a conventional continuous addressing mode and a selective continuous addressing mode. The conventional continuous addressing mode refers to: using the first clock edge trigger to receive a binary current address signal, and using the first counter logic to add 1 to the received current address signal as the next address signal to the second multiplexer. The selective continuous addressing mode refers to: using the first clock edge trigger to receive a binary current address signal, and using the auxiliary data received by the third clock edge trigger as a selection table; the selection table stores information on whether an address area needs to be addressed, and confirms whether the current address belongs to the address area to be addressed based on the information; if the current address belongs to the address area to be addressed, the received current address signal + 1 is input to the second multiplexer as the next address signal; if the current address does not belong to the address area to be addressed, the address area where the current address is located is skipped, and the starting address of the next address area to be addressed is input to the second multiplexer as the next address signal. The specific implementation method of selecting to use one of the above-mentioned continuous addressing modes is to receive the addressing mode selection signal through the second clock edge trigger and transmit it to the second multiplexer. The second multiplexer determines to use a corresponding continuous addressing mode according to the addressing mode selection signal, and outputs the next address signal generated by this continuous addressing mode.

[0012] In one advantageous implementation, the size of the minimum addressing area is predefined for the selection table; and whether each address area of ​​the minimum addressing area size needs to be addressed is defined in turn according to whether the data in the selection table is 0 or 1.

[0013] In another advantageous implementation, the multiplexed address register further includes a Gray code encoder and a Gray code decoder; the counter logic further includes a second counter logic; the input of the Gray code decoder is connected to the output Q of the first clock edge trigger, and its output is connected to the input of the second counter logic; the input of the Gray code encoder is connected to the output of the second counter logic, and its output is connected to the input of the second multiplexer. In this design, the multiplexed address register further includes a Gray code encoder and a Gray code decoder, so that the address signal can be converted between binary code and Gray code.

[0014] In another advantageous implementation, the multiplexed address register supports at least three continuous addressing modes: a conventional continuous addressing mode, a selective continuous addressing mode, and a Gray code continuous addressing mode. The conventional continuous addressing mode refers to: using the first clock edge trigger to receive a binary current address signal, and using the first counter logic to add 1 to the received current address signal as the next address signal to the second multiplexer. The selective continuous addressing mode refers to: using the first clock edge trigger to receive a binary current address signal, and using the auxiliary data received by the third clock edge trigger as a selection table; the selection table stores information on whether an address area needs to be addressed, and confirms whether the current address belongs to the address area to be addressed based on the information; if the current address belongs to the address area to be addressed, the received current address signal + 1 is input to the second multiplexer as the next address signal; if the current address does not belong to the address area to be addressed, the address area where the current address is located is skipped, and the starting address of the next address area to be addressed is input to the second multiplexer as the next address signal. The Gray code continuous addressing mode is to use the first clock edge trigger to receive the current address signal of the Gray code, first decode the received current address signal into a binary address signal through the Gray code decoder, then use the second counter logic to add 1 to the binary address signal, and then use the Gray code encoder to re-encode it into a Gray code signal as the next address signal to input into the second multiplexer. The specific implementation method of selecting to use one of the above continuous addressing modes is to receive the addressing mode selection signal through the second clock edge trigger and transmit it to the second multiplexer, and the second multiplexer determines to use a corresponding continuous addressing mode according to the addressing mode selection signal, and outputs the next address signal generated by this continuous addressing mode.

[0015] In one advantageous implementation, the size of the minimum addressing area is predefined for the selection table; and whether each address area of ​​the minimum addressing area size needs to be addressed is defined in turn according to whether the data in the selection table is 0 or 1.

[0016] In a feasible approach, the first counter logic and the second counter logic can use the same counter logic to implement functions using control logic.

[0017] In a favorable implementation, the addressing mode expansion of a multi-way address register is achieved by setting different numbers of first clock edge triggers, second clock edge triggers, and third clock edge triggers, defining the addressing mode selection signal received by the second clock edge trigger, and defining the required auxiliary data received by the third clock edge trigger.

[0018] In another specific implementation, in the multi-way address register, at least two second clock edge triggers are provided, which can receive at least four different addressing mode selection signals and determine the corresponding addressing mode selection signal for each addressing mode.

[0019] In a specific implementation, the multi-way address register adopts a 32-bit register, wherein the first clock edge trigger is set with 20, the second clock edge trigger is set with 2, and the third clock edge trigger is set with 10; and 4 addressing mode selection signals received by the second clock edge trigger are set, when the addressing mode selection signal is 00, the traditional continuous addressing mode is selected; when the addressing mode selection signal is 01, the Gray code continuous addressing mode is selected; when the addressing mode selection signal is 10, the selective continuous addressing mode is selected; when the addressing mode selection signal is 11, the addressing mode is not set, and the addressing mode when the addressing mode selection signal is 11 can be customized to achieve addressing mode expansion.

[0020] The present invention also provides a probe card integrated with the above multi-channel address register. The multi-channel address register is integrated on the probe card and is not affected by the integrated circuit manufacturing process, so that the performance of the multi-channel address register is stable and the test accuracy is guaranteed.

[0021] The present invention also provides a high-density addressable test chip supporting selective addressing, comprising an addressing circuit, a switching circuit, a plurality of devices to be tested, a plurality of pads and the above-mentioned multi-way address register; the input end of the addressing circuit is connected to the output port of the multi-way address register, and the output end of the addressing circuit is connected to the control end of the switching circuit, so as to control the selected device to be tested to be connected to the test signal line through the switching circuit; the plurality of pads at least include a plurality of power access pads, a plurality of address pads and a plurality of test signal pads; the address pads are connected to the multi-way address register; and the test signal pads are connected to the test signal line.

[0022] In a feasible implementation, the addressing circuit includes a row address decoder and a column address decoder; the switch circuit includes a row switch circuit and a column switch circuit; the row address decoder is connected to the row switch circuit, and is used to control the row switch circuit to select the row where the device under test is located; the column address decoder is connected to the column switch circuit, and is used to control the column switch circuit to select the column where the device under test is located. During testing, the row address decoder outputs an address signal to control the on-off state of the switch in the row switch circuit, and selects the row where the device under test is located; the column address decoder outputs an address signal to control the on-off state of the switch in the column switch circuit, and selects the column where the device under test is located. The device under test is uniquely determined to be turned on, and the test signal can smoothly enter the device under test for detection.

[0023] The present invention also provides a test system, including a test instrument, a probe card, an addressable test chip and the above-mentioned multi-way address register; the multi-way address register is integrated on the probe card or integrated on the addressable test chip; the addressable test chip includes an addressing circuit, a switching circuit, a plurality of devices to be tested and a plurality of pads; the test instrument and the addressable test chip are connected to each other through the probe card to form a test path, and the multi-way address register is connected to the addressing circuit in the addressable test chip, and the multi-way address register can transmit an address signal to the addressing circuit according to the input signal of the test instrument.

[0024] The present invention also provides a testing method, which uses the aforementioned testing system for testing, including the following steps: the testing instrument inputs the generated reset signal, clock signal, shift register enable signal and shift register input signal into the multi-way address register; each device under test in the addressable test chip has a different address bit, and by selecting the device under test at each address bit in the addressable test chip, the testing instrument tests each selected device under test.

[0025] The beneficial effects brought by the present invention are as follows: a multi-way address register provided by the present invention, on the basis of supporting fixed-point addressing, also supports traditional continuous addressing mode, selective continuous addressing mode and Gray code continuous addressing mode, and can support subsequent expansion of customized continuous addressing mode.

[0026] The present invention provides a probe card, which integrates the multi-channel address register of the present invention. Because the manufacturing cost of the probe card is low, the manufacturing technology is stable and mature, and it is not affected by the integrated circuit manufacturing process, the performance of the multi-channel address register is stable and the test accuracy is guaranteed; at the same time, the probe card is different from the test chip in that it can be recycled, saving chip testing and production costs.

[0027] The present invention provides a high-density addressable test chip supporting selective addressing, including the multi-way address register of the present invention. On the basis of supporting the traditional continuous addressing mode and the fixed-point addressing mode, it can also at least support the selective continuous addressing mode and the Gray code continuous addressing mode for configuration selection, so that the application is more flexible and both the test efficiency and the test stability are improved.

[0028] The present invention provides a test system in which the multi-channel address register of the present invention is integrated on an addressable test chip or a probe card, and has the above advantages in test applications.

[0029] A testing method provided by the present invention is based on the above-mentioned testing system and is conducive to improving the flexibility and efficiency of testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 FIG. 4 is a schematic diagram of a multi-way address register according to an embodiment of the present invention.

[0031] Figure 2 yes Figure 1 Schematic diagram of "next address calculation" in Figure 1.

[0032] Figure 3 Schematic diagram of a 32-bit multi-way address register in an embodiment of the present invention.

[0033] Figure 4 Schematic diagram of a high-density addressable test chip according to another embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the technical means, creative features, objectives and effects of the present invention easy to understand, the following embodiments are combined with the accompanying drawings to specifically describe the multi-way address register, probe card, high-density addressable test chip supporting selective addressing, and its test system and addressable test method of the present invention. For the convenience of display in the following drawings, some components are only shown as a schematic illustration, and the actual possible number cannot be limited by the number of components shown in the drawings.

[0035] like Figure 1 and Figure 2As shown, a multiplexer address register of an embodiment of the present invention includes a counter logic, a shifter logic, a multiplexer mux, a selective addressing module, a Gray code encoder Gray Encode, a Gray code decoder Gray Decode and a clock edge trigger. The counter logic includes a first counter logic and a second counter logic. The multiplexer mux includes a first multiplexer mux and a second multiplexer mux. There are multiple clock edge triggers, including: a plurality of first clock edge triggers, a plurality of second clock edge triggers and a plurality of third clock edge triggers; the first clock edge trigger is used to receive an address signal address, the second clock edge trigger is used to receive an addressing mode selection signal mode ctrl, and the third clock edge trigger is used to receive auxiliary data aux data. The selective addressing module can realize: judging whether the received current address belongs to the address area to be addressed, if the current address belongs to the address area to be addressed, then the received current address signal +1 (which can be implemented by counter logic) is output as the next address signal; if the current address does not belong to the address area to be addressed, then the address area where the current address is located is skipped, and the starting address of the next address area to be addressed is output as the next address signal. The input port of the multi-way address register includes a reset signal port RST, a clock signal port CLK, a shift register enable port SE and a shift register input port SI; the output port of the multi-way address register includes an address signal port addr and a data type port GB, the address signal port addr is used to output the address signal, and the data type port GB is used to output the data type of the address signal output by the address signal port addr.

[0036] The internal connection relationship of the multi-way address register is as follows: the input end D of the clock edge trigger is connected to the output end of the first multiplexer mux, the input end R is connected to the reset signal port RST, and the input end CK is connected to the clock signal port CLK; the output end Q of the first clock edge trigger is connected to the address signal port addr of the multi-way address register, and the output end Q of the second clock edge trigger is connected to the data type port GB of the multi-way address register; the input end of the shifter logic is connected to the shift register input port SI and the output end Q of the clock edge trigger; the input end of the first counter logic is connected to the output end Q of the first clock edge trigger; the input end of the selection addressing module is connected to the output end Q of the first clock edge trigger; The input end is connected to the output end Q of the first clock edge trigger and the output end Q of the third clock edge trigger; the input end of the Gray code decoder is connected to the output end Q of the first clock edge trigger; the input end of the second counter logic is connected to the output end of the Gray code decoder; the input end of the Gray code encoder is connected to the output end of the second counter logic; the input end of the second multiplexer mux is connected to the output end of the first counter logic, the output end of the selection addressing module, the output end of the Gray code encoder and the output end Q of the second clock edge trigger; the input end of the first multiplexer mux is connected to the shift register enable port SE, the output end of the shifter logic and the output end of the second multiplexer mux.

[0037] In a specific embodiment, the output port of the multi-way address register further includes an auxiliary debugging port AUX, which is connected to the output terminal Q of the first clock edge trigger for address verification, such as connected to the output terminal Q of the first clock edge trigger as the lowest address bit for address verification.

[0038] In a specific embodiment, the first counter logic and the second counter logic can use the same counter logic to implement functions by using control logic. For example, a multiplexer is added to control which signal input to the multiplexer is output to the counter logic, so that the same counter logic can complete the required function.

[0039] The multiplexed address register in this embodiment supports at least four addressing modes: fixed-point addressing mode, conventional continuous addressing mode, selective continuous addressing mode, and Gray code continuous addressing mode. The fixed-point addressing mode will not be described again. Figure 2As shown in the figure, the calculation process of the next address signal for the three continuous addressing modes, namely the traditional continuous addressing mode, the selective continuous addressing mode and the gray code continuous addressing mode, is as follows: from the left data input (current address signal address, auxiliary data aux data, and addressing mode selection signal mode ctrl) to the right data output next address signal next address, there are three data paths in total, corresponding to: the traditional continuous addressing mode (binary mode), the gray code continuous addressing mode (gray mode) and the selective continuous addressing mode (selective mode). The three data paths are finally sent to the second multiplexer mux, which determines which data will be output according to the addressing mode selection signal mode ctrl.

[0040] 1) In the traditional continuous addressing mode (binary mode), the current binary address signal address is increased by 1 each time as the next address signal input to the second multiplexer mux.

[0041] 2) In the gray code continuous addressing mode (gray mode), the current address signal address is encoded by the gray code, so it is necessary to first decode the gray code to convert it into a binary address signal and then add 1, and finally re-encode it into the gray code as the next address signal to the second multiplexer mux.

[0042] It is worth noting that, compared with the traditional continuous addressing method, the address information of the Gray code continuous addressing method is encoded by Gray code. The characteristic of Gray code is that the expression of the two numbers before and after is different by one bit, taking the binary code and Gray code of 0 to 15 as an example.

[0043]

[0044] As in the above example, in binary code, there is a phenomenon of multiple data changes in the preceding and following digits. For example, when the number 7 changes to 8, there are a total of 4 bits in the binary code that change: the first bit 0 changes to 1, and the second to fourth bits 1 change to 0. In Gray code, when 7 changes to 8, only the first bit 0 changes to 1. In fact, in Gray code, the number of bits of data change between any two adjacent digits is only 1. This feature of Gray code can greatly improve the stability of the chip when the multi-channel register is used in the test chip. The stability of the chip is generally inversely proportional to the degree of change of the data stored in it, that is: the more frequently and more the data in the chip changes, the lower its stability; the less it changes, the higher its stability. The reason is that during the data change process, it will have a one-time impact on the power supply. For example, when 0 changes to 1, a large current will flow from the power supply to the ground in an instant. These impacts will have a little impact on the power supply itself. The greater these impacts, the higher the possibility of abnormal chip operation, that is, the lower the stability. Because there is only one bit change between two adjacent digits of Gray code, its stability is very high in Gray code continuous addressing; and based on the fact that test chips are mostly used in processes with low stability, improving its stability is of positive significance.

[0045] 3) Selective continuous addressing mode (selective mode), the current address signal address is a binary signal, the auxiliary data aux data is a selection table, the size of the minimum addressing area is predefined for the selection table, and the address area of ​​each minimum addressing area size is defined in turn according to whether the data in the selection table is 0 or 1, that is, the selection table marks which address areas need to be addressed for testing and which address areas need to be skipped. In the selective continuous addressing mode, it will be confirmed whether the current address belongs to the address area that needs to be addressed according to the selection table: if the current address belongs to the address area to be addressed, the address + 1 is input to the second multiplexer mux as the next address signal; if the current address does not belong to the address area to be addressed, the address area is skipped, and the starting address of the next address area to be addressed is input to the second multiplexer mux as the next address signal.

[0046] It is worth noting that if the desired test area is divided into several blocks, the addresses in each block are continuous, but the addresses between blocks are not continuous, if the traditional continuous addressing method is used, the efficiency of the traditional continuous addressing will be low because the change of address information is always one-way and increases by 1 each time. For example: there are three blocks in the area to be tested, and the address ranges of the three blocks are: 0x0000 ~ 0x3FFF, 0x10000 ~ 0x13FFF, 0x20000 ~ 0x23FFF. The range of the three block address intervals is larger than the address range itself, so the efficiency of using traditional continuous addressing is not high. Taking the above three address ranges as an example, the addressable area is divided into three blocks, namely: 0x0000 ~ 0x3FFF, 0x10000 ~ 0x13FFF, 0x20000 ~ 0x23FFF; if the size of the minimum addressable area is 0x4000 (that is, 128x128, which is consistent with the array size in the test chip), the correspondence between the data in the selection table and the address area can be referred to the following table.

[0047]

[0048] In the above example, the selection table data is 10 bits (expandable). 1 in the selection table indicates that the corresponding address range needs to be addressed, and 0 indicates that the corresponding address range is not addressed. After configuring according to the data in this table, the addressing process is as follows.

[0049] 0x0000 ~ 0x3FFF: within the addressing range, so continuous addressing.

[0050] 0x4000: Found not within the addressing range, skipping this area.

[0051] 0x8000 : Still not in addressing range, skip this area.

[0052] 0xC000: Still not within the addressing range, skip this area.

[0053] 0x10000 ~ 0x13FFF: Start continuous addressing within the addressing range.

[0054] 0x14000: Found not within the addressing range, skipping this area.

[0055] 0x18000: Still not within the addressing range, skip this area.

[0056] 0x1C000: Still not within the addressing range, skip this area.

[0057] 0x20000 ~ 0x23FFF: Start continuous addressing within the addressing range.

[0058] 0x24000: Found not within the addressing range, skipping this area.

[0059] 0x28000: Out of address space, address is meaningless.

[0060] The above examples are provided for easier understanding and are not intended to limit the present invention.

[0061] In a specific application, by setting different numbers of first clock edge triggers, second clock edge triggers and third clock edge triggers, defining the addressing mode selection signal received by the second clock edge trigger, and defining the required auxiliary data received by the third clock edge trigger, the addressing mode expansion of the multi-way address register can be achieved.

[0062] The following takes a 32-bit address register as an example to specifically introduce the multi-way address register of the present invention, but does not limit the present invention in any way.

[0063] Combined with reference Figure 2 ,like Figure 3 As shown, the multi-way address register in the embodiment of the present invention is a 32-bit register (32-bit register), including 20 first clock edge triggers, 2 second clock edge triggers and 10 third clock edge triggers, that is, among the 32 address bits, only the lower 20 bits (19:0) are address signals address; the middle 2 bits (21:20) are addressing mode selection signals mode ctrl. In this embodiment, when it is set to 00, the multi-way address register works in the traditional continuous addressing mode; when it is 01, the multi-way address register works in the Gray code continuous addressing mode (the most stable addressing mode, generally used when the continuous addressing mode is unstable); when it is 10, the multi-way address register works in the selective continuous addressing mode, and the auxiliary data aux data of the upper 10 bits (31:22) are used as a selection table (in other addressing modes, the upper 10 bits of data are meaningless). The addressing mode when the addressing scheme selection signal is 11 is not defined. Signal 11 is reserved for expanding more addressing modes in the future. Through customization, the addressing mode expansion of high-density addressable test chips that support selective addressing can be achieved.

[0064] like Figure 4As shown, based on the above-mentioned multi-way address register, a high-density addressable test chip supporting selective addressing is disclosed, including an addressing circuit, a switch circuit, a plurality of devices under test DUT, a plurality of pads and the above-mentioned multi-way address register. The input end of the addressing circuit is connected to the address signal port addr and the data type port GB of the multi-way address register, and the output end of the addressing circuit is connected to the control end of the switch circuit to control the selected device under test to be connected to the test signal line through the switch circuit. The plurality of pads at least include: a plurality of power supply access pads, such as VSS pads, VDD pads, etc.; a plurality of address pads, such as RST pads, SI pads, AUX pads, CLK pads, SE pads, etc.; and a plurality of test signal pads, such as T1 pads, T2 pads, T3 pads, T4 pads, etc. The address pads are connected to the multi-way address register; and the test signal pads are connected to the test signal line.

[0065] In this embodiment, the switch circuit includes a row switch circuit and a column switch circuit, and the addressing circuit includes a row address decoder and a column address decoder; the row address decoder is connected to the row switch circuit, and is used to control the row switch circuit to select the row where the device under test is located; the column address decoder is connected to the column switch circuit, and is used to control the column switch circuit to select the column where the device under test is located. During testing, the row address decoder outputs an address signal to control the on-off state of the switch in the row switch circuit, and selects the row where the device under test is located, and the column address decoder outputs an address signal to control the on-off state of the switch in the column switch circuit, and selects the column where the device under test is located. When the device under test is uniquely determined to be turned on, the test signal can smoothly enter the device under test for detection.

[0066] Based on the above multi-channel address register, the present invention also discloses an embodiment of a probe card, on which the above multi-channel address register is integrated, so as to be not affected by the integrated circuit manufacturing process, so that the performance of the multi-channel address register is stable and the test accuracy is guaranteed.

[0067] Based on the above-mentioned multi-way address register, a test system is disclosed, which includes a test instrument, a probe card, an addressable test chip and the above-mentioned multi-way address register; the multi-way address register is integrated on the probe card or integrated on the addressable test chip. The addressable test chip includes an addressing circuit, a switch circuit, a plurality of devices to be tested and a plurality of pads. The test instrument is connected to the addressable test chip through the probe card and forms a test path, and the multi-way address register is connected to the addressing circuit in the addressable test chip, and the multi-way address register can transmit an address signal to the addressing circuit according to the input signal of the test instrument. In this embodiment, the test system can provide three continuous addressing modes, namely, a traditional continuous addressing mode, a selective continuous addressing mode and a Gray code continuous addressing mode, for configuration selection. In practical applications, it can be used more flexibly according to different scenarios, and effectively exert the advantages of various addressing modes to obtain more favorable test efficiency and test stability.

[0068] In one embodiment of testing using the above-mentioned test system, the following steps are included: the test instrument inputs the generated reset signal, clock signal, shift register enable signal and shift register input signal into the multi-way address register; each device under test DUT in the addressable test chip has a different address bit, and by selecting the device under test DUT at each address bit in the addressable test chip, the test instrument tests each selected device under test DUT.

[0069] From the above, it can be understood that the present invention achieves the expected beneficial effects. The above embodiments are preferred cases of the present invention and are not intended to limit the scope of protection of the present invention. In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes, and do not specifically refer to the order or sequence, nor are they intended to limit the present invention. They are only used to distinguish components or operations described with the same technical terms, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated.

Claims

1. A multi-way address register, characterized in that: Includes counter logic, shifter logic, multiplexer, select addressing module and clock edge trigger; The counter logic includes at least a first counter logic; The multiplexer is provided with at least two, which are set as a first multiplexer and a second multiplexer; The clock edge trigger is provided with a plurality of them, including: a plurality of first clock edge triggers, a plurality of second clock edge triggers and a plurality of third clock edge triggers; the first clock edge trigger is used to receive an address signal, the second clock edge trigger is used to receive an addressing mode selection signal, and the third clock edge trigger is used to receive auxiliary data; The selective addressing module can realize: judging whether the received current address belongs to the address area to be addressed, if the current address belongs to the address area to be addressed, then the received current address signal + 1 and output as the next address signal; if the current address does not belong to the address area to be addressed, then skipping the address area where the current address is located, and outputting the starting address of the next address area to be addressed as the next address signal; The input ports of the multi-way address register include: a reset signal port RST, a clock signal port CLK, a shift register enable port SE and a shift register input port SI; in: The input terminal D of the clock edge trigger is connected to the output terminal of the first multiplexer, the input terminal R of the clock edge trigger is connected to the reset signal port RST, and the input terminal CK of the clock edge trigger is connected to the clock signal port CLK; the output terminal Q of the first clock edge trigger and the output terminal Q of the second clock edge trigger are respectively connected to the output port of the multi-way address register; The input end of the shifter logic is connected to the shift register input port SI and the output end Q of the clock edge trigger; The input terminal of the first counter logic is connected to the output terminal Q of the first clock edge trigger; The input end of the selection addressing module is connected to the output end Q of the first clock edge trigger and the output end Q of the third clock edge trigger; The input end of the second multiplexer is connected to the output end of the first counter logic, the output end of the selection addressing module and the output end Q of the second clock edge trigger; An input terminal of the first multiplexer is connected to a shift register enable port SE, an output terminal of the shifter logic, and an output terminal of the second multiplexer.

2. A multi-way address register according to claim 1, characterized in that: The output port of the multi-way address register includes an address signal port addr and a data type port GB; the address signal port addr is connected to the output terminal Q of the first clock edge trigger; the data type port GB is connected to the output terminal Q of the second clock edge trigger.

3. A multi-way address register according to claim 2, characterized in that: The output port of the multi-channel address register further includes an auxiliary debugging port AUX, and the auxiliary debugging port AUX is connected to the output terminal Q of the first clock edge trigger for address verification.

4. A multi-way address register according to claim 1, characterized in that: The multi-way address register supports at least two continuous addressing modes: a traditional continuous addressing mode and a selective continuous addressing mode; The conventional continuous addressing method refers to: using the first clock edge trigger to receive a binary current address signal, and using the first counter logic to increase the received current address signal by 1, and inputting the received current address signal into the second multiplexer as the next address signal; The selective continuous addressing mode refers to: using the first clock edge trigger to receive the binary current address signal, and using the auxiliary data received by the third clock edge trigger as a selection table; the selection table stores information on whether the address area needs to be addressed, and confirms whether the current address belongs to the address area to be addressed based on the information; if the current address belongs to the address area to be addressed, the received current address signal + 1 is input into the second multiplexer as the next address signal; if the current address does not belong to the address area to be addressed, the address area where the current address is located is skipped, and the starting address of the next address area to be addressed is input into the second multiplexer as the next address signal; The specific implementation method of selecting to use one of the above-mentioned continuous addressing modes is to receive the addressing mode selection signal through the second clock edge trigger and transmit it to the second multiplexer. The second multiplexer determines to use a corresponding continuous addressing mode according to the addressing mode selection signal, and outputs the next address signal generated by this continuous addressing mode.

5. A multi-way address register according to claim 1, characterized in that: Also includes a Gray code encoder and a Gray code decoder; the counter logic also includes a second counter logic; The input end of the Gray code decoder is connected to the output end Q of the first clock edge trigger, and the output end thereof is connected to the input end of the second counter logic; The input of the Gray code encoder is connected to the output of the second counter logic, and its output is connected to the input of the second multiplexer.

6. A multi-way address register according to claim 5, characterized in that: The multi-way address register supports at least three continuous addressing modes: a traditional continuous addressing mode, a selective continuous addressing mode and a Gray code continuous addressing mode; The conventional continuous addressing method refers to: using the first clock edge trigger to receive a binary current address signal, and using the first counter logic to increase the received current address signal by 1, and inputting the received current address signal into the second multiplexer as the next address signal; The selective continuous addressing mode refers to: using the first clock edge trigger to receive the binary current address signal, and using the auxiliary data received by the third clock edge trigger as a selection table; the selection table stores information on whether the address area needs to be addressed, and confirms whether the current address belongs to the address area to be addressed based on the information; if the current address belongs to the address area to be addressed, the received current address signal + 1 is input into the second multiplexer as the next address signal; if the current address does not belong to the address area to be addressed, the address area where the current address is located is skipped, and the starting address of the next address area to be addressed is input into the second multiplexer as the next address signal; The Gray code continuous addressing mode is to use the first clock edge trigger to receive the current address signal of the Gray code, first decode the received current address signal into a binary address signal through the Gray code decoder, then use the second counter logic to increase the binary address signal by 1, and then use the Gray code encoder to re-encode it into a Gray code signal as the next address signal to input into the second multiplexer; The specific implementation method of selecting to use one of the above-mentioned continuous addressing modes is to receive the addressing mode selection signal through the second clock edge trigger and transmit it to the second multiplexer. The second multiplexer determines to use a corresponding continuous addressing mode according to the addressing mode selection signal, and outputs the next address signal generated by this continuous addressing mode.

7. A multi-way address register according to claim 5, characterized in that: The first counter logic and the second counter logic can use the same counter logic to implement functions using control logic.

8. A multi-way address register according to claim 1, characterized in that: By setting different numbers of first clock edge triggers, second clock edge triggers and third clock edge triggers, defining the addressing mode selection signal received by the second clock edge trigger, and defining the required auxiliary data received by the third clock edge trigger, the addressing mode expansion of the multi-channel address register is achieved.

9. A probe card, characterized in that: The multi-way address register according to any one of claims 1 to 8 is integrated.

10. A high-density addressable test chip supporting selective addressing, characterized in that: It comprises an addressing circuit, a switch circuit, a plurality of devices to be tested, a plurality of pads and a multi-way address register as claimed in any one of claims 1 to 8; The input end of the addressing circuit is connected to the output port of the multi-way address register, and the output end of the addressing circuit is connected to the control end of the switch circuit, so as to control the selected device under test to be connected to the test signal line through the switch circuit for testing; The plurality of pads at least include a plurality of power supply access pads, a plurality of address pads and a plurality of test signal pads; the address pads are connected to the multi-channel address register; and the test signal pads are connected to the test signal lines.

11. The high-density addressable test chip supporting selective addressing according to claim 10, characterized in that: The addressing circuit includes a row address decoder and a column address decoder; the switch circuit includes a row switch circuit and a column switch circuit; The row address decoder is connected to the row switch circuit and is used to control the row switch circuit to select the row where the device under test is located; the column address decoder is connected to the column switch circuit and is used to control the column switch circuit to select the column where the device under test is located.

12. A testing system, characterized in that: It comprises a test instrument, a probe card, an addressable test chip and the multi-way address register according to any one of claims 1 to 8; the multi-way address register is integrated on the probe card or integrated on the addressable test chip; The addressable test chip includes an addressing circuit, a switching circuit, a plurality of devices to be tested and a plurality of pads; the test instrument is connected to the addressable test chip through a probe card to form a test path, and a multi-way address register is connected to the addressing circuit in the addressable test chip, and the multi-way address register can transmit an address signal to the addressing circuit according to an input signal of the test instrument.

13. A testing method, characterized in that: Testing using the test system described in claim 12 includes the following steps: the test instrument inputs the generated reset signal, clock signal, shift register enable signal and shift register input signal into the multi-way address register; each device under test in the addressable test chip has a different address bit, and the test instrument tests each selected device under test by selecting the device under test at each address bit in the addressable test chip.

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